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Information for RPM vhd2vl-2.5-7.fc30.src.rpm

ID	317469
Name	vhd2vl
Version	2.5
Release	7.fc30
Epoch
Arch	src
Summary	VHDL to Verilog translator
Description	vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthetisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs.
Build Time	2018-12-10 00:51:30 GMT
Size	53.98 KB
SIGMD5	b969d6fd3a4fb2362e8a3db7dacd8f57
License	GPLv2+
Buildroot	f30-build-41425-23217
Provides	No Provides
Obsoletes	No Obsoletes
Conflicts	No Conflicts
Requires	bison flex flex-devel gcc rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1
Recommends	No Recommends
Suggests	No Suggests
Supplements	No Supplements
Enhances	No Enhances
Files	1 through 2 of 2 Name Size vhd2vl-2.5.tar.gz 45.16 KB vhd2vl.spec 4.78 KB
Component of	No Buildroots