verilator-5.026-7.fc41 | Build Info

Information for build verilator-5.026-7.fc41

333376

Package Name

verilator

Version

5.026

Release

7.fc41

Epoch

Source

git+https://src.fedoraproject.org/rpms/verilator.git#b41054f222af47f93c451727da5a0b94c7983fe6

Summary

A fast simulator for synthesizable Verilog

Description

Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.

Built by

davidlt

State

complete

Volume

DEFAULT

Started

Thu, 08 Aug 2024 08:28:21 UTC

Completed

Thu, 08 Aug 2024 11:23:55 UTC

Task

build (f41, /rpms/verilator.git:b41054f222af47f93c451727da5a0b94c7983fe6)

Extra

{'source': {'original_url': 'git+https://src.fedoraproject.org/rpms/verilator.git#b41054f222af47f93c451727da5a0b94c7983fe6'}}

Tags

f41

RPMs

src
	verilator-5.026-7.fc41.src.rpm (info) (download)
noarch
	verilator-doc-5.026-7.fc41.noarch.rpm (info) (download)
riscv64
	verilator-5.026-7.fc41.riscv64.rpm (info) (download)
	verilator-devel-5.026-7.fc41.riscv64.rpm (info) (download)
	verilator-debuginfo-5.026-7.fc41.riscv64.rpm (info) (download)
	verilator-debugsource-5.026-7.fc41.riscv64.rpm (info) (download)

Logs

riscv64
	hw_info.log
	state.log
	build.log
	root.log
	mock_output.log
	noarch_rpmdiff.json

Changelog

* Sat Jul 20 2024 Fedora Release Engineering <releng@fedoraproject.org> None-7 - Rebuilt for https://fedoraproject.org/wiki/Fedora_41_Mass_Rebuild * Mon Jul 15 2024 Nolan Poe <npgo22@gmail.com> None-6 - Update to Verilator 5.026 * Fri Apr 05 2024 Nolan Poe <npgo22@gmail.com> None-5 - RPMAUTOSPEC: unresolvable merge

Main Site Links:

Information for build verilator-5.026-7.fc41