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Rebase riscv patch 

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
This commit is contained in:
David Abdurachmanov 2019-07-25 19:00:57 +03:00
parent cef2095caf
commit a84dace056
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
2 changed files with 6 additions and 6 deletions
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10
VTK-7.1.1-riscv64.patch → VTK-8.2.0-riscv64.patch
View File

@ -1,9 +1,9 @@
diff --git a/Utilities/KWIML/vtkkwiml/include/kwiml/abi.h b/Utilities/KWIML/vtkkwiml/include/kwiml/abi.h
index 3626361..2050da1 100644
index 546bacd0..b188f8f2 100644
--- a/Utilities/KWIML/vtkkwiml/include/kwiml/abi.h
+++ b/Utilities/KWIML/vtkkwiml/include/kwiml/abi.h
@@ -467,6 +467,10 @@ suppression macro KWIML_ABI_NO_VERIFY was defined.
#elif defined(__XTENSA_EL__)
@@ -471,6 +471,10 @@ suppression macro KWIML_ABI_NO_VERIFY was defined.
#elif defined(__riscv__)
# define KWIML_ABI_ENDIAN_ID KWIML_ABI_ENDIAN_ID_LITTLE
+/* RISC-V */
@ -14,10 +14,10 @@ index 3626361..2050da1 100644
#elif !defined(KWIML_ABI_NO_ERROR_ENDIAN)
# error "Byte order of target CPU unknown."
diff --git a/Wrapping/Tools/vtkParsePreprocess.c b/Wrapping/Tools/vtkParsePreprocess.c
index 383785a..af306e5 100644
index 539a953f..8d92db95 100644
--- a/Wrapping/Tools/vtkParsePreprocess.c
+++ b/Wrapping/Tools/vtkParsePreprocess.c
@@ -2706,6 +2706,9 @@ void vtkParsePreprocess_AddStandardMacros(
@@ -2705,6 +2705,9 @@ void vtkParsePreprocess_AddStandardMacros(
#ifdef __xtensa__
PREPROC_ADD_MACRO(info, __xtensa__);
#endif

2
vtk.spec
View File

@ -29,7 +29,7 @@ Source3: FindPEGTL.cmake
# Python 3.7 compat
Patch0: https://gitlab.kitware.com/vtk/vtk/merge_requests/4490.patch
# Support for RISC-V (riscv64)
Patch10: VTK-7.1.1-riscv64.patch
Patch10: VTK-8.2.0-riscv64.patch
URL: http://vtk.org/