42 lines
1.8 KiB
Diff
42 lines
1.8 KiB
Diff
commit 097f20df1653c33035b6dcfefbbef22572426c65
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Author: Josh Blum <josh@joshknows.com>
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Date: Mon Mar 26 14:25:56 2012 -0700
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dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHz
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This fixes the lockup/clocking condition when the following hw combo is used:
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USRP1 r4.5 + DBSRX + another i2c board
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diff --git a/host/lib/usrp/dboard/db_dbsrx.cpp b/host/lib/usrp/dboard/db_dbsrx.cpp
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index 846597f..95c5c5d 100644
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--- a/host/lib/usrp/dboard/db_dbsrx.cpp
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+++ b/host/lib/usrp/dboard/db_dbsrx.cpp
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@@ -1,5 +1,5 @@
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//
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-// Copyright 2010-2011 Ettus Research LLC
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+// Copyright 2010-2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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@@ -58,6 +58,8 @@ static const uhd::dict<std::string, gain_range_t> dbsrx_gain_ranges = map_list_o
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("GC2", gain_range_t(0, 24, 1))
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;
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+static const double usrp1_gpio_clock_rate_limit = 4e6;
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+
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/***********************************************************************
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* The DBSRX dboard class
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**********************************************************************/
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@@ -265,6 +267,11 @@ double dbsrx::set_lo_freq(double target_freq){
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std::vector<double> clock_rates = this->get_iface()->get_clock_rates(dboard_iface::UNIT_RX);
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const double max_clock_rate = uhd::sorted(clock_rates).back();
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BOOST_FOREACH(ref_clock, uhd::reversed(uhd::sorted(clock_rates))){
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+ //USRP1 feeds the DBSRX clock from a FPGA GPIO line.
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+ //make sure that this clock does not exceed rate limit.
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+ if (this->get_iface()->get_special_props().soft_clock_divider){
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+ if (ref_clock > usrp1_gpio_clock_rate_limit) continue;
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+ }
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if (ref_clock > 27.0e6) continue;
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if (size_t(max_clock_rate/ref_clock)%2 == 1) continue; //reject asymmetric clocks (odd divisors)
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