commit 097f20df1653c33035b6dcfefbbef22572426c65
Author: Josh Blum <josh@joshknows.com>
Date:   Mon Mar 26 14:25:56 2012 -0700

    dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHz
    
    This fixes the lockup/clocking condition when the following hw combo is used:
    USRP1 r4.5 + DBSRX + another i2c board

diff --git a/host/lib/usrp/dboard/db_dbsrx.cpp b/host/lib/usrp/dboard/db_dbsrx.cpp
index 846597f..95c5c5d 100644
--- a/host/lib/usrp/dboard/db_dbsrx.cpp
+++ b/host/lib/usrp/dboard/db_dbsrx.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2011 Ettus Research LLC
+// Copyright 2010-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -58,6 +58,8 @@ static const uhd::dict<std::string, gain_range_t> dbsrx_gain_ranges = map_list_o
     ("GC2", gain_range_t(0, 24, 1))
 ;
 
+static const double usrp1_gpio_clock_rate_limit = 4e6;
+
 /***********************************************************************
  * The DBSRX dboard class
  **********************************************************************/
@@ -265,6 +267,11 @@ double dbsrx::set_lo_freq(double target_freq){
     std::vector<double> clock_rates = this->get_iface()->get_clock_rates(dboard_iface::UNIT_RX);
     const double max_clock_rate = uhd::sorted(clock_rates).back();
     BOOST_FOREACH(ref_clock, uhd::reversed(uhd::sorted(clock_rates))){
+        //USRP1 feeds the DBSRX clock from a FPGA GPIO line.
+        //make sure that this clock does not exceed rate limit.
+        if (this->get_iface()->get_special_props().soft_clock_divider){
+            if (ref_clock > usrp1_gpio_clock_rate_limit) continue;
+        }
         if (ref_clock > 27.0e6) continue;
         if (size_t(max_clock_rate/ref_clock)%2 == 1) continue; //reject asymmetric clocks (odd divisors)