1037 lines
33 KiB
Diff
1037 lines
33 KiB
Diff
From 020d7166a6896f1b50f6596c66aec8e7f1d00b19 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Mon, 22 May 2017 05:17:21 -0600
|
|
Subject: [PATCH 01/16] arm: arm720t: Support CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
|
|
|
This option allows skipping the call to lowlevel() while still performing
|
|
CP15 init. Support this on ARM720T so it can be used with Tegra.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
---
|
|
arch/arm/cpu/arm720t/start.S | 6 ++++--
|
|
1 file changed, 4 insertions(+), 2 deletions(-)
|
|
|
|
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
|
|
index 0bb3441fb8..365d8f08cb 100644
|
|
--- a/arch/arm/cpu/arm720t/start.S
|
|
+++ b/arch/arm/cpu/arm720t/start.S
|
|
@@ -38,7 +38,8 @@ reset:
|
|
* we do sys-critical inits only at reboot,
|
|
* not when booting from ram!
|
|
*/
|
|
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
|
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
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+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
|
bl cpu_init_crit
|
|
#endif
|
|
|
|
@@ -62,7 +63,8 @@ c_runtime_cpu_setup:
|
|
*************************************************************************
|
|
*/
|
|
|
|
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
|
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
|
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
|
cpu_init_crit:
|
|
|
|
mov ip, lr
|
|
--
|
|
2.13.0
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|
|
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From 4ad88c5fe7417849cdf9469a89df114a802fd192 Mon Sep 17 00:00:00 2001
|
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From: Simon Glass <sjg@chromium.org>
|
|
Date: Mon, 22 May 2017 05:17:22 -0600
|
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Subject: [PATCH 02/16] tegra: Init clocks even when SPL did not run
|
|
|
|
At present early clock init happens in SPL. If SPL did not run (because
|
|
for example U-Boot is chain-loaded from another boot loader) then the
|
|
clocks are not set as U-Boot expects.
|
|
|
|
Add a function to detect this and call the early clock init in U-Boot
|
|
proper.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
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arch/arm/include/asm/arch-tegra/clock.h | 3 +++
|
|
arch/arm/mach-tegra/board2.c | 3 +++
|
|
arch/arm/mach-tegra/clock.c | 5 +++++
|
|
arch/arm/mach-tegra/tegra124/clock.c | 18 ++++++++++++++++++
|
|
4 files changed, 29 insertions(+)
|
|
|
|
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
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|
index 388afcb723..f62b2a4378 100644
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|
--- a/arch/arm/include/asm/arch-tegra/clock.h
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|
+++ b/arch/arm/include/asm/arch-tegra/clock.h
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@@ -288,6 +288,9 @@ void clock_init(void);
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/* Initialize the PLLs */
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void clock_early_init(void);
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+/* @return true if hardware indicates that clock_early_init() was called */
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+bool clock_early_init_done(void);
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+
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/* Returns a pointer to the clock source register for a peripheral */
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u32 *get_periph_source_reg(enum periph_id periph_id);
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|
|
|
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
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index 84f1ee5035..1e627ba603 100644
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--- a/arch/arm/mach-tegra/board2.c
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|
+++ b/arch/arm/mach-tegra/board2.c
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@@ -191,6 +191,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
|
|
|
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int board_early_init_f(void)
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{
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+ if (!clock_early_init_done())
|
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+ clock_early_init();
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|
+
|
|
#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
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#define USBCMD_FS2 (1 << 15)
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{
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diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
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index 3bb72331a4..76436d8d91 100644
|
|
--- a/arch/arm/mach-tegra/clock.c
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|
+++ b/arch/arm/mach-tegra/clock.c
|
|
@@ -825,3 +825,8 @@ int clock_external_output(int clk_id)
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|
|
|
return 0;
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}
|
|
+
|
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+__weak bool clock_early_init_done(void)
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|
+{
|
|
+ return true;
|
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+}
|
|
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
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index 5e4406102f..5ae718b342 100644
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--- a/arch/arm/mach-tegra/tegra124/clock.c
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+++ b/arch/arm/mach-tegra/tegra124/clock.c
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@@ -891,6 +891,24 @@ void clock_early_init(void)
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udelay(2);
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}
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|
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+/*
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+ * clock_early_init_done - Check if clock_early_init() has been called
|
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+ *
|
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+ * Check a register that we set up to see if clock_early_init() has already
|
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+ * been called.
|
|
+ *
|
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+ * @return true if clock_early_init() was called, false if not
|
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+ */
|
|
+bool clock_early_init_done(void)
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+{
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+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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|
+ u32 val;
|
|
+
|
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+ val = readl(&clkrst->crc_sclk_brst_pol);
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|
+
|
|
+ return val == 0x20002222;
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+}
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|
+
|
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void arch_timer_init(void)
|
|
{
|
|
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
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--
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2.13.0
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|
|
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From 7a620d51326418a688c2c8a0eb3d12477f137509 Mon Sep 17 00:00:00 2001
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From: Simon Glass <sjg@chromium.org>
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Date: Mon, 22 May 2017 05:17:23 -0600
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Subject: [PATCH 03/16] tegra: dts: Add cros-ec SPI settings
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|
At present the interrupt does not work and the SPI bus runs much less
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quickly than it should. Add settings to fix this.
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|
|
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Signed-off-by: Simon Glass <sjg@chromium.org>
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---
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arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
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index fff1d78169..65c3851aff 100644
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--- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
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+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
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@@ -12,4 +12,13 @@
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u-boot,dm-pre-reloc;
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};
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};
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+
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+ spi@7000d400 {
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+ spi-deactivate-delay = <200>;
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+ spi-max-frequency = <3000000>;
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+
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+ cros_ec: cros-ec@0 {
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+ ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
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+ };
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+ };
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};
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--
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2.13.0
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|
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From 2572367d6ac97d1570895d95b48e552b3368b946 Mon Sep 17 00:00:00 2001
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From: Simon Glass <sjg@chromium.org>
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Date: Mon, 22 May 2017 05:17:24 -0600
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Subject: [PATCH 04/16] arm: Rename HCTR to HTCR
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This appears to be a typo. Fix it.
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Signed-off-by: Simon Glass <sjg@chromium.org>
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Reviewed-by: Tom Rini <trini@konsulko.com>
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---
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arch/arm/lib/cache-cp15.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
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index e9bbcf5122..0f7020a315 100644
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--- a/arch/arm/lib/cache-cp15.c
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+++ b/arch/arm/lib/cache-cp15.c
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@@ -147,7 +147,7 @@ static inline void mmu_setup(void)
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#endif
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if (is_hyp()) {
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- /* Set HCTR to enable LPAE */
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+ /* Set HTCR to enable LPAE */
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asm volatile("mcr p15, 4, %0, c2, c0, 2"
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: : "r" (reg) : "memory");
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/* Set HTTBR0 */
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--
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2.13.0
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From 0774ee2d776a94db3643712e6ae2d17478d1d4f9 Mon Sep 17 00:00:00 2001
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From: Simon Glass <sjg@chromium.org>
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Date: Mon, 22 May 2017 05:17:25 -0600
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Subject: [PATCH 05/16] arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T
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At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
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instructions which are invalid on ARMv4T. This happens on Tegra since it
|
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has an ARMv4T boot CPU. Add a check for the architecture version to allow
|
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the code to be built. It will not actually be executed by the boot CPU,
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but needs to compile.
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Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
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|
arch/arm/lib/cache-cp15.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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|
|
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diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
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|
index 0f7020a315..f293573601 100644
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--- a/arch/arm/lib/cache-cp15.c
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|
+++ b/arch/arm/lib/cache-cp15.c
|
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@@ -129,7 +129,7 @@ static inline void mmu_setup(void)
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dram_bank_mmu_setup(i);
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}
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|
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-#ifdef CONFIG_ARMV7_LPAE
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+#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
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/* Set up 4 PTE entries pointing to our 4 1GB page tables */
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for (i = 0; i < 4; i++) {
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u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
|
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--
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2.13.0
|
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|
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From ee429961064d33b40fe1c11a09bc92611db46dd8 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Mon, 22 May 2017 05:17:26 -0600
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Subject: [PATCH 06/16] arm: Disable LPAE if not enabled
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|
|
If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
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is disabled. This can happen if U-Boot is chain-loaded from another boot
|
|
loader which does enable LPAE.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
---
|
|
arch/arm/lib/cache-cp15.c | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
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|
index f293573601..cf852c061b 100644
|
|
--- a/arch/arm/lib/cache-cp15.c
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|
+++ b/arch/arm/lib/cache-cp15.c
|
|
@@ -172,6 +172,15 @@ static inline void mmu_setup(void)
|
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: : "r" (MEMORY_ATTRIBUTES) : "memory");
|
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}
|
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#elif defined(CONFIG_CPU_V7)
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+ if (is_hyp()) {
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+ /* Set HTCR to disable LPAE */
|
|
+ asm volatile("mcr p15, 4, %0, c2, c0, 2"
|
|
+ : : "r" (0) : "memory");
|
|
+ } else {
|
|
+ /* Set TTBCR to disable LPAE */
|
|
+ asm volatile("mcr p15, 0, %0, c2, c0, 2"
|
|
+ : : "r" (0) : "memory");
|
|
+ }
|
|
/* Set TTBR0 */
|
|
reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
|
|
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
|
|
--
|
|
2.13.0
|
|
|
|
From 3c8e3993c6b8cd34aefebf98e1cbeb49259c516c Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Mon, 22 May 2017 05:17:27 -0600
|
|
Subject: [PATCH 07/16] tegra: spi: Wait a little after setting the clocks
|
|
|
|
For devices that need a delay between SPI transactions we seem to need an
|
|
additional delay before the first one if the CPU is running at full speed.
|
|
Add this, under control of the existing setting. At present it will only
|
|
be enabled with the Chrome OS EC.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
drivers/spi/tegra114_spi.c | 1 +
|
|
1 file changed, 1 insertion(+)
|
|
|
|
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
|
|
index 897409ca02..055cec599c 100644
|
|
--- a/drivers/spi/tegra114_spi.c
|
|
+++ b/drivers/spi/tegra114_spi.c
|
|
@@ -152,6 +152,7 @@ static int tegra114_spi_probe(struct udevice *bus)
|
|
bus->name, priv->freq, rate);
|
|
}
|
|
}
|
|
+ udelay(plat->deactivate_delay_us);
|
|
|
|
/* Clear stale status here */
|
|
setbits_le32(®s->fifo_status,
|
|
--
|
|
2.13.0
|
|
|
|
From f60aa6adeb8dd601d0edd2944956b7f3866971e0 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Mon, 22 May 2017 05:17:29 -0600
|
|
Subject: [PATCH 08/16] tegra: video: Don't power up the SOR twice
|
|
|
|
If U-Boot is the secondary boot loader, or has been run from itself, the
|
|
SOR may already be powered up. Powering it up again causes a hang, so
|
|
detect this situation and skip it.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
drivers/video/tegra124/sor.c | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c
|
|
index 5e4140ff53..4324071cdc 100644
|
|
--- a/drivers/video/tegra124/sor.c
|
|
+++ b/drivers/video/tegra124/sor.c
|
|
@@ -466,11 +466,20 @@ void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count)
|
|
static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds)
|
|
{
|
|
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
|
|
+ u32 reg;
|
|
int ret;
|
|
|
|
if (sor->power_is_up)
|
|
return 0;
|
|
|
|
+ /*
|
|
+ * If for some reason it is already powered up, don't do it again.
|
|
+ * This can happen if U-Boot is the secondary boot loader.
|
|
+ */
|
|
+ reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
|
|
+ if (reg & DP_PADCTL_PD_TXD_0_NO)
|
|
+ return 0;
|
|
+
|
|
/* Set link bw */
|
|
tegra_dc_sor_set_link_bandwidth(dev, is_lvds ?
|
|
CLK_CNTRL_DP_LINK_SPEED_LVDS :
|
|
--
|
|
2.13.0
|
|
|
|
From c57061d42d97d0680906e3d61746dcf0659124b6 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Mon, 22 May 2017 05:17:30 -0600
|
|
Subject: [PATCH 09/16] tegra: Enable CP15 init
|
|
|
|
At present CP15 init is disabled on tegra. Use the correct option so that
|
|
this init is performed on boot. This enables the instruction cache, for
|
|
example, which is critical to the machine running at full speed.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
include/configs/tegra-common-post.h | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
|
|
index ab4136ab13..35d5d8bdc0 100644
|
|
--- a/include/configs/tegra-common-post.h
|
|
+++ b/include/configs/tegra-common-post.h
|
|
@@ -105,7 +105,7 @@
|
|
/* overrides for SPL build here */
|
|
#ifdef CONFIG_SPL_BUILD
|
|
|
|
-#define CONFIG_SKIP_LOWLEVEL_INIT
|
|
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
|
|
|
/* remove I2C support */
|
|
#ifdef CONFIG_SYS_I2C_TEGRA
|
|
--
|
|
2.13.0
|
|
|
|
From 1f6a9c44b31b1bd18669715e58269e15666ac6f9 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Mon, 22 May 2017 05:17:31 -0600
|
|
Subject: [PATCH 10/16] tegra: clock: Avoid a divide-by-zero error
|
|
|
|
The clock fix-up for tegra is still present in the code. It causes a
|
|
divide-by-zero bug after relocation when chain-loading U-Boot from
|
|
coreboot. Fix this by adding a check.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks)
|
|
---
|
|
arch/arm/mach-tegra/clock.c | 5 ++++-
|
|
1 file changed, 4 insertions(+), 1 deletion(-)
|
|
|
|
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
|
|
index 76436d8d91..bac42119cd 100644
|
|
--- a/arch/arm/mach-tegra/clock.c
|
|
+++ b/arch/arm/mach-tegra/clock.c
|
|
@@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
|
|
* return value doesn't help. In summary this clock driver is
|
|
* quite broken but I'm afraid I have no idea how to fix it
|
|
* without completely replacing it.
|
|
+ *
|
|
+ * Be careful to avoid a divide by zero error.
|
|
*/
|
|
- div -= 2;
|
|
+ if (div >= 1)
|
|
+ div -= 2;
|
|
break;
|
|
#endif
|
|
default:
|
|
--
|
|
2.13.0
|
|
|
|
From 164683eb90821555d90c7f471e12781eb278edf1 Mon Sep 17 00:00:00 2001
|
|
From: Peter Robinson <pbrobinson@gmail.com>
|
|
Date: Mon, 29 May 2017 14:22:28 +0100
|
|
Subject: [PATCH 11/16] tegra: nyan-big: Enable the dhrystone benchmark
|
|
|
|
Enable this so we can roughly measure CPU performance. Also enable the
|
|
cache command to allow for timing.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
configs/nyan-big_defconfig | 2 ++
|
|
1 file changed, 2 insertions(+)
|
|
|
|
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
|
|
index 42fe120786..85a8bb80c3 100644
|
|
--- a/configs/nyan-big_defconfig
|
|
+++ b/configs/nyan-big_defconfig
|
|
@@ -23,6 +23,7 @@ CONFIG_CMD_GPIO=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
# CONFIG_CMD_NFS is not set
|
|
CONFIG_CMD_BMP=y
|
|
+CONFIG_CMD_CACHE=y
|
|
CONFIG_CMD_PMIC=y
|
|
CONFIG_CMD_REGULATOR=y
|
|
CONFIG_CMD_TPM=y
|
|
@@ -63,5 +64,6 @@ CONFIG_DM_VIDEO=y
|
|
CONFIG_DISPLAY=y
|
|
CONFIG_VIDEO_TEGRA124=y
|
|
CONFIG_VIDEO_BRIDGE=y
|
|
+CONFIG_CMD_DHRYSTONE=y
|
|
CONFIG_TPM=y
|
|
CONFIG_ERRNO_STR=y
|
|
--
|
|
2.13.0
|
|
|
|
From a7ae84b53bf008a2491854fb57ce55e769a7ed79 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Wed, 31 May 2017 17:57:09 -0600
|
|
Subject: [PATCH 12/16] display_options: Refactor to allow obtaining the banner
|
|
|
|
Move the display options code into a separate function so that the U-Boot
|
|
banner can be obtained from other code. Adjust the 'version' command to
|
|
use it.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
cmd/version.c | 4 +++-
|
|
include/display_options.h | 15 +++++++++++++++
|
|
lib/display_options.c | 21 +++++++++++++++++----
|
|
3 files changed, 35 insertions(+), 5 deletions(-)
|
|
|
|
diff --git a/cmd/version.c b/cmd/version.c
|
|
index 1be0667f09..15aab5dc18 100644
|
|
--- a/cmd/version.c
|
|
+++ b/cmd/version.c
|
|
@@ -17,7 +17,9 @@ const char __weak version_string[] = U_BOOT_VERSION_STRING;
|
|
|
|
static int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
- printf("\n%s\n", version_string);
|
|
+ char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
|
|
+
|
|
+ printf(display_options_get_banner(false, buf, sizeof(buf)));
|
|
#ifdef CC_VERSION_STRING
|
|
puts(CC_VERSION_STRING "\n");
|
|
#endif
|
|
diff --git a/include/display_options.h b/include/display_options.h
|
|
index ac44c459b3..90891a817f 100644
|
|
--- a/include/display_options.h
|
|
+++ b/include/display_options.h
|
|
@@ -56,4 +56,19 @@ int print_buffer(ulong addr, const void *data, uint width, uint count,
|
|
*/
|
|
int display_options(void);
|
|
|
|
+/* Suggested length of the buffer to pass to display_options_get_banner() */
|
|
+#define DISPLAY_OPTIONS_BANNER_LENGTH 120
|
|
+
|
|
+/**
|
|
+ * display_options_get_banner() - Get the U-Boot banner as a string
|
|
+ *
|
|
+ * This returns the U-Boot banner string
|
|
+ *
|
|
+ * @newlines: true to include two newlines at the start
|
|
+ * @buf: place to put string
|
|
+ * @size: Size of buf
|
|
+ * @return buf
|
|
+ */
|
|
+char *display_options_get_banner(bool newlines, char *buf, int size);
|
|
+
|
|
#endif
|
|
diff --git a/lib/display_options.c b/lib/display_options.c
|
|
index 29343fc00e..ebf684f43b 100644
|
|
--- a/lib/display_options.c
|
|
+++ b/lib/display_options.c
|
|
@@ -13,13 +13,26 @@
|
|
#include <linux/ctype.h>
|
|
#include <asm/io.h>
|
|
|
|
-int display_options (void)
|
|
+char *display_options_get_banner(bool newlines, char *buf, int size)
|
|
{
|
|
+ int len;
|
|
+
|
|
+ len = snprintf(buf, size, "%s%s", newlines ? "\n\n" : "",
|
|
+ version_string);
|
|
#if defined(BUILD_TAG)
|
|
- printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG);
|
|
-#else
|
|
- printf ("\n\n%s\n\n", version_string);
|
|
+ len += snprintf(buf + len, size - len, ", Build: %s", BUILD_TAG);
|
|
#endif
|
|
+ len += snprintf(buf + len, size - len, "\n\n");
|
|
+
|
|
+ return buf;
|
|
+}
|
|
+
|
|
+int display_options(void)
|
|
+{
|
|
+ char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
|
|
+
|
|
+ printf(display_options_get_banner(true, buf, sizeof(buf)));
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
--
|
|
2.13.0
|
|
|
|
From 68b78517e76a87445147dc76b774d3995d825933 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Wed, 31 May 2017 17:57:10 -0600
|
|
Subject: [PATCH 13/16] Allow displaying the U-Boot banner on a video display
|
|
|
|
At present the U-Boot banner is only displayed on the serial console. If
|
|
this is not visible to the user, the banner does not show. Some devices
|
|
have a video display which can usefully display this information.
|
|
|
|
Add a banner which is printed after relocation only on non-serial devices
|
|
if CONFIG_DISPLAY_BOARDINFO_LATE is defined.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
common/board_r.c | 1 +
|
|
common/console.c | 15 +++++++++++----
|
|
include/console.h | 12 ++++++++++++
|
|
3 files changed, 24 insertions(+), 4 deletions(-)
|
|
|
|
diff --git a/common/board_r.c b/common/board_r.c
|
|
index d69a33c4a3..20d412293a 100644
|
|
--- a/common/board_r.c
|
|
+++ b/common/board_r.c
|
|
@@ -844,6 +844,7 @@ static init_fnc_t init_sequence_r[] = {
|
|
#endif
|
|
console_init_r, /* fully init console as a device */
|
|
#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
|
|
+ console_announce_r,
|
|
show_board_info,
|
|
#endif
|
|
#ifdef CONFIG_ARCH_MISC_INIT
|
|
diff --git a/common/console.c b/common/console.c
|
|
index 1232808df5..3fcd7ce66b 100644
|
|
--- a/common/console.c
|
|
+++ b/common/console.c
|
|
@@ -202,7 +202,6 @@ static void console_putc(int file, const char c)
|
|
}
|
|
}
|
|
|
|
-#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
|
|
static void console_puts_noserial(int file, const char *s)
|
|
{
|
|
int i;
|
|
@@ -214,7 +213,6 @@ static void console_puts_noserial(int file, const char *s)
|
|
dev->puts(dev, s);
|
|
}
|
|
}
|
|
-#endif
|
|
|
|
static void console_puts(int file, const char *s)
|
|
{
|
|
@@ -248,13 +246,11 @@ static inline void console_putc(int file, const char c)
|
|
stdio_devices[file]->putc(stdio_devices[file], c);
|
|
}
|
|
|
|
-#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
|
|
static inline void console_puts_noserial(int file, const char *s)
|
|
{
|
|
if (strcmp(stdio_devices[file]->name, "serial") != 0)
|
|
stdio_devices[file]->puts(stdio_devices[file], s);
|
|
}
|
|
-#endif
|
|
|
|
static inline void console_puts(int file, const char *s)
|
|
{
|
|
@@ -699,6 +695,17 @@ static void console_update_silent(void)
|
|
#endif
|
|
}
|
|
|
|
+int console_announce_r(void)
|
|
+{
|
|
+ char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
|
|
+
|
|
+ display_options_get_banner(false, buf, sizeof(buf));
|
|
+
|
|
+ console_puts_noserial(stdout, buf);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
/* Called before relocation - use serial functions */
|
|
int console_init_f(void)
|
|
{
|
|
diff --git a/include/console.h b/include/console.h
|
|
index 3d37f6a53b..511b38e9e7 100644
|
|
--- a/include/console.h
|
|
+++ b/include/console.h
|
|
@@ -42,6 +42,18 @@ void console_record_reset(void);
|
|
*/
|
|
void console_record_reset_enable(void);
|
|
|
|
+/**
|
|
+ * console_announce_r() - print a U-Boot console on non-serial consoles
|
|
+ *
|
|
+ * When U-Boot starts up with a display it generally does not account itself
|
|
+ * on the display. The banner is emitted on the UART before relocation instead.
|
|
+ * This function prints a banner on devices which (we assume) did not receive
|
|
+ * it before relocation.
|
|
+ *
|
|
+ * @return 0 (meaning no errors)
|
|
+ */
|
|
+int console_announce_r(void);
|
|
+
|
|
/*
|
|
* CONSOLE multiplexing.
|
|
*/
|
|
--
|
|
2.13.0
|
|
|
|
From 20a987d243ea956a34409b241519c015eabead85 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Wed, 31 May 2017 17:57:15 -0600
|
|
Subject: [PATCH 14/16] power: regulator: Add more debugging and fix a missing
|
|
newline
|
|
|
|
This file does not report a few possible errors and one message is missing
|
|
a newline. Fix these.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
|
|
---
|
|
drivers/power/regulator/regulator-uclass.c | 8 +++++---
|
|
1 file changed, 5 insertions(+), 3 deletions(-)
|
|
|
|
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
|
|
index 2e0b5ed307..5a245d3c6b 100644
|
|
--- a/drivers/power/regulator/regulator-uclass.c
|
|
+++ b/drivers/power/regulator/regulator-uclass.c
|
|
@@ -146,8 +146,10 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp)
|
|
|
|
for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev;
|
|
ret = uclass_find_next_device(&dev)) {
|
|
- if (ret)
|
|
+ if (ret) {
|
|
+ debug("regulator %s, ret=%d\n", dev->name, ret);
|
|
continue;
|
|
+ }
|
|
|
|
uc_pdata = dev_get_uclass_platdata(dev);
|
|
if (!uc_pdata || strcmp(plat_name, uc_pdata->name))
|
|
@@ -156,7 +158,7 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp)
|
|
return uclass_get_device_tail(dev, 0, devp);
|
|
}
|
|
|
|
- debug("%s: can't find: %s\n", __func__, plat_name);
|
|
+ debug("%s: can't find: %s, ret=%d\n", __func__, plat_name, ret);
|
|
|
|
return -ENODEV;
|
|
}
|
|
@@ -219,7 +221,7 @@ int regulator_autoset_by_name(const char *platname, struct udevice **devp)
|
|
if (devp)
|
|
*devp = dev;
|
|
if (ret) {
|
|
- debug("Can get the regulator: %s!", platname);
|
|
+ debug("Can get the regulator: %s (err=%d)\n", platname, ret);
|
|
return ret;
|
|
}
|
|
|
|
--
|
|
2.13.0
|
|
|
|
From 42ef87e5d135c47c542546d50a57c5c3a585ac0f Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Wed, 31 May 2017 17:57:23 -0600
|
|
Subject: [PATCH 15/16] tegra: nyan-big: Add a .its file for chromium
|
|
|
|
Add a sample .its file for booting U-Boot on a nyan-big Chromebook.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
doc/chromium/nyan-big.its | 42 ++++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 42 insertions(+)
|
|
create mode 100644 doc/chromium/nyan-big.its
|
|
|
|
diff --git a/doc/chromium/nyan-big.its b/doc/chromium/nyan-big.its
|
|
new file mode 100644
|
|
index 0000000000..8dc8d73041
|
|
--- /dev/null
|
|
+++ b/doc/chromium/nyan-big.its
|
|
@@ -0,0 +1,42 @@
|
|
+/dts-v1/;
|
|
+
|
|
+/ {
|
|
+ description = "U-Boot mainline";
|
|
+ #address-cells = <1>;
|
|
+
|
|
+ images {
|
|
+ kernel@1 {
|
|
+ description = "U-Boot mainline";
|
|
+ type = "kernel_noload";
|
|
+ arch = "arm";
|
|
+ os = "linux";
|
|
+ data = /incbin/("../.././b/nyan-big/u-boot.bin");
|
|
+ compression = "none";
|
|
+ load = <0>;
|
|
+ entry = <0>;
|
|
+ hash@2 {
|
|
+ algo = "sha1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fdt@1{
|
|
+ description = "tegra124-nyan-big.dtb";
|
|
+ data = /incbin/("../.././b/nyan-big/u-boot.dtb");
|
|
+ type = "flat_dt";
|
|
+ arch = "arm";
|
|
+ compression = "none";
|
|
+ hash@1{
|
|
+ algo = "sha1";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ configurations {
|
|
+ default = "config@1";
|
|
+ config@1 {
|
|
+ description = "Boot U-Boot";
|
|
+ kernel = "kernel@1";
|
|
+ fdt = "fdt@1";
|
|
+ };
|
|
+ };
|
|
+};
|
|
--
|
|
2.13.0
|
|
|
|
From 38a4a9121f479a9ed85a351223bb6cf83b088810 Mon Sep 17 00:00:00 2001
|
|
From: Simon Glass <sjg@chromium.org>
|
|
Date: Wed, 31 May 2017 17:57:24 -0600
|
|
Subject: [PATCH 16/16] README: Add instructions for chain-loading U-Boot
|
|
|
|
Most Chromebooks support chain-loading U-Boot but instructions are
|
|
somewhat scattered. Add a README to hold this information within the
|
|
U-Boot tree. Also add the standard developer keys to simplify the
|
|
instructions, since they are small.
|
|
|
|
For now this only supports nyan-big.
|
|
|
|
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
---
|
|
doc/README.chromium | 182 +++++++++++++++++++++++++++
|
|
doc/chromium/devkeys/kernel.keyblock | Bin 0 -> 1208 bytes
|
|
doc/chromium/devkeys/kernel_data_key.vbprivk | Bin 0 -> 1199 bytes
|
|
3 files changed, 182 insertions(+)
|
|
create mode 100644 doc/README.chromium
|
|
create mode 100644 doc/chromium/devkeys/kernel.keyblock
|
|
create mode 100644 doc/chromium/devkeys/kernel_data_key.vbprivk
|
|
|
|
diff --git a/doc/README.chromium b/doc/README.chromium
|
|
new file mode 100644
|
|
index 0000000000..61e285da5e
|
|
--- /dev/null
|
|
+++ b/doc/README.chromium
|
|
@@ -0,0 +1,182 @@
|
|
+Running U-Boot from coreboot on Chromebooks
|
|
+===========================================
|
|
+
|
|
+U-Boot can be used as a secondary boot loader in a few situations such as from
|
|
+UEFI and coreboot (see README.x86). Recent Chromebooks use coreboot even on
|
|
+ARM platforms to start up the machine.
|
|
+
|
|
+This document aims to provide a guide to booting U-Boot on a Chromebook. It
|
|
+is only a starting point, and there are many guides on the interwebs. But
|
|
+placing this information in the U-Boot tree should make it easier to find for
|
|
+those who use U-Boot habitually.
|
|
+
|
|
+Most of these platforms are supported by U-Boot natively, but it is risky to
|
|
+replace the ROM unless you have a servo board and cable to restore it with.
|
|
+
|
|
+
|
|
+For all of these the standard U-Boot build instructions apply. For example on
|
|
+ARM:
|
|
+
|
|
+ sudo apt install gcc-arm-linux-gnueabi
|
|
+ mkdir b
|
|
+ make O=b/nyan_big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all
|
|
+
|
|
+You can obtain the vbutil_kernel utility here:
|
|
+
|
|
+ https://drive.google.com/open?id=0B7WYZbZ9zd-3dHlVVXo4VXE2T0U
|
|
+
|
|
+
|
|
+Snow (Samsung ARM Chromebook)
|
|
+-----------------------------
|
|
+
|
|
+See here:
|
|
+
|
|
+https://www.chromium.org/chromium-os/firmware-porting-guide/using-nv-u-boot-on-the-samsung-arm-chromebook
|
|
+
|
|
+
|
|
+Nyan-big
|
|
+--------
|
|
+
|
|
+Compiled based on information here:
|
|
+https://lists.denx.de/pipermail/u-boot/2015-March/209530.html
|
|
+https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big
|
|
+https://lists.denx.de/pipermail/u-boot/2017-May/289491.html
|
|
+https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13#copy-data-to-the-sd-card
|
|
+
|
|
+1. Patch U-Boot
|
|
+
|
|
+Open include/configs/tegra124-common.h
|
|
+
|
|
+Change:
|
|
+
|
|
+#define CONFIG_SYS_TEXT_BASE 0x80110000
|
|
+
|
|
+to:
|
|
+
|
|
+#define CONFIG_SYS_TEXT_BASE 0x81000100
|
|
+
|
|
+
|
|
+2. Build U-Boot
|
|
+
|
|
+ mkdir b
|
|
+ make -j8 O=b/nyan-big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all
|
|
+
|
|
+
|
|
+3. Select a .its file
|
|
+
|
|
+Select something from doc/chromium which matches your board, or create your
|
|
+own.
|
|
+
|
|
+Note that the device tree node is required, even though it is not actually
|
|
+used by U-Boot. This is because the Chromebook expects to pass it to the
|
|
+kernel, and crashes if it is not present.
|
|
+
|
|
+
|
|
+4. Build and sign an image
|
|
+
|
|
+ ./b/nyan-big/tools/mkimage -f doc/chromium/nyan-big.its u-boot-chromium.fit
|
|
+ echo test >dummy.txt
|
|
+ vbutil_kernel --arch arm --keyblock doc/chromium/devkeys/kernel.keyblock \
|
|
+ --signprivate doc/chromium/devkeys/kernel_data_key.vbprivk \
|
|
+ --version 1 --config dummy.txt --vmlinuz u-boot-chromium.fit \
|
|
+ --bootloader dummy.txt --pack u-boot.kpart
|
|
+
|
|
+
|
|
+5. Prepare an SD card
|
|
+
|
|
+ DISK=/dev/sdc # Replace with your actual SD card device
|
|
+ sudo cgpt create $DISK
|
|
+ sudo cgpt add -b 34 -s 32768 -P 1 -S 1 -t kernel $DISK
|
|
+ sudo cgpt add -b 32802 -s 2000000 -t rootfs $DISK
|
|
+ sudo gdisk $DISK # Enter command 'w' to write a protective MBR to the disk
|
|
+
|
|
+
|
|
+6. Write U-Boot to the SD card
|
|
+
|
|
+ sudo dd if=u-boot.kpart of=/dev/sdc1; sync
|
|
+
|
|
+
|
|
+7. Start it up
|
|
+
|
|
+Reboot the device in dev mode. Make sure that you have USB booting enabled. To
|
|
+do this, login as root (via Ctrl-Alt-forward_arrow) and type
|
|
+'enable_dev_usb_boot'. You only need to do this once.
|
|
+
|
|
+Reboot the device with the SD card inserted. Press Clrl-U at the developer
|
|
+mode screen. It should show something like the following on the display:
|
|
+
|
|
+ U-Boot 2017.07-00637-g242eb42-dirty (May 22 2017 - 06:14:21 -0600)
|
|
+
|
|
+ Model: Acer Chromebook 13 CB5-311
|
|
+ Board: Google/NVIDIA Nyan-big, ID: 1
|
|
+
|
|
+ Net: No ethernet found.
|
|
+ Hit any key to stop autoboot: 0
|
|
+ Tegra124 (Nyan-big) #
|
|
+
|
|
+
|
|
+8. Known problems
|
|
+
|
|
+On the serial console the word MMC is chopped at the start of the line:
|
|
+
|
|
+C: sdhci@700b0000: 2, sdhci@700b0400: 1, sdhci@700b0600: 0
|
|
+
|
|
+This is likely due to some problem with change-over of the serial driver
|
|
+during relocation (or perhaps updating the clock setup in board_init()).
|
|
+
|
|
+
|
|
+9. Notes
|
|
+
|
|
+To check that you copied the u-boot.its file correctly, use these commands.
|
|
+You should see that the data at 0x100 in u-boot-chromium.fit is the first few
|
|
+bytes of U-Boot:
|
|
+
|
|
+ hd u-boot-chromium.fit |head -20
|
|
+ ...
|
|
+ 00000100 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
|
|
+
|
|
+ hd b/nyan-big/u-boot.bin |head
|
|
+ 00000000 b8 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
|
|
+
|
|
+
|
|
+The 'data' property of the FIT is set up to start at offset 0x100 bytes into
|
|
+the file. The change to CONFIG_SYS_TEXT_BASE is also an offset of 0x100 bytes
|
|
+from the load address. If this changes, you either need to modify U-Boot to be
|
|
+fully relocatable, or expect it to hang.
|
|
+
|
|
+
|
|
+Other notes
|
|
+===========
|
|
+
|
|
+flashrom
|
|
+--------
|
|
+
|
|
+ Used to make a backup of your firmware, or to replace it.
|
|
+
|
|
+ See: https://www.chromium.org/chromium-os/packages/cros-flashrom
|
|
+
|
|
+
|
|
+coreboot
|
|
+--------
|
|
+
|
|
+Coreboot itself is not designed to actually boot an OS. Instead, a program
|
|
+called Depthcharge is used. This originally came out of U-Boot and was then
|
|
+heavily hacked and modified such that is is almost unrecognisable. It does
|
|
+include a very small part of the U-Boot command-line interface but is not
|
|
+usable as a general-purpose boot loader.
|
|
+
|
|
+In addition, it has a very unusual design in that it does not do device init
|
|
+itself, but instead relies on coreboot. This is similar to (in U-Boot) having
|
|
+a SPI driver with an empty probe() method, relying on whatever was set up
|
|
+beforehand. It can be quite hard to figure out between these two code bases
|
|
+what settings are actually used. When chain-loading into U-Boot we must be
|
|
+careful to reinit anything that U-Boot expects. If not, some peripherals (or
|
|
+the whole machine) may not work. This makes the process of chainloading more
|
|
+complicated than it could be on some platforms.
|
|
+
|
|
+Finally, it supports only a subset of the U-Boot's FIT format. In particular
|
|
+it uses a fixed address to load the FIT and does not support load/exec
|
|
+addresses. This means that U-Boot must be able to boot from whatever
|
|
+address Depthcharge happens to use (it is the CONFIG_KERNEL_START setting
|
|
+in Depthcharge). In practice this means that the data in the kernel@1 FIT node
|
|
+(see above) must start at the same address as U-Boot's CONFIG_SYS_TEXT_BASE.
|
|
diff --git a/doc/chromium/devkeys/kernel.keyblock b/doc/chromium/devkeys/kernel.keyblock
|
|
new file mode 100644
|
|
index 0000000000000000000000000000000000000000..9740be4e60070658d01e96c13acba8e726f68a59
|
|
GIT binary patch
|
|
literal 1208
|
|
zcmZ?v2=e!J^$%uZU|?Vb;vFnN0tgm>1V8{vS3qeGDD422WMF`avqSj`P?`g(4r(0O
|
|
zY><=#5T9mpaFo?;<IfE~b7uK$=~H)<jvTToS}LUYuR?YXb1Ki2UAED2GsL>quTPJ1
|
|
z>(Ke2mAdzM<e7q(jDEE}&U!MrMWX936wcpb_1vZDVsrQ0oRpdCZ+D%!c&&Nal2<Dm
|
|
zW#>yr_58T4rnsp(c+!WgqdkJV>YPu@g)hvz`magDHh1sz4KIGncd$uw9qpf%>5=KE
|
|
z6?A>OaYc9j^yRg8E@<CuOh0MAa*G@{N60b8V+zlXamI5UWn#^Cm?o(3bWw+S*5zBb
|
|
zZk5SAvDNvP+BRd+3eQ?KR}mJ0#}?jcb7FK}++@3Qn01OwwQ^^htkG`e3ED;1Cj<ux
|
|
z2wgbzsHm~PW}~{(oBi4$*G?zC+Hz&Zz0db;FN)u5>-@4%BktA~cgfj@&UwB{zU3s-
|
|
zDziH0`k}uj(pLo+xood$O=RA6CFP-K`=n=gET_!b^*&-ApV^G-mwZGDr&O$Od#?ZT
|
|
zr-JXlTi5M74@R!rn=pI&k~D_h)fYTl^Q#$E4tqR0o;YL9)5+~DoK}-U<hM3xiaxFX
|
|
zcW3?Ohe=1a-PV`l_#DD!buO;6@V<3SPj>T49@c>B7EXz@mWOo-*Y50>Src>Tna{ih
|
|
zUXcd>Cr*%4)C`ze_E$eDJ&PgRLH+q&@n`Y#o@75@omYE$!b_Vul_%YQMC`HOxb%Jc
|
|
z2c?At#%3F0-oEm?r@|9`!*}1BEFr^Xaq%qMA{JiMTx>iiWn-W9ul1%=s+N2`Juh9l
|
|
z*YuP?X78(tL*J4Q2!8yQR-iZS!=7q6F|~V->koX%vEdGS#D1@!dwt7PX}77Ftdm}u
|
|
zEj<-*+w+9WyBbdi6V}gc@-k;ClBDN8^0#A|w(G+2MOLf6A6|DL`_zfZ2@hPWy%YAY
|
|
z6IH#iNPlXUp1F!>CZAQVgW|W6m}T=HFek7?78ERS`*NSlTV!=R&#IK!O{Ww$6#eQp
|
|
z|C(@pyI)b9uyS!r&c)uMMWWq-785ci-0V&@NW2}`5OMeL2TkKUmXr3YKRe#^?bUh3
|
|
zOA9QR!h^ovWuN(&^ZMF(a?d}<6)iY6*RgF{Q;C~A>m^oIP4%>gt7F){ta*On$FsO@
|
|
z$<RYH`<Cma@n|J(nBh2?HDto7eWGg7<ux0AaAa)Tapmrf75;a>O@6wtL%NE!@#qW_
|
|
z*^cDU^|Kb9_Fmt%+4a_vElUNe0<xao%I`lQJ9XnkkKn^k<@s1kR~^4$b|E*w<I1zW
|
|
z7j&nK>uz>iEy?#}&ELtZd3@IHkC0xac9!?n`qQsBNXEFy&)%>@C}+9fj^*+~*+2Gq
|
|
zuVmTs)9lR6s}tAMy%auBf9m?3eJeLy(-7CccAqcXL-1PQ@!a-r9NTj;zhBb`s4H1J
|
|
zEsN(=_QsF*7RM`p)p8N!U;JIgOxpNa-A%rw-3xYfx4ygZB-8oW&v^BvCljsv)+d!a
|
|
zZBvhbJFRW=dm}?<z3TPRk4l@0)>_9-Iw-p8w<7z?RYx9OpV^#KWSMWOF!#ZYAGeEC
|
|
Tp7v_~RjJ<N@pAW}mg74Ct|TeM
|
|
|
|
literal 0
|
|
HcmV?d00001
|
|
|
|
diff --git a/doc/chromium/devkeys/kernel_data_key.vbprivk b/doc/chromium/devkeys/kernel_data_key.vbprivk
|
|
new file mode 100644
|
|
index 0000000000000000000000000000000000000000..8d392fb294c15edb09cbf1bf775a1d87d0d2bc2d
|
|
GIT binary patch
|
|
literal 1199
|
|
zcmV;g1W@|~000000000mf&`-i0RRGm0RaHZ)>JFM>_R88JaB<>;=<4p5K>c+*K#Y6
|
|
zBfBykhKVD49Fzsa)CSq;EL@ysOE}{Y1QbOkeMzXIn1*HkEIs5LcG}w7(`q+}qU9hF
|
|
zmOyI-0>uhn3C89i#sS7u2n!yxsXxhQf!Qn2+<m8)Z;N;{x7SiCL1{>7mXE~>8wQ9U
|
|
z`{=Njy=^@xg8tQRp;sQuLw>pujKym3l2d!KAtu}Sj9MF?9f7Ipq^5(`(aeh5ubE_Q
|
|
zor{Cff<)&!w4ZU%uN87_94<qQeNF-CaLif9y=5x!EQm&0XRoh{7MNaJJ-U<(WdocY
|
|
zc>W<0rE)sL#3J0v8=I%h%u{U-hAkZe0|5X50)hbmO}OfvNAK|kt9k7>9<xF(4n#EX
|
|
z@-c)m0wV3S-8VQvR3`v+_C|SHOF`!fC!-Y%*F}cu8x;7e8C_`^sKNWwXWJF_4=g{r
|
|
z?-`Yz6}F+*Y_PJc60_>4Lgd{xUqUtGK4q?vz$)#)+(E{Z$(32Fx}>GBiMA<A*dFz;
|
|
z-ujUdRo0#1r=0Tioqv`|daLQ049gH)XYd{KGlZ^g<h!R=n3*f{9jojCqAolTT>t3I
|
|
zP(>jx1Zmv@TM*V%HcWF29>M>tU|qZugy^KbX3EO1Rf_nB7n8qcq?hSOfdl$XGWP6x
|
|
z1G_Cdo9f(bVSfe4El`Q+5IsBsuw6bSanhmT0)c@5_B?+TV+0D+Xz1BXf4s`IgaL68
|
|
zGfm+N=%<y;BUu@>f~v0MkTaDa8vXB%Ho;fkl--$c6bz0q;OAsBryc#7+*nCYR)Rz7
|
|
z+4syE^$9pk_J@zAK$g*gV!KIGX;$A#h5d3gAy%V%+E65j#tQ?K4dMeTJX+mz=LZ3O
|
|
z-8g|60)c@5)9Z3S_L~EYtJy(EzHA47*URp|MH3!VHPYm26Y1FF^eA5I*wTk!+@~Sf
|
|
zGtSCjP#cH8afpy{Z{FK89Xzow8$q~Lp<Jl4a~nBnT%lK+F3k;bLf<OWPf^@8Toi^D
|
|
zxFU>mH+pQh{s9}P#qs~z)MHqI;cBnKJ-Zh_Ecv*l0)c@5(H?83R3aF-a42AMm={y%
|
|
zcqM5{{82@)C<;4M)hSelEM%OAj921p6Tn$?W7sRP;-{D?7t`71bo$Q3cSk21MqtcP
|
|
z^>auL>GEQ#`ZG*dK!3btt1#-=foma1?~75hPP_sGchtt7=C^HcqY<-)M~n=(5AE}4
|
|
z{b`%Pvf<0|0)c==#@pe5`$V)hu-KfPe0K!9jo_~U;^DpMyatVD88X)IG>m^ZYZuGG
|
|
z<`3tkW$Q6NkMc%-B%T>W!>MuT(cD{KKNHb~lI+B+tm^;8a2--M&qXc{r+OwB*S<6q
|
|
z492_9!@4BE;-YNO=#A7+NCK;qLz>IQ{adyJ=lENpDaHW;fq)Jeya1zt+QP{D3cY`~
|
|
zf1wzENw_kDOK~+>QG4!=PSQfCY=T$!H1>j7>2-RK3XMh{p?9H7vz~^N7~ekofzZ5V
|
|
zqO*YTk8>}z#J~frB>GPU;}$7=|6|n(3cc55I<;QsBm6xG>SDs<O1p+y#go^(v`o*>
|
|
Nc%M>kp-Cb4AVU2jMyUV*
|
|
|
|
literal 0
|
|
HcmV?d00001
|
|
|
|
--
|
|
2.13.0
|
|
|