37df227bc0
Fix booting from MMC for Rockchip 3399 (rhbz #2014182) Enable new rk3399 devices (Leez, NanoPi-M4B, NanoPi-4S, NanoPi-T4) (rhbz #2009126)
153 lines
4.6 KiB
Diff
153 lines
4.6 KiB
Diff
From e3e6018d0b67fbab3d05053688e53f5baac63bc3 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Thu, 14 Oct 2021 16:01:56 +0100
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Subject: [PATCH 1/2] Revert "mmc: rockchip_sdhci: Add support for RK3568"
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This reverts commit a63a57e59d864a1ca2b0acb5fadc5c3579c3e79c.
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---
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drivers/mmc/rockchip_sdhci.c | 109 -----------------------------------
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1 file changed, 109 deletions(-)
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diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
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index 1ac00587d4..eff134c8f5 100644
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--- a/drivers/mmc/rockchip_sdhci.c
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+++ b/drivers/mmc/rockchip_sdhci.c
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@@ -42,34 +42,6 @@
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((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
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PHYCTRL_DLLRDY_DONE)
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-/* Rockchip specific Registers */
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-#define DWCMSHC_EMMC_DLL_CTRL 0x800
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-#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
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-#define DWCMSHC_EMMC_DLL_RXCLK 0x804
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-#define DWCMSHC_EMMC_DLL_TXCLK 0x808
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-#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
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-#define DWCMSHC_EMMC_DLL_STATUS0 0x840
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-#define DWCMSHC_EMMC_DLL_STATUS1 0x844
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-#define DWCMSHC_EMMC_DLL_START BIT(0)
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-#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
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-#define DWCMSHC_EMMC_DLL_START_POINT 16
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-#define DWCMSHC_EMMC_DLL_START_DEFAULT 5
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-#define DWCMSHC_EMMC_DLL_INC_VALUE 2
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-#define DWCMSHC_EMMC_DLL_INC 8
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-#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
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-#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
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-#define DLL_STRBIN_TAPNUM_DEFAULT 0x3
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-#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
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-#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
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-#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
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-#define DLL_RXCLK_NO_INVERTER 1
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-#define DLL_RXCLK_INVERTER 0
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-#define DWCMSHC_ENHANCED_STROBE BIT(8)
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-#define DLL_LOCK_WO_TMOUT(x) \
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- ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
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- (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
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-#define ROCKCHIP_MAX_CLKS 3
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-
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struct rockchip_sdhc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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@@ -195,77 +167,6 @@ static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
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return 0;
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}
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-static int rk3568_emmc_phy_init(struct udevice *dev)
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-{
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- struct rockchip_sdhc *prv = dev_get_priv(dev);
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- struct sdhci_host *host = &prv->host;
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- u32 extra;
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-
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- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
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- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
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-
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- return 0;
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-}
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-
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-static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
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-{
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- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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- int val, ret;
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- u32 extra;
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-
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- if (clock > host->max_clk)
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- clock = host->max_clk;
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- if (clock)
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- clk_set_rate(&priv->emmc_clk, clock);
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-
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- sdhci_set_clock(host->mmc, clock);
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-
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- if (clock >= 100 * MHz) {
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- /* reset DLL */
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- sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
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- udelay(1);
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- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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-
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- /* Init DLL settings */
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- extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
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- DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
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- DWCMSHC_EMMC_DLL_START;
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- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
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-
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- ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
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- val, DLL_LOCK_WO_TMOUT(val), 1, 500);
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- if (ret)
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- return ret;
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-
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- extra = DWCMSHC_EMMC_DLL_DLYENA |
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- DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
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- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
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-
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- extra = DWCMSHC_EMMC_DLL_DLYENA |
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- DLL_TXCLK_TAPNUM_DEFAULT |
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- DLL_TXCLK_TAPNUM_FROM_SW;
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- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
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-
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- extra = DWCMSHC_EMMC_DLL_DLYENA |
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- DLL_STRBIN_TAPNUM_DEFAULT;
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- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
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- } else {
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- /* reset the clock phase when the frequency is lower than 100MHz */
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- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
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- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
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- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
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- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
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- }
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-
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- return 0;
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-}
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-
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-static int rk3568_emmc_get_phy(struct udevice *dev)
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-{
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- return 0;
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-}
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-
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static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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@@ -438,21 +339,11 @@ static const struct sdhci_data rk3399_data = {
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.emmc_phy_init = rk3399_emmc_phy_init,
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};
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-static const struct sdhci_data rk3568_data = {
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- .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
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- .get_phy = rk3568_emmc_get_phy,
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- .emmc_phy_init = rk3568_emmc_phy_init,
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-};
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-
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static const struct udevice_id sdhci_ids[] = {
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{
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.compatible = "arasan,sdhci-5.1",
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.data = (ulong)&rk3399_data,
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},
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- {
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- .compatible = "rockchip,rk3568-dwcmshc",
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- .data = (ulong)&rk3568_data,
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- },
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{ }
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};
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--
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2.33.0
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