2527 lines
111 KiB
Diff
2527 lines
111 KiB
Diff
From patchwork Tue May 12 18:47:08 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288721
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=d38K5udu;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de
|
|
[IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest
|
|
SHA256) (No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6Hv66Ygz9sRR
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:47:55 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id B84F981CA7;
|
|
Tue, 12 May 2020 20:47:46 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="d38K5udu";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id 58E8981CB4; Tue, 12 May 2020 20:47:46 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com
|
|
[210.118.77.11])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id 5033481CA7
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:47:43 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p2.samsung.com (unknown [182.198.249.207])
|
|
by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184742euoutp01bc8b3eb5b03aea7061c9771d94376063~OXFqTZrdZ0824908249euoutp01M
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:47:42 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com
|
|
20200512184742euoutp01bc8b3eb5b03aea7061c9771d94376063~OXFqTZrdZ0824908249euoutp01M
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309262;
|
|
bh=y/xHx6cn6ZNuvX3V5jxpugf8Q65fZIBo5wp4jEitdVo=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=d38K5uduUnUgAuBY2HpLVidScZmwLS83XuAEP71VwqJPtHkIEcrtqnNuN+x7Vo5LB
|
|
xI47QIftGzVsub55jILxMD5WJglh2JRL6h/sha0zJZGbRvnGclE1yePigHBSvHJq8e
|
|
NKVp6Rgvvlb/0F3rQzneLiaVnOQ04AM1cU+Q0O5U=
|
|
Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184741eucas1p2f963249ca616e99f379cb8519a45c7df~OXFpSf8vj0944309443eucas1p2h;
|
|
Tue, 12 May 2020 18:47:41 +0000 (GMT)
|
|
Received: from eucas1p1.samsung.com ( [182.198.249.206]) by
|
|
eusmges3new.samsung.com (EUCPMTA) with SMTP id 06.03.60698.D4FEABE5; Tue, 12
|
|
May 2020 19:47:41 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9~OXFopWAVc0733307333eucas1p2p;
|
|
Tue, 12 May 2020 18:47:40 +0000 (GMT)
|
|
Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184740eusmtrp285c7f01d30cd705bf6708beea010fb5e~OXFootnX41654116541eusmtrp2e;
|
|
Tue, 12 May 2020 18:47:40 +0000 (GMT)
|
|
X-AuditID: cbfec7f5-a0fff7000001ed1a-48-5ebaef4d163d
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms1.samsung.com (EUCPMTA) with SMTP id 87.DA.08375.C4FEABE5; Tue, 12
|
|
May 2020 19:47:40 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184740eusmtip1218b8e5fecda20fd55cc193294a6f3b1~OXFoEyWsp2574925749eusmtip16;
|
|
Tue, 12 May 2020 18:47:40 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 1/9] usb: xhci: Add missing cache flush in the scratchpad
|
|
array initialization
|
|
Date: Tue, 12 May 2020 20:47:08 +0200
|
|
Message-Id: <20200512184716.2869-2-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsWy7djPc7q+73fFGWxeLm2xccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGXc
|
|
XfWasWAKZ8XHpQeYGhjPsncxcnJICJhIrF/3BMjm4hASWMEo8fr8L1YI5wujxJmdXcwQzmdG
|
|
idPv17PAtNxZtJQRIrGcUWLemw8scC33Vj8EG8wmYCjRe7SPEcQWEQiQuPZzGlgHs8BRRok1
|
|
+/+AjRIWSJbY+GYJmM0ioCpxsucAmM0rYCXx7u4iVoh18hKrNxxgBrE5Bawlrm8+BnaThMAq
|
|
dokV/6ZAveEiMXnjaqgGYYlXx7dAxWUk/u+czwTR0Mwo0bP7NjuEM4FR4v7xBYwQVdYSd879
|
|
Yuti5AC6T1Ni/S59EFNCwFHi83MtCJNP4sZbQZBiZiBz0rbpzBBhXomONiGIGSoSv1dNZ4Kw
|
|
pSS6n/yHhpaHxIFJu8DOFxLoY5SY9NFzAqP8LIRVCxgZVzGKp5YW56anFhvnpZbrFSfmFpfm
|
|
pesl5+duYgSmmtP/jn/dwbjvT9IhRgEORiUe3oj6XXFCrIllxZW5hxglOJiVRHhbMnfGCfGm
|
|
JFZWpRblxxeV5qQWH2KU5mBREuc1XvQyVkggPbEkNTs1tSC1CCbLxMEp1cAY8FeRl+/HltTN
|
|
X4Xs903RVHy5e6dgqpeg0jm+4OVBkrPvpUVJPnj+KVdkzo41t/PuMjReEPlxUCtyWmyHz103
|
|
rgXPZq0ykbWOfJ3YefagS9XPQu/PB+O5tq6w9/7zm4Vf6+bV1z8qDodnyLT/WPJqT6T6+32H
|
|
jgl/27XgeAnrlllibgaZdotvKrEUZyQaajEXFScCAAKlHx8xAwAA
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7o+73fFGUxZr2+xccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF
|
|
G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GXcXfWasWAKZ8XHpQeYGhjPsncx
|
|
cnJICJhI3Fm0lLGLkYtDSGApo8SCbWtZuhg5gBJSEvNblCBqhCX+XOtig6j5xCixZOleFpAE
|
|
m4ChRO/RPkYQW0QgROLF0StMIEXMAmcZJRZ1fmAFSQgLJErMbDgGZrMIqEqc7DkA1swrYCXx
|
|
7u4iVogN8hKrNxxgBrE5Bawlrm8+BmYLAdXs+faObQIj3wJGhlWMIqmlxbnpucWGesWJucWl
|
|
eel6yfm5mxiBgb/t2M/NOxgvbQw+xCjAwajEw8tQuytOiDWxrLgy9xCjBAezkghvS+bOOCHe
|
|
lMTKqtSi/Pii0pzU4kOMpkBHTWSWEk3OB0ZlXkm8oamhuYWlobmxubGZhZI4b4fAwRghgfTE
|
|
ktTs1NSC1CKYPiYOTqkGRvHA5utdDK+71Gc8yncU/Jl1s8GwlfnWtf/fvVcf2j1n1dGNJtMn
|
|
+bzXEb/JdkYl/OLZA3Vvo7aKLFyzg7Gsd9N+h4PpR6bHn7zJ79VRWnHmnV1WVtDq6BmPbh3d
|
|
8qTxqqDqXif96Ra5p80yGxK5+NgP7Gd22F52neeB/7I+A4//v1Y946i/MFmJpTgj0VCLuag4
|
|
EQDJGyeQkgIAAA==
|
|
X-CMS-MailID: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9@eucas1p2.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
In current code there is no cache flush after initializing the scratchpad
|
|
buffer array with the scratchpad buffer pointers. This leads to a failure
|
|
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
|
|
controller + VL805 USB hub) - the very first TRB transfer on the command
|
|
ring fails and there is a timeout while waiting for the command completion
|
|
event. After adding the missing cache flush everything seems to be working
|
|
as expected.
|
|
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
|
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
---
|
|
Changes since v1:
|
|
- none.
|
|
---
|
|
drivers/usb/host/xhci-mem.c | 3 +++
|
|
1 file changed, 3 insertions(+)
|
|
|
|
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
|
|
index 93450ee..729bdc3 100644
|
|
--- a/drivers/usb/host/xhci-mem.c
|
|
+++ b/drivers/usb/host/xhci-mem.c
|
|
@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
|
|
scratchpad->sp_array[i] = cpu_to_le64(ptr);
|
|
}
|
|
|
|
+ xhci_flush_cache((uintptr_t)scratchpad->sp_array,
|
|
+ sizeof(u64) * num_sp);
|
|
+
|
|
return 0;
|
|
|
|
fail_sp3:
|
|
|
|
From patchwork Tue May 12 18:47:09 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288726
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=grr5hJg0;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de
|
|
[IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6J52FSkz9sSc
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:48:05 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 031D381CCA;
|
|
Tue, 12 May 2020 20:47:52 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="grr5hJg0";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id DBE4481CCA; Tue, 12 May 2020 20:47:49 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com
|
|
[210.118.77.11])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id 3D53381CC5
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:47:47 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p2.samsung.com (unknown [182.198.249.207])
|
|
by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184746euoutp01fb38409a07247ba29f423e8e26c681a3~OXFtquXqn0815408154euoutp01S
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:47:46 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com
|
|
20200512184746euoutp01fb38409a07247ba29f423e8e26c681a3~OXFtquXqn0815408154euoutp01S
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309266;
|
|
bh=mpc5rYw/U19wNz9z3l9qIGYqOM/GqAOeD9khN0UIZwU=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=grr5hJg01HyaYOSo5sRsqNi8H29+t1SJtvzpcW0TcS7Uq3xNGmFHYWcWw2hlEFBXm
|
|
SQcD5H70xlOq1k6aVxDV3EJK128Qww1iZyma0H7nEfCs1WuOaohM/qnzdBhfwcwftI
|
|
AmLAlKxzDpQym+Hg21E2PBd9E56u9ZhxeKuVbjNs=
|
|
Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184745eucas1p29454eee0ca9ecc030620e98c3cb0577f~OXFspLApW2836228362eucas1p2B;
|
|
Tue, 12 May 2020 18:47:45 +0000 (GMT)
|
|
Received: from eucas1p2.samsung.com ( [182.198.249.207]) by
|
|
eusmges3new.samsung.com (EUCPMTA) with SMTP id C6.03.60698.05FEABE5; Tue, 12
|
|
May 2020 19:47:44 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58~OXFrcGgkD0735407354eucas1p2X;
|
|
Tue, 12 May 2020 18:47:43 +0000 (GMT)
|
|
Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184743eusmtrp22630032f69ad78af217c4cc4e810fb3e~OXFrbdvJf1654916549eusmtrp2d;
|
|
Tue, 12 May 2020 18:47:43 +0000 (GMT)
|
|
X-AuditID: cbfec7f5-a0fff7000001ed1a-4c-5ebaef500edc
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms1.samsung.com (EUCPMTA) with SMTP id 48.DA.08375.F4FEABE5; Tue, 12
|
|
May 2020 19:47:43 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184743eusmtip16a33a390496025d0cd045c1a3826c2c0~OXFqzC1Wy3146231462eusmtip1f;
|
|
Tue, 12 May 2020 18:47:43 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>, Sergey Temerkhanov
|
|
<s.temerkhanov@gmail.com>
|
|
Subject: [PATCH v3 2/9] usb: xhci: Use only 32-bit accesses in
|
|
xhci_writeq/xhci_readq
|
|
Date: Tue, 12 May 2020 20:47:09 +0200
|
|
Message-Id: <20200512184716.2869-3-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRju2845O5qL05R8M8EYRRhecdQhLylJnh8ikpJSNFt5UPHappb1
|
|
Q0NZzjuJGou8NGyhpKlrOW95NxLTJE1KUcMyRQu1RTPRnEfr3/M+l/d9+PhIvqgatyNjEpJZ
|
|
eYIsTkxYYvp+07Bz8I8WqVtrhxfd8KAep0vyIuj2pUKCnlhX4vSz3ikBvaS8i+jK4jmc1qu1
|
|
BN2zdA+nq9UdAvqXTo/o5XaVwNeKUU8PEczDjHcYU65+jTEG9ZSAGZpsRkyBrgYx9boxjGka
|
|
vBNMXrL0imTjYlJZuavPVctoQ3EVnrRG3VrJ1hAZaFaYgyxIoCSge1mO5yBLUkQ9RfBdtUhw
|
|
w08Ekwuju8MaAlONUrAXaVQqESdoETR8LOH9i+hqX/DMLoJyh/y+AmTGNlQwjJtKdxJ8yojg
|
|
Te4IZhasqTBQjc4SZoxRx0G7odkJC6kz8HWwA+POOUDt806+GVtQnvChqZ9vXgRUnQDaCvMJ
|
|
zuQPBqMK57A1LA7odrvaw5ahgscFMhHktX4ScEMRgumBSsS5PGHy7fr2JnK7nyPUt7hytB9U
|
|
/NbzzDRQB2Bi+aCZ5m/D+/oyPkcLIVsp4tzH4E9NGY/DdpA7t7Xbn4G1vjoB90IFCDK7THgR
|
|
clD/P1aJUA2yZVMU8VGswiOBvemikMUrUhKiXK4nxjei7c8zuDlgbEYdG9e6EUUisZUwPL1F
|
|
KsJlqYq0+G4EJF9sI8yKMUhFwkhZ2m1WnhghT4ljFd3oCImJbYUejxeuiKgoWTIby7JJrHxP
|
|
5ZEWdhno9GbOeQf7Vl+Jk8nnRLVIMhTnGHaoR+Kq6kppqzi7fMF7ZSKwp9d/3njKu0UyrZUG
|
|
Tc84TXaFfjOi1dHQi/OJY5rxG6VPqoZfHVWpIoICwvcHhkCAW2Rr+8RI+rBGmV13+Zzmi/Oj
|
|
GTj8WYhQFa/Or3a1d19tQ2xI5/ssqU2BGFNEy9xP8uUK2V8p3t8YOAMAAA==
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42I5/e/4XV3/97viDHb26llsnLGe1WJqT7zF
|
|
3jf9bBY3frWxWqw9cpfd4k1bI6PFgslPWC22zVrOZnH4TTurxdJZ+9gtvm3Zxmjxdm8nuwOP
|
|
x6z7Z9k8ZjdcZPGYN+sEi8fOWXfZPc7e2cHo0bdlFaPH+i1XWTw2n64O4IjSsynKLy1JVcjI
|
|
Ly6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQy9g5eSFrwWeBio8di9ka
|
|
GB/ydjFyckgImEhsamtj7GLk4hASWMoosWrtQiCHAyghJTG/RQmiRljiz7UuNoiaT4wSjVff
|
|
soAk2AQMJXqP9jGC2CICIRIvjl5hAiliFvjLKDGp9QkrSEJYIFTi7tP5YDaLgKrE8j+LmUBs
|
|
XgEriWen97FAbJCXWL3hADOIzSlgLXF98zEwWwioZs+3d2wTGPkWMDKsYhRJLS3OTc8tNtQr
|
|
TswtLs1L10vOz93ECIyBbcd+bt7BeGlj8CFGAQ5GJR5ehtpdcUKsiWXFlbmHGCU4mJVEeFsy
|
|
d8YJ8aYkVlalFuXHF5XmpBYfYjQFOmois5Rocj4wPvNK4g1NDc0tLA3Njc2NzSyUxHk7BA7G
|
|
CAmkJ5akZqemFqQWwfQxcXBKNTB6nbS75KLLcXaSEefxVQuf7fj8f9bj7/+W83UdTBPtbEo9
|
|
LXT2+/znb9WWx/X7dl++fTu/uqBaPixV8t3/v6YG/SXmdQ/NeHqaT3MnmTe3rbNZkZFrr1IY
|
|
y//PRYDVYEtvSsrjr8UK0VdCpk42XPb0vaNeRErYDM4ZZm4ajV3LF4k56rzcN0uJpTgj0VCL
|
|
uag4EQCTL19flwIAAA==
|
|
X-CMS-MailID: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58@eucas1p2.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
There might be hardware configurations where 64-bit data accesses
|
|
to XHCI registers are not supported properly. This patch removes
|
|
the readq/writeq so always two 32-bit accesses are used to read/write
|
|
64-bit XHCI registers, similarly as it is done in Linux kernel.
|
|
|
|
This patch fixes operation of the XHCI controller on RPI4 Broadcom
|
|
BCM2711 SoC based board, where the VL805 USB XHCI controller is
|
|
connected to the PCIe Root Complex, which is attached to the system
|
|
through the SCB bridge.
|
|
|
|
Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
|
|
the 64-bit wide register accesses initiated by the CPU are not properly
|
|
translated to a sequence of 32-bit PCIe accesses.
|
|
xhci_readq(), for example, always returns same value in upper and lower
|
|
32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.
|
|
|
|
Cc: Sergey Temerkhanov <s.temerkhanov@gmail.com>
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
|
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
---
|
|
Changes since v1:
|
|
- none.
|
|
Changes since RFC:
|
|
- dropped Kconfig option, switched to not using readq/writeq
|
|
unconditionally.
|
|
---
|
|
include/usb/xhci.h | 8 --------
|
|
1 file changed, 8 deletions(-)
|
|
|
|
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
|
|
index 6017504..c16106a 100644
|
|
--- a/include/usb/xhci.h
|
|
+++ b/include/usb/xhci.h
|
|
@@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
|
|
*/
|
|
static inline u64 xhci_readq(__le64 volatile *regs)
|
|
{
|
|
-#if BITS_PER_LONG == 64
|
|
- return readq(regs);
|
|
-#else
|
|
__u32 *ptr = (__u32 *)regs;
|
|
u64 val_lo = readl(ptr);
|
|
u64 val_hi = readl(ptr + 1);
|
|
return val_lo + (val_hi << 32);
|
|
-#endif
|
|
}
|
|
|
|
static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
|
|
{
|
|
-#if BITS_PER_LONG == 64
|
|
- writeq(val, regs);
|
|
-#else
|
|
__u32 *ptr = (__u32 *)regs;
|
|
u32 val_lo = lower_32_bits(val);
|
|
/* FIXME */
|
|
u32 val_hi = upper_32_bits(val);
|
|
writel(val_lo, ptr);
|
|
writel(val_hi, ptr + 1);
|
|
-#endif
|
|
}
|
|
|
|
int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
|
|
|
|
From patchwork Tue May 12 18:47:10 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288728
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=MQb96qeW;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de
|
|
[IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6JZ0HY9z9sRR
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:48:29 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 97A5E81CE6;
|
|
Tue, 12 May 2020 20:47:55 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="MQb96qeW";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id 91CEA81CD5; Tue, 12 May 2020 20:47:52 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com
|
|
[210.118.77.11])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id EC86281C9C
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:47:49 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p1.samsung.com (unknown [182.198.249.206])
|
|
by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184749euoutp01f49ee1d587539ddc7a686993e968522f~OXFw3ZAYX0815408154euoutp01T
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:47:49 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com
|
|
20200512184749euoutp01f49ee1d587539ddc7a686993e968522f~OXFw3ZAYX0815408154euoutp01T
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309269;
|
|
bh=o2n59jAOXed94iksPXrzyyjRiAB6FlEj8rUQ47ogyyk=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=MQb96qeW8BGeMLYvoFF8R5AK1VxRLBF9DKrHdA78h1FGD56P/N3T9UWKZFfPK+zeT
|
|
0f2oSHQ2MVqRnuwpxzTWSHmbVuBZJE89UYjb1wU+vXivuiwfqiftxIkx0H74WHDljA
|
|
QPw23KgCLp0pZQt4sPsJz2xniqkbi21z32ANnwxM=
|
|
Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by
|
|
eucas1p1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184748eucas1p11ef796b4c399aa64b9557a31eeeb908b~OXFwGTfiE2309523095eucas1p1z;
|
|
Tue, 12 May 2020 18:47:48 +0000 (GMT)
|
|
Received: from eucas1p1.samsung.com ( [182.198.249.206]) by
|
|
eusmges2new.samsung.com (EUCPMTA) with SMTP id 52.AA.60679.45FEABE5; Tue, 12
|
|
May 2020 19:47:48 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5~OXFvEnnod0735407354eucas1p2Z;
|
|
Tue, 12 May 2020 18:47:47 +0000 (GMT)
|
|
Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184747eusmtrp220606fb120fb3b6d130b61b70b1a907f~OXFvD_isr1654116541eusmtrp2g;
|
|
Tue, 12 May 2020 18:47:47 +0000 (GMT)
|
|
X-AuditID: cbfec7f4-0cbff7000001ed07-c4-5ebaef540342
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms1.samsung.com (EUCPMTA) with SMTP id 89.DA.08375.35FEABE5; Tue, 12
|
|
May 2020 19:47:47 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184747eusmtip1652b74d3fc922a12e92ef0d0910e99c5~OXFub85B-3146231462eusmtip1g;
|
|
Tue, 12 May 2020 18:47:46 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 3/9] pci: Move some PCIe register offset definitions to a
|
|
common header
|
|
Date: Tue, 12 May 2020 20:47:10 +0200
|
|
Message-Id: <20200512184716.2869-4-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDKsWRmVeSWpSXmKPExsWy7djPc7oh73fFGTw6rm2xccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGVM
|
|
nqNYMF2y4vHC/4wNjM9Euhg5OSQETCSm/ZvDDmILCaxglOjZH9DFyAVkf2GUeLzoMzuE85lR
|
|
ou/UDXaYjlM9R1khEssZJQ4+P8UK0Q7Usmy+B4jNJmAo0Xu0jxHEFhEIkLj2cxojSAOzwFFG
|
|
iTX7/7CAJIQFYiTO77/MBGKzCKhKTL1xBKyBV8BKYs3S12wQ2+QlVm84wAxicwpYS1zffIwZ
|
|
ZJCEwDJ2iVW7F0Kd5CKx79h1RghbWOLV8S1QcRmJ/zvnM0E0NAM9t/s2O4QzgVHi/vEFUB3W
|
|
EnfO/QJaxwF0n6bE+l36EGFHiemPdoCFJQT4JG68FQQJMwOZk7ZNZ4YI80p0tAlBVKtI/F41
|
|
nQnClpLofvKfBaLEQ2L5NAdIYPUB/d76iW0Co/wshF0LGBlXMYqnlhbnpqcWG+WllusVJ+YW
|
|
l+al6yXn525iBKaZ0/+Of9nBuOtP0iFGAQ5GJR5ehtpdcUKsiWXFlbmHGCU4mJVEeFsyd8YJ
|
|
8aYkVlalFuXHF5XmpBYfYpTmYFES5zVe9DJWSCA9sSQ1OzW1ILUIJsvEwSnVwLh1z5TeG0az
|
|
+Xfd3FB0+/pjvrtznq13cFFY6DvDfpdPqclmFr4pB1beCCs7lOQ78cOhHwlnVjI6zEmc2Ozz
|
|
UzA48qrRrx/LPvqqt87Nqaz10/n2edvVDtvtE8Xe3rXad+vYkdXTZH6FOV5copT6IaCd1+u9
|
|
COurmnJJL6c5pbV9++z8vrjw1O5UYinOSDTUYi4qTgQAvI6vdC8DAAA=
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xu7rB73fFGTxpUbXYOGM9q8XUnniL
|
|
vW/62Sxu/GpjtVh75C67xZu2RkaLBZOfsFpsm7WczeLwm3ZWi29btjFavN3bye7A7THr/lk2
|
|
j9kNF1k85s06weKxc9Zddo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi
|
|
DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DImz1EsmC5Z8Xjhf8YGxmciXYyc
|
|
HBICJhKneo6ydjFycQgJLGWUOL/kGnsXIwdQQkpifosSRI2wxJ9rXWwQNZ8YJe61LGACSbAJ
|
|
GEr0Hu1jBLFFBEIkXhy9wgRSxCxwllFiUecHVpCEsECUxIvfjWBFLAKqElNvHAGzeQWsJNYs
|
|
fc0GsUFeYvWGA8wgNqeAtcT1zcfAbCGgmj3f3rFNYORbwMiwilEktbQ4Nz232FCvODG3uDQv
|
|
XS85P3cTIzDstx37uXkH46WNwYcYBTgYlXh4GWp3xQmxJpYVV+YeYpTgYFYS4W3J3BknxJuS
|
|
WFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnAmMwriTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliS
|
|
mp2aWpBaBNPHxMEp1cAo8NYxO8Jqj6PRV77edRqM6d/fPNh+ckp9/fKwsoWn/NSufp8boJey
|
|
O+/Wy/nTzpj1bt4798PtHSdmhmywaQj0KVYtD5qat1b7GMvEYBcra0Ze5hft2f6SH/t0Lumf
|
|
lXf9Pqv43uddiwVjUyRvrP5qZmy664CmlFb7nrstPeLfGxjWC3ooze9TYinOSDTUYi4qTgQA
|
|
d2ZzFZECAAA=
|
|
X-CMS-MailID: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5@eucas1p2.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
Some PCI Express register offsets are currently defined in multiple
|
|
drivers, move them to a common header to avoid re-definitions and
|
|
as a pre-requisite for adding new PCIe driver.
|
|
While at it replace some spaces with tabs.
|
|
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
|
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
---
|
|
Changes since v1:
|
|
- none.
|
|
Changes since RFC:
|
|
- whitespace clean up.
|
|
---
|
|
drivers/pci/pci-rcar-gen3.c | 8 --------
|
|
drivers/pci/pcie_intel_fpga.c | 3 ---
|
|
include/pci.h | 13 +++++++++++--
|
|
3 files changed, 11 insertions(+), 13 deletions(-)
|
|
|
|
diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
|
|
index 30eff67..393f1c9 100644
|
|
--- a/drivers/pci/pci-rcar-gen3.c
|
|
+++ b/drivers/pci/pci-rcar-gen3.c
|
|
@@ -117,14 +117,6 @@
|
|
#define RCAR_PCI_MAX_RESOURCES 4
|
|
#define MAX_NR_INBOUND_MAPS 6
|
|
|
|
-#define PCI_EXP_FLAGS 2 /* Capabilities register */
|
|
-#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
|
|
-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
|
|
-#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
|
|
-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
|
-#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
|
-#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
|
-
|
|
enum {
|
|
RCAR_PCI_ACCESS_READ,
|
|
RCAR_PCI_ACCESS_WRITE,
|
|
diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
|
|
index 6a9f29c..69363a0 100644
|
|
--- a/drivers/pci/pcie_intel_fpga.c
|
|
+++ b/drivers/pci/pcie_intel_fpga.c
|
|
@@ -65,9 +65,6 @@
|
|
#define IS_ROOT_PORT(pcie, bdf) \
|
|
((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
|
|
|
|
-#define PCI_EXP_LNKSTA 18 /* Link Status */
|
|
-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
|
-
|
|
/**
|
|
* struct intel_fpga_pcie - Intel FPGA PCIe controller state
|
|
* @bus: Pointer to the PCI bus
|
|
diff --git a/include/pci.h b/include/pci.h
|
|
index aff56b2..dfdbb32 100644
|
|
--- a/include/pci.h
|
|
+++ b/include/pci.h
|
|
@@ -471,10 +471,19 @@
|
|
#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
|
|
|
|
/* PCI Express capabilities */
|
|
+#define PCI_EXP_FLAGS 2 /* Capabilities register */
|
|
+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
|
|
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
|
|
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
|
|
-#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
|
|
+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
|
|
#define PCI_EXP_DEVCTL 8 /* Device Control */
|
|
-#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
|
|
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
|
|
+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
|
|
+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
|
+#define PCI_EXP_LNKSTA 18 /* Link Status */
|
|
+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
|
+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
|
+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
|
|
|
/* Include the ID list */
|
|
|
|
|
|
From patchwork Tue May 12 18:47:11 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288729
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=DMPfLXHn;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de
|
|
[IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6Jq5kVFz9sSW
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:48:43 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 6DD0981CA0;
|
|
Tue, 12 May 2020 20:48:35 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="DMPfLXHn";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id 1708981CCA; Tue, 12 May 2020 20:48:34 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com
|
|
[210.118.77.11])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id 268AA81C8F
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:48:31 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p2.samsung.com (unknown [182.198.249.207])
|
|
by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184830euoutp01ccbc955d4e553cfcc652df2a8a26a7bd~OXGXNrozu0823008230euoutp01U
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:48:30 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com
|
|
20200512184830euoutp01ccbc955d4e553cfcc652df2a8a26a7bd~OXGXNrozu0823008230euoutp01U
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309310;
|
|
bh=3E0AOgx9hU8sLyjssq8h9uGtoMBKiYQYmWKYKj8g+7M=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=DMPfLXHnOgmW1Z4KlAl/NdPP5dLcXH56gib60eMcKVBH/cg4pQkIlBSZPlg8WU47T
|
|
OSf3QryKG/0HgRi0epoYgVCWYqdtWu+elalkhjiDXrHEaN9KpotUASwVVmKc6vxZUq
|
|
sQhwySR6duVQzCazExVuqPC71RShDpAqqkiFjqrg=
|
|
Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184830eucas1p26b67732246d5cd7a6247fa6e114db6d0~OXGW73iC-0949309493eucas1p2v;
|
|
Tue, 12 May 2020 18:48:30 +0000 (GMT)
|
|
Received: from eucas1p2.samsung.com ( [182.198.249.207]) by
|
|
eusmges3new.samsung.com (EUCPMTA) with SMTP id 7D.03.60698.E7FEABE5; Tue, 12
|
|
May 2020 19:48:30 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7~OXGVv7OF12080520805eucas1p1u;
|
|
Tue, 12 May 2020 18:48:29 +0000 (GMT)
|
|
Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184829eusmtrp262ea470daeba61b3d4efb349c6418007~OXGVvS8Ut1654916549eusmtrp2n;
|
|
Tue, 12 May 2020 18:48:29 +0000 (GMT)
|
|
X-AuditID: cbfec7f5-a29ff7000001ed1a-89-5ebaef7eefa5
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms2.samsung.com (EUCPMTA) with SMTP id 22.F8.07950.D7FEABE5; Tue, 12
|
|
May 2020 19:48:29 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184828eusmtip1a8d7ad1b8a25aeb694a863a0e7798f73~OXGVOX36p1659716597eusmtip1h;
|
|
Tue, 12 May 2020 18:48:28 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 4/9] rpi4: shorten a mapping for the DRAM
|
|
Date: Tue, 12 May 2020 20:47:11 +0200
|
|
Message-Id: <20200512184716.2869-5-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm81x2XC5O0/JLLWPUj6J0YuQhpQv24/wKIQgzUpee3NBN2bxk
|
|
oS4Mzfs0dDIlh3jDvOVs3tPMqWFzpmiS1x9aZLMQU9KstXlm/Xue532f73le+AiEX4G5ERJZ
|
|
PCOXiWIEOBfVD22bzqV+7woVDhYfp16UNmNUcW4Y1WsuwKmZnQyMahyc51DmjEeA0j5dxii9
|
|
phan3pgzMWqrTQ+otd4szpUDtGbRiNNlyvco/UwzgtKdmnkObZzrAHR+Wz2gm9umUFo3+jCI
|
|
COEGRDIxkkRG7n0pnCve2tWicUv4/W1LHq4ERiwbOBKQPA8/Npai2YBL8Mk6AFd/btjJDwBL
|
|
THMISzasRNXH2bcY2iftg1oAK7+asH+WpkIdYtvCSR+YZ8gHNuxCBsHp7RJgW0JIA4ANfbuo
|
|
beBMBsCcniLchlHyFPxdZNlrxSMvwkrLCmDjPOHzlv69Rx1Jf/hBN7QXDckaDlypWbGfcQ2O
|
|
j1fbDc5wdbjN3tUDWjorHFhDOoC53bMclqgAXBzW2h3+cG5sx1qDsPY7DZu7vFn5Kuxez0Jt
|
|
MiQPwpm1QzYZscIivRphZR58ksFnt0/CX/VqBxa7wZxlC8piGr6c+LSH+WQ+gB2tUSrgqfmf
|
|
pQWgHrgyCQppFKPwlTFJXgqRVJEgi/KKiJW2Auu3Gf0zvNkBXu3eHQAkAQROvOC0rlA+JkpU
|
|
JEsHACQQgQvvsaQzlM+LFCU/YOSxYfKEGEYxANwJVODK8638codPRonimWiGiWPk+1MHwtFN
|
|
CYQpQnVaT2nysfDE1aaIqtbArJWlneYF9eWFw7cmMt3zI/JC1lMLouP8/IzY5G2TIbVxqvCd
|
|
wXzEYEkp32whdEwVphuZnvFQjZWVI6iY+rYutIyf1SjXTtyQ3HybHmjYckraaA++J25AEi+o
|
|
xrizkuu6sv7Pr49W96fWVaVwBahCLPI5g8gVor/Jvg12MgMAAA==
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7q173fFGcx6xW2xccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF
|
|
G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GV8+7OApeABW8XP/71sDYxnWbsY
|
|
OTkkBEwkjm6/zNzFyMUhJLCUUaJjUzuQwwGUkJKY36IEUSMs8edaFxtEzSdGif+9b5hAEmwC
|
|
hhK9R/sYQWwRgRCJF0evMIEUMQucZZRY1PkBbIOwgI1E955JbCA2i4CqxN9J/8HivAJWEov+
|
|
P2WE2CAvsXrDAWYQm1PAWuL65mNgthBQzZ5v79gmMPItYGRYxSiSWlqcm55bbKRXnJhbXJqX
|
|
rpecn7uJERj424793LKDsetd8CFGAQ5GJR7eiPpdcUKsiWXFlbmHGCU4mJVEeFsyd8YJ8aYk
|
|
VlalFuXHF5XmpBYfYjQFOmois5Rocj4wKvNK4g1NDc0tLA3Njc2NzSyUxHk7BA7GCAmkJ5ak
|
|
ZqemFqQWwfQxcXBKNTCeUDjUsfdYk+GanwELP95YN2/J9NfGstu3nn42YcH/6UqTTE3bU24L
|
|
K74vEv6+x/hg276183j4TsoumBXpvTTv7cVjU+IfTC3dfey+2rcNU7fGmcuxiewVihLapvRL
|
|
0n1/s5XyjSCz0n3PbGavd9gQt2xnnWCOWl68jfxdD++dF5ce1wrYx2xorcRSnJFoqMVcVJwI
|
|
AKKisECSAgAA
|
|
X-CMS-MailID: 20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7@eucas1p1.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
From: Marek Szyprowski <m.szyprowski@samsung.com>
|
|
|
|
Remove the overlap between DRAM and device's IO area.
|
|
|
|
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
---
|
|
Changes since v1:
|
|
- none.
|
|
---
|
|
arch/arm/mach-bcm283x/init.c | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
|
|
index 9966d6c..4295356 100644
|
|
--- a/arch/arm/mach-bcm283x/init.c
|
|
+++ b/arch/arm/mach-bcm283x/init.c
|
|
@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = {
|
|
{
|
|
.virt = 0x00000000UL,
|
|
.phys = 0x00000000UL,
|
|
- .size = 0xfe000000UL,
|
|
+ .size = 0xfc000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
|
|
From patchwork Tue May 12 18:47:12 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288730
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=PpqM0F3J;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de
|
|
[IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6K33sdWz9sSW
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:48:55 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 305E681CD4;
|
|
Tue, 12 May 2020 20:48:38 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="PpqM0F3J";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id 2729181CA1; Tue, 12 May 2020 20:48:35 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com
|
|
[210.118.77.12])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id 520C381CA0
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:48:32 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p2.samsung.com (unknown [182.198.249.207])
|
|
by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184831euoutp0223716d2be7dd8466639bb75ecdcd79b0~OXGXwE2rE0645506455euoutp02c
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:48:31 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com
|
|
20200512184831euoutp0223716d2be7dd8466639bb75ecdcd79b0~OXGXwE2rE0645506455euoutp02c
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309311;
|
|
bh=1pvJmD4788qVg9pTe/vSEzdnItJirsmIW08n7dgVDSA=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=PpqM0F3JtuV/Gbbx4WZDA0/EUnzelZKHiPHcezW/bOT3ROKOpL5P+hTILHd2Fa9az
|
|
AgjMlAoSUTV5jgyC183yxJiA00nZs3FMJ0Bs5apO3yGnMQ0VplTKbdtZOYCjfPLsW9
|
|
X1PqGYiWoAETAzfxMLvtiQYLn2baNQR7KG6BB4jc=
|
|
Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184831eucas1p28c8414af443b820cd0031316c0b5f158~OXGXgiZCQ0944309443eucas1p2q;
|
|
Tue, 12 May 2020 18:48:31 +0000 (GMT)
|
|
Received: from eucas1p2.samsung.com ( [182.198.249.207]) by
|
|
eusmges1new.samsung.com (EUCPMTA) with SMTP id 2E.FF.61286.F7FEABE5; Tue, 12
|
|
May 2020 19:48:31 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184830eucas1p198b1439122e2da299c563726fe17f9ef~OXGXJNK8p2314823148eucas1p1B;
|
|
Tue, 12 May 2020 18:48:30 +0000 (GMT)
|
|
Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184830eusmtrp2079ea429a5356a2e5cc978b0d5f43d24~OXGXIonFW1654116541eusmtrp2p;
|
|
Tue, 12 May 2020 18:48:30 +0000 (GMT)
|
|
X-AuditID: cbfec7f2-f0bff7000001ef66-8a-5ebaef7f3368
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms2.samsung.com (EUCPMTA) with SMTP id E2.F8.07950.E7FEABE5; Tue, 12
|
|
May 2020 19:48:30 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184830eusmtip128dac35d637f9caa48c5da04fe7aeb84~OXGWqET-G2778327783eusmtip1U;
|
|
Tue, 12 May 2020 18:48:30 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 5/9] rpi4: add a mapping for the PCIe XHCI controller
|
|
MMIO registers (ARM 64bit)
|
|
Date: Tue, 12 May 2020 20:47:12 +0200
|
|
Message-Id: <20200512184716.2869-6-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPKsWRmVeSWpSXmKPExsWy7djP87r173fFGXxfxWKxccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGV8
|
|
WriNvWCTYMWOfbvYGxgX8HUxcnJICJhITDy4ka2LkYtDSGAFo0TT213MEM4XRokzu3YwQjif
|
|
GSXajuxjg2npnd7MBJFYzihx7fJ5FriWpYe+M4NUsQkYSvQe7WMEsUUEAiSu/ZwGNopZ4Cij
|
|
xJr9f1hAEsICqRKNrx6CjWURUJX4Nm82WJxXwEriSu8/qHXyEqs3HAAbyilgLXF98zFmiPgy
|
|
domli0UgbBeJ39tnM0HYwhKvjm9hh7BlJP7vnA92qoRAM6NEz+7b7BDOBEaJ+8cXMEJUWUvc
|
|
OfcLaBsH0HmaEut36UOEHSWWbO5iBQlLCPBJ3HgrCBJmBjInbZvODBHmlehoE4KoVpH4vWo6
|
|
1AlSEt1P/rNA2B4St/YcYIUEUB8wgP6dZ5zAKD8LYdkCRsZVjOKppcW56anFhnmp5XrFibnF
|
|
pXnpesn5uZsYgcnm9L/jn3Ywfr2UdIhRgINRiYeXoXZXnBBrYllxZe4hRgkOZiUR3pbMnXFC
|
|
vCmJlVWpRfnxRaU5qcWHGKU5WJTEeY0XvYwVEkhPLEnNTk0tSC2CyTJxcEo1MM6MW6vHlv9O
|
|
LFWw4mzJiaOX1tgbcVh+DyhbVxBTPOG2iGxd2Z4Xll4nbb/t4i7Uli7/c69kR8TPP/0y3085
|
|
Vj6bYJ3UkaklyinuIOjU32D/wGfFROcjPf0LmWOyko9vzpQ+8m5a1vbG6Ci9qXytx2L3WDz5
|
|
PG/nWzffGb6Vz5lVNPRa7Y9PUmIpzkg01GIuKk4EAHeTlcEyAwAA
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7p173fFGbxeo2WxccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF
|
|
G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GV8WriNvWCTYMWOfbvYGxgX8HUx
|
|
cnJICJhI9E5vZupi5OIQEljKKHGu/wJjFyMHUEJKYn6LEkSNsMSfa11sEDWfGCXO7z3LDJJg
|
|
EzCU6D3axwhiiwiESLw4egVsELPAWUaJRZ0fWEESwgLJEk17voPZLAKqEt/mzWYBsXkFrCSu
|
|
9P5jg9ggL7F6wwGwoZwC1hLXNx8Ds4WAavZ8e8c2gZFvASPDKkaR1NLi3PTcYiO94sTc4tK8
|
|
dL3k/NxNjMDA33bs55YdjF3vgg8xCnAwKvHwRtTvihNiTSwrrsw9xCjBwawkwtuSuTNOiDcl
|
|
sbIqtSg/vqg0J7X4EKMp0FETmaVEk/OBUZlXEm9oamhuYWlobmxubGahJM7bIXAwRkggPbEk
|
|
NTs1tSC1CKaPiYNTqoGx5PTNH9vfNYXt1fTI2Ri57W1dk3bLB5Oe1B677C7vZQ+UNDK97736
|
|
GtxycMG/FZ1LPORF49uy7zIsCZ7yWaS86edL/cnPJy8yvPHwlfWjq88f3fuxPeLDtLv3DQwX
|
|
HQjYNnX2LFsJnrKN/Ie9Fuzg5Z80z6DQUyG07uzDQvtHUSKTnBo2Ki3xUmIpzkg01GIuKk4E
|
|
AGD+HDOSAgAA
|
|
X-CMS-MailID: 20200512184830eucas1p198b1439122e2da299c563726fe17f9ef
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184830eucas1p198b1439122e2da299c563726fe17f9ef
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184830eucas1p198b1439122e2da299c563726fe17f9ef
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184830eucas1p198b1439122e2da299c563726fe17f9ef@eucas1p1.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
From: Marek Szyprowski <m.szyprowski@samsung.com>
|
|
|
|
Create a non-cacheable mapping for the 0x600000000 physical memory region,
|
|
where MMIO registers for the PCIe XHCI controller are instantiated by the
|
|
PCIe bridge.
|
|
|
|
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
---
|
|
Changes since v2:
|
|
- fixed typo MAX_MAP_MAX_ENTRIES -> MEM_MAP_MAX_ENTRIES
|
|
Changes since v1:
|
|
- none.
|
|
---
|
|
arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++---
|
|
1 file changed, 15 insertions(+), 3 deletions(-)
|
|
|
|
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
|
|
index 4295356..9f5bca3 100644
|
|
--- a/arch/arm/mach-bcm283x/init.c
|
|
+++ b/arch/arm/mach-bcm283x/init.c
|
|
@@ -11,10 +11,15 @@
|
|
#include <dm/device.h>
|
|
#include <fdt_support.h>
|
|
|
|
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL
|
|
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
|
|
+
|
|
#ifdef CONFIG_ARM64
|
|
#include <asm/armv8/mmu.h>
|
|
|
|
-static struct mm_region bcm283x_mem_map[] = {
|
|
+#define MEM_MAP_MAX_ENTRIES (4)
|
|
+
|
|
+static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
|
|
{
|
|
.virt = 0x00000000UL,
|
|
.phys = 0x00000000UL,
|
|
@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = {
|
|
}
|
|
};
|
|
|
|
-static struct mm_region bcm2711_mem_map[] = {
|
|
+static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
|
|
{
|
|
.virt = 0x00000000UL,
|
|
.phys = 0x00000000UL,
|
|
@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
+ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
|
|
+ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
|
|
+ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
|
|
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
+ PTE_BLOCK_NON_SHARE |
|
|
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
+ }, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
|
|
{
|
|
int i;
|
|
|
|
- for (i = 0; i < 2; i++) {
|
|
+ for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
|
|
mem_map[i].virt = pd[i].virt;
|
|
mem_map[i].phys = pd[i].phys;
|
|
mem_map[i].size = pd[i].size;
|
|
|
|
From patchwork Tue May 12 18:47:13 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288732
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=OrqQU0UN;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de
|
|
[IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6KH0ykgz9sSW
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:49:07 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 43B8081CF5;
|
|
Tue, 12 May 2020 20:48:39 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="OrqQU0UN";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id A041C81CD4; Tue, 12 May 2020 20:48:36 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com
|
|
[210.118.77.12])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id AF9CA81CB4
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:48:33 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p2.samsung.com (unknown [182.198.249.207])
|
|
by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184833euoutp02024bfc004b3a38e7abe168cdd77f5dbb~OXGZmHDwG0461204612euoutp024
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:48:33 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com
|
|
20200512184833euoutp02024bfc004b3a38e7abe168cdd77f5dbb~OXGZmHDwG0461204612euoutp024
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309313;
|
|
bh=gVSWmpdQ36VgD8o/W/rduik6grJJCng+jGVfBPUAF8U=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=OrqQU0UN8Z7QKS+4Unt5PDDDw3i2iYhOJT4TdbEKloVbg23X7ARl1QJTAaFBBNzJT
|
|
8AXLlGfGZj4mJo1gPBdQ/TOVDG7RDy4i/+ujixIckKJXDA+AjclrJdeEAcngq0Ulnn
|
|
NbOUAtPbCSEM0S/0RPnWwC90UpPAmcqGeCkVrazE=
|
|
Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by
|
|
eucas1p1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184833eucas1p1dc7466ebb73dd2f787e4253f171a3b9d~OXGZbAMzF2083120831eucas1p1w;
|
|
Tue, 12 May 2020 18:48:33 +0000 (GMT)
|
|
Received: from eucas1p2.samsung.com ( [182.198.249.207]) by
|
|
eusmges2new.samsung.com (EUCPMTA) with SMTP id F5.AA.60679.18FEABE5; Tue, 12
|
|
May 2020 19:48:33 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad~OXGZA7swA2288022880eucas1p17;
|
|
Tue, 12 May 2020 18:48:32 +0000 (GMT)
|
|
Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184832eusmtrp2c7ee802f60d431184d93a34cbe4b5279~OXGZAXbrx1654916549eusmtrp2o;
|
|
Tue, 12 May 2020 18:48:32 +0000 (GMT)
|
|
X-AuditID: cbfec7f4-0e5ff7000001ed07-fd-5ebaef8142ae
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms2.samsung.com (EUCPMTA) with SMTP id A3.F8.07950.08FEABE5; Tue, 12
|
|
May 2020 19:48:32 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184832eusmtip1ffa9d15a350dcc63557ad23be081cb76~OXGYefx_f2778327783eusmtip1V;
|
|
Tue, 12 May 2020 18:48:32 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 6/9] linux/bitfield.h: Add primitives for manipulating
|
|
bitfields both in host- and fixed-endian
|
|
Date: Tue, 12 May 2020 20:47:13 +0200
|
|
Message-Id: <20200512184716.2869-7-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAKsWRmVeSWpSXmKPExsWy7djP87qN73fFGdy/yWqxccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGW8
|
|
v/6XuWCuSMXm151sDYzHBboYOTkkBEwkrv3+z9LFyMUhJLCCUeLqqz+MEM4XRom+t9+gnM+M
|
|
Em3XbrLAtGy428wOkVjOKPG0YSMbXMvD1X3sIFVsAoYSvUf7GEFsEYEAiWs/p4GNYhY4yiix
|
|
Zv8fsFHCAiUSs/9OZgWxWQRUJZbeOQXWwCtgJfH35FwmiHXyEqs3HGAGsTkFrCWubz7GDDJI
|
|
QmAVu8S60+uhbnKRmL9tJTuELSzx6vgWKFtG4v/O+UwQDc2MEj27b7NDOBMYJe4fX8AIUWUt
|
|
cefcL6AnOIDu05RYv0sfIuwo0Xb0KTtIWEKAT+LGW0GQMDOQOWnbdGaIMK9ER5sQRLWKxO9V
|
|
06FulpLofvIf6jQPiebdl6Ah1McocXD2TqYJjPKzEJYtYGRcxSieWlqcm55abJSXWq5XnJhb
|
|
XJqXrpecn7uJEZhuTv87/mUH464/SYcYBTgYlXh4GWp3xQmxJpYVV+YeYpTgYFYS4W3J3Bkn
|
|
xJuSWFmVWpQfX1Sak1p8iFGag0VJnNd40ctYIYH0xJLU7NTUgtQimCwTB6dUA6ODfX6J8vRP
|
|
kS+KX7b+sr18ZKLND/H+CxvqW3meFD769EE8d07Cr1VxR9y0XX2uzm7Ya7jTOKjbT6fT7NTx
|
|
ctavcrxzXr8sF/94MOp3a0neVQeztyzlwSmL/z0VS1j6k2HvYg9180Vfo4KOzvp5jX/63V7/
|
|
KbVNp0sWCu+TUPHIenjq2JX2Xy5KLMUZiYZazEXFiQAsWJztMwMAAA==
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xu7oN73fFGWxZpGGxccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF
|
|
G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GW8v/6XuWCuSMXm151sDYzHBboY
|
|
OTkkBEwkNtxtZu9i5OIQEljKKNG88z5jFyMHUEJKYn6LEkSNsMSfa11sILaQwCdGiQPbpUFs
|
|
NgFDid6jfYwgtohAiMSLo1eYQOYwC5xllFjU+YEVJCEsUCRxef86JhCbRUBVYumdU2ANvAJW
|
|
En9PzmWCWCAvsXrDAWYQm1PAWuL65mPMEMusJPZ8e8c2gZFvASPDKkaR1NLi3PTcYiO94sTc
|
|
4tK8dL3k/NxNjMCw33bs55YdjF3vgg8xCnAwKvHwRtTvihNiTSwrrsw9xCjBwawkwtuSuTNO
|
|
iDclsbIqtSg/vqg0J7X4EKMp0FETmaVEk/OBMZlXEm9oamhuYWlobmxubGahJM7bIXAwRkgg
|
|
PbEkNTs1tSC1CKaPiYNTqoGRL+bltk22/7+9+eEy57X8YZkID4Uj5VoKoSuTez9IRTw9cJA9
|
|
f+mEOlbeZyvTnFlM/r3fsWl2FUuAYz97waprdvs3vpx9QyUl8rbyZJloPYMp4k5TRTm2vecX
|
|
qjC8NG3F+bgO9kV25i0VwYy7Fnjm/ZmhHZI93Y7bduZik0DpvXJcJvwfj8opsRRnJBpqMRcV
|
|
JwIAdir705ECAAA=
|
|
X-CMS-MailID: 20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad@eucas1p1.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
|
|
Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
|
|
an in depth explanation and two fixes from Johannes Berg:
|
|
e7d4a95da86e0 "bitfield: fix *_encode_bits()",
|
|
37a3862e12382 "bitfield: add u8 helpers".
|
|
|
|
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
[s.nawrocki: added empty lines between functions and macros]
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
---
|
|
Changes since v1:
|
|
- added empty lines between functions and macros.
|
|
|
|
Changes since RFC:
|
|
- new patch.
|
|
---
|
|
include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 50 insertions(+)
|
|
|
|
diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
|
|
index 8b9d6ff..7acba4c 100644
|
|
--- a/include/linux/bitfield.h
|
|
+++ b/include/linux/bitfield.h
|
|
@@ -103,4 +103,54 @@
|
|
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
|
|
})
|
|
|
|
+extern void __compiletime_error("value doesn't fit into mask")
|
|
+__field_overflow(void);
|
|
+extern void __compiletime_error("bad bitfield mask")
|
|
+__bad_mask(void);
|
|
+static __always_inline u64 field_multiplier(u64 field)
|
|
+{
|
|
+ if ((field | (field - 1)) & ((field | (field - 1)) + 1))
|
|
+ __bad_mask();
|
|
+ return field & -field;
|
|
+}
|
|
+static __always_inline u64 field_mask(u64 field)
|
|
+{
|
|
+ return field / field_multiplier(field);
|
|
+}
|
|
+
|
|
+#define ____MAKE_OP(type,base,to,from) \
|
|
+static __always_inline __##type type##_encode_bits(base v, base field) \
|
|
+{ \
|
|
+ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \
|
|
+ __field_overflow(); \
|
|
+ return to((v & field_mask(field)) * field_multiplier(field)); \
|
|
+} \
|
|
+static __always_inline __##type type##_replace_bits(__##type old, \
|
|
+ base val, base field) \
|
|
+{ \
|
|
+ return (old & ~to(field)) | type##_encode_bits(val, field); \
|
|
+} \
|
|
+static __always_inline void type##p_replace_bits(__##type *p, \
|
|
+ base val, base field) \
|
|
+{ \
|
|
+ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \
|
|
+} \
|
|
+static __always_inline base type##_get_bits(__##type v, base field) \
|
|
+{ \
|
|
+ return (from(v) & field)/field_multiplier(field); \
|
|
+}
|
|
+
|
|
+#define __MAKE_OP(size) \
|
|
+ ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
|
|
+ ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
|
|
+ ____MAKE_OP(u##size,u##size,,)
|
|
+
|
|
+____MAKE_OP(u8,u8,,)
|
|
+__MAKE_OP(16)
|
|
+__MAKE_OP(32)
|
|
+__MAKE_OP(64)
|
|
+
|
|
+#undef __MAKE_OP
|
|
+#undef ____MAKE_OP
|
|
+
|
|
#endif
|
|
|
|
From patchwork Tue May 12 18:47:14 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288733
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=85.214.62.61; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=Fm50fcBL;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de [85.214.62.61])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6KV3jXsz9sRR
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:49:18 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 7663481CC1;
|
|
Tue, 12 May 2020 20:48:44 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="Fm50fcBL";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id 497CE81CE3; Tue, 12 May 2020 20:48:41 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com
|
|
[210.118.77.11])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id 53C8F81CD9
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:48:38 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p1.samsung.com (unknown [182.198.249.206])
|
|
by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184838euoutp019e25bda09342202a0eda043f595e3c22~OXGd7TgBd0706107061euoutp01m
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:48:38 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com
|
|
20200512184838euoutp019e25bda09342202a0eda043f595e3c22~OXGd7TgBd0706107061euoutp01m
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309318;
|
|
bh=HzMTU/TXuht/pqPHaK0Ik2xR+VGQDcf9rtO4VMSyKJM=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=Fm50fcBLGZyjlJzMo4Jk2kL21fNnnNiYQPGuvZ9uYJHcoSJzOfuJZKLNBoAFhG6Q1
|
|
7NBIjapXv/0ZFqIcyF8vg14dGk5aNjSHNtjyeLaSxxf0+jcM23co7gshLtNg2WB2Jv
|
|
1m1YEKUU/fA0BznXct760bitBngMWoUq+d7qDQHM=
|
|
Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by
|
|
eucas1p1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184836eucas1p1135921d83070d86d6e8b1bb64b8f8be4~OXGczeB0p2080520805eucas1p1w;
|
|
Tue, 12 May 2020 18:48:36 +0000 (GMT)
|
|
Received: from eucas1p2.samsung.com ( [182.198.249.207]) by
|
|
eusmges3new.samsung.com (EUCPMTA) with SMTP id 7F.03.60698.48FEABE5; Tue, 12
|
|
May 2020 19:48:36 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985~OXGcRwgxc0943909439eucas1p25;
|
|
Tue, 12 May 2020 18:48:36 +0000 (GMT)
|
|
Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184836eusmtrp2d133993e54b8ae3b6e45209e4cf24ca5~OXGcRC2XF1654116541eusmtrp2q;
|
|
Tue, 12 May 2020 18:48:36 +0000 (GMT)
|
|
X-AuditID: cbfec7f5-a0fff7000001ed1a-92-5ebaef84302e
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms2.samsung.com (EUCPMTA) with SMTP id 64.F8.07950.48FEABE5; Tue, 12
|
|
May 2020 19:48:36 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184835eusmtip109d2fc69bebbcdfc5800da0da0dc6fc3~OXGbx_UD72778327783eusmtip1W;
|
|
Tue, 12 May 2020 18:48:35 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 7/9] pci: Add some PCI Express capability register offset
|
|
definitions
|
|
Date: Tue, 12 May 2020 20:47:14 +0200
|
|
Message-Id: <20200512184716.2869-8-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA0WSfUhTURjGObt323U6uV4FDysQhoUFaaLgJUUqpW4QaP1lxrSZFzXnB7vT
|
|
siBXyTS/MXQyQ6dBs6lpOYabzGqls0Qtxa9STDHF0kLLcqYt59X67/c+53nO+3A4GELUckVY
|
|
SrqClqdLZWKeADX22AeP5H0zxx1VLviTT6pbuWRlcTxpWSrjkeMbKi7Z8mqKTy6pbgFSe2+O
|
|
Sxo1Oh75cimfS/40GAG5bLnLP+5Kaab7eVSN8h1K1Wp6UcqkmeJT/ZMdgCo16AHVahhBqfa+
|
|
G9FYrCAskZalZNPygPBLguTBolkks8v9mvK1GlGCdddC4IJBPBh+LankFwIBRuCNAFavlvHY
|
|
4QeAM58+ok4XgX8HULUQtZeoaejisCYdgGrdEPdfQmfJ5zhdPDwQlnSXAid74dFw1F4FnCYE
|
|
7waw+dnmzrWeeCwsGOjdCaD4AWhvuo84WYgfg1vvGzjsOh/Y1PZ8R3fBQ+FYew/C6g/5cP6B
|
|
H8uRcO2LhceyJ/xsM/BZ3g8dprqdqhC/A2Bx5wc+O5QDOG3TAtYVCicHNrbT2Ha9Q7DVHMDK
|
|
J+DKozXglCHuDseXPZwyso0VRjXCykJYoCJYty/8rVfvVhbBojkHyjIF+yre7j5pKYCWF/1o
|
|
OfDR/F+mBUAPvOksJi2JZoLS6av+jDSNyUpP8r+ckfYUbP+avj+2tQ7QtZlgBTgGxG7CmFxz
|
|
HMGVZjM5aVYAMUTsJcxLMcURwkRpznVanhEvz5LRjBXsw1CxtzCoYVFC4ElSBZ1K05m0fO+U
|
|
g7mIlOCg92jfROiKbSLLrf4cdabRivg9doQREZ0z4cGySNFJ02xeSU3RWcEUNbKuNtd7RNAJ
|
|
FaYW/akoEedmSArhMNpDtAXJt+fDJb+ar2z4etddOJ9rLpD0SqrGKmN835we2qoYlcQr/Vwj
|
|
U1eNwQp1m+bicEeTTr94UVESmz8cJ0aZZGngYUTOSP8C7G85NjEDAAA=
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7ot73fFGTRO47HYOGM9q8XUnniL
|
|
vW/62Sxu/GpjtVh75C67xZu2RkaLBZOfsFpsm7WczeLwm3ZWi29btjFavN3bye7A7THr/lk2
|
|
j9kNF1k85s06weKxc9Zddo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi
|
|
DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DLOdz9iLtjHV9FwcjpzA+MP7i5G
|
|
Tg4JAROJ2Yv2MXUxcnEICSxllHj+p5+ti5EDKCElMb9FCaJGWOLPtS42iJpPjBITXm1gBEmw
|
|
CRhK9B7tA7NFBEIkXhy9AjaIWeAso8Sizg+sIAlhgQiJHXOusoDYLAKqEj9Xz2EGsXkFrCT+
|
|
3lrEBLFBXmL1hgNgcU4Ba4nrm4+B2UJANXu+vWObwMi3gJFhFaNIamlxbnpusZFecWJucWle
|
|
ul5yfu4mRmDgbzv2c8sOxq53wYcYBTgYlXh4I+p3xQmxJpYVV+YeYpTgYFYS4W3J3BknxJuS
|
|
WFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnAqMwriTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliS
|
|
mp2aWpBaBNPHxMEp1cCY/4XD7PPi+S+2KkXMPlP5dGW7dVZWdvNlA7N3Sw6+ZOOuq5RnEq38
|
|
/Hri8TyzzOI1Zop5dQadajuPpBekXn9f6P/3t+Mlo5d+fKvCcsUu+u4L59j6PlMo6vszCVXn
|
|
A0d2PnB/kCX47mLjVS3XtoS1P7J82hflcfkF+dxsDLSex/XRxFGj5roSS3FGoqEWc1FxIgBl
|
|
vUv9kgIAAA==
|
|
X-CMS-MailID: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985@eucas1p2.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
Add PCI Express capability definitions required by the Broadcom
|
|
STB PCIe controller driver.
|
|
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
|
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
---
|
|
Changes since v2:
|
|
- added Current Link Speed defines.
|
|
Changes since v1:
|
|
- none.
|
|
Changes since RFC:
|
|
- ensure the entries are added in order, sorted by ascending
|
|
address values.
|
|
---
|
|
include/pci.h | 9 +++++++++
|
|
1 file changed, 9 insertions(+)
|
|
|
|
diff --git a/include/pci.h b/include/pci.h
|
|
index dfdbb32..ff5f620 100644
|
|
--- a/include/pci.h
|
|
+++ b/include/pci.h
|
|
@@ -479,11 +479,20 @@
|
|
#define PCI_EXP_DEVCTL 8 /* Device Control */
|
|
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
|
|
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
|
|
+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
|
|
+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
|
|
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
|
#define PCI_EXP_LNKSTA 18 /* Link Status */
|
|
+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
|
|
+#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
|
|
+#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
|
|
+#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
|
|
+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
|
|
+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
|
|
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
|
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
|
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
|
+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
|
|
|
|
/* Include the ID list */
|
|
|
|
|
|
From patchwork Tue May 12 18:47:15 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288734
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=85.214.62.61; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=BIPbrQ8g;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de [85.214.62.61])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6Kj3M0tz9sRR
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:49:29 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 185C181CF7;
|
|
Tue, 12 May 2020 20:48:49 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="BIPbrQ8g";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id 26C8D81D0A; Tue, 12 May 2020 20:48:45 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com
|
|
[210.118.77.12])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id 1403981CFD
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:48:41 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p2.samsung.com (unknown [182.198.249.207])
|
|
by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184840euoutp0291a9b700643a42d241b5e145554cb765~OXGfyehRC0461204612euoutp027
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:48:40 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com
|
|
20200512184840euoutp0291a9b700643a42d241b5e145554cb765~OXGfyehRC0461204612euoutp027
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309320;
|
|
bh=TE9MyxK4mFntVW0fX+JmwIIwSpgKd4htbD5XCXxsM1I=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=BIPbrQ8gtigJfiy8ORfo+Qpp6HkymthVnUJBjoJlhoRKQAFXeIndDOOroFN8+Givz
|
|
5kQXtvIJNzzZLnA1WeEtInnFBydhbpbY34BCuDFzq0lH7QCPH4ZHj7ScIRySxzJNEt
|
|
gdGeQ4yOBI/arQQSbBp77pL23dh1EFNbN/7gAdNw=
|
|
Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184839eucas1p2fd05e5c1731867685fef1171042b653c~OXGfJVP1W2380523805eucas1p2c;
|
|
Tue, 12 May 2020 18:48:39 +0000 (GMT)
|
|
Received: from eucas1p1.samsung.com ( [182.198.249.206]) by
|
|
eusmges1new.samsung.com (EUCPMTA) with SMTP id 0F.FF.61286.78FEABE5; Tue, 12
|
|
May 2020 19:48:39 +0100 (BST)
|
|
Received: from eusmtrp1.samsung.com (unknown [182.198.249.138]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae~OXGegIxSM0944309443eucas1p2t;
|
|
Tue, 12 May 2020 18:48:38 +0000 (GMT)
|
|
Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by
|
|
eusmtrp1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184838eusmtrp1b8fcb72a4b1949c5b25111f77829cebe~OXGefeG9e0405704057eusmtrp1W;
|
|
Tue, 12 May 2020 18:48:38 +0000 (GMT)
|
|
X-AuditID: cbfec7f2-f0bff7000001ef66-94-5ebaef873740
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms1.samsung.com (EUCPMTA) with SMTP id 9E.DA.08375.68FEABE5; Tue, 12
|
|
May 2020 19:48:38 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184838eusmtip1e590ff27b66706ef16e7b7683ec1cc3d~OXGd_Ln563146531465eusmtip1X;
|
|
Tue, 12 May 2020 18:48:38 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 8/9] pci: Add driver for Broadcom BCM2711 SoC PCIe
|
|
controller
|
|
Date: Tue, 12 May 2020 20:47:15 +0200
|
|
Message-Id: <20200512184716.2869-9-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTcRTH/Xkfu65m12n5S4XhKqgsHyh40bSC/rgRyQgMKpyueZmWTtnU
|
|
0iiMytmcTrdKnWBm4TNdzTVfmLbyEaI9wLJSJBhCqQSViU5Wu95J/33O95zvOYfDIRDhfSyI
|
|
yFTmMSqlLEuM81HbyOrkQc2PPmnkQjdJPa0xY9RdXSo1sKjHqem1EozqeDXLoxZLrgOqwejA
|
|
KJupGadeLmow6o/VBqilgdu8I1to09wETtcVv0PpetMYSveaZnn0xEwPoCusbYA2W6dQumv8
|
|
ioQ4yz+UzmRlFjCqiMQ0fkadqwPJfWgBl/WvzWgxMFUBLfAhIBkDn3VrUJaFZAuAL+xxWsB3
|
|
828AHxtmcC74BeCKed5702EsH0O5RDOAJY9WPHa3RdNygmWcjILlwxUbIwJICfyweg+wBoQc
|
|
drcdXHcbCMKfPAXN1sNsDUrugYsdeoRlARkHay1TCDdMBNufDG2wDxkPP3aNIGwfSDbx4ODQ
|
|
W89Gx+Cas8nD/vD7qJXHcQgcN+pQznADQF3/Fx4XVAI4N9rguUA8nJlcw9mNEHIfNPdFcPJR
|
|
6HLewlgZkr5wesmPlRE3GmzVCCcLYGmJkKveDZ1t1Z4VgmCZ4y/KMQ2nmzu9uWNVAFjb/ACp
|
|
BCLT/2ENALSBQCZfna1g1FFK5lK4WpatzlcqwuU52Rbgfptx1+jPHrD8/rwdkAQQbxV4Xe2T
|
|
CjFZgbow2w4ggYgDBDcze6VCQbqssIhR5aSq8rMYtR0EE6g4UBDd+C1FSCpkecxFhsllVJtZ
|
|
b8InqBh0++ZJtMtarcsiSIqxDPkZOlun8OBtjuQDjV7zocvHd+iSQyIXUgoLqhrl1zD+emd0
|
|
GhlW018lb2/MfX4nLKe+CMZLkwYUVlqpD3WezqyN3RlSHphgM+2dKN31OUG+XeI4+fWTwUdU
|
|
UI/56USCC3gkk2g8FyttLVO9OWPOE6PqDFnUfkSllv0DEe0vVDIDAAA=
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkkeLIzCtJLcpLzFFi42I5/e/4Xd2297viDGbcUrbYOGM9q8XUnniL
|
|
vW/62Sxu/GpjtVh75C67xZu2RkaLBZOfsFpsm7WczeLwm3ZWi29btjFavN3bye7A7THr/lk2
|
|
j9kNF1k85s06weKxc9Zddo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi
|
|
DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DJm/1vLXLB4E2NF/8n1LA2MsyYy
|
|
djFyckgImEhM7j3B0sXIxSEksJRR4tmUu+xdjBxACSmJ+S1KEDXCEn+udbFB1HxilOib8JkZ
|
|
JMEmYCjRe7QPbJCIQIjEi6NXmECKmAXOMkos6vzACpIQFgiQuLD+PlgDi4CqxJu1/WA2r4CV
|
|
xMxNV5khNshLrN5wAMzmFLCWuL75GJgtBFSz59s7tgmMfAsYGVYxiqSWFuem5xYb6hUn5haX
|
|
5qXrJefnbmIEBv+2Yz8372C8tDH4EKMAB6MSDy9D7a44IdbEsuLK3EOMEhzMSiK8LZk744R4
|
|
UxIrq1KL8uOLSnNSiw8xmgIdNZFZSjQ5HxiZeSXxhqaG5haWhubG5sZmFkrivB0CB2OEBNIT
|
|
S1KzU1MLUotg+pg4OKUaGJPlvkyzyk+preH72cpxeeuD0O6oZUuNDc6o7P/6ZEOS840NPztO
|
|
zFocIGBSrq8toH7DTqlo+xFl5cUxn++VzqmJ1dnc+TTr4cFVZVYcppGhk4w3f/jD9fxs3+WL
|
|
Wnb8zSL+Ns2veIuTnb2qf8vebr9gOEl60xZ9E5XA+gz5i8fX7pF+yWCWpsRSnJFoqMVcVJwI
|
|
AL42I8OUAgAA
|
|
X-CMS-MailID: 20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae@eucas1p2.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
This patch adds basic driver PCI Express controller found on Broadcom
|
|
set-top-box SoCs, e.g. BCM2711.
|
|
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
|
|
handling removed. The inbound access memory region is not currently
|
|
parsed from dma-ranges DT property and a fixed 3GB region is used.
|
|
|
|
The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
|
|
USB Host Controller.
|
|
|
|
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
---
|
|
Changes since v2:
|
|
- removed MDO_RD_DONE, MDIO_WT_DONE macro definitions,
|
|
- updated the Kconfig entry help text,
|
|
- reordered #include entries to match the coding style,
|
|
- s/udev/dev,
|
|
- s/ENODEV/EINVAL in brcm_pcie_probe() and brcm_pcie_config_address()
|
|
functions,
|
|
- Simplified brcm_pcie_mdio_{read, write} functions (readl_poll_timeout),
|
|
- shortened register bit fields macro definitions,
|
|
- dropped brcm_pcie_perst_set() and brcm_pcie_bridge_sw_init_set()
|
|
function in favour of direct clrbits_le32/setbits_le32 calls,
|
|
- use setbits_le32/clrbits_le32/clrsetbits_le32 instead of
|
|
readl(), u32p_replace_bits(), writel() sequence
|
|
- simplified brcm_pcie_config_address(), brcm_pcie_set_gen() functions,
|
|
- changed reset pulse delay to 100 us,
|
|
- Replaced FIELD_GET() with open coded bitwise operations,
|
|
- brcm_cpie_cfg_index() function merged into brcm_pcie_config_address(),
|
|
- use standard PCI PCI_EXP_LNKSTA_CLS_* link speed defines
|
|
- added kernel-doc function comments.
|
|
|
|
Changes since v1:
|
|
- fixed argument in brcm_pcie_set_ssc() function call,
|
|
- changed rc_bar2_size assignment to value 0xC0000000, as in upstream
|
|
devicetree.
|
|
Changes since RFC:
|
|
- reworked to align with current Linux mainline version and u-boot
|
|
driver by Nicolas Saenz Julienne.
|
|
---
|
|
drivers/pci/Kconfig | 9 +
|
|
drivers/pci/Makefile | 1 +
|
|
drivers/pci/pcie_brcmstb.c | 623 +++++++++++++++++++++++++++++++++++++++++++++
|
|
3 files changed, 633 insertions(+)
|
|
create mode 100644 drivers/pci/pcie_brcmstb.c
|
|
|
|
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
|
|
index 437cd9a..543bd46 100644
|
|
--- a/drivers/pci/Kconfig
|
|
+++ b/drivers/pci/Kconfig
|
|
@@ -197,4 +197,13 @@ config PCIE_MEDIATEK
|
|
Say Y here if you want to enable Gen2 PCIe controller,
|
|
which could be found on MT7623 SoC family.
|
|
|
|
+config PCI_BRCMSTB
|
|
+ bool "Broadcom STB PCIe controller"
|
|
+ depends on DM_PCI
|
|
+ depends on ARCH_BCM283X
|
|
+ help
|
|
+ Say Y here if you want to enable support for PCIe controller
|
|
+ on Broadcom set-top-box (STB) SoCs.
|
|
+ This driver currently supports only BCM2711 SoC and RC mode
|
|
+ of the controller.
|
|
endif
|
|
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
|
|
index c051ecc..3e53b1f 100644
|
|
--- a/drivers/pci/Makefile
|
|
+++ b/drivers/pci/Makefile
|
|
@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
|
|
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
|
|
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
|
|
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
|
|
+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
|
|
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
|
|
new file mode 100644
|
|
index 0000000..dade79e
|
|
--- /dev/null
|
|
+++ b/drivers/pci/pcie_brcmstb.c
|
|
@@ -0,0 +1,623 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Broadcom STB PCIe controller driver
|
|
+ *
|
|
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
|
|
+ *
|
|
+ * Based on upstream Linux kernel driver:
|
|
+ * drivers/pci/controller/pcie-brcmstb.c
|
|
+ * Copyright (C) 2009 - 2017 Broadcom
|
|
+ *
|
|
+ * Based driver by Nicolas Saenz Julienne
|
|
+ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
|
+ */
|
|
+
|
|
+#include <common.h>
|
|
+#include <errno.h>
|
|
+#include <dm.h>
|
|
+#include <dm/ofnode.h>
|
|
+#include <pci.h>
|
|
+#include <asm/io.h>
|
|
+#include <linux/bitfield.h>
|
|
+#include <linux/log2.h>
|
|
+#include <linux/iopoll.h>
|
|
+
|
|
+/* Offset of the mandatory PCIe capability config registers */
|
|
+#define BRCM_PCIE_CAP_REGS 0x00ac
|
|
+
|
|
+/* The PCIe controller register offsets */
|
|
+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
|
|
+#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
|
|
+#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
|
|
+
|
|
+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
|
|
+#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
|
|
+
|
|
+#define PCIE_RC_DL_MDIO_ADDR 0x1100
|
|
+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
|
|
+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
|
|
+
|
|
+#define PCIE_MISC_MISC_CTRL 0x4008
|
|
+#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
|
|
+#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
|
|
+#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
|
|
+#define MISC_CTRL_MAX_BURST_SIZE_128 0x0
|
|
+#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
|
|
+
|
|
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
|
|
+#define PCIE_MEM_WIN0_LO(win) \
|
|
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
|
|
+
|
|
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
|
|
+#define PCIE_MEM_WIN0_HI(win) \
|
|
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
|
|
+
|
|
+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
|
|
+#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
|
|
+
|
|
+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
|
|
+#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
|
|
+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
|
|
+
|
|
+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
|
|
+#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
|
|
+
|
|
+#define PCIE_MISC_PCIE_STATUS 0x4068
|
|
+#define STATUS_PCIE_PORT_MASK 0x80
|
|
+#define STATUS_PCIE_PORT_SHIFT 7
|
|
+#define STATUS_PCIE_DL_ACTIVE_MASK 0x20
|
|
+#define STATUS_PCIE_DL_ACTIVE_SHIFT 5
|
|
+#define STATUS_PCIE_PHYLINKUP_MASK 0x10
|
|
+#define STATUS_PCIE_PHYLINKUP_SHIFT 4
|
|
+
|
|
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
|
|
+#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
|
|
+#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
|
|
+#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
|
|
+#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
|
|
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
|
|
+
|
|
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
|
|
+#define MEM_WIN0_BASE_HI_BASE_MASK 0xff
|
|
+#define PCIE_MEM_WIN0_BASE_HI(win) \
|
|
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
|
|
+
|
|
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
|
|
+#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
|
|
+#define PCIE_MEM_WIN0_LIMIT_HI(win) \
|
|
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
|
|
+
|
|
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
|
|
+#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
|
|
+#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
|
|
+
|
|
+#define PCIE_MSI_INTR2_CLR 0x4508
|
|
+#define PCIE_MSI_INTR2_MASK_SET 0x4510
|
|
+
|
|
+#define PCIE_EXT_CFG_DATA 0x8000
|
|
+
|
|
+#define PCIE_EXT_CFG_INDEX 0x9000
|
|
+#define PCIE_EXT_BUSNUM_SHIFT 20
|
|
+#define PCIE_EXT_SLOT_SHIFT 15
|
|
+#define PCIE_EXT_FUNC_SHIFT 12
|
|
+
|
|
+#define PCIE_RGR1_SW_INIT_1 0x9210
|
|
+#define RGR1_SW_INIT_1_PERST_MASK 0x1
|
|
+#define RGR1_SW_INIT_1_INIT_MASK 0x2
|
|
+
|
|
+/* PCIe parameters */
|
|
+#define BRCM_NUM_PCIE_OUT_WINS 4
|
|
+
|
|
+/* MDIO registers */
|
|
+#define MDIO_PORT0 0x0
|
|
+#define MDIO_DATA_MASK 0x7fffffff
|
|
+#define MDIO_DATA_SHIFT 0
|
|
+#define MDIO_PORT_MASK 0xf0000
|
|
+#define MDIO_PORT_SHIFT 16
|
|
+#define MDIO_REGAD_MASK 0xffff
|
|
+#define MDIO_REGAD_SHIFT 0
|
|
+#define MDIO_CMD_MASK 0xfff00000
|
|
+#define MDIO_CMD_SHIFT 20
|
|
+#define MDIO_CMD_READ 0x1
|
|
+#define MDIO_CMD_WRITE 0x0
|
|
+#define MDIO_DATA_DONE_MASK 0x80000000
|
|
+#define SSC_REGS_ADDR 0x1100
|
|
+#define SET_ADDR_OFFSET 0x1f
|
|
+#define SSC_CNTL_OFFSET 0x2
|
|
+#define SSC_CNTL_OVRD_EN_MASK 0x8000
|
|
+#define SSC_CNTL_OVRD_VAL_MASK 0x4000
|
|
+#define SSC_STATUS_OFFSET 0x1
|
|
+#define SSC_STATUS_SSC_MASK 0x400
|
|
+#define SSC_STATUS_SSC_SHIFT 10
|
|
+#define SSC_STATUS_PLL_LOCK_MASK 0x800
|
|
+#define SSC_STATUS_PLL_LOCK_SHIFT 11
|
|
+
|
|
+/**
|
|
+ * struct brcm_pcie - the PCIe controller state
|
|
+ * @base: Base address of memory mapped IO registers of the controller
|
|
+ * @gen: Non-zero value indicates limitation of the PCIe controller operation
|
|
+ * to a specific generation (1, 2 or 3)
|
|
+ * @ssc: true indicates active Spread Spectrum Clocking operation
|
|
+ */
|
|
+struct brcm_pcie {
|
|
+ void __iomem *base;
|
|
+
|
|
+ int gen;
|
|
+ bool ssc;
|
|
+};
|
|
+
|
|
+/**
|
|
+ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
|
|
+ * @size: The inbound region size
|
|
+ *
|
|
+ * This function converts size of the inbound "BAR" region to the non-linear
|
|
+ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
|
|
+ *
|
|
+ * Return: The encoded inbound region size
|
|
+ */
|
|
+static int brcm_pcie_encode_ibar_size(u64 size)
|
|
+{
|
|
+ int log2_in = ilog2(size);
|
|
+
|
|
+ if (log2_in >= 12 && log2_in <= 15)
|
|
+ /* Covers 4KB to 32KB (inclusive) */
|
|
+ return (log2_in - 12) + 0x1c;
|
|
+ else if (log2_in >= 16 && log2_in <= 37)
|
|
+ /* Covers 64KB to 32GB, (inclusive) */
|
|
+ return log2_in - 15;
|
|
+
|
|
+ /* Something is awry so disable */
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/**
|
|
+ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
|
|
+ * @pcie: Pointer to the PCIe controller state
|
|
+ *
|
|
+ * The controller is capable of serving in both RC and EP roles.
|
|
+ *
|
|
+ * Return: true for RC mode, false for EP mode.
|
|
+ */
|
|
+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
|
|
+{
|
|
+ u32 val;
|
|
+
|
|
+ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
|
|
+
|
|
+ return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
|
|
+}
|
|
+
|
|
+/**
|
|
+ * brcm_pcie_link_up() - Check whether the PCIe link is up
|
|
+ * @pcie: Pointer to the PCIe controller state
|
|
+ *
|
|
+ * Return: true if the link is up, false otherwise.
|
|
+ */
|
|
+static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
|
|
+{
|
|
+ u32 val, dla, plu;
|
|
+
|
|
+ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
|
|
+ dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
|
|
+ plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
|
|
+
|
|
+ return dla && plu;
|
|
+}
|
|
+
|
|
+static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
|
|
+ uint offset, void **paddress)
|
|
+{
|
|
+ struct brcm_pcie *pcie = dev_get_priv(dev);
|
|
+ unsigned int pci_bus = PCI_BUS(bdf);
|
|
+ unsigned int pci_dev = PCI_DEV(bdf);
|
|
+ unsigned int pci_func = PCI_FUNC(bdf);
|
|
+ int idx;
|
|
+
|
|
+ /*
|
|
+ * Busses 0 (host PCIe bridge) and 1 (its immediate child)
|
|
+ * are limited to a single device each
|
|
+ */
|
|
+ if (pci_bus < 2 && pci_dev > 0)
|
|
+ return -EINVAL;
|
|
+
|
|
+ /* Accesses to the RC go right to the RC registers */
|
|
+ if (pci_bus == 0) {
|
|
+ *paddress = pcie->base + offset;
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ /* For devices, write to the config space index register */
|
|
+ idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
|
|
+ | (pci_dev << PCIE_EXT_SLOT_SHIFT)
|
|
+ | (pci_func << PCIE_EXT_FUNC_SHIFT);
|
|
+
|
|
+ writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
|
|
+ *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
|
|
+ uint offset, ulong *valuep,
|
|
+ enum pci_size_t size)
|
|
+{
|
|
+ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
|
|
+ bdf, offset, valuep, size);
|
|
+}
|
|
+
|
|
+static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
|
|
+ uint offset, ulong value,
|
|
+ enum pci_size_t size)
|
|
+{
|
|
+ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
|
|
+ bdf, offset, value, size);
|
|
+}
|
|
+
|
|
+static const char *link_speed_to_str(unsigned int cls)
|
|
+{
|
|
+ switch (cls) {
|
|
+ case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
|
|
+ case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
|
|
+ case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
|
|
+ default:
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ return "??";
|
|
+}
|
|
+
|
|
+static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
|
|
+ unsigned int cmd)
|
|
+{
|
|
+ u32 pkt;
|
|
+
|
|
+ pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
|
|
+ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
|
|
+ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
|
|
+
|
|
+ return pkt;
|
|
+}
|
|
+
|
|
+/**
|
|
+ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
|
|
+ * @base: Pointer to the PCIe controller IO registers
|
|
+ * @port: The MDIO port number
|
|
+ * @regad: The register address
|
|
+ * @val: A pointer at which to store the read value
|
|
+ *
|
|
+ * Return: 0 on success and register value in @val, negative error value
|
|
+ * on failure.
|
|
+ */
|
|
+static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
|
|
+ unsigned int regad, u32 *val)
|
|
+{
|
|
+ u32 data, addr;
|
|
+ int ret;
|
|
+
|
|
+ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
|
|
+ writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
|
|
+ readl(base + PCIE_RC_DL_MDIO_ADDR);
|
|
+
|
|
+ ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
|
|
+ (data & MDIO_DATA_DONE_MASK), 100);
|
|
+
|
|
+ *val = data & MDIO_DATA_MASK;
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+/**
|
|
+ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
|
|
+ * @base: Pointer to the PCIe controller IO registers
|
|
+ * @port: The MDIO port number
|
|
+ * @regad: Address of the register
|
|
+ * @wrdata: The value to write
|
|
+ *
|
|
+ * Return: 0 on success, negative error value on failure.
|
|
+ */
|
|
+static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
|
|
+ unsigned int regad, u16 wrdata)
|
|
+{
|
|
+ u32 data, addr;
|
|
+
|
|
+ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
|
|
+ writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
|
|
+ readl(base + PCIE_RC_DL_MDIO_ADDR);
|
|
+ writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
|
|
+
|
|
+ return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
|
|
+ !(data & MDIO_DATA_DONE_MASK), 100);
|
|
+}
|
|
+
|
|
+/**
|
|
+ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
|
|
+ * @base: pointer to the PCIe controller IO registers
|
|
+ *
|
|
+ * Return: 0 on success, negative error value on failure.
|
|
+ */
|
|
+static int brcm_pcie_set_ssc(void __iomem *base)
|
|
+{
|
|
+ int pll, ssc;
|
|
+ int ret;
|
|
+ u32 tmp;
|
|
+
|
|
+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
|
|
+ SSC_REGS_ADDR);
|
|
+ if (ret < 0)
|
|
+ return ret;
|
|
+
|
|
+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
|
|
+ if (ret < 0)
|
|
+ return ret;
|
|
+
|
|
+ tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
|
|
+
|
|
+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
|
|
+ if (ret < 0)
|
|
+ return ret;
|
|
+
|
|
+ udelay(1000);
|
|
+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
|
|
+ if (ret < 0)
|
|
+ return ret;
|
|
+
|
|
+ ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
|
|
+ pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
|
|
+
|
|
+ return ssc && pll ? 0 : -EIO;
|
|
+}
|
|
+
|
|
+/**
|
|
+ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
|
|
+ * @pcie: pointer to the PCIe controller state
|
|
+ * @gen: PCIe generation to limit the controller's operation to
|
|
+ */
|
|
+static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
|
|
+{
|
|
+ void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
|
|
+
|
|
+ u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
|
|
+ u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
|
|
+
|
|
+ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
|
|
+ writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
|
|
+
|
|
+ lnkctl2 = (lnkctl2 & ~0xf) | gen;
|
|
+ writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
|
|
+}
|
|
+
|
|
+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
|
|
+ unsigned int win, u64 phys_addr,
|
|
+ u64 pcie_addr, u64 size)
|
|
+{
|
|
+ void __iomem *base = pcie->base;
|
|
+ u32 phys_addr_mb_high, limit_addr_mb_high;
|
|
+ phys_addr_t phys_addr_mb, limit_addr_mb;
|
|
+ int high_addr_shift;
|
|
+ u32 tmp;
|
|
+
|
|
+ /* Set the base of the pcie_addr window */
|
|
+ writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
|
|
+ writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
|
|
+
|
|
+ /* Write the addr base & limit lower bits (in MBs) */
|
|
+ phys_addr_mb = phys_addr / SZ_1M;
|
|
+ limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
|
|
+
|
|
+ tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
|
|
+ u32p_replace_bits(&tmp, phys_addr_mb,
|
|
+ MEM_WIN0_BASE_LIMIT_BASE_MASK);
|
|
+ u32p_replace_bits(&tmp, limit_addr_mb,
|
|
+ MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
|
|
+ writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
|
|
+
|
|
+ /* Write the cpu & limit addr upper bits */
|
|
+ high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
|
|
+ phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
|
|
+ tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
|
|
+ u32p_replace_bits(&tmp, phys_addr_mb_high,
|
|
+ MEM_WIN0_BASE_HI_BASE_MASK);
|
|
+ writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
|
|
+
|
|
+ limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
|
|
+ tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
|
|
+ u32p_replace_bits(&tmp, limit_addr_mb_high,
|
|
+ PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
|
|
+ writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
|
|
+}
|
|
+
|
|
+static int brcm_pcie_probe(struct udevice *dev)
|
|
+{
|
|
+ struct udevice *ctlr = pci_get_controller(dev);
|
|
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
|
+ struct brcm_pcie *pcie = dev_get_priv(dev);
|
|
+ void __iomem *base = pcie->base;
|
|
+ bool ssc_good = false;
|
|
+ int num_out_wins = 0;
|
|
+ u64 rc_bar2_offset, rc_bar2_size;
|
|
+ unsigned int scb_size_val;
|
|
+ int i, ret;
|
|
+ u16 nlw, cls, lnksta;
|
|
+ u32 tmp;
|
|
+
|
|
+ /*
|
|
+ * Reset the bridge, assert the fundamental reset. Note for some SoCs,
|
|
+ * e.g. BCM7278, the fundamental reset should not be asserted here.
|
|
+ * This will need to be changed when support for other SoCs is added.
|
|
+ */
|
|
+ setbits_le32(base + PCIE_RGR1_SW_INIT_1,
|
|
+ RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
|
|
+ /*
|
|
+ * The delay is a safety precaution to preclude the reset signal
|
|
+ * from looking like a glitch.
|
|
+ */
|
|
+ udelay(100);
|
|
+
|
|
+ /* Take the bridge out of reset */
|
|
+ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
|
|
+
|
|
+ clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
|
|
+ PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
|
|
+
|
|
+ /* Wait for SerDes to be stable */
|
|
+ udelay(100);
|
|
+
|
|
+ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
|
|
+ clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
|
|
+ MISC_CTRL_MAX_BURST_SIZE_MASK,
|
|
+ MISC_CTRL_SCB_ACCESS_EN_MASK |
|
|
+ MISC_CTRL_CFG_READ_UR_MODE_MASK |
|
|
+ MISC_CTRL_MAX_BURST_SIZE_128);
|
|
+ /*
|
|
+ * TODO: When support for other SoCs than BCM2711 is added we may
|
|
+ * need to use the base address and size(s) provided in the dma-ranges
|
|
+ * property.
|
|
+ */
|
|
+ rc_bar2_offset = 0;
|
|
+ rc_bar2_size = 0xc0000000;
|
|
+
|
|
+ tmp = lower_32_bits(rc_bar2_offset);
|
|
+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
|
|
+ RC_BAR2_CONFIG_LO_SIZE_MASK);
|
|
+ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
|
|
+ writel(upper_32_bits(rc_bar2_offset),
|
|
+ base + PCIE_MISC_RC_BAR2_CONFIG_HI);
|
|
+
|
|
+ scb_size_val = rc_bar2_size ?
|
|
+ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
|
|
+
|
|
+ tmp = readl(base + PCIE_MISC_MISC_CTRL);
|
|
+ u32p_replace_bits(&tmp, scb_size_val,
|
|
+ MISC_CTRL_SCB0_SIZE_MASK);
|
|
+ writel(tmp, base + PCIE_MISC_MISC_CTRL);
|
|
+
|
|
+ /* Disable the PCIe->GISB memory window (RC_BAR1) */
|
|
+ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
|
|
+ RC_BAR1_CONFIG_LO_SIZE_MASK);
|
|
+
|
|
+ /* Disable the PCIe->SCB memory window (RC_BAR3) */
|
|
+ clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
|
|
+ RC_BAR3_CONFIG_LO_SIZE_MASK);
|
|
+
|
|
+ /* Mask all interrupts since we are not handling any yet */
|
|
+ writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
|
|
+
|
|
+ /* Clear any interrupts we find on boot */
|
|
+ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
|
|
+
|
|
+ if (pcie->gen)
|
|
+ brcm_pcie_set_gen(pcie, pcie->gen);
|
|
+
|
|
+ /* Unassert the fundamental reset */
|
|
+ clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
|
|
+ RGR1_SW_INIT_1_PERST_MASK);
|
|
+
|
|
+ /* Give the RC/EP time to wake up, before trying to configure RC.
|
|
+ * Intermittently check status for link-up, up to a total of 100ms.
|
|
+ */
|
|
+ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
|
|
+ mdelay(5);
|
|
+
|
|
+ if (!brcm_pcie_link_up(pcie)) {
|
|
+ printf("PCIe BRCM: link down\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if (!brcm_pcie_rc_mode(pcie)) {
|
|
+ printf("PCIe misconfigured; is in EP mode\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < hose->region_count; i++) {
|
|
+ struct pci_region *reg = &hose->regions[i];
|
|
+
|
|
+ if (reg->flags != PCI_REGION_MEM)
|
|
+ continue;
|
|
+
|
|
+ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
|
|
+ return -EINVAL;
|
|
+
|
|
+ brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
|
|
+ reg->bus_start, reg->size);
|
|
+
|
|
+ num_out_wins++;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * For config space accesses on the RC, show the right class for
|
|
+ * a PCIe-PCIe bridge (the default setting is to be EP mode).
|
|
+ */
|
|
+ clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
|
|
+ CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
|
|
+
|
|
+ if (pcie->ssc) {
|
|
+ ret = brcm_pcie_set_ssc(pcie->base);
|
|
+ if (!ret)
|
|
+ ssc_good = true;
|
|
+ else
|
|
+ printf("PCIe BRCM: failed attempt to enter SSC mode\n");
|
|
+ }
|
|
+
|
|
+ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
|
|
+ cls = lnksta & PCI_EXP_LNKSTA_CLS;
|
|
+ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
|
|
+
|
|
+ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
|
|
+ nlw, ssc_good ? "(SSC)" : "(!SSC)");
|
|
+
|
|
+ /* PCIe->SCB endian mode for BAR */
|
|
+ clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
|
|
+ VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
|
|
+ VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
|
|
+ /*
|
|
+ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
|
|
+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
|
|
+ */
|
|
+ setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
|
|
+ PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int brcm_pcie_ofdata_to_platdata(struct udevice *dev)
|
|
+{
|
|
+ struct brcm_pcie *pcie = dev_get_priv(dev);
|
|
+ ofnode dn = dev_ofnode(dev);
|
|
+ u32 max_link_speed;
|
|
+ int ret;
|
|
+
|
|
+ /* Get the controller base address */
|
|
+ pcie->base = dev_read_addr_ptr(dev);
|
|
+ if (!pcie->base)
|
|
+ return -EINVAL;
|
|
+
|
|
+ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
|
|
+
|
|
+ ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
|
|
+ if (ret < 0 || max_link_speed > 4)
|
|
+ pcie->gen = 0;
|
|
+ else
|
|
+ pcie->gen = max_link_speed;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct dm_pci_ops brcm_pcie_ops = {
|
|
+ .read_config = brcm_pcie_read_config,
|
|
+ .write_config = brcm_pcie_write_config,
|
|
+};
|
|
+
|
|
+static const struct udevice_id brcm_pcie_ids[] = {
|
|
+ { .compatible = "brcm,bcm2711-pcie" },
|
|
+ { }
|
|
+};
|
|
+
|
|
+U_BOOT_DRIVER(pcie_brcm_base) = {
|
|
+ .name = "pcie_brcm",
|
|
+ .id = UCLASS_PCI,
|
|
+ .ops = &brcm_pcie_ops,
|
|
+ .of_match = brcm_pcie_ids,
|
|
+ .probe = brcm_pcie_probe,
|
|
+ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata,
|
|
+ .priv_auto_alloc_size = sizeof(struct brcm_pcie),
|
|
+};
|
|
|
|
From patchwork Tue May 12 18:47:16 2020
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
X-Patchwork-Submitter: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
X-Patchwork-Id: 1288735
|
|
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
X-Original-To: incoming@patchwork.ozlabs.org
|
|
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
|
|
Authentication-Results: ozlabs.org;
|
|
spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
|
|
(client-ip=85.214.62.61; helo=phobos.denx.de;
|
|
envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
|
|
Authentication-Results: ozlabs.org;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256
|
|
header.s=mail20170921 header.b=cv2KHkH+;
|
|
dkim-atps=neutral
|
|
Received: from phobos.denx.de (phobos.denx.de [85.214.62.61])
|
|
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
|
|
key-exchange X25519 server-signature RSA-PSS (4096 bits))
|
|
(No client certificate requested)
|
|
by ozlabs.org (Postfix) with ESMTPS id 49M6Kw6S8rz9sRR
|
|
for <incoming@patchwork.ozlabs.org>; Wed, 13 May 2020 04:49:40 +1000 (AEST)
|
|
Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
|
|
by phobos.denx.de (Postfix) with ESMTP id 6561C81D0C;
|
|
Tue, 12 May 2020 20:48:50 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
|
|
Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
|
|
unprotected) header.d=samsung.com header.i=@samsung.com header.b="cv2KHkH+";
|
|
dkim-atps=neutral
|
|
Received: by phobos.denx.de (Postfix, from userid 109)
|
|
id C928581D0C; Tue, 12 May 2020 20:48:47 +0200 (CEST)
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
|
|
X-Spam-Level:
|
|
X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
|
|
DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3,
|
|
RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham
|
|
autolearn_force=no version=3.4.2
|
|
Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com
|
|
[210.118.77.12])
|
|
(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))
|
|
(No client certificate requested)
|
|
by phobos.denx.de (Postfix) with ESMTPS id A273781CE3
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 20:48:44 +0200 (CEST)
|
|
Authentication-Results: phobos.denx.de;
|
|
dmarc=pass (p=none dis=none) header.from=samsung.com
|
|
Authentication-Results: phobos.denx.de;
|
|
spf=pass smtp.mailfrom=s.nawrocki@samsung.com
|
|
Received: from eucas1p2.samsung.com (unknown [182.198.249.207])
|
|
by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184844euoutp02e55ba929fd9f79911a420a566ce0e756~OXGjzHTY40461204612euoutp028
|
|
for <u-boot@lists.denx.de>; Tue, 12 May 2020 18:48:44 +0000 (GMT)
|
|
DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com
|
|
20200512184844euoutp02e55ba929fd9f79911a420a566ce0e756~OXGjzHTY40461204612euoutp028
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com;
|
|
s=mail20170921; t=1589309324;
|
|
bh=hzK/mVSsiHm3Pc+zxgVzX6oxEFhxHphU75wkCaQSwV4=;
|
|
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
|
|
b=cv2KHkH+WRTNWeHkLSgxvaKrbRdv4aXDBJ9rm82p9sUIKoZ2ZUWHIBjiSVlx4KkeE
|
|
fEVI2vFzo+mNlTVnEelEvDqFzVOXb6dvim6uuExIcjBm08RtCT6hIIYdvb01II9zw8
|
|
4YrLGyDb5u4RQ0w28BrdUJzxip35lr+/ro5y+Xgw=
|
|
Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by
|
|
eucas1p2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184843eucas1p2ba3d75b717bad767d94d483b4c7ce11d~OXGix0EoA0735307353eucas1p2x;
|
|
Tue, 12 May 2020 18:48:43 +0000 (GMT)
|
|
Received: from eucas1p1.samsung.com ( [182.198.249.206]) by
|
|
eusmges1new.samsung.com (EUCPMTA) with SMTP id CF.FF.61286.B8FEABE5; Tue, 12
|
|
May 2020 19:48:43 +0100 (BST)
|
|
Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by
|
|
eucas1p1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184842eucas1p1b2edc2128ddf134553805db77451648f~OXGhrdRbd2314823148eucas1p1D;
|
|
Tue, 12 May 2020 18:48:42 +0000 (GMT)
|
|
Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by
|
|
eusmtrp2.samsung.com (KnoxPortal) with ESMTP id
|
|
20200512184842eusmtrp2c531b7ae799511a665083c7202f8cf1c~OXGhqxf_u1654916549eusmtrp2q;
|
|
Tue, 12 May 2020 18:48:42 +0000 (GMT)
|
|
X-AuditID: cbfec7f2-ef1ff7000001ef66-99-5ebaef8bc506
|
|
Received: from eusmtip1.samsung.com ( [203.254.199.221]) by
|
|
eusmgms2.samsung.com (EUCPMTA) with SMTP id 35.F8.07950.98FEABE5; Tue, 12
|
|
May 2020 19:48:41 +0100 (BST)
|
|
Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by
|
|
eusmtip1.samsung.com (KnoxPortal) with ESMTPA id
|
|
20200512184841eusmtip10bf41891c807e8917bd954874636d5ef~OXGhLVMJk2778327783eusmtip1X;
|
|
Tue, 12 May 2020 18:48:41 +0000 (GMT)
|
|
From: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com
|
|
Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org,
|
|
jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com,
|
|
Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
Subject: [PATCH v3 9/9] configs: Enable support for the XHCI controller on
|
|
RPI4 board (ARM 64-bit)
|
|
Date: Tue, 12 May 2020 20:47:16 +0200
|
|
Message-Id: <20200512184716.2869-10-s.nawrocki@samsung.com>
|
|
X-Mailer: git-send-email 2.17.1
|
|
In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG/XbO2Y7T2WlafqhgDIMUUkdGpxRNKDp/Cl3+CFJnO03Jqeyo
|
|
ZREtlXm/oJi2UMeMzKlt5ZrXYaw2K9FUugzULJBMmdjFC2q0th2t/37v8z4Pz8vHhyNCDRaE
|
|
Z2Tl0oosSaaIy0dNts3xwxUrA8nRb3t9yCdNeoxsqEwhzY4aLmnfUmFk98tZHulQ3QGkpn4e
|
|
I03qdi75wlGCketGEyCXzWW8kz6Uem6MS91XTqJUi/oVSvWrZ3nU2EwfoKqNOkDpje9Rqmf0
|
|
ZhJ+kR8npTMz8mlFVHwqP326YRjLMfldn2i1Y0rQ6lsOvHFIxMB7IypQDvi4kHgE4JRFi7DD
|
|
KoCLPYUcdvjl2qzVcHcjXUPOHVc7gENjX7n/IssTHZjbxSXEsMpaDdwcQCTBD5t3PSUIYQWw
|
|
a/g36l74E1K4al7wMEochHXlhZ4KARELrYZBjK0LhZ2G54ibvV36xx6bpxoSD3mwaFMLWNMp
|
|
+KZxfYf94dKIkcdyCHT2t3LYQBGAlYPTPHaoBXBuRLOTiIUz41uuatx1XzjUD0SxciJcMDs4
|
|
bhkSftC+vNctIy6sMzUirCyApSoh6w6D27pGDstBsGLeibJMwS9l7Sj7QtUATsxUgVoQqv5f
|
|
pgFABwLpPEYuoxlxFn0tkpHImbwsWeTlbPlT4Po3o39GfvaBtak0CyBwIPIVeN0aSBZiknym
|
|
QG4BEEdEAYLijP5koUAqKbhBK7JTFHmZNGMBwTgqChQc0S5eEhIySS59laZzaMXuloN7BymB
|
|
cKWgqiXttOJBRaU+xkboTQm+VRPbD3jhne+WnKU2wQG5jFvS9v3E6meDoAy90pEabN5TH5cQ
|
|
0db7rXnKdMgAa5uRpo3l2LP7DUfrZn9sKJtrzr0+XxQUPVZ83P/ZGXviBeUnzT7d427oEzZw
|
|
W+wVptjWTlrVHevxxxhpSHaeCGXSJeIIRMFI/gJkR9I/MwMAAA==
|
|
X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7qd73fFGVxeZWOxccZ6VoupPfEW
|
|
e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs
|
|
HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF
|
|
G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GXcnrqftWAbX8WF+TdYGxjn83Qx
|
|
cnJICJhIrNnzn7mLkYtDSGApo8TXHX1sXYwcQAkpifktShA1whJ/rnWxQdR8YpSY9PMgK0iC
|
|
TcBQovdoHyOILSIQIvHi6BUmkCJmgbOMEos6P4AVCQskSczvPccOYrMIqEpM6mpiA7F5Bawl
|
|
jm7YzQqxQV5i9YYDzCA2J1D8+uZjYLaQgJXEnm/v2CYw8i1gZFjFKJJaWpybnltspFecmFtc
|
|
mpeul5yfu4kRGPjbjv3csoOx613wIUYBDkYlHt6I+l1xQqyJZcWVuYcYJTiYlUR4WzJ3xgnx
|
|
piRWVqUW5ccXleakFh9iNAU6aiKzlGhyPjAq80riDU0NzS0sDc2NzY3NLJTEeTsEDsYICaQn
|
|
lqRmp6YWpBbB9DFxcEo1MJZuMOdQWFlcxNH1cnlrV4CI9YveFVpbur+ZL3998nbrx5IJO+5v
|
|
NQnONn+wO4m3/3tYYOTuoMvVPAmZDS/anbJea/5TzOpcFnR9x5G3L0zaRfS23RPYadWx1kVi
|
|
pvyV8/EB7wQLzOxvdPXy3agLUd4qc0Q9xNdok+uL3ZJbS/2Wpfa8TVjxTomlOCPRUIu5qDgR
|
|
ANQtnEOSAgAA
|
|
X-CMS-MailID: 20200512184842eucas1p1b2edc2128ddf134553805db77451648f
|
|
X-Msg-Generator: CA
|
|
X-RootMTR: 20200512184842eucas1p1b2edc2128ddf134553805db77451648f
|
|
X-EPHeader: CA
|
|
CMS-TYPE: 201P
|
|
X-CMS-RootMailID: 20200512184842eucas1p1b2edc2128ddf134553805db77451648f
|
|
References: <20200512184716.2869-1-s.nawrocki@samsung.com>
|
|
<CGME20200512184842eucas1p1b2edc2128ddf134553805db77451648f@eucas1p1.samsung.com>
|
|
X-BeenThere: u-boot@lists.denx.de
|
|
X-Mailman-Version: 2.1.30rc1
|
|
Precedence: list
|
|
List-Id: U-Boot discussion <u-boot.lists.denx.de>
|
|
List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
|
|
List-Archive: <https://lists.denx.de/pipermail/u-boot/>
|
|
List-Post: <mailto:u-boot@lists.denx.de>
|
|
List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
|
|
List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
|
|
<mailto:u-boot-request@lists.denx.de?subject=subscribe>
|
|
Errors-To: u-boot-bounces@lists.denx.de
|
|
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
|
|
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
X-Virus-Status: Clean
|
|
|
|
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
|
|
and USB commands. To get it working one has to call the following commands:
|
|
"pci enum; usb start;", thus such commands have been added to the default
|
|
"preboot" environment variable. One has to update their environment if it
|
|
is already configured to get this feature working out of the box.
|
|
|
|
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
|
|
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
|
---
|
|
Changes since v2:
|
|
- rpi_4_32b_defconfig, rpi_4_defconfig changes moved to separate
|
|
patch
|
|
Changes since v1:
|
|
- removed unneeded CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY entry.
|
|
|
|
Changes since RFC:
|
|
- none.
|
|
---
|
|
configs/rpi_arm64_defconfig | 8 +++++++-
|
|
1 file changed, 7 insertions(+), 1 deletion(-)
|
|
|
|
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
|
|
index fea86be..f12d1e3 100644
|
|
--- a/configs/rpi_arm64_defconfig
|
|
+++ b/configs/rpi_arm64_defconfig
|
|
@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2
|
|
CONFIG_DISTRO_DEFAULTS=y
|
|
CONFIG_OF_BOARD_SETUP=y
|
|
CONFIG_USE_PREBOOT=y
|
|
-CONFIG_PREBOOT="usb start"
|
|
+CONFIG_PREBOOT="pci enum; usb start;"
|
|
CONFIG_MISC_INIT_R=y
|
|
# CONFIG_DISPLAY_CPUINFO is not set
|
|
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
CONFIG_SYS_PROMPT="U-Boot> "
|
|
CONFIG_CMD_GPIO=y
|
|
CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_PCI=y
|
|
CONFIG_CMD_USB=y
|
|
CONFIG_CMD_FS_UUID=y
|
|
CONFIG_OF_BOARD=y
|
|
@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y
|
|
CONFIG_MMC_SDHCI_BCM2835=y
|
|
CONFIG_DM_ETH=y
|
|
CONFIG_BCMGENET=y
|
|
+CONFIG_PCI=y
|
|
+CONFIG_DM_PCI=y
|
|
+CONFIG_PCI_BRCMSTB=y
|
|
CONFIG_PINCTRL=y
|
|
# CONFIG_PINCTRL_GENERIC is not set
|
|
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
|
|
CONFIG_USB=y
|
|
CONFIG_DM_USB=y
|
|
+CONFIG_USB_XHCI_HCD=y
|
|
+CONFIG_USB_XHCI_PCI=y
|
|
CONFIG_USB_DWC2=y
|
|
CONFIG_USB_KEYBOARD=y
|
|
CONFIG_USB_HOST_ETHER=y
|