921 lines
24 KiB
Diff
921 lines
24 KiB
Diff
From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Sat, 31 Dec 2022 09:20:34 +0000
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Subject: [PATCH v2 0/2] Initial support for Pinephone Pro
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This adds initial support for the PINE64 Pinephone Pro. It's a rebase
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to upstream core rk3399 DT pieces, and the addition of the upstream
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PPP DT from 6.2-rc1 and the U-Boot pieces are based on my work on
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the Pinebook Pro.
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Changes v2:
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- Drop the rk3399.dtsi sync for time being, causing issues around
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clock/dram
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- Sync the Pinephone DT to 6.2-rc1
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- Update for the CONFIG_SYS_TEXT_BASE -> CONFIG_TEXT_BASE change
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- usb: ohci: Use a flexible array member for portstatus
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- Rename CONFIG_DM_VIDEO to CONFIG_VIDEO
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- Enable DM_REGULATOR_FAN53555
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- Don't initialize i2c before relocation
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Peter Robinson (2):
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arm64: dts: rk3399: Add upstream Pinephone Pro dts
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rockchip: Add initial support for the PINE64 Pinephone Pro
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arch/arm/dts/Makefile | 1 +
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arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++
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arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++
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arch/arm/mach-rockchip/rk3399/Kconfig | 8 +
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board/pine64/pinephone-pro-rk3399/Kconfig | 15 +
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board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 +
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board/pine64/pinephone-pro-rk3399/Makefile | 1 +
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.../pinephone-pro-rk3399.c | 76 +++
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configs/pinephone-pro-rk3399_defconfig | 104 ++++
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include/configs/pinephone-pro-rk3399.h | 19 +
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10 files changed, 737 insertions(+)
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create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts
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create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig
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create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS
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create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile
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create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
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create mode 100644 configs/pinephone-pro-rk3399_defconfig
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create mode 100644 include/configs/pinephone-pro-rk3399.h
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--
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2.39.0
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From 9976caacb35316cbe047ded58855d2ca1a54243b Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Sat, 31 Dec 2022 09:18:44 +0000
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Subject: [PATCH v2 1/2] arm64: dts: rk3399: Add upstream Pinephone Pro dts
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Initial support for the PinePhone Pro has now landed upstream in
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Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support.
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Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
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---
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arch/arm/dts/Makefile | 1 +
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arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++++++++++
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2 files changed, 475 insertions(+)
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create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 43951a7731e..8c1eec1025f 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -153,6 +153,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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rk3399-nanopi-r4s.dtb \
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rk3399-orangepi.dtb \
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rk3399-pinebook-pro.dtb \
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+ rk3399-pinephone-pro.dtb \
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rk3399-puma-haikou.dtb \
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rk3399-roc-pc.dtb \
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rk3399-roc-pc-mezzanine.dtb \
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diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts
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new file mode 100644
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index 00000000000..04403a76238
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--- /dev/null
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+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
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@@ -0,0 +1,474 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2020 Martijn Braam <martijn@brixit.nl>
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+ * Copyright (c) 2021 Kamil Trzciński <ayufan@ayufan.eu>
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+ */
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+
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+/*
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+ * PinePhone Pro datasheet:
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+ * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf
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+ */
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+
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+/dts-v1/;
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+#include <dt-bindings/input/linux-event-codes.h>
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+#include "rk3399.dtsi"
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+#include "rk3399-opp.dtsi"
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+
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+/ {
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+ model = "Pine64 PinePhonePro";
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+ compatible = "pine64,pinephone-pro", "rockchip,rk3399";
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+ chassis-type = "handset";
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+
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+ aliases {
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+ mmc0 = &sdio0;
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+ mmc1 = &sdmmc;
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+ mmc2 = &sdhci;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial2:115200n8";
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwrbtn_pin>;
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+
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+ key-power {
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+ debounce-interval = <20>;
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+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
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+ label = "Power";
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+ linux,code = <KEY_POWER>;
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+ wakeup-source;
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+ };
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+ };
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+
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+ vcc_sys: vcc-sys-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ vcc3v3_sys: vcc3v3-sys-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_sys>;
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+ };
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+
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+ vcca1v8_s3: vcc1v8-s3-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcca1v8_s3";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ vin-supply = <&vcc3v3_sys>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ vcc1v8_codec: vcc1v8-codec-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc1v8_codec_en>;
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+ regulator-name = "vcc1v8_codec";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ vin-supply = <&vcc3v3_sys>;
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+ };
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+
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+ wifi_pwrseq: sdio-wifi-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rk818 1>;
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+ clock-names = "ext_clock";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wifi_enable_h_pin>;
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+ /*
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+ * Wait between power-on and SDIO access for CYP43455
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+ * POR circuit.
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+ */
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+ post-power-on-delay-ms = <110>;
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+ /*
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+ * Wait between consecutive toggles for CYP43455 CBUCK
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+ * regulator discharge.
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+ */
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+ power-off-delay-us = <10000>;
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+
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+ /* WL_REG_ON on module */
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+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
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+ };
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+};
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+
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+&cpu_l0 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_l1 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_l2 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_l3 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_b0 {
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+ cpu-supply = <&vdd_cpu_b>;
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+};
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+
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+&cpu_b1 {
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+ cpu-supply = <&vdd_cpu_b>;
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+};
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+
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+&emmc_phy {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ clock-frequency = <400000>;
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+ i2c-scl-rising-time-ns = <168>;
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+ i2c-scl-falling-time-ns = <4>;
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+ status = "okay";
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+
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+ rk818: pmic@1c {
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+ compatible = "rockchip,rk818";
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+ reg = <0x1c>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk808-clkout2";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pmic_int_l>;
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+
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+ vcc1-supply = <&vcc_sys>;
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+ vcc2-supply = <&vcc_sys>;
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+ vcc3-supply = <&vcc_sys>;
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+ vcc4-supply = <&vcc_sys>;
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+ vcc6-supply = <&vcc_sys>;
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+ vcc7-supply = <&vcc3v3_sys>;
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+ vcc8-supply = <&vcc_sys>;
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+ vcc9-supply = <&vcc3v3_sys>;
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+
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+ regulators {
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+ vdd_cpu_l: DCDC_REG1 {
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+ regulator-name = "vdd_cpu_l";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <875000>;
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+ regulator-max-microvolt = <975000>;
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+ regulator-ramp-delay = <6001>;
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vdd_center: DCDC_REG2 {
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+ regulator-name = "vdd_center";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <800000>;
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+ regulator-max-microvolt = <1000000>;
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+ regulator-ramp-delay = <6001>;
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-name = "vcc_ddr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_1v8: DCDC_REG4 {
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+ regulator-name = "vcc_1v8";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcca3v0_codec: LDO_REG1 {
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+ regulator-name = "vcca3v0_codec";
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+ regulator-min-microvolt = <3000000>;
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+ regulator-max-microvolt = <3000000>;
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+ };
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+
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+ vcc3v0_touch: LDO_REG2 {
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+ regulator-name = "vcc3v0_touch";
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+ regulator-min-microvolt = <3000000>;
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+ regulator-max-microvolt = <3000000>;
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+ };
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+
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+ vcca1v8_codec: LDO_REG3 {
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+ regulator-name = "vcca1v8_codec";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ };
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+
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+ rk818_pwr_on: LDO_REG4 {
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+ regulator-name = "rk818_pwr_on";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_3v0: LDO_REG5 {
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+ regulator-name = "vcc_3v0";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3000000>;
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+ regulator-max-microvolt = <3000000>;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_1v5: LDO_REG6 {
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+ regulator-name = "vcc_1v5";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1500000>;
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+ regulator-max-microvolt = <1500000>;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc1v8_dvp: LDO_REG7 {
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+ regulator-name = "vcc1v8_dvp";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ };
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+
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+ vcc3v3_s3: LDO_REG8 {
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+ regulator-name = "vcc3v3_s3";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
|
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+ };
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+
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+ vccio_sd: LDO_REG9 {
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+ regulator-name = "vccio_sd";
|
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+ regulator-min-microvolt = <1800000>;
|
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+ regulator-max-microvolt = <3300000>;
|
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+ };
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+
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+ vcc3v3_s0: SWITCH_REG {
|
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+ regulator-name = "vcc3v3_s0";
|
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+ regulator-always-on;
|
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+ regulator-boot-on;
|
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+ regulator-state-mem {
|
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+ regulator-on-in-suspend;
|
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+ };
|
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+ };
|
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+ };
|
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+ };
|
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+
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+ vdd_cpu_b: regulator@40 {
|
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+ compatible = "silergy,syr827";
|
|
+ reg = <0x40>;
|
|
+ fcs,suspend-voltage-selector = <1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&vsel1_pin>;
|
|
+ regulator-name = "vdd_cpu_b";
|
|
+ regulator-min-microvolt = <875000>;
|
|
+ regulator-max-microvolt = <1150000>;
|
|
+ regulator-ramp-delay = <1000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+
|
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+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
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+ vdd_gpu: regulator@41 {
|
|
+ compatible = "silergy,syr828";
|
|
+ reg = <0x41>;
|
|
+ fcs,suspend-voltage-selector = <1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&vsel2_pin>;
|
|
+ regulator-name = "vdd_gpu";
|
|
+ regulator-min-microvolt = <875000>;
|
|
+ regulator-max-microvolt = <975000>;
|
|
+ regulator-ramp-delay = <1000>;
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+
|
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+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&cluster0_opp {
|
|
+ opp04 {
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ opp05 {
|
|
+ status = "disabled";
|
|
+ };
|
|
+};
|
|
+
|
|
+&cluster1_opp {
|
|
+ opp06 {
|
|
+ opp-hz = /bits/ 64 <1500000000>;
|
|
+ opp-microvolt = <1100000 1100000 1150000>;
|
|
+ };
|
|
+
|
|
+ opp07 {
|
|
+ status = "disabled";
|
|
+ };
|
|
+};
|
|
+
|
|
+&io_domains {
|
|
+ bt656-supply = <&vcc1v8_dvp>;
|
|
+ audio-supply = <&vcca1v8_codec>;
|
|
+ sdmmc-supply = <&vccio_sd>;
|
|
+ gpio1830-supply = <&vcc_3v0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pmu_io_domains {
|
|
+ pmu1830-supply = <&vcc_1v8>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ buttons {
|
|
+ pwrbtn_pin: pwrbtn-pin {
|
|
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ pmic_int_l: pmic-int-l {
|
|
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ vsel1_pin: vsel1-pin {
|
|
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+
|
|
+ vsel2_pin: vsel2-pin {
|
|
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdio-pwrseq {
|
|
+ wifi_enable_h_pin: wifi-enable-h-pin {
|
|
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sound {
|
|
+ vcc1v8_codec_en: vcc1v8-codec-en {
|
|
+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wireless-bluetooth {
|
|
+ bt_wake_pin: bt-wake-pin {
|
|
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ bt_host_wake_pin: bt-host-wake-pin {
|
|
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ bt_reset_pin: bt-reset-pin {
|
|
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdio0 {
|
|
+ bus-width = <4>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-sdio-irq;
|
|
+ disable-wp;
|
|
+ keep-power-in-suspend;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ non-removable;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
|
+ sd-uhs-sdr104;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc {
|
|
+ bus-width = <4>;
|
|
+ cap-sd-highspeed;
|
|
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
|
+ disable-wp;
|
|
+ max-frequency = <150000000>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
|
+ vmmc-supply = <&vcc3v3_sys>;
|
|
+ vqmmc-supply = <&vccio_sd>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ bus-width = <8>;
|
|
+ mmc-hs200-1_8v;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ rockchip,hw-tshut-mode = <1>;
|
|
+ rockchip,hw-tshut-polarity = <1>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
|
+ uart-has-rtscts;
|
|
+ status = "okay";
|
|
+
|
|
+ bluetooth {
|
|
+ compatible = "brcm,bcm4345c5";
|
|
+ clocks = <&rk818 1>;
|
|
+ clock-names = "lpo";
|
|
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
|
|
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
|
+ max-speed = <1500000>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>;
|
|
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
|
+ vbat-supply = <&vcc3v3_sys>;
|
|
+ vddio-supply = <&vcc_1v8>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ status = "okay";
|
|
+};
|
|
--
|
|
2.39.0
|
|
|
|
From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001
|
|
From: Peter Robinson <pbrobinson@gmail.com>
|
|
Date: Wed, 28 Dec 2022 03:52:27 +0000
|
|
Subject: [PATCH v2 2/2] rockchip: Add initial support for the PINE64 Pinephone
|
|
Pro
|
|
|
|
The Pinephone Pro is another device by PINE64. It's closely related
|
|
to the Pinebook Pro of which this initial support is derived from.
|
|
|
|
Specification:
|
|
- A variant of the Rockchip RK3399
|
|
- A 6 inch 720*1440 DSI display
|
|
- Front and rear cameras
|
|
- Type-C interface with alt mode display (DP 1.2) and PD charging
|
|
- 4GB LPDDR4 RAM
|
|
- 128GB eMMC
|
|
- mSD card slot
|
|
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
|
|
- Quectel EG25-G 4G/LTE modem
|
|
|
|
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
|
---
|
|
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++++++
|
|
arch/arm/mach-rockchip/rk3399/Kconfig | 8 ++
|
|
board/pine64/pinephone-pro-rk3399/Kconfig | 15 +++
|
|
board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 ++
|
|
board/pine64/pinephone-pro-rk3399/Makefile | 1 +
|
|
.../pinephone-pro-rk3399.c | 76 +++++++++++++
|
|
configs/pinephone-pro-rk3399_defconfig | 104 ++++++++++++++++++
|
|
include/configs/pinephone-pro-rk3399.h | 19 ++++
|
|
8 files changed, 262 insertions(+)
|
|
create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
|
|
create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig
|
|
create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS
|
|
create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile
|
|
create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
|
|
create mode 100644 configs/pinephone-pro-rk3399_defconfig
|
|
create mode 100644 include/configs/pinephone-pro-rk3399.h
|
|
|
|
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
|
|
new file mode 100644
|
|
index 00000000000..1dad283ad05
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
|
|
@@ -0,0 +1,31 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+
|
|
+/*
|
|
+ * Copyright (C) 2022 Peter Robinson <pbrobinson at gmail.com>
|
|
+ */
|
|
+
|
|
+#include "rk3399-u-boot.dtsi"
|
|
+#include "rk3399-sdram-lpddr4-100.dtsi"
|
|
+
|
|
+/ {
|
|
+ chosen {
|
|
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
|
+ };
|
|
+
|
|
+ config {
|
|
+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
|
|
+ };
|
|
+};
|
|
+
|
|
+&rng {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ max-frequency = <25000000>;
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
+
|
|
+&sdmmc {
|
|
+ max-frequency = <20000000>;
|
|
+ u-boot,dm-pre-reloc;
|
|
+};
|
|
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
|
|
index b48feeb3466..d01063ac98b 100644
|
|
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
|
|
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
|
|
@@ -39,6 +39,13 @@ config TARGET_PINEBOOK_PRO_RK3399
|
|
with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port,
|
|
1920*1080 screen and all the usual laptop features.
|
|
|
|
+config TARGET_PINEPHONE_PRO_RK3399
|
|
+ bool "PinePhone Pro"
|
|
+ help
|
|
+ PinePhone Pro is a phone based on a variant of the Rockchip
|
|
+ rk3399 SoC with 4Gb RAM, onboard eMMC, USB-C, headphone jack,
|
|
+ 720x1440 screen and a Quectel 4G/LTE modem.
|
|
+
|
|
config TARGET_PUMA_RK3399
|
|
bool "Theobroma Systems RK3399-Q7 (Puma)"
|
|
help
|
|
@@ -165,6 +172,7 @@ endif # BOOTCOUNT_LIMIT
|
|
source "board/firefly/roc-pc-rk3399/Kconfig"
|
|
source "board/google/gru/Kconfig"
|
|
source "board/pine64/pinebook-pro-rk3399/Kconfig"
|
|
+source "board/pine64/pinephone-pro-rk3399/Kconfig"
|
|
source "board/pine64/rockpro64_rk3399/Kconfig"
|
|
source "board/rockchip/evb_rk3399/Kconfig"
|
|
source "board/theobroma-systems/puma_rk3399/Kconfig"
|
|
diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig
|
|
new file mode 100644
|
|
index 00000000000..13d6465ae6e
|
|
--- /dev/null
|
|
+++ b/board/pine64/pinephone-pro-rk3399/Kconfig
|
|
@@ -0,0 +1,15 @@
|
|
+if TARGET_PINEPHONE_PRO_RK3399
|
|
+
|
|
+config SYS_BOARD
|
|
+ default "pinephone-pro-rk3399"
|
|
+
|
|
+config SYS_VENDOR
|
|
+ default "pine64"
|
|
+
|
|
+config SYS_CONFIG_NAME
|
|
+ default "pinephone-pro-rk3399"
|
|
+
|
|
+config BOARD_SPECIFIC_OPTIONS
|
|
+ def_bool y
|
|
+
|
|
+endif
|
|
diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
|
|
new file mode 100644
|
|
index 00000000000..c923ff1be32
|
|
--- /dev/null
|
|
+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
|
|
@@ -0,0 +1,8 @@
|
|
+PINEPHONE_PRO
|
|
+M: Peter Robinson <pbrobinson@gmail.com>
|
|
+S: Maintained
|
|
+F: board/pine64/rk3399-pinephone-pro/
|
|
+F: include/configs/rk3399-pinephone-pro.h
|
|
+F: arch/arm/dts/rk3399-pinephone-pro.dts
|
|
+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
|
|
+F: configs/pinephone-pro-rk3399_defconfig
|
|
diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile
|
|
new file mode 100644
|
|
index 00000000000..8d9203053e5
|
|
--- /dev/null
|
|
+++ b/board/pine64/pinephone-pro-rk3399/Makefile
|
|
@@ -0,0 +1 @@
|
|
+obj-y += pinephone-pro-rk3399.o
|
|
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
|
|
new file mode 100644
|
|
index 00000000000..eb639cd0d07
|
|
--- /dev/null
|
|
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
|
|
@@ -0,0 +1,76 @@
|
|
+// SPDX-License-Identifier: GPL-2.0+
|
|
+/*
|
|
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
|
+ * (C) Copyright 2022 Peter Robinson <pbrobinson at gmail.com>
|
|
+ */
|
|
+
|
|
+#include <common.h>
|
|
+#include <dm.h>
|
|
+#include <init.h>
|
|
+#include <syscon.h>
|
|
+#include <asm/io.h>
|
|
+#include <asm/arch-rockchip/clock.h>
|
|
+#include <asm/arch-rockchip/grf_rk3399.h>
|
|
+#include <asm/arch-rockchip/hardware.h>
|
|
+#include <asm/arch-rockchip/misc.h>
|
|
+#include <power/regulator.h>
|
|
+
|
|
+#define GRF_IO_VSEL_BT565_SHIFT 0
|
|
+#define PMUGRF_CON0_VSEL_SHIFT 8
|
|
+
|
|
+#ifndef CONFIG_SPL_BUILD
|
|
+int board_early_init_f(void)
|
|
+{
|
|
+ struct udevice *regulator;
|
|
+ int ret;
|
|
+
|
|
+ ret = regulator_get_by_platname("vcc5v0_usb", ®ulator);
|
|
+ if (ret) {
|
|
+ pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret);
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ ret = regulator_set_enable(regulator, true);
|
|
+ if (ret)
|
|
+ pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret);
|
|
+
|
|
+out:
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_MISC_INIT_R
|
|
+static void setup_iodomain(void)
|
|
+{
|
|
+ struct rk3399_grf_regs *grf =
|
|
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
+ struct rk3399_pmugrf_regs *pmugrf =
|
|
+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
|
|
+
|
|
+ /* BT565 is in 1.8v domain */
|
|
+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
|
|
+
|
|
+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
|
|
+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
|
|
+}
|
|
+
|
|
+int misc_init_r(void)
|
|
+{
|
|
+ const u32 cpuid_offset = 0x7;
|
|
+ const u32 cpuid_length = 0x10;
|
|
+ u8 cpuid[cpuid_length];
|
|
+ int ret;
|
|
+
|
|
+ setup_iodomain();
|
|
+
|
|
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+#endif
|
|
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
|
|
new file mode 100644
|
|
index 00000000000..eb979f6c051
|
|
--- /dev/null
|
|
+++ b/configs/pinephone-pro-rk3399_defconfig
|
|
@@ -0,0 +1,104 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
|
+CONFIG_COUNTER_FREQUENCY=24000000
|
|
+CONFIG_ARCH_ROCKCHIP=y
|
|
+CONFIG_TEXT_BASE=0x00200000
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_ENV_SIZE=0x8000
|
|
+CONFIG_ENV_OFFSET=0x3F8000
|
|
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
|
|
+CONFIG_ROCKCHIP_RK3399=y
|
|
+CONFIG_TARGET_PINEPHONE_PRO_RK3399=y
|
|
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
|
+CONFIG_DEBUG_UART_CLOCK=24000000
|
|
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|
+CONFIG_SPL_SPI=y
|
|
+CONFIG_SYS_LOAD_ADDR=0x800800
|
|
+CONFIG_DEBUG_UART=y
|
|
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
|
+CONFIG_BOOTDELAY=3
|
|
+CONFIG_USE_PREBOOT=y
|
|
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
|
|
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
|
+CONFIG_MISC_INIT_R=y
|
|
+CONFIG_SPL_MAX_SIZE=0x2e000
|
|
+CONFIG_SPL_PAD_TO=0x7f8000
|
|
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
|
+CONFIG_SPL_BSS_START_ADDR=0x400000
|
|
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
|
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
|
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
|
+CONFIG_SPL_STACK=0x400000
|
|
+CONFIG_SPL_STACK_R=y
|
|
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
|
+CONFIG_SPL_SPI_LOAD=y
|
|
+CONFIG_TPL=y
|
|
+CONFIG_CMD_BOOTZ=y
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_GPT=y
|
|
+CONFIG_CMD_I2C=y
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_PCI=y
|
|
+CONFIG_CMD_USB=y
|
|
+# CONFIG_CMD_SETEXPR is not set
|
|
+CONFIG_CMD_TIME=y
|
|
+CONFIG_CMD_PMIC=y
|
|
+CONFIG_CMD_REGULATOR=y
|
|
+CONFIG_SPL_OF_CONTROL=y
|
|
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
|
+CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
+CONFIG_SPL_DM_SEQ_ALIAS=y
|
|
+CONFIG_ROCKCHIP_GPIO=y
|
|
+CONFIG_SYS_I2C_ROCKCHIP=y
|
|
+CONFIG_DM_KEYBOARD=y
|
|
+CONFIG_LED=y
|
|
+CONFIG_LED_GPIO=y
|
|
+CONFIG_MISC=y
|
|
+CONFIG_ROCKCHIP_EFUSE=y
|
|
+CONFIG_MMC_DW=y
|
|
+CONFIG_MMC_DW_ROCKCHIP=y
|
|
+CONFIG_MMC_SDHCI=y
|
|
+CONFIG_MMC_SDHCI_SDMA=y
|
|
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
|
+CONFIG_SF_DEFAULT_BUS=1
|
|
+CONFIG_SF_DEFAULT_SPEED=20000000
|
|
+CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
+CONFIG_SPI_FLASH_WINBOND=y
|
|
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
|
+CONFIG_PHY_ROCKCHIP_TYPEC=y
|
|
+CONFIG_DM_PMIC_FAN53555=y
|
|
+CONFIG_DM_REGULATOR_FAN53555=y
|
|
+CONFIG_PMIC_RK8XX=y
|
|
+CONFIG_REGULATOR_PWM=y
|
|
+CONFIG_REGULATOR_RK8XX=y
|
|
+CONFIG_PWM_ROCKCHIP=y
|
|
+CONFIG_RAM_RK3399_LPDDR4=y
|
|
+CONFIG_DM_RESET=y
|
|
+CONFIG_DM_RNG=y
|
|
+CONFIG_RNG_ROCKCHIP=y
|
|
+CONFIG_BAUDRATE=1500000
|
|
+CONFIG_DEBUG_UART_SHIFT=2
|
|
+CONFIG_ROCKCHIP_SPI=y
|
|
+CONFIG_SYSRESET=y
|
|
+CONFIG_USB=y
|
|
+CONFIG_USB_XHCI_HCD=y
|
|
+CONFIG_USB_XHCI_DWC3=y
|
|
+CONFIG_USB_EHCI_HCD=y
|
|
+CONFIG_USB_EHCI_GENERIC=y
|
|
+CONFIG_USB_OHCI_HCD=y
|
|
+CONFIG_USB_OHCI_GENERIC=y
|
|
+CONFIG_USB_DWC3=y
|
|
+CONFIG_USB_DWC3_GENERIC=y
|
|
+CONFIG_USB_KEYBOARD=y
|
|
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
|
+CONFIG_USB_HOST_ETHER=y
|
|
+CONFIG_USB_ETHER_ASIX=y
|
|
+CONFIG_USB_ETHER_RTL8152=y
|
|
+CONFIG_DISPLAY=y
|
|
+CONFIG_VIDEO=y
|
|
+CONFIG_VIDEO_ROCKCHIP=y
|
|
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
|
|
+CONFIG_SPL_TINY_MEMSET=y
|
|
+CONFIG_ERRNO_STR=y
|
|
diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h
|
|
new file mode 100644
|
|
index 00000000000..78017d6bcc3
|
|
--- /dev/null
|
|
+++ b/include/configs/pinephone-pro-rk3399.h
|
|
@@ -0,0 +1,19 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0+ */
|
|
+/*
|
|
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd
|
|
+ * Copyright (C) 2022 Peter Robinson <pbrobinson at gmail.com>
|
|
+ */
|
|
+
|
|
+#ifndef __PINEPHONE_PRO_RK3399_H
|
|
+#define __PINEPHONE_PRO_RK3399_H
|
|
+
|
|
+#define ROCKCHIP_DEVICE_SETTINGS \
|
|
+ "stdin=serial,usbkbd\0" \
|
|
+ "stdout=serial,vidconsole\0" \
|
|
+ "stderr=serial,vidconsole\0"
|
|
+
|
|
+#include <configs/rk3399_common.h>
|
|
+
|
|
+#define SDRAM_BANK_SIZE (2UL << 30)
|
|
+
|
|
+#endif
|
|
--
|
|
2.39.0
|