711 lines
20 KiB
Diff
711 lines
20 KiB
Diff
From patchwork Wed Mar 25 18:21:51 2020
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X-Patchwork-Submitter: Tom Warren <tomcwarren3959@gmail.com>
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X-Patchwork-Delegate: twarren@nvidia.com
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From: <tomcwarren3959@gmail.com>
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To: <u-boot@lists.denx.de>
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
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<twarren@nvidia.com>
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Subject: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
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Date: Wed, 25 Mar 2020 11:21:51 -0700
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Message-ID: <1585160511-15347-1-git-send-email-tomcwarren3959@gmail.com>
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From: Tom Warren <twarren@nvidia.com>
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The Jetson Nano Developer Kit is a Tegra X1-based development board. It
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is similar to Jetson TX1 but it is not pin compatible. It features 4GB
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of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
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used for storage.
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HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
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and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
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Ethernet controller provides onboard network connectivity. NVMe support
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has also been added. Env save is at the end of QSPI (4MB-8K).
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A 40-pin header on the board can be used to extend the capabilities and
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exposed interfaces of the Jetson Nano.
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Signed-off-by: Thierry Reding <treding@nvidia.com>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
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---
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retry send-email to see if it shows up in Patchwork
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arch/arm/dts/Makefile | 3 +-
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arch/arm/dts/tegra210-p3450-0000.dts | 147 +++++++++++++++++++++++++++++
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arch/arm/mach-tegra/board2.c | 25 +++++
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arch/arm/mach-tegra/tegra210/Kconfig | 7 ++
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board/nvidia/p3450-0000/Kconfig | 12 +++
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board/nvidia/p3450-0000/MAINTAINERS | 6 ++
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board/nvidia/p3450-0000/Makefile | 8 ++
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board/nvidia/p3450-0000/p3450-0000.c | 178 +++++++++++++++++++++++++++++++++++
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configs/p3450-0000_defconfig | 64 +++++++++++++
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include/configs/p3450-0000.h | 46 +++++++++
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10 files changed, 495 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts
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create mode 100644 board/nvidia/p3450-0000/Kconfig
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create mode 100644 board/nvidia/p3450-0000/MAINTAINERS
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create mode 100644 board/nvidia/p3450-0000/Makefile
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create mode 100644 board/nvidia/p3450-0000/p3450-0000.c
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create mode 100644 configs/p3450-0000_defconfig
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create mode 100644 include/configs/p3450-0000.h
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 9c593b2..820ee97 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-e2220-1170.dtb \
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tegra210-p2371-0000.dtb \
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tegra210-p2371-2180.dtb \
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- tegra210-p2571.dtb
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+ tegra210-p2571.dtb \
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+ tegra210-p3450-0000.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-3720-db.dtb \
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diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts
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new file mode 100644
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index 0000000..9ef744a
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--- /dev/null
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+++ b/arch/arm/dts/tegra210-p3450-0000.dts
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@@ -0,0 +1,147 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
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+ */
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+/dts-v1/;
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+
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+#include "tegra210.dtsi"
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+
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+/ {
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+ model = "NVIDIA Jetson Nano Developer Kit";
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+ compatible = "nvidia,p3450-0000", "nvidia,tegra210";
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+
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+ chosen {
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+ stdout-path = &uarta;
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+ };
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+
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+ aliases {
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+ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
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+ i2c0 = "/i2c@7000d000";
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+ i2c2 = "/i2c@7000c400";
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+ i2c3 = "/i2c@7000c500";
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+ i2c4 = "/i2c@7000c700";
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+ mmc0 = "/sdhci@700b0600";
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+ mmc1 = "/sdhci@700b0000";
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+ spi0 = "/spi@70410000";
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+ usb0 = "/usb@7d000000";
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+ };
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+
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+ memory {
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+ reg = <0x0 0x80000000 0x0 0xc0000000>;
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+ };
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+
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+ pcie@1003000 {
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+ status = "okay";
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+
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+ pci@1,0 {
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+ status = "okay";
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+ };
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+
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+ pci@2,0 {
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+ status = "okay";
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+
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+ ethernet@0,0 {
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+ reg = <0x000000 0 0 0 0>;
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+ local-mac-address = [ 00 00 00 00 00 00 ];
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+ };
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+ };
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+ };
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+
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+ serial@70006000 {
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+ status = "okay";
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+ };
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+
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+ padctl@7009f000 {
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+ pinctrl-0 = <&padctl_default>;
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+ pinctrl-names = "default";
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+
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+ padctl_default: pinmux {
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+ xusb {
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+ nvidia,lanes = "otg-1", "otg-2";
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+ nvidia,function = "xusb";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ usb3 {
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+ nvidia,lanes = "pcie-5", "pcie-6";
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+ nvidia,function = "usb3";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ pcie-x1 {
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+ nvidia,lanes = "pcie-0";
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+ nvidia,function = "pcie-x1";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ pcie-x4 {
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+ nvidia,lanes = "pcie-1", "pcie-2",
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+ "pcie-3", "pcie-4";
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+ nvidia,function = "pcie-x4";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ sata {
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+ nvidia,lanes = "sata-0";
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+ nvidia,function = "sata";
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+ nvidia,iddq = <0>;
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+ };
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+ };
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+ };
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+
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+ sdhci@700b0000 {
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+ status = "okay";
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+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
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+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
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+ bus-width = <4>;
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+ };
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+
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+ sdhci@700b0600 {
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+ status = "okay";
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+ bus-width = <8>;
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+ non-removable;
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+ };
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+
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+ i2c@7000c400 {
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+ status = "okay";
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+ clock-frequency = <400000>;
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+ };
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+
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+ i2c@7000c500 {
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+ status = "okay";
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+ clock-frequency = <400000>;
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+ };
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+
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+ i2c@7000c700 {
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+ status = "okay";
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+ clock-frequency = <400000>;
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+ };
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+
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+ i2c@7000d000 {
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+ status = "okay";
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+ clock-frequency = <400000>;
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+ };
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+
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+ spi@70410000 {
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+ status = "okay";
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+ spi-max-frequency = <80000000>;
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+ };
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+
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+ usb@7d000000 {
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+ status = "okay";
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+ dr_mode = "peripheral";
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+ };
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+
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+ clocks {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ clk32k_in: clock@0 {
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+ compatible = "fixed-clock";
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+ reg = <0>;
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+ #clock-cells = <0>;
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+ clock-frequency = <32768>;
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+ };
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+ };
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+};
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diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
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index 787ff97..224efc9 100644
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--- a/arch/arm/mach-tegra/board2.c
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+++ b/arch/arm/mach-tegra/board2.c
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@@ -217,6 +217,31 @@ int board_early_init_f(void)
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arch_timer_init();
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#endif
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+#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
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+ /*
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+ * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
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+ * We do this because earlier bootloaders have enabled power to
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+ * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
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+ * results in power being back-driven into the SD-card and SDMMC1
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+ * HW, which is 'bad' as per the HW team.
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+ *
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+ * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
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+ * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
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+ * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
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+ * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
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+ * voltage turns off. Since the SDCard voltage is no longer there, the
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+ * SDMMC CLK/DAT lines are backdriving into what essentially is a
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+ * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
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+ *
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+ * Note that this can probably be removed when we change over to storing
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+ * all BL components on QSPI on Nano, and U-Boot then becomes the first
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+ * one to turn on SDMMC1 power. Another fix would be to have CBoot
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+ * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
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+ */
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+ reset_set_enable(PERIPH_ID_SDMMC1, 1);
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+ clock_set_enable(PERIPH_ID_SDMMC1, 0);
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+#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
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+
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pinmux_init();
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board_init_uart_f();
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diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
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index 3637473..97ed8e0 100644
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--- a/arch/arm/mach-tegra/tegra210/Kconfig
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+++ b/arch/arm/mach-tegra/tegra210/Kconfig
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@@ -35,6 +35,12 @@ config TARGET_P2571
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help
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P2571 is a P2530 married to a P1963 I/O board
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+config TARGET_P3450_0000
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+ bool "NVIDIA Jetson Nano Developer Kit"
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+ select BOARD_LATE_INIT
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+ help
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+ P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
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+
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endchoice
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config SYS_SOC
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@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
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source "board/nvidia/p2371-0000/Kconfig"
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source "board/nvidia/p2371-2180/Kconfig"
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source "board/nvidia/p2571/Kconfig"
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+source "board/nvidia/p3450-0000/Kconfig"
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|
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endif
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diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig
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|
new file mode 100644
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|
index 0000000..7a08cd8
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--- /dev/null
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|
+++ b/board/nvidia/p3450-0000/Kconfig
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|
@@ -0,0 +1,12 @@
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+if TARGET_P3450_0000
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|
+
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|
+config SYS_BOARD
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|
+ default "p3450-0000"
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|
+
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+config SYS_VENDOR
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|
+ default "nvidia"
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+
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+config SYS_CONFIG_NAME
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|
+ default "p3450-0000"
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+
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+endif
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diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS
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new file mode 100644
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|
index 0000000..4070006
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--- /dev/null
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|
+++ b/board/nvidia/p3450-0000/MAINTAINERS
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|
@@ -0,0 +1,6 @@
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+P3450-0000 BOARD
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|
+M: Tom Warren <twarren@nvidia.com>
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|
+S: Maintained
|
|
+F: board/nvidia/p3450-0000/
|
|
+F: include/configs/p3450-0000.h
|
|
+F: configs/p3450-0000_defconfig
|
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diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile
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new file mode 100644
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|
index 0000000..993c506
|
|
--- /dev/null
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|
+++ b/board/nvidia/p3450-0000/Makefile
|
|
@@ -0,0 +1,8 @@
|
|
+#
|
|
+# (C) Copyright 2018
|
|
+# NVIDIA Corporation <www.nvidia.com>
|
|
+#
|
|
+# SPDX-License-Identifier: GPL-2.0+
|
|
+#
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|
+
|
|
+obj-y += p3450-0000.o
|
|
diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c
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new file mode 100644
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index 0000000..f4212ab
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--- /dev/null
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+++ b/board/nvidia/p3450-0000/p3450-0000.c
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@@ -0,0 +1,178 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2018-2019
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+ * NVIDIA Corporation <www.nvidia.com>
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+ *
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+ */
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+
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+#include <common.h>
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+#include <fdtdec.h>
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+#include <i2c.h>
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+#include <linux/libfdt.h>
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+#include <pca953x.h>
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+#include <asm/arch-tegra/cboot.h>
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+#include <asm/arch/gpio.h>
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+#include <asm/arch/pinmux.h>
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+#include "../p2571/max77620_init.h"
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+
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+void pin_mux_mmc(void)
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+{
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+ struct udevice *dev;
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+ uchar val;
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+ int ret;
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+
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+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
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+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
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+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
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+ if (ret) {
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+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
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+ return;
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+ }
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+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
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+ val = 0xF2;
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+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
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+ if (ret)
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+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
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+
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+ /* Disable LDO4 discharge */
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+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
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+ if (ret) {
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+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
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+ } else {
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+ val &= ~BIT(1); /* ADE */
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+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
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+ if (ret)
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+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
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+ }
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+
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+ /* Set MBLPD */
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+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
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+ if (ret) {
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+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
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+ } else {
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+ val |= BIT(6); /* MBLPD */
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+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
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+ if (ret)
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+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
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+ }
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+}
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+
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+#ifdef CONFIG_PCI_TEGRA
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+int tegra_pcie_board_init(void)
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+{
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+ struct udevice *dev;
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+ uchar val;
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+ int ret;
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+
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+ /* Turn on MAX77620 LDO1 to 1.05V for PEX power */
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+ debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
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+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
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+ if (ret) {
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+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
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+ return -1;
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+ }
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+ /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
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+ val = 0xCA;
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+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
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+ if (ret)
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+ printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
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+
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+ return 0;
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+}
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+#endif /* PCI */
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+
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+static void ft_mac_address_setup(void *fdt)
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+{
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+ const void *cboot_fdt = (const void *)cboot_boot_x0;
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+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
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+ const char *path;
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+ int offset, err;
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+
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+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
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+ if (err < 0)
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+ memset(local_mac, 0, ETH_ALEN);
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+
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+ path = fdt_get_alias(fdt, "ethernet");
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+ if (!path)
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+ return;
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+
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+ debug("ethernet alias found: %s\n", path);
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+
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+ offset = fdt_path_offset(fdt, path);
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+ if (offset < 0) {
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+ printf("ethernet alias points to absent node %s\n", path);
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+ return;
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+ }
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+
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+ if (is_valid_ethaddr(local_mac)) {
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+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
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+ ETH_ALEN);
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+ if (!err)
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+ debug("Local MAC address set: %pM\n", local_mac);
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+ }
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+
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+ if (eth_env_get_enetaddr("ethaddr", mac)) {
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+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
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+ err = fdt_setprop(fdt, offset, "mac-address", mac,
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+ ETH_ALEN);
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+ if (!err)
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+ debug("MAC address set: %pM\n", mac);
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+ }
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+ }
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+}
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+
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+static int ft_copy_carveout(void *dst, const void *src, const char *node)
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+{
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+ struct fdt_memory fb;
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+ int err;
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+
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+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
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+ if (err < 0) {
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+ if (err != -FDT_ERR_NOTFOUND)
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+ printf("failed to get carveout for %s: %d\n", node,
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+ err);
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+
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+ return err;
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+ }
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+
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+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
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+ &fb);
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+ if (err < 0) {
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+ printf("failed to set carveout for %s: %d\n", node, err);
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+ return err;
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+ }
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+
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+ return 0;
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+}
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+
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+static void ft_carveout_setup(void *fdt)
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+{
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+ const void *cboot_fdt = (const void *)cboot_boot_x0;
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+ static const char * const nodes[] = {
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+ "/host1x@50000000/dc@54200000",
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+ "/host1x@50000000/dc@54240000",
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+ };
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+ unsigned int i;
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+ int err;
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+
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+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
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+ printf("copying carveout for %s...\n", nodes[i]);
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+
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+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
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+ if (err < 0) {
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+ if (err != -FDT_ERR_NOTFOUND)
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+ printf("failed to copy carveout for %s: %d\n",
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+ nodes[i], err);
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+
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+ continue;
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+ }
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+ }
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+}
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+
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+int ft_board_setup(void *fdt, bd_t *bd)
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+{
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+ ft_mac_address_setup(fdt);
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+ ft_carveout_setup(fdt);
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+
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+ return 0;
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+}
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diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
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new file mode 100644
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index 0000000..c861d13
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--- /dev/null
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+++ b/configs/p3450-0000_defconfig
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@@ -0,0 +1,64 @@
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+CONFIG_ARM=y
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+CONFIG_TEGRA=y
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+CONFIG_SYS_TEXT_BASE=0x80080000
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+CONFIG_TEGRA210=y
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+CONFIG_TARGET_P3450_0000=y
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+CONFIG_NR_DRAM_BANKS=2
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+CONFIG_OF_SYSTEM_SETUP=y
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+CONFIG_OF_BOARD_SETUP=y
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+CONFIG_CONSOLE_MUX=y
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+CONFIG_SYS_STDIO_DEREGISTER=y
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+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
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+# CONFIG_CMD_IMI is not set
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+CONFIG_CMD_DFU=y
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+# CONFIG_CMD_FLASH is not set
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_I2C=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_PCI=y
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+CONFIG_CMD_SF=y
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+CONFIG_CMD_SPI=y
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+CONFIG_CMD_USB=y
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+CONFIG_CMD_USB_MASS_STORAGE=y
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+# CONFIG_CMD_SETEXPR is not set
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+# CONFIG_CMD_NFS is not set
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+CONFIG_CMD_EXT4_WRITE=y
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+CONFIG_OF_LIVE=y
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+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
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+CONFIG_DFU_MMC=y
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+CONFIG_DFU_RAM=y
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+CONFIG_DFU_SF=y
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+CONFIG_SYS_I2C_TEGRA=y
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+CONFIG_SPI_FLASH=y
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+CONFIG_SPI_FLASH_MACRONIX=y
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+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
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+CONFIG_SF_DEFAULT_MODE=0
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+CONFIG_SF_DEFAULT_SPEED=24000000
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+CONFIG_RTL8169=y
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+CONFIG_PCI=y
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+CONFIG_DM_PCI=y
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+CONFIG_DM_PCI_COMPAT=y
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+CONFIG_PCI_TEGRA=y
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+CONFIG_SYS_NS16550=y
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+CONFIG_TEGRA114_SPI=y
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+CONFIG_TEGRA210_QSPI=y
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+CONFIG_USB=y
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+CONFIG_DM_USB=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_TEGRA=y
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+CONFIG_USB_GADGET=y
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+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
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+CONFIG_USB_GADGET_VENDOR_NUM=0x0955
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+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a
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+CONFIG_CI_UDC=y
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+CONFIG_USB_GADGET_DOWNLOAD=y
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+CONFIG_USB_HOST_ETHER=y
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+CONFIG_USB_ETHER_ASIX=y
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+# CONFIG_ENV_IS_IN_MMC is not set
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+CONFIG_ENV_IS_IN_SPI_FLASH=y
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+CONFIG_ENV_SIZE=0x2000
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+CONFIG_ENV_SECT_SIZE=0x1000
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+CONFIG_ENV_OFFSET=0xFFFFE000
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+CONFIG_BOOTP_PREFER_SERVERIP=y
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+CONFIG_DISABLE_SDMMC1_EARLY=y
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+CONFIG_NVME=y
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diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
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new file mode 100644
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index 0000000..7f05beb
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--- /dev/null
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+++ b/include/configs/p3450-0000.h
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@@ -0,0 +1,46 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * (C) Copyright 2018-2019 NVIDIA Corporation.
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+ */
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+
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+#ifndef _P3450_0000_H
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+#define _P3450_0000_H
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+
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+#include <linux/sizes.h>
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+
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+#include "tegra210-common.h"
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+
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+/* High-level configuration options */
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+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000"
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+
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+/* Board-specific serial config */
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+#define CONFIG_TEGRA_ENABLE_UARTA
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+
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+/* Only MMC/PXE/DHCP for now, add USB back in later when supported */
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+#define BOOT_TARGET_DEVICES(func) \
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+ func(MMC, mmc, 1) \
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+ func(MMC, mmc, 0) \
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+ func(PXE, pxe, na) \
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+ func(DHCP, dhcp, na)
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+
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+/* Environment at end of QSPI, in the VER partition */
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+#define CONFIG_ENV_SPI_MAX_HZ 48000000
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+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
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+
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+#define CONFIG_PREBOOT
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+
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+#define BOARD_EXTRA_ENV_SETTINGS \
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+ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
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+ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
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+ "source ${scriptaddr}; " \
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+ "fi\0"
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+
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+/* General networking support */
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+#include "tegra-common-usb-gadget.h"
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+#include "tegra-common-post.h"
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+
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+/* Crystal is 38.4MHz. clk_m runs at half that rate */
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+#define COUNTER_FREQUENCY 19200000
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+
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+#endif /* _P3450_0000_H */
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