130 lines
3.2 KiB
Diff
130 lines
3.2 KiB
Diff
From d0c5ac609ca8c4c2eed36fca380202b62bb4451e Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Wed, 27 Apr 2016 17:00:10 +0100
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Subject: [PATCH] Revert "video: ipu: avoid overflow issue"
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This reverts commit 3cb4f25cc702db17455583599d0940c81337a17a.
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---
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drivers/video/ipu_common.c | 73 ++++++++++++----------------------------------
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1 file changed, 19 insertions(+), 54 deletions(-)
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diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
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index 36d4b23..9f85102 100644
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--- a/drivers/video/ipu_common.c
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+++ b/drivers/video/ipu_common.c
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@@ -19,7 +19,6 @@
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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-#include <div64.h>
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#include "ipu.h"
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#include "ipu_regs.h"
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@@ -276,84 +275,50 @@ static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
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static void ipu_pixel_clk_recalc(struct clk *clk)
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{
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- u32 div;
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- u64 final_rate = (unsigned long long)clk->parent->rate * 16;
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-
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- div = __raw_readl(DI_BS_CLKGEN0(clk->id));
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- debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
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- div, final_rate, clk->parent->rate);
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-
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- clk->rate = 0;
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- if (div != 0) {
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- do_div(final_rate, div);
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- clk->rate = final_rate;
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- }
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+ u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
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+ if (div == 0)
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+ clk->rate = 0;
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+ else
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+ clk->rate = (clk->parent->rate * 16) / div;
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}
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static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
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unsigned long rate)
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{
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- u64 div, final_rate;
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- u32 remainder;
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- u64 parent_rate = (unsigned long long)clk->parent->rate * 16;
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-
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+ u32 div, div1;
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+ u32 tmp;
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/*
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* Calculate divider
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* Fractional part is 4 bits,
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* so simply multiply by 2^4 to get fractional part.
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*/
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- div = parent_rate;
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- remainder = do_div(div, rate);
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- /* Round the divider value */
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- if (remainder > (rate / 2))
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- div++;
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+ tmp = (clk->parent->rate * 16);
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+ div = tmp / rate;
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+
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if (div < 0x10) /* Min DI disp clock divider is 1 */
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div = 0x10;
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if (div & ~0xFEF)
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div &= 0xFF8;
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else {
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- /* Round up divider if it gets us closer to desired pix clk */
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- if ((div & 0xC) == 0xC) {
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- div += 0x10;
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- div &= ~0xF;
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- }
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+ div1 = div & 0xFE0;
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+ if ((tmp/div1 - tmp/div) < rate / 4)
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+ div = div1;
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+ else
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+ div &= 0xFF8;
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}
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- final_rate = parent_rate;
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- do_div(final_rate, div);
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-
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- return final_rate;
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+ return (clk->parent->rate * 16) / div;
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}
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static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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- u64 div, parent_rate;
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- u32 remainder;
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-
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- parent_rate = (unsigned long long)clk->parent->rate * 16;
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- div = parent_rate;
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- remainder = do_div(div, rate);
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- /* Round the divider value */
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- if (remainder > (rate / 2))
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- div++;
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-
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- /* Round up divider if it gets us closer to desired pix clk */
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- if ((div & 0xC) == 0xC) {
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- div += 0x10;
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- div &= ~0xF;
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- }
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- if (div > 0x1000)
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- debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div);
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+ u32 div = (clk->parent->rate * 16) / rate;
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__raw_writel(div, DI_BS_CLKGEN0(clk->id));
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- /*
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- * Setup pixel clock timing
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- * Down time is half of period
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- */
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+ /* Setup pixel clock timing */
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__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
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- clk->rate = (u64)(clk->parent->rate * 16) / div;
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-
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+ clk->rate = (clk->parent->rate * 16) / div;
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return 0;
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}
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--
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2.7.4
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