602 lines
18 KiB
Diff
602 lines
18 KiB
Diff
From 9c3e5ff69a47086bb7428043ed91261a6b6b9d18 Mon Sep 17 00:00:00 2001
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From: Dennis Gilmore <dennis@ausil.us>
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Date: Mon, 21 Apr 2014 12:33:43 -0500
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Subject: [PATCH 13/36] add hackish utilite build based on wandboard
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---
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board/compulab/utilite/Makefile | 7 +
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board/compulab/utilite/README | 45 ++++++
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board/compulab/utilite/utilite.c | 316 +++++++++++++++++++++++++++++++++++++++
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boards.cfg | 1 +
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include/configs/utilite.h | 177 ++++++++++++++++++++++
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5 files changed, 546 insertions(+)
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create mode 100644 board/compulab/utilite/Makefile
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create mode 100644 board/compulab/utilite/README
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create mode 100644 board/compulab/utilite/utilite.c
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create mode 100644 include/configs/utilite.h
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diff --git a/board/compulab/utilite/Makefile b/board/compulab/utilite/Makefile
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new file mode 100644
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index 0000000..f0d8f12
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--- /dev/null
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+++ b/board/compulab/utilite/Makefile
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@@ -0,0 +1,7 @@
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+#
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+# (C) Copyright 2013 Freescale Semiconductor, Inc.
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+obj-y := utilite.o
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diff --git a/board/compulab/utilite/README b/board/compulab/utilite/README
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new file mode 100644
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index 0000000..8ebb650
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--- /dev/null
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+++ b/board/compulab/utilite/README
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@@ -0,0 +1,45 @@
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+U-Boot for Utilite
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+--------------------
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+
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+This file contains information for the port of U-Boot to the Utilite.
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+
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+Utilite is a development board that has three variants based on the following
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+SoCs: mx6 quad, mx6 dual lite and mx6 solo.
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+
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+For more details about Utilite, please refer to:
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+http://www.utilite.org/
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+
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+Building U-boot for Utilite
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+-----------------------------
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+
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+To build U-Boot for the Utilite Dual Lite version:
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+
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+$ make utilite_dl_config
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+$ make
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+
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+To build U-Boot for the Utilite Solo version:
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+
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+$ make utilite_solo_config
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+$ make
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+
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+To build U-Boot for the Utilite Quad version:
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+
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+$ make utilite_quad_config
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+$ make
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+
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+Flashing U-boot into the SD card
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+--------------------------------
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+
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+- After the 'make' command completes, the generated 'u-boot.imx' binary must be
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+flashed into the SD card;
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+
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+$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync
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+
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+(Note - the SD card node may vary, so adjust this as needed).
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+
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+- Insert the SD card into the slot located in the bottom of the board (same side
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+as the mx6 processor)
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+
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+- Connect the serial cable to the host PC
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+
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+- Power up the board and U-boot messages will appear in the serial console.
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diff --git a/board/compulab/utilite/utilite.c b/board/compulab/utilite/utilite.c
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new file mode 100644
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index 0000000..55490ee
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--- /dev/null
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+++ b/board/compulab/utilite/utilite.c
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@@ -0,0 +1,316 @@
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+/*
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+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
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+ *
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+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <asm/arch/clock.h>
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+#include <asm/arch/crm_regs.h>
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+#include <asm/arch/iomux.h>
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+#include <asm/arch/imx-regs.h>
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+#include <asm/arch/mx6-pins.h>
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+#include <asm/arch/mxc_hdmi.h>
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+#include <asm/arch/sys_proto.h>
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+#include <asm/gpio.h>
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+#include <asm/imx-common/iomux-v3.h>
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+#include <asm/imx-common/boot_mode.h>
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+#include <asm/io.h>
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+#include <linux/sizes.h>
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+#include <common.h>
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+#include <fsl_esdhc.h>
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+#include <ipu_pixfmt.h>
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+#include <mmc.h>
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+#include <miiphy.h>
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+#include <netdev.h>
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+#include <linux/fb.h>
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+#include <phy.h>
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+#include <input.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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+
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+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
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+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
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+#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
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+
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+int dram_init(void)
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+{
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+ gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
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+
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+ return 0;
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+}
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+
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+static iomux_v3_cfg_t const uart1_pads[] = {
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+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const usdhc1_pads[] = {
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+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ /* Carrier MicroSD Card Detect */
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+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const usdhc3_pads[] = {
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+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ /* SOM MicroSD Card Detect */
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+ MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const enet_pads[] = {
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+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ /* AR8031 PHY Reset */
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+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static void setup_iomux_uart(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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+}
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+
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+static void setup_iomux_enet(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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+
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+ /* Reset AR8031 PHY */
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+ gpio_direction_output(ETH_PHY_RESET, 0);
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+ udelay(500);
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+ gpio_set_value(ETH_PHY_RESET, 1);
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+}
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+
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+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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+ {USDHC3_BASE_ADDR},
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+ {USDHC1_BASE_ADDR},
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+};
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+
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+int board_mmc_getcd(struct mmc *mmc)
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+{
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+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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+ int ret = 0;
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+
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+ switch (cfg->esdhc_base) {
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+ case USDHC1_BASE_ADDR:
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+ ret = !gpio_get_value(USDHC1_CD_GPIO);
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+ break;
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+ case USDHC3_BASE_ADDR:
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+ ret = !gpio_get_value(USDHC3_CD_GPIO);
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+int board_mmc_init(bd_t *bis)
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+{
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+ s32 status = 0;
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+ u32 index = 0;
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+
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+ /*
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+ * Following map is done:
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+ * (U-boot device node) (Physical Port)
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+ * mmc0 SOM MicroSD
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+ * mmc1 Carrier board MicroSD
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+ */
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+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
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+ switch (index) {
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+ case 0:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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+ usdhc_cfg[0].max_bus_width = 4;
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+ gpio_direction_input(USDHC3_CD_GPIO);
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+ break;
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+ case 1:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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+ usdhc_cfg[1].max_bus_width = 4;
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+ gpio_direction_input(USDHC1_CD_GPIO);
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+ break;
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+ default:
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+ printf("Warning: you configured more USDHC controllers"
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+ "(%d) then supported by the board (%d)\n",
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+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
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+ return status;
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+ }
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+
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+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
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+ }
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+
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+ return status;
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+}
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+
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+static int mx6_rgmii_rework(struct phy_device *phydev)
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+{
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+ unsigned short val;
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+
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+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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+
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+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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+ val &= 0xffe3;
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+ val |= 0x18;
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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+
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+ /* introduce tx clock delay */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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+ val |= 0x0100;
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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+
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+ return 0;
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+}
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+
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+int board_phy_config(struct phy_device *phydev)
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+{
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+ mx6_rgmii_rework(phydev);
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+
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+ if (phydev->drv->config)
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+ phydev->drv->config(phydev);
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+
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+ return 0;
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+}
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+
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+#if defined(CONFIG_VIDEO_IPUV3)
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+static struct fb_videomode const hdmi = {
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+ .name = "HDMI",
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+ .refresh = 60,
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+ .xres = 1024,
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+ .yres = 768,
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+ .pixclock = 15385,
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+ .left_margin = 220,
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+ .right_margin = 40,
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+ .upper_margin = 21,
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+ .lower_margin = 7,
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+ .hsync_len = 60,
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+ .vsync_len = 10,
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+ .sync = FB_SYNC_EXT,
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+ .vmode = FB_VMODE_NONINTERLACED
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+};
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+
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+int board_video_skip(void)
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+{
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+ int ret;
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+
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+ ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
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+
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+ if (ret) {
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+ printf("HDMI cannot be configured: %d\n", ret);
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+ return ret;
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+ }
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+
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+ imx_enable_hdmi_phy();
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+
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+ return ret;
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+}
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+
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+static void setup_display(void)
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+{
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+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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+ int reg;
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+
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+ enable_ipu_clock();
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+ imx_setup_hdmi();
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+
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+ reg = readl(&mxc_ccm->chsccdr);
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+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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+ writel(reg, &mxc_ccm->chsccdr);
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+}
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+#endif /* CONFIG_VIDEO_IPUV3 */
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+
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+int board_eth_init(bd_t *bis)
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+{
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+ setup_iomux_enet();
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+
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+ return cpu_eth_init(bis);
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+}
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+
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+int board_early_init_f(void)
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+{
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+ setup_iomux_uart();
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+#if defined(CONFIG_VIDEO_IPUV3)
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+ setup_display();
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+#endif
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+ return 0;
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+}
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+
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+/*
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+ * Do not overwrite the console
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+ * Use always serial for U-Boot console
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+ */
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+int overwrite_console(void)
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+{
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+ return 1;
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+}
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+
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+#ifdef CONFIG_CMD_BMODE
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+static const struct boot_mode board_boot_modes[] = {
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+ /* 4 bit bus width */
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+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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+ {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
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+ {NULL, 0},
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+};
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+#endif
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+
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+int board_late_init(void)
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+{
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+#ifdef CONFIG_CMD_BMODE
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+ add_board_boot_modes(board_boot_modes);
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+#endif
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+
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+ return 0;
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+}
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+
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+int board_init(void)
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+{
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+ /* address of boot parameters */
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+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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+
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+ return 0;
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+}
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+
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+int checkboard(void)
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+{
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+ puts("Board: Utilite\n");
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+
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+ return 0;
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+}
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diff --git a/boards.cfg b/boards.cfg
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index b4203f1..49ea4ab 100644
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--- a/boards.cfg
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+++ b/boards.cfg
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@@ -316,6 +316,7 @@ Active arm armv7 mx6 boundary nitrogen6x
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Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
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Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
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Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
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+Active arm armv7 mx6 compulab utilite utilite_quad utilite:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
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Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
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Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
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Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
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diff --git a/include/configs/utilite.h b/include/configs/utilite.h
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new file mode 100644
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index 0000000..fb382f9
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--- /dev/null
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+++ b/include/configs/utilite.h
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@@ -0,0 +1,177 @@
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+/*
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+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
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+ *
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+ * Configuration settings for the Wandboard.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#ifndef __CONFIG_H
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+#define __CONFIG_H
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+
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+#include "mx6_common.h"
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+#include <asm/arch/imx-regs.h>
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+#include <asm/imx-common/gpio.h>
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+#include <linux/sizes.h>
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+
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+#define CONFIG_MX6
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+#define CONFIG_DISPLAY_CPUINFO
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+#define CONFIG_DISPLAY_BOARDINFO
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+
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+#define MACH_TYPE_UTILITE 4412
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+#define CONFIG_MACH_TYPE MACH_TYPE_UTILITE
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+
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+#define CONFIG_CMDLINE_TAG
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+#define CONFIG_SETUP_MEMORY_TAGS
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+#define CONFIG_INITRD_TAG
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+#define CONFIG_REVISION_TAG
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+
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+/* Size of malloc() pool */
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+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
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+
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+#define CONFIG_BOARD_EARLY_INIT_F
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+#define CONFIG_BOARD_LATE_INIT
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+#define CONFIG_MXC_GPIO
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+
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+#define CONFIG_MXC_UART
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+#define CONFIG_MXC_UART_BASE UART1_BASE
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+
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+/* allow to overwrite serial and ethaddr */
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+#define CONFIG_ENV_OVERWRITE
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+#define CONFIG_CONS_INDEX 1
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+#define CONFIG_BAUDRATE 115200
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+
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+/* Command definition */
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+#include <config_cmd_default.h>
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+
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+#undef CONFIG_CMD_IMLS
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+
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+#define CONFIG_CMD_BMODE
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+#define CONFIG_CMD_SETEXPR
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+
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+#define CONFIG_SYS_MEMTEST_START 0x10000000
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+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
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+#define CONFIG_LOADADDR 0x12000000
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+#define CONFIG_SYS_TEXT_BASE 0x17800000
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+
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+/* MMC Configuration */
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+#define CONFIG_FSL_ESDHC
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+#define CONFIG_FSL_USDHC
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+#define CONFIG_SYS_FSL_USDHC_NUM 2
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+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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+
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+#define CONFIG_MMC
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+#define CONFIG_CMD_MMC
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+#define CONFIG_GENERIC_MMC
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+#define CONFIG_BOUNCE_BUFFER
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+
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+/* Ethernet Configuration */
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+#define CONFIG_FEC_MXC
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+#define CONFIG_MII
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+#define IMX_FEC_BASE ENET_BASE_ADDR
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+#define CONFIG_FEC_XCV_TYPE RGMII
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+#define CONFIG_ETHPRIME "FEC"
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+#define CONFIG_FEC_MXC_PHYADDR 1
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+#define CONFIG_PHYLIB
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+#define CONFIG_PHY_ATHEROS
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+
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+/* Framebuffer */
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+#define CONFIG_VIDEO
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+#define CONFIG_VIDEO_IPUV3
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+#define CONFIG_CFB_CONSOLE
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+#define CONFIG_VGA_AS_SINGLE_DEVICE
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+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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+#define CONFIG_VIDEO_BMP_RLE8
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+#define CONFIG_SPLASH_SCREEN
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+#define CONFIG_SPLASH_SCREEN_ALIGN
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+#define CONFIG_BMP_16BPP
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+#define CONFIG_VIDEO_LOGO
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+#define CONFIG_VIDEO_BMP_LOGO
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+#define CONFIG_IPUV3_CLK 260000000
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+#define CONFIG_IMX_HDMI
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+
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+#ifndef CONFIG_SPL_BUILD
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+#include <config_distro_defaults.h>
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+#include <config_distro_bootcmd.h>
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+#endif
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+
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+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
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+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-cm-fx6.dtb"
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+#elif defined(CONFIG_MX6Q)
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+#define CONFIG_DEFAULT_FDT_FILE "imx6q-cm-fx6.dtb"
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+#endif
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+
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+#define CONFIG_EXTRA_ENV_SETTINGS \
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+ "script=boot.scr\0" \
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+ "image=zImage\0" \
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+ "console=ttymxc3,115200\0" \
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+ "splashpos=m,m\0" \
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+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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+ "fdt_addr_r=0x18000000\0" \
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+ "boot_fdt=try\0" \
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+ "pxefile_addr_r=0x17f00000\0" \
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+ "scriptaddr=0x17e00000\0" \
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+ "kernel_addr_r=0x11000000\0" \
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+ "ramdisk_addr_r=0x18100000\0" \
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+ "bootm_size=0x20000000\0" \
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+ "ip_dyn=yes\0" \
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+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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+ "mmcpart=1\0" \
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+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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+ "update_sd_firmware_filename=u-boot.imx\0" \
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+ "update_sd_firmware=" \
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+ "if test ${ip_dyn} = yes; then " \
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+ "setenv get_cmd dhcp; " \
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+ "else " \
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+ "setenv get_cmd tftp; " \
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+ "fi; " \
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+ "if mmc dev ${mmcdev}; then " \
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+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
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+ "setexpr fw_sz ${filesize} / 0x200; " \
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+ "setexpr fw_sz ${fw_sz} + 1; " \
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+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
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+ "fi; " \
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+ "fi\0" \
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+ BOOTCMDS_COMMON
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+
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+#define CONFIG_BOOTCOMMAND \
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+ "for target in ${boot_targets}; do run bootcmd_${target}; done"
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+
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+/* Miscellaneous configurable options */
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+#define CONFIG_SYS_CBSIZE 256
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+
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+/* Print Buffer Size */
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+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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+#define CONFIG_SYS_MAXARGS 16
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+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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+
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+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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+
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+/* Physical Memory Map */
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+#define CONFIG_NR_DRAM_BANKS 1
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+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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+
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+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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+
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+#define CONFIG_SYS_INIT_SP_OFFSET \
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+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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+#define CONFIG_SYS_INIT_SP_ADDR \
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+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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+
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+/* FLASH and environment organization */
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+#define CONFIG_SYS_NO_FLASH
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+
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+#define CONFIG_ENV_SIZE (8 * 1024)
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+
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+#define CONFIG_ENV_IS_IN_MMC
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+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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+#define CONFIG_SYS_MMC_ENV_DEV 0
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+
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+#ifndef CONFIG_SYS_DCACHE_OFF
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+#define CONFIG_CMD_CACHE
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+#endif
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+
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+#endif /* __CONFIG_H * */
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--
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1.9.0
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