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From patchwork Sun Feb 25 22:10:19 2024
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From: Jonas Karlman <jonas@kwiboo.se>
To: Kever Yang <kever.yang@rock-chips.com>, Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>, Tom Rini <trini@konsulko.com>,
Ren Jianing <jianing.ren@rock-chips.com>, Manoj Sai
<abbaraju.manojsai@amarulasolutions.com>, Jagan Teki
<jagan@amarulasolutions.com>, Eugen Hristev <eugen.hristev@collabora.com>,
Frank Wang <frank.wang@rock-chips.com>, Xavier Drudis Ferran
<xdrudis@tinet.cat>
Cc: u-boot@lists.denx.de, Jonas Karlman <jonas@kwiboo.se>
Subject: [PATCH 1/2] phy: rockchip-inno-usb2: Write to correct GRF
Date: Sun, 25 Feb 2024 22:10:19 +0000
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On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs
that is supported by this driver have the USB2PHY regs in a different
GRF.
When support for RK356x, RK3588 and RK3328 was added this driver was
never updated to use correct GRF and have instead incorrectly written
to wrong GRF for these SoCs.
The default reset values for the USB2PHY have made USB mostly working
even when wrong GRF was used, however, following have been observed:
scanning bus usb@fd840000 for devices...
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
unable to get device descriptor (error=-1)
Fix this by using a regmap from rockchip,usbgrf prop and fall back to
getting a regmap for parent udevice instead of always getting the
common GRF.
Also protect against accidental clear of bit 0 in a reg with offset 0,
only bind driver to enabled otg/host-ports and remove unused headers.
Fixes: 3da15f0b49a2 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568")
Fixes: cdf9010f6e17 ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY")
Fixes: 9aa93d84038b ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 41 ++++++++++---------
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 70e61eccb79a..7317128d135e 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -6,23 +6,16 @@
* Copyright (C) 2020 Amarula Solutions(India)
*/
-#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
-#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <generic-phy.h>
-#include <reset.h>
+#include <regmap.h>
#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <linux/iopoll.h>
#include <asm/arch-rockchip/clock.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define usleep_range(a, b) udelay((b))
#define BIT_WRITEABLE_SHIFT 16
@@ -61,30 +54,39 @@ struct rockchip_usb2phy_cfg {
};
struct rockchip_usb2phy {
- void *reg_base;
+ struct regmap *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
};
-static inline int property_enable(void *reg_base,
+static inline int property_enable(struct regmap *base,
const struct usb2phy_reg *reg, bool en)
{
unsigned int val, mask, tmp;
+ if (!reg->offset && !reg->enable && !reg->disable)
+ return 0;
+
tmp = en ? reg->enable : reg->disable;
mask = GENMASK(reg->bitend, reg->bitstart);
val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
- return writel(val, reg_base + reg->offset);
+ return regmap_write(base, reg->offset, val);
}
-static inline bool property_enabled(void *reg_base,
+static inline bool property_enabled(struct regmap *base,
const struct usb2phy_reg *reg)
{
+ int ret;
unsigned int tmp, orig;
unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
- orig = readl(reg_base + reg->offset);
+ if (!reg->offset && !reg->enable && !reg->disable)
+ return false;
+
+ ret = regmap_read(base, reg->offset, &orig);
+ if (ret)
+ return false;
tmp = (orig & mask) >> reg->bitstart;
return tmp != reg->disable;
@@ -248,7 +250,11 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
unsigned int reg;
int index, ret;
- priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (dev_read_bool(dev, "rockchip,usbgrf"))
+ priv->reg_base =
+ syscon_regmap_lookup_by_phandle(dev, "rockchip,usbgrf");
+ else
+ priv->reg_base = syscon_get_regmap(dev_get_parent(dev));
if (IS_ERR(priv->reg_base))
return PTR_ERR(priv->reg_base);
@@ -305,11 +311,8 @@ static int rockchip_usb2phy_bind(struct udevice *dev)
int ret = 0;
dev_for_each_subnode(node, dev) {
- if (!ofnode_valid(node)) {
- dev_info(dev, "subnode %s not found\n", dev->name);
- ret = -ENXIO;
- goto bind_fail;
- }
+ if (!ofnode_is_enabled(node))
+ continue;
name = ofnode_get_name(node);
dev_dbg(dev, "subnode %s\n", name);
From patchwork Sun Feb 25 22:10:20 2024
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From: Jonas Karlman <jonas@kwiboo.se>
To: Kever Yang <kever.yang@rock-chips.com>, Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>, Tom Rini <trini@konsulko.com>
Cc: u-boot@lists.denx.de, Jonas Karlman <jonas@kwiboo.se>
Subject: [PATCH 2/2] phy: rockchip-inno-usb2: Limit changes made to regs
Date: Sun, 25 Feb 2024 22:10:20 +0000
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The USB2PHY regs already contain working default reset values for RK3328
and RK35xx as evidenced by the fact that this driver never has changed a
single value for these SoCs.
Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
what is currently done on RK3399. Also add missing clkout_ctl for RK3588.
When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
use otg/host controller utmi interface to phy. When disabled
utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
interface to phy.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 117 +++---------------
1 file changed, 14 insertions(+), 103 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 7317128d135e..d392aed2d4de 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -35,16 +35,6 @@ struct usb2phy_reg {
struct rockchip_usb2phy_port_cfg {
struct usb2phy_reg phy_sus;
- struct usb2phy_reg bvalid_det_en;
- struct usb2phy_reg bvalid_det_st;
- struct usb2phy_reg bvalid_det_clr;
- struct usb2phy_reg ls_det_en;
- struct usb2phy_reg ls_det_st;
- struct usb2phy_reg ls_det_clr;
- struct usb2phy_reg utmi_avalid;
- struct usb2phy_reg utmi_bvalid;
- struct usb2phy_reg utmi_ls;
- struct usb2phy_reg utmi_hstdet;
};
struct rockchip_usb2phy_cfg {
@@ -131,7 +121,6 @@ static int rockchip_usb2phy_init(struct phy *phy)
{
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
- const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
int ret;
ret = clk_enable(&priv->phyclk);
@@ -140,14 +129,6 @@ static int rockchip_usb2phy_init(struct phy *phy)
return ret;
}
- if (phy->id == USB2PHY_PORT_OTG) {
- property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
- property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
- } else if (phy->id == USB2PHY_PORT_HOST) {
- property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
- property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
- }
-
return 0;
}
@@ -351,27 +332,13 @@ bind_fail:
static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
{
.reg = 0x100,
- .clkout_ctl = { 0x108, 4, 4, 1, 0 },
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
- .bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
- .bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
- .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
- .ls_det_en = { 0x0110, 0, 0, 0, 1 },
- .ls_det_st = { 0x0114, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
- .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
- .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
- .utmi_ls = { 0x0120, 5, 4, 0, 1 },
+ .phy_sus = { 0x0100, 1, 0, 2, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
- .ls_det_en = { 0x110, 1, 1, 0, 1 },
- .ls_det_st = { 0x114, 1, 1, 0, 1 },
- .ls_det_clr = { 0x118, 1, 1, 0, 1 },
- .utmi_ls = { 0x120, 17, 16, 0, 1 },
- .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
+ .phy_sus = { 0x0104, 1, 0, 2, 1 },
}
},
},
@@ -385,19 +352,9 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0xe454, 1, 0, 2, 1 },
- .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
- .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
- .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
- .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
- .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
- .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
- .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
- .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
- .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
- .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
+ .phy_sus = { 0xe458, 1, 0, 2, 1 },
}
},
},
@@ -407,19 +364,9 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0xe464, 1, 0, 2, 1 },
- .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
- .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
- .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
- .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
- .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
- .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
- .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
- .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
- .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
- .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
+ .phy_sus = { 0xe468, 1, 0, 2, 1 },
}
},
},
@@ -432,24 +379,10 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
.clkout_ctl = { 0x0008, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 },
- .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
- .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
- .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
- .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
- .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
+ .phy_sus = { 0x0000, 1, 0, 2, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
- .ls_det_en = { 0x0080, 1, 1, 0, 1 },
- .ls_det_st = { 0x0084, 1, 1, 0, 1 },
- .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
- .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
- .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
+ .phy_sus = { 0x0004, 1, 0, 2, 1 },
}
},
},
@@ -458,20 +391,10 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
.clkout_ctl = { 0x0008, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
- .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
+ .phy_sus = { 0x0000, 1, 0, 2, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
- .ls_det_en = { 0x0080, 1, 1, 0, 1 },
- .ls_det_st = { 0x0084, 1, 1, 0, 1 },
- .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
- .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
- .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
+ .phy_sus = { 0x0004, 1, 0, 2, 1 },
}
},
},
@@ -481,49 +404,37 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
{
.reg = 0x0000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x000c, 11, 11, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
},
},
{
.reg = 0x4000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x000c, 11, 11, 0, 0 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
+ .phy_sus = { 0x000c, 11, 11, 0, 1 },
}
},
},
{
.reg = 0x8000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0008, 2, 2, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
},
},
{
.reg = 0xc000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0008, 2, 2, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
},
},
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