From patchwork Thu Jun 18 14:03:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1312150 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.a=rsa-sha256 header.s=google header.b=p2JV38kW; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49nkDv6QMDz9sVB for ; Fri, 19 Jun 2020 00:03:41 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F2C6382095; Thu, 18 Jun 2020 16:03:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="p2JV38kW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5B7478209C; Thu, 18 Jun 2020 16:03:29 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 405D682094 for ; Thu, 18 Jun 2020 16:03:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jagan@amarulasolutions.com Received: by mail-pg1-x544.google.com with SMTP id l63so2934483pge.12 for ; Thu, 18 Jun 2020 07:03:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CV+hHfK9TAO+pQC8PJPW6c55h0n2inkWKuN1Vxg7SJc=; b=p2JV38kWm3RwP5F+tk+zn9L45s28eZZdf6WYIyRzWvcNpa+cdS5r2EGgYNf9n5Sy+g /2qUb1648TqviMk+h5pYZ5FjHuo/ebvq7kB+XCQUI053og85IzaunFoHWp0lK9JdYMAv BZWNHdEEJxW1ym/a1xbgaG8t5hTQxxZNPW/7E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CV+hHfK9TAO+pQC8PJPW6c55h0n2inkWKuN1Vxg7SJc=; b=qO9U8KokdHUFiqhrRgFl4nHyQYO3tSLB0WtE9txbby4Y03rW0qOlUi7FnGYgDEEZgc l530CIQBkRfWIcv6x0Y96oWXFKYTSrMxX09kM7fwXlk3sIR9TGi9uj2DKkKFN0uxh2Dz P4ona0/qgXZ6c+Uh9zrtdMEPkqgcKrFGmJ6275Y02X1MfAxHOJH9j0IL0QKcVlsVDN1g BM16XxOIG61rkpwCSw5bAG7fKnz88fcdRtIw8V+zZcZbFPlA7qMFRatstz6rXudj8I6W uWOk4Wnia7IdsTKhO2RzcqmAfUrpdSp5igf5Zng67kE8ugEClaOPuPNSMIHXmajvuslz p3Kw== X-Gm-Message-State: AOAM5306s2s9jncJZm6mInFtR87gLRuVCnJdkX506YdcY+iCzHesBfDJ yztzZbfkdUPyBkAU/4qKQ9wodQ== X-Google-Smtp-Source: ABdhPJyGLX2R5Jk5tUcM8s3JQZ7fjp2LkglvCHfsANHUt7Y0AAko/RtPYz1Azex3Cpn1fP2yhCTDzQ== X-Received: by 2002:a62:7ccb:: with SMTP id x194mr3911489pfc.318.1592489003175; Thu, 18 Jun 2020 07:03:23 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:b0c7:f192:869b:df87]) by smtp.gmail.com with ESMTPSA id w18sm2779047pgj.31.2020.06.18.07.03.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 07:03:22 -0700 (PDT) From: Jagan Teki To: Peng Fan Cc: u-boot@lists.denx.de, Jagan Teki , Kever Yang , Suniel Mahesh Subject: [PATCH v4] mmc: sdhci: Fix HISPD bit handling Date: Thu, 18 Jun 2020 19:33:12 +0530 Message-Id: <20200618140312.155157-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean SDHCI HISPD bits need to be configured based on desired mmc timings mode and some HISPD quirks. So, handle the HISPD bit based on the mmc computed selected mode(timing parameter) rather than fixed mmc card clock frequency. Linux handle the HISPD similar like this in below commit but no SDHCI_QUIRK_BROKEN_HISPD_MODE, commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling") This eventually fixed the mmc write issue observed in rk3399 sdhci controller. Bug log for refernece, => gpt write mmc 0 $partitions Writing GPT: mmc write failed ** Can't write to device 0 ** ** Can't write to device 0 ** error! Cc: Kever Yang Cc: Peng Fan Tested-by: Suniel Mahesh # roc-rk3399-pc Signed-off-by: Jagan Teki --- Changes for v4: - update commit message - simplify the logic. drivers/mmc/sdhci.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 92cc8434af..6cb702111b 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -567,6 +567,7 @@ static int sdhci_set_ios(struct mmc *mmc) #endif u32 ctrl; struct sdhci_host *host = mmc->priv; + bool no_hispd_bit = false; if (host->ops && host->ops->set_control_reg) host->ops->set_control_reg(host); @@ -594,14 +595,24 @@ static int sdhci_set_ios(struct mmc *mmc) ctrl &= ~SDHCI_CTRL_4BITBUS; } - if (mmc->clock > 26000000) - ctrl |= SDHCI_CTRL_HISPD; - else - ctrl &= ~SDHCI_CTRL_HISPD; - if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) || (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) - ctrl &= ~SDHCI_CTRL_HISPD; + no_hispd_bit = true; + + if (!no_hispd_bit) { + if (mmc->selected_mode == MMC_HS || + mmc->selected_mode == SD_HS || + mmc->selected_mode == MMC_DDR_52 || + mmc->selected_mode == MMC_HS_200 || + mmc->selected_mode == MMC_HS_400 || + mmc->selected_mode == UHS_SDR25 || + mmc->selected_mode == UHS_SDR50 || + mmc->selected_mode == UHS_SDR104 || + mmc->selected_mode == UHS_DDR50) + ctrl |= SDHCI_CTRL_HISPD; + else + ctrl &= ~SDHCI_CTRL_HISPD; + } sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);