Merge remote-tracking branch 'up/f40' into f40-riscv64

Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
2024.04 GA, rk3328 USB fixes
2024-04-11 16:11:23 +03:00 · 2024-04-03 05:55:01 +01:00 · 2024-03-27 04:44:15 +00:00
4 changed files with 1276 additions and 4 deletions
--- a/phy-rockchip-inno-usb2-Write-to-correct-GRF.patch
+++ b/phy-rockchip-inno-usb2-Write-to-correct-GRF.patch
@ -0,0 +1,572 @@
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+From: Jonas Karlman <jonas@kwiboo.se>
+To: Kever Yang <kever.yang@rock-chips.com>, Simon Glass <sjg@chromium.org>,
+ Philipp Tomsich <philipp.tomsich@vrull.eu>, Tom Rini <trini@konsulko.com>,
+ Ren Jianing <jianing.ren@rock-chips.com>, Manoj Sai
+ <abbaraju.manojsai@amarulasolutions.com>, Jagan Teki
+ <jagan@amarulasolutions.com>, Eugen Hristev <eugen.hristev@collabora.com>,
+ Frank Wang <frank.wang@rock-chips.com>, Xavier Drudis Ferran
+ <xdrudis@tinet.cat>
+Cc: u-boot@lists.denx.de, Jonas Karlman <jonas@kwiboo.se>
+Subject: [PATCH 1/2] phy: rockchip-inno-usb2: Write to correct GRF
+Date: Sun, 25 Feb 2024 22:10:19 +0000
+Message-ID: <20240225221024.1974853-2-jonas@kwiboo.se>
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+
+On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs
+that is supported by this driver have the USB2PHY regs in a different
+GRF.
+
+When support for RK356x, RK3588 and RK3328 was added this driver was
+never updated to use correct GRF and have instead incorrectly written
+to wrong GRF for these SoCs.
+
+The default reset values for the USB2PHY have made USB mostly working
+even when wrong GRF was used, however, following have been observed:
+
+  scanning bus usb@fd840000 for devices...
+  ERROR:  USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
+  not provide a handshake (OUT) (5)
+  ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
+  not provide a handshake (OUT) (5)
+  unable to get device descriptor (error=-1)
+
+Fix this by using a regmap from rockchip,usbgrf prop and fall back to
+getting a regmap for parent udevice instead of always getting the
+common GRF.
+
+Also protect against accidental clear of bit 0 in a reg with offset 0,
+only bind driver to enabled otg/host-ports and remove unused headers.
+
+Fixes: 3da15f0b49a2 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568")
+Fixes: cdf9010f6e17 ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY")
+Fixes: 9aa93d84038b ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328")
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 41 ++++++++++---------
+ 1 file changed, 22 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+index 70e61eccb79a..7317128d135e 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -6,23 +6,16 @@
+  * Copyright (C) 2020 Amarula Solutions(India)
+  */
+ 
+-#include <common.h>
+ #include <clk-uclass.h>
+ #include <dm.h>
+-#include <asm/global_data.h>
+ #include <dm/device_compat.h>
+ #include <dm/device-internal.h>
+ #include <dm/lists.h>
+ #include <generic-phy.h>
+-#include <reset.h>
+#include <regmap.h>
+ #include <syscon.h>
+-#include <asm/gpio.h>
+-#include <asm/io.h>
+-#include <linux/iopoll.h>
+ #include <asm/arch-rockchip/clock.h>
+ 
+-DECLARE_GLOBAL_DATA_PTR;
+-
+ #define usleep_range(a, b) udelay((b))
+ #define BIT_WRITEABLE_SHIFT	16
+ 
+@@ -61,30 +54,39 @@ struct rockchip_usb2phy_cfg {
+ };
+ 
+ struct rockchip_usb2phy {
+-	void *reg_base;
+	struct regmap *reg_base;
+ 	struct clk phyclk;
+ 	const struct rockchip_usb2phy_cfg *phy_cfg;
+ };
+ 
+-static inline int property_enable(void *reg_base,
+static inline int property_enable(struct regmap *base,
+ 				  const struct usb2phy_reg *reg, bool en)
+ {
+ 	unsigned int val, mask, tmp;
+ 
+	if (!reg->offset && !reg->enable && !reg->disable)
+		return 0;
+
+ 	tmp = en ? reg->enable : reg->disable;
+ 	mask = GENMASK(reg->bitend, reg->bitstart);
+ 	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+ 
+-	return writel(val, reg_base + reg->offset);
+	return regmap_write(base, reg->offset, val);
+ }
+ 
+-static inline bool property_enabled(void *reg_base,
+static inline bool property_enabled(struct regmap *base,
+ 				    const struct usb2phy_reg *reg)
+ {
+	int ret;
+ 	unsigned int tmp, orig;
+ 	unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
+ 
+-	orig = readl(reg_base + reg->offset);
+	if (!reg->offset && !reg->enable && !reg->disable)
+		return false;
+
+	ret = regmap_read(base, reg->offset, &orig);
+	if (ret)
+		return false;
+ 
+ 	tmp = (orig & mask) >> reg->bitstart;
+ 	return tmp != reg->disable;
+@@ -248,7 +250,11 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
+ 	unsigned int reg;
+ 	int index, ret;
+ 
+-	priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (dev_read_bool(dev, "rockchip,usbgrf"))
+		priv->reg_base =
+			syscon_regmap_lookup_by_phandle(dev, "rockchip,usbgrf");
+	else
+		priv->reg_base = syscon_get_regmap(dev_get_parent(dev));
+ 	if (IS_ERR(priv->reg_base))
+ 		return PTR_ERR(priv->reg_base);
+ 
+@@ -305,11 +311,8 @@ static int rockchip_usb2phy_bind(struct udevice *dev)
+ 	int ret = 0;
+ 
+ 	dev_for_each_subnode(node, dev) {
+-		if (!ofnode_valid(node)) {
+-			dev_info(dev, "subnode %s not found\n", dev->name);
+-			ret = -ENXIO;
+-			goto bind_fail;
+-		}
+		if (!ofnode_is_enabled(node))
+			continue;
+ 
+ 		name = ofnode_get_name(node);
+ 		dev_dbg(dev, "subnode %s\n", name);
+
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+From: Jonas Karlman <jonas@kwiboo.se>
+To: Kever Yang <kever.yang@rock-chips.com>, Simon Glass <sjg@chromium.org>,
+ Philipp Tomsich <philipp.tomsich@vrull.eu>, Tom Rini <trini@konsulko.com>
+Cc: u-boot@lists.denx.de, Jonas Karlman <jonas@kwiboo.se>
+Subject: [PATCH 2/2] phy: rockchip-inno-usb2: Limit changes made to regs
+Date: Sun, 25 Feb 2024 22:10:20 +0000
+Message-ID: <20240225221024.1974853-3-jonas@kwiboo.se>
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+
+The USB2PHY regs already contain working default reset values for RK3328
+and RK35xx as evidenced by the fact that this driver never has changed a
+single value for these SoCs.
+
+Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
+what is currently done on RK3399. Also add missing clkout_ctl for RK3588.
+
+When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
+use otg/host controller utmi interface to phy. When disabled
+utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
+interface to phy.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 117 +++---------------
+ 1 file changed, 14 insertions(+), 103 deletions(-)
+
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+index 7317128d135e..d392aed2d4de 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -35,16 +35,6 @@ struct usb2phy_reg {
+ 
+ struct rockchip_usb2phy_port_cfg {
+ 	struct usb2phy_reg	phy_sus;
+-	struct usb2phy_reg	bvalid_det_en;
+-	struct usb2phy_reg	bvalid_det_st;
+-	struct usb2phy_reg	bvalid_det_clr;
+-	struct usb2phy_reg	ls_det_en;
+-	struct usb2phy_reg	ls_det_st;
+-	struct usb2phy_reg	ls_det_clr;
+-	struct usb2phy_reg	utmi_avalid;
+-	struct usb2phy_reg	utmi_bvalid;
+-	struct usb2phy_reg	utmi_ls;
+-	struct usb2phy_reg	utmi_hstdet;
+ };
+ 
+ struct rockchip_usb2phy_cfg {
+@@ -131,7 +121,6 @@ static int rockchip_usb2phy_init(struct phy *phy)
+ {
+ 	struct udevice *parent = dev_get_parent(phy->dev);
+ 	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+-	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+ 	int ret;
+ 
+ 	ret = clk_enable(&priv->phyclk);
+@@ -140,14 +129,6 @@ static int rockchip_usb2phy_init(struct phy *phy)
+ 		return ret;
+ 	}
+ 
+-	if (phy->id == USB2PHY_PORT_OTG) {
+-		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+-		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+-	} else if (phy->id == USB2PHY_PORT_HOST) {
+-		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+-		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -351,27 +332,13 @@ bind_fail:
+ static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
+ 	{
+ 		.reg = 0x100,
+-		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
+		.clkout_ctl	= { 0x0108, 4, 4, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+-				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
+-				.bvalid_det_en	= { 0x0110, 3, 2, 0, 3 },
+-				.bvalid_det_st	= { 0x0114, 3, 2, 0, 3 },
+-				.bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
+-				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
+-				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
+-				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
+-				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
+-				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
+-				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
+				.phy_sus	= { 0x0100, 1, 0, 2, 1 },
+ 			},
+ 			[USB2PHY_PORT_HOST] = {
+-				.phy_sus	= { 0x104, 15, 0, 0, 0x1d1 },
+-				.ls_det_en	= { 0x110, 1, 1, 0, 1 },
+-				.ls_det_st	= { 0x114, 1, 1, 0, 1 },
+-				.ls_det_clr	= { 0x118, 1, 1, 0, 1 },
+-				.utmi_ls	= { 0x120, 17, 16, 0, 1 },
+-				.utmi_hstdet	= { 0x120, 19, 19, 0, 1 }
+				.phy_sus	= { 0x0104, 1, 0, 2, 1 },
+ 			}
+ 		},
+ 	},
+@@ -385,19 +352,9 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+ 				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
+-				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
+-				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
+-				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
+-				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
+-				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
+ 			},
+ 			[USB2PHY_PORT_HOST] = {
+-				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
+-				.ls_det_en	= { 0xe3c0, 6, 6, 0, 1 },
+-				.ls_det_st	= { 0xe3e0, 6, 6, 0, 1 },
+-				.ls_det_clr	= { 0xe3d0, 6, 6, 0, 1 },
+-				.utmi_ls	= { 0xe2ac, 22, 21, 0, 1 },
+-				.utmi_hstdet	= { 0xe2ac, 23, 23, 0, 1 }
+				.phy_sus	= { 0xe458, 1, 0, 2, 1 },
+ 			}
+ 		},
+ 	},
+@@ -407,19 +364,9 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+ 				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
+-				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
+-				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
+-				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
+-				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
+-				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
+ 			},
+ 			[USB2PHY_PORT_HOST] = {
+-				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
+-				.ls_det_en	= { 0xe3c0, 11, 11, 0, 1 },
+-				.ls_det_st	= { 0xe3e0, 11, 11, 0, 1 },
+-				.ls_det_clr	= { 0xe3d0, 11, 11, 0, 1 },
+-				.utmi_ls	= { 0xe2ac, 26, 25, 0, 1 },
+-				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
+				.phy_sus	= { 0xe468, 1, 0, 2, 1 },
+ 			}
+ 		},
+ 	},
+@@ -432,24 +379,10 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
+ 		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+-				.phy_sus	= { 0x0000, 8, 0, 0x052, 0x1d1 },
+-				.bvalid_det_en	= { 0x0080, 2, 2, 0, 1 },
+-				.bvalid_det_st	= { 0x0084, 2, 2, 0, 1 },
+-				.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
+-				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
+-				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
+-				.utmi_avalid	= { 0x00c0, 10, 10, 0, 1 },
+-				.utmi_bvalid	= { 0x00c0, 9, 9, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
+				.phy_sus	= { 0x0000, 1, 0, 2, 1 },
+ 			},
+ 			[USB2PHY_PORT_HOST] = {
+-				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },
+-				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
+-				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
+-				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
+				.phy_sus	= { 0x0004, 1, 0, 2, 1 },
+ 			}
+ 		},
+ 	},
+@@ -458,20 +391,10 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
+ 		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+-				.phy_sus	= { 0x0000, 8, 0, 0x1d2, 0x1d1 },
+-				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
+-				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
+-				.utmi_hstdet	= { 0x00c0, 7, 7, 0, 1 }
+				.phy_sus	= { 0x0000, 1, 0, 2, 1 },
+ 			},
+ 			[USB2PHY_PORT_HOST] = {
+-				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },
+-				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
+-				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
+-				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
+				.phy_sus	= { 0x0004, 1, 0, 2, 1 },
+ 			}
+ 		},
+ 	},
+@@ -481,49 +404,37 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
+ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
+ 	{
+ 		.reg		= 0x0000,
+		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+ 				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
+-				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
+-				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
+ 			}
+ 		},
+ 	},
+ 	{
+ 		.reg		= 0x4000,
+		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+-				.phy_sus	= { 0x000c, 11, 11, 0, 0 },
+-				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
+-				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
+				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
+ 			}
+ 		},
+ 	},
+ 	{
+ 		.reg		= 0x8000,
+		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_HOST] = {
+ 				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
+-				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
+-				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
+ 			}
+ 		},
+ 	},
+ 	{
+ 		.reg		= 0xc000,
+		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_HOST] = {
+ 				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
+-				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
+-				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
+-				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
+-				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
+ 			}
+ 		},
+ 	},
--- a/rockchip-Migrate-to-use-DM_USB_GADGET-on-RK3328.patch
+++ b/rockchip-Migrate-to-use-DM_USB_GADGET-on-RK3328.patch
@ -0,0 +1,691 @@
+From 0149cf303734fad55f1d733628f76a6994d1436d Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 10 Mar 2024 18:50:57 +0000
+Subject: [PATCH 1/4] rockchip: Update the default USB Product ID value
+
+RK3036 is using the USB product id normally used by RK3066B, and RK3328
+is using the product id normally used by RK3368.
+
+Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option
+for remaining supported Rockchip SoCs to match the product id used in
+Maskrom mode.
+
+Also remove a reference to an undefined ROCKCHIP_RK3229 Kconfig symbol.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ drivers/usb/gadget/Kconfig | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
+index c72a8047635..4621a6fd5e6 100644
+--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
+@@ -70,12 +70,21 @@ config USB_GADGET_PRODUCT_NUM
+ 	hex "Product ID of the USB device"
+ 	default 0x701a if ARCH_TEGRA
+ 	default 0x1010 if ARCH_SUNXI
+-	default 0x310a if ROCKCHIP_RK3036
+	default 0x110a if ROCKCHIP_RV1108
+	default 0x110b if ROCKCHIP_RV1126
+ 	default 0x300a if ROCKCHIP_RK3066
+	default 0x301a if ROCKCHIP_RK3036
+	default 0x310b if ROCKCHIP_RK3188
+ 	default 0x310c if ROCKCHIP_RK3128
+-	default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288
+-	default 0x330a if ROCKCHIP_RK3328
+	default 0x320a if ROCKCHIP_RK3288
+	default 0x320b if ROCKCHIP_RK322X
+	default 0x320c if ROCKCHIP_RK3328
+	default 0x330a if ROCKCHIP_RK3368
+ 	default 0x330c if ROCKCHIP_RK3399
+	default 0x330d if ROCKCHIP_PX30
+	default 0x330e if ROCKCHIP_RK3308
+	default 0x350a if ROCKCHIP_RK3568
+	default 0x350b if ROCKCHIP_RK3588
+ 	default 0x0
+ 	help
+ 	  Product ID of the USB device emulated, reported to the host device.
+-- 
+2.44.0
+
+From 3b4d52ef627bb3899c331ff24fe31cec5f445069 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 10 Mar 2024 18:50:58 +0000
+Subject: [PATCH 2/4] rockchip: board: Prepare for use of DM_USB_GADGET with
+ DWC2_OTG
+
+The board_usb_init() and board_usb_cleanup() functions is always
+included when USB_GADGET and USB_GADGET_DWC2_OTG is enabled.
+
+Prepare for a change to use DM_USB_GADGET with DWC2_OTG by adding an
+extra ifdef condition. The extra separate ifdef for USB_GADGET prepare
+for next patch that adds a g_dnl_bind_fixup() function.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ arch/arm/mach-rockchip/board.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
+index 2620530e03f..2ec670dde69 100644
+--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
+@@ -205,7 +205,8 @@ void enable_caches(void)
+ }
+ #endif
+ 
+-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#if IS_ENABLED(CONFIG_USB_GADGET)
+#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET)
+ #include <usb.h>
+ #include <linux/usb/otg.h>
+ #include <usb/dwc2_udc.h>
+@@ -281,6 +282,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
+ 	return 0;
+ }
+ #endif /* CONFIG_USB_GADGET_DWC2_OTG */
+#endif /* CONFIG_USB_GADGET */
+ 
+ #if IS_ENABLED(CONFIG_FASTBOOT)
+ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
+-- 
+2.44.0
+
+From 201da409a8c879482a00867010b772327aba6a51 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 10 Mar 2024 18:50:59 +0000
+Subject: [PATCH 3/4] rockchip: board: Use a common USB Product ID for UMS
+
+Change to use the common Product ID 0x0010 when the ums command is used.
+
+This matches downstream vendor U-Boot and is a Product ID that tools
+such as rkdeveloptool and RKDevTool will identify as MSC mode.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+---
+ arch/arm/mach-rockchip/board.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
+index 2ec670dde69..2db746b27fb 100644
+--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
+@@ -206,8 +206,23 @@ void enable_caches(void)
+ #endif
+ 
+ #if IS_ENABLED(CONFIG_USB_GADGET)
+-#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET)
+ #include <usb.h>
+
+#if IS_ENABLED(CONFIG_USB_GADGET_DOWNLOAD)
+#define ROCKCHIP_G_DNL_UMS_PRODUCT_NUM	0x0010
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	if (!strcmp(name, "usb_dnl_ums"))
+		put_unaligned(ROCKCHIP_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct);
+	else
+		put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
+
+	return 0;
+}
+#endif /* CONFIG_USB_GADGET_DOWNLOAD */
+
+#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET)
+ #include <linux/usb/otg.h>
+ #include <usb/dwc2_udc.h>
+ 
+-- 
+2.44.0
+
+From 2cb2428ae571956dfafb2eeed8b54857b12e17d0 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Wed, 3 Apr 2024 05:29:20 +0100
+Subject: [PATCH 4/4] rockchip: Migrate to use DM_USB_GADGET on RK3328
+
+USB gadget is not working fully as expected on RK3328, it uses a
+board_usb_init() function to initialize the DWC2 OTG port.
+
+The board_usb_init() function does not intgrate with the generic phy
+framework and as a result the USB phy is not properly configured before
+or after USB gadget use.
+
+Having both USB_DWC2 and DWC2_OTG enabled for the same board is also
+causing some issues.
+
+Trying to use rockusb or ums command after usb stop result in a freeze
+due to usb stop is putting the phy in a suspended state.
+
+  => usb start
+  => usb stop
+  => ums 0 mmc 0
+  --> freeze due to usb phy is suspended <--
+
+Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral)
+depending on the most likely usage of the otg port and by migrating to
+use DM_USB_GADGET instead of a board_usb_init() function.
+
+The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a
+Type-C connector, mark these boards dr_mode as peripheral, the most
+likely usage is for recovery and image download.
+
+The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG
+driver from these boards to ensure that the USB_DWC2 driver is used.
+
+The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2
+and DWC2_OTG is removed from this board.
+
+Enable RockUSB and UMS on all boards with a otg port in peripheral mode.
+
+Also with the migration to DM_USB_GADGET completed the U-Boot specific
+change to reorder usb nodes in the soc device tree can be reverted.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi    |  4 ++
+ .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi   |  4 ++
+ .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi   |  4 ++
+ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi        |  4 ++
+ arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi     |  9 ++++
+ arch/arm/dts/rk3328-rock64-u-boot.dtsi        |  4 ++
+ arch/arm/dts/rk3328-u-boot.dtsi               |  4 --
+ arch/arm/dts/rk3328.dtsi                      | 41 ++++++++-----------
+ configs/evb-rk3328_defconfig                  |  7 +++-
+ configs/nanopi-r2c-plus-rk3328_defconfig      |  7 +++-
+ configs/nanopi-r2c-rk3328_defconfig           |  7 +++-
+ configs/nanopi-r2s-rk3328_defconfig           |  7 +++-
+ configs/orangepi-r1-plus-lts-rk3328_defconfig |  7 +++-
+ configs/orangepi-r1-plus-rk3328_defconfig     |  7 +++-
+ configs/roc-cc-rk3328_defconfig               |  7 ----
+ configs/rock-pi-e-rk3328_defconfig            |  7 ----
+ configs/rock64-rk3328_defconfig               |  6 ---
+ 17 files changed, 75 insertions(+), 61 deletions(-)
+
+diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+index 78d37ab4755..3a16f86c18a 100644
+--- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+@@ -28,6 +28,10 @@
+ 	bootph-pre-ram;
+ };
+ 
+&usb20_otg {
+	dr_mode = "peripheral";
+};
+
+ /* Need this and all the pinctrl/gpio stuff above to set pinmux */
+ &vcc_sd {
+ 	bootph-pre-ram;
+diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+index ebe33e48cb9..2247daebc13 100644
+--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+@@ -28,6 +28,10 @@
+ 	bootph-pre-ram;
+ };
+ 
+&usb20_otg {
+	dr_mode = "peripheral";
+};
+
+ /* Need this and all the pinctrl/gpio stuff above to set pinmux */
+ &vcc_sd {
+ 	bootph-pre-ram;
+diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+index 637c70adf19..79942a49a29 100644
+--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+@@ -28,6 +28,10 @@
+ 	bootph-pre-ram;
+ };
+ 
+&usb20_otg {
+	dr_mode = "peripheral";
+};
+
+ /* Need this and all the pinctrl/gpio stuff above to set pinmux */
+ &vcc_sd {
+ 	bootph-pre-ram;
+diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+index 2062f34bf82..1aeb0083631 100644
+--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+@@ -48,6 +48,10 @@
+ 	bootph-pre-ram;
+ };
+ 
+&usb20_otg {
+	hnp-srp-disable;
+};
+
+ /* Need this and all the pinctrl/gpio stuff above to set pinmux */
+ &vcc_sd {
+ 	bootph-pre-ram;
+diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+index 1f220c6dcd0..c2371fb1688 100644
+--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+@@ -45,6 +45,15 @@
+ 	bootph-pre-ram;
+ };
+ 
+&u2phy_host {
+	phy-supply = <&vcc_host_5v>;
+};
+
+&vcc_host_5v {
+	/delete-property/ regulator-always-on;
+	/delete-property/ regulator-boot-on;
+};
+
+ /* Need this and all the pinctrl/gpio stuff above to set pinmux */
+ &vcc_sd {
+ 	bootph-pre-ram;
+diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+index 6904515b969..1e4649ae120 100644
+--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+@@ -48,6 +48,10 @@
+ 	bootph-pre-ram;
+ };
+ 
+&usb20_otg {
+	hnp-srp-disable;
+};
+
+ /* Need this and all the pinctrl/gpio stuff above to set pinmux */
+ &vcc_sd {
+ 	bootph-pre-ram;
+diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
+index a9f2536de2a..b5da4518ec9 100644
+--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
+@@ -61,10 +61,6 @@
+ 	u-boot,spl-fifo-mode;
+ };
+ 
+-&usb20_otg {
+-	hnp-srp-disable;
+-};
+-
+ &spi0 {
+ 	bootph-all;
+ };
+diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
+index e8d8f00be8a..8c821acb21f 100644
+--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
+@@ -944,6 +944,22 @@
+ 		};
+ 	};
+ 
+	usb20_otg: usb@ff580000 {
+		compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+			     "snps,dwc2";
+		reg = <0x0 0xff580000 0x0 0x40000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_OTG>;
+		clock-names = "otg";
+		dr_mode = "otg";
+		g-np-tx-fifo-size = <16>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
+		phys = <&u2phy_otg>;
+		phy-names = "usb2-phy";
+		status = "disabled";
+	};
+
+ 	usb_host0_ehci: usb@ff5c0000 {
+ 		compatible = "generic-ehci";
+ 		reg = <0x0 0xff5c0000 0x0 0x10000>;
+@@ -983,31 +999,6 @@
+ 		status = "disabled";
+ 	};
+ 
+-	/*
+-	 * U-Boot Specific Change
+-	 *
+-	 * The OTG controller must come after the USB host pair for it
+-	 * to work. This is likely due to lack of support for the USB
+-	 * PHYs. This must be manually changed after each device tree
+-	 * sync. There is no clean way to handle this in -u-boot.dtsi
+-	 * files.
+-	 */
+-	usb20_otg: usb@ff580000 {
+-		compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+-			     "snps,dwc2";
+-		reg = <0x0 0xff580000 0x0 0x40000>;
+-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cru HCLK_OTG>;
+-		clock-names = "otg";
+-		dr_mode = "otg";
+-		g-np-tx-fifo-size = <16>;
+-		g-rx-fifo-size = <280>;
+-		g-tx-fifo-size = <256 128 128 64 32 16>;
+-		phys = <&u2phy_otg>;
+-		phy-names = "usb2-phy";
+-		status = "disabled";
+-	};
+-
+ 	gic: interrupt-controller@ff811000 {
+ 		compatible = "arm,gic-400";
+ 		#interrupt-cells = <3>;
+diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
+index b9c541a92a1..ed2e2b7aa6f 100644
+--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
+@@ -46,6 +46,8 @@ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+@@ -93,17 +95,18 @@ CONFIG_SYS_NS16550_MEM32=y
+ CONFIG_SYSRESET=y
+ # CONFIG_TPL_SYSRESET is not set
+ CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+ CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+-CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+-CONFIG_USB_DWC3_GENERIC=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig
+index 320ed8b434a..015bcfef369 100644
+--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
+@@ -48,6 +48,8 @@ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+@@ -98,17 +100,18 @@ CONFIG_SYSINFO=y
+ CONFIG_SYSRESET=y
+ # CONFIG_TPL_SYSRESET is not set
+ CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+ CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+-CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+-CONFIG_USB_DWC3_GENERIC=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
+index 583179d7c54..5742567a3d4 100644
+--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
+@@ -48,6 +48,8 @@ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+@@ -98,17 +100,18 @@ CONFIG_SYSINFO=y
+ CONFIG_SYSRESET=y
+ # CONFIG_TPL_SYSRESET is not set
+ CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+ CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+-CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+-CONFIG_USB_DWC3_GENERIC=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
+index f7ed71e4122..180a76e0eeb 100644
+--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
+@@ -48,6 +48,8 @@ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+@@ -98,17 +100,18 @@ CONFIG_SYSINFO=y
+ CONFIG_SYSRESET=y
+ # CONFIG_TPL_SYSRESET is not set
+ CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+ CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+-CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+-CONFIG_USB_DWC3_GENERIC=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
+index d3d9417509e..a1a96bf2f28 100644
+--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
+@@ -48,6 +48,8 @@ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+@@ -99,17 +101,18 @@ CONFIG_SYSINFO=y
+ CONFIG_SYSRESET=y
+ # CONFIG_TPL_SYSRESET is not set
+ CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+ CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+-CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+-CONFIG_USB_DWC3_GENERIC=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
+index 9356e87132e..04273a0491c 100644
+--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
+@@ -48,6 +48,8 @@ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+@@ -99,17 +101,18 @@ CONFIG_SYSINFO=y
+ CONFIG_SYSRESET=y
+ # CONFIG_TPL_SYSRESET is not set
+ CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+ CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+-CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+ # CONFIG_USB_DWC3_GADGET is not set
+-CONFIG_USB_DWC3_GENERIC=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
+index 4ac3c9403b0..0e4edcc999d 100644
+--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
+@@ -23,7 +23,6 @@ CONFIG_DEBUG_UART_BASE=0xFF130000
+ CONFIG_DEBUG_UART_CLOCK=24000000
+ CONFIG_SYS_LOAD_ADDR=0x800800
+ CONFIG_DEBUG_UART=y
+-# CONFIG_ANDROID_BOOT_IMAGE is not set
+ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_SPL_LOAD_FIT=y
+@@ -48,7 +47,6 @@ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPT=y
+ CONFIG_CMD_MMC=y
+ CONFIG_CMD_USB=y
+-CONFIG_CMD_USB_MASS_STORAGE=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+@@ -68,8 +66,6 @@ CONFIG_SPL_SYSCON=y
+ CONFIG_TPL_SYSCON=y
+ CONFIG_CLK=y
+ CONFIG_SPL_CLK=y
+-CONFIG_FASTBOOT_BUF_ADDR=0x800800
+-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
+@@ -110,10 +106,7 @@ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+-# CONFIG_USB_DWC3_GADGET is not set
+ CONFIG_USB_DWC3_GENERIC=y
+-CONFIG_USB_GADGET=y
+-CONFIG_USB_GADGET_DWC2_OTG=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
+index 6dda900a9b4..6a4284120d2 100644
+--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
+@@ -24,7 +24,6 @@ CONFIG_DEBUG_UART_BASE=0xFF130000
+ CONFIG_DEBUG_UART_CLOCK=24000000
+ CONFIG_SYS_LOAD_ADDR=0x800800
+ CONFIG_DEBUG_UART=y
+-# CONFIG_ANDROID_BOOT_IMAGE is not set
+ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_SPL_LOAD_FIT=y
+@@ -69,8 +68,6 @@ CONFIG_SPL_SYSCON=y
+ CONFIG_TPL_SYSCON=y
+ CONFIG_CLK=y
+ CONFIG_SPL_CLK=y
+-CONFIG_FASTBOOT_BUF_ADDR=0x800800
+-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
+@@ -109,12 +106,8 @@ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_GENERIC=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+-CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+-# CONFIG_USB_DWC3_GADGET is not set
+ CONFIG_USB_DWC3_GENERIC=y
+-CONFIG_USB_GADGET=y
+-CONFIG_USB_GADGET_DWC2_OTG=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
+index 0297d098761..fd42059565a 100644
+--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
+@@ -23,7 +23,6 @@ CONFIG_DEBUG_UART_BASE=0xFF130000
+ CONFIG_DEBUG_UART_CLOCK=24000000
+ CONFIG_SYS_LOAD_ADDR=0x800800
+ CONFIG_DEBUG_UART=y
+-# CONFIG_ANDROID_BOOT_IMAGE is not set
+ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_SPL_LOAD_FIT=y
+@@ -67,8 +66,6 @@ CONFIG_SPL_SYSCON=y
+ CONFIG_TPL_SYSCON=y
+ CONFIG_CLK=y
+ CONFIG_SPL_CLK=y
+-CONFIG_FASTBOOT_BUF_ADDR=0x800800
+-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
+@@ -111,10 +108,7 @@ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_GENERIC=y
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_DWC3=y
+-# CONFIG_USB_DWC3_GADGET is not set
+ CONFIG_USB_DWC3_GENERIC=y
+-CONFIG_USB_GADGET=y
+-CONFIG_USB_GADGET_DWC2_OTG=y
+ CONFIG_SPL_TINY_MEMSET=y
+ CONFIG_TPL_TINY_MEMSET=y
+ CONFIG_ERRNO_STR=y
+-- 
+2.44.0
+
--- a/2
+++ b/2
@ -1 +1 @@
-SHA512 (u-boot-2024.04-rc4.tar.bz2) = 4a546eb790d54c9aadd423888baa5c909249afeedfd71f85c8b424421c08463b0e65f3addfc2d00f4a38fb56d8051ed70c8368d49a89bd33ec69773474d4d62d
+SHA512 (u-boot-2024.04.tar.bz2) = a71270302b38e9e68a83b3acdf8f7635f72d9fa75169e3c2241cdfa21eab834b8f25dfd35c281191bccb2fcec1e86d6b64afcf1d2ed5cd4fdc02258cd75fc236
--- a/uboot-tools.spec
+++ b/uboot-tools.spec
@ -1,4 +1,4 @@
-%global candidate rc4
+#global candidate rc5
 %if 0%{?rhel}
 %bcond_with toolsonly
 %else
@ -10,7 +10,7 @@

 Name:     uboot-tools
 Version:  2024.04
-Release:  0.7%{?candidate:.%{candidate}}.0.riscv64%{?dist}
+Release:  1%{?candidate:.%{candidate}}.0.riscv64%{?dist}
 Epoch:    1
 Summary:  U-Boot utilities
 License:  GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
@ -39,6 +39,8 @@ Patch10:  rpi-Switch-to-OF_HAS_PRIOR_STAGE-by-default.patch
 # Rockchips improvements
 Patch11:  rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
 Patch12:  rockchip-Enable-preboot-start-for-pci-usb.patch
+Patch13:  phy-rockchip-inno-usb2-Write-to-correct-GRF.patch
+Patch14:  rockchip-Migrate-to-use-DM_USB_GADGET-on-RK3328.patch

 # RISCV (riscv64):
 Patch20: improve-riscv64-configs.patch
@ -232,9 +234,16 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir}
 %endif

 %changelog
-* Fri Mar 22 2024 David Abdurachmanov <davidlt@rivosinc.com> - 1:2024.04-0.7.rc4.0.riscv64
+* Thu Apr 11 2024 David Abdurachmanov <davidlt@rivosinc.com> - 1:2024.04-1.0.riscv64
 - Add support for riscv64

+* Wed Apr 03 2024 Peter Robinson <pbrobinson@fedoraproject.org> - 1:2024.04-1
+- Update to 2024.04 GA
+- Rockchip rk3328 USB fixes
+
+* Wed Mar 27 2024 Peter Robinson <pbrobinson@fedoraproject.org> - 1:2024.04-0.8.rc5
+- Update to 2024.04 RC5
+
 * Thu Mar 21 2024 Peter Robinson <pbrobinson@fedoraproject.org> - 1:2024.04-0.7.rc4
 - Updated patch for DTB loading
Author	SHA1	Message	Date
David Abdurachmanov	e9602bfe2d	Merge remote-tracking branch 'up/f40' into f40-riscv64 Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>	2024-04-11 16:11:23 +03:00
Peter Robinson	dcafedfd49	2024.04 GA, rk3328 USB fixes	2024-04-03 05:55:01 +01:00
Peter Robinson	2a31c9025b	2024.04 RC5	2024-03-27 04:44:15 +00:00