Add support for riscv64

Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
Merge branch 'rawhide' into f38
2023-05-03 11:03:58 +03:00 · 2023-04-06 07:57:20 +01:00 · 2023-04-05 23:03:46 +01:00 · 2023-04-05 22:53:23 +01:00 · 2023-04-02 22:33:04 +01:00 · 2023-03-14 17:19:11 +00:00
12 changed files with 475 additions and 636 deletions
--- a/0001-Improve-riscv-defconfigs.patch
+++ b/0001-Improve-riscv-defconfigs.patch
@ -0,0 +1,102 @@
+From 71cc03c5c98c4d2dbf13061690f61394711ccc66 Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <davidlt@rivosinc.com>
+Date: Wed, 3 May 2023 07:33:11 +0000
+Subject: [PATCH 1/3] Improve riscv defconfigs
+
+- Enable "sbi" command.
+- Enable SBI based reset and poweroff commands.
+- Set max supported CPUs on QEMU targets to 32.
+- Enable relocation and use firmware FDT/DTB (i.e. generated by QEMU) for QEMU targets.
+
+Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
+---
+ configs/qemu-riscv64_defconfig       | 8 ++++++++
+ configs/qemu-riscv64_smode_defconfig | 5 +++++
+ configs/qemu-riscv64_spl_defconfig   | 3 +++
+ configs/sifive_unleashed_defconfig   | 5 +++++
+ configs/sifive_unmatched_defconfig   | 5 +++++
+ include/configs/qemu-riscv.h         | 2 --
+ 6 files changed, 26 insertions(+), 2 deletions(-)
+
+diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
+index d64f3400..09816973 100644
+--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
+@@ -23,3 +23,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+ CONFIG_DM_MTD=y
+ CONFIG_FLASH_SHOW_PROGRESS=0
+ CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_NR_CPUS=32
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x20000;"
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
+index 53c2f489..c9bdc485 100644
+--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
+@@ -26,3 +26,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+ CONFIG_DM_MTD=y
+ CONFIG_FLASH_SHOW_PROGRESS=0
+ CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
+index 9c8eb155..de65d4f0 100644
+--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
+@@ -28,3 +28,6 @@ CONFIG_DM_MTD=y
+ CONFIG_FLASH_SHOW_PROGRESS=0
+ CONFIG_SYS_MAX_FLASH_BANKS=2
+ # CONFIG_BINMAN_FDT is not set
+CONFIG_NR_CPUS=32
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x20000;"
+diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
+index ae0f9b42..c4958785 100644
+--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
+@@ -41,3 +41,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+ CONFIG_SPL_DM_SEQ_ALIAS=y
+ CONFIG_SPL_CLK=y
+ CONFIG_DM_MTD=y
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
+index c24feb68..74cdb4ea 100644
+--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
+@@ -63,3 +63,8 @@ CONFIG_DM_SCSI=y
+ CONFIG_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_PCI=y
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
+index 20135f56..23db7b6f 100644
+--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
+@@ -35,8 +35,6 @@
+ 	"qemu "
+ 
+ #define CFG_EXTRA_ENV_SETTINGS \
+-	"fdt_high=0xffffffffffffffff\0" \
+-	"initrd_high=0xffffffffffffffff\0" \
+ 	"kernel_addr_r=0x84000000\0" \
+ 	"kernel_comp_addr_r=0x88000000\0" \
+ 	"kernel_comp_size=0x4000000\0" \
+-- 
+2.40.1
+
--- a/0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
+++ b/0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
@ -0,0 +1,104 @@
+From 039f475da3e1e140ef5dd0c6d8dfb0676af0d39e Mon Sep 17 00:00:00 2001
+From: Vincent Chen <vincent.chen@sifive.com>
+Date: Wed, 3 May 2023 07:34:48 +0000
+Subject: [PATCH 2/3] board: sifive: spl: Initialized the PWM setting in the
+ SPL stage
+
+LEDs and multiple fans can be controlled by SPL. This patch ensures
+that all fans have been enabled in the SPL stage. In addition, the
+LED's color will be set to yellow.
+---
+ board/sifive/unmatched/Makefile |  1 +
+ board/sifive/unmatched/pwm.c    | 57 +++++++++++++++++++++++++++++++++
+ board/sifive/unmatched/spl.c    |  2 ++
+ 3 files changed, 60 insertions(+)
+ create mode 100644 board/sifive/unmatched/pwm.c
+
+diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
+index 13453300..5df01982 100644
+--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
+@@ -9,3 +9,4 @@ obj-y += spl.o
+ else
+ obj-y += unmatched.o
+ endif
+obj-y += pwm.o
+diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
+new file mode 100644
+index 00000000..e1cc0231
+--- /dev/null
+++ b/board/sifive/unmatched/pwm.c
+@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021, SiFive Inc
+ *
+ * Authors:
+ *   Vincent Chen <vincent.chen@sifive.com>
+ *   David Abdurachmanov <david.abdurachmanov@sifive.com>
+ */
+
+#include <linux/io.h>
+#include <asm/arch/eeprom.h>
+
+struct pwm_sifive_regs {
+	unsigned int cfg;	/* PWM configuration register */
+	unsigned int pad0;	/* Reserved */
+	unsigned int cnt;	/* PWM count register */
+	unsigned int pad1;	/* Reserved */
+	unsigned int pwms;	/* Scaled PWM count register */
+	unsigned int pad2;	/* Reserved */
+	unsigned int pad3;	/* Reserved */
+	unsigned int pad4;	/* Reserved */
+	unsigned int cmp0;	/* PWM 0 compare register */
+	unsigned int cmp1;	/* PWM 1 compare register */
+	unsigned int cmp2;	/* PWM 2 compare register */
+	unsigned int cmp3;	/* PWM 3 compare register */
+};
+
+#define PWM0_BASE		0x10020000
+#define PWM1_BASE		0x10021000
+#define PWM_CFG_INIT		0x1000
+#define PWM_CMP_ENABLE_VAL	0x0
+#define PWM_CMP_DISABLE_VAL	0xffff
+
+void pwm_device_init(void)
+{
+	struct pwm_sifive_regs *pwm0, *pwm1;
+	pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
+	pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
+	/* Set the 3-color PWM LEDs to yellow in SPL */
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+	writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
+
+	writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+	/* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
+	/* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
+	   so here sets the initial value of PWM_COMP0 as DISABLE */
+	if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
+		writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
+	else
+		writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
+	writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+	writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+}
+diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
+index 7c0beedc..f3a661a8 100644
+--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
+@@ -90,6 +90,8 @@ int spl_board_init_f(void)
+ 		goto end;
+ 	}
+ 
+	pwm_device_init();
+
+ 	ret = spl_gemgxl_init();
+ 	if (ret) {
+ 		debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
+-- 
+2.40.1
+
--- a/0003-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
+++ b/0003-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
@ -0,0 +1,123 @@
+From e1dcf7e7a3b5c0e76171ba0b7145af12693adcc4 Mon Sep 17 00:00:00 2001
+From: Vincent Chen <vincent.chen@sifive.com>
+Date: Wed, 3 May 2023 07:46:41 +0000
+Subject: [PATCH 3/3] board: sifive: spl: Set remote thermal of TMP451 to 85
+ deg C for the unmatched board
+
+For TMP451 on the unmatched board, the default value of the remote
+thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL.
+---
+ board/sifive/unmatched/spl.c       | 29 +++++++++++++++++++++++++++++
+ configs/sifive_unmatched_defconfig |  3 +++
+ drivers/misc/Kconfig               | 14 ++++++++++++++
+ include/configs/sifive-unmatched.h |  4 ++++
+ 4 files changed, 50 insertions(+)
+
+diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
+index f3a661a8..05ba5916 100644
+--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
+@@ -10,6 +10,8 @@
+ #include <spl.h>
+ #include <misc.h>
+ #include <log.h>
+#include <config.h>
+#include <i2c.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <asm/gpio.h>
+@@ -26,6 +28,27 @@
+ #define MODE_SELECT_SD		0xb
+ #define MODE_SELECT_MASK	GENMASK(3, 0)
+ 
+#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET	0x19
+#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE	0x55
+
+static inline int init_tmp451_remote_therm_limit(void)
+{
+	struct udevice *dev;
+	unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM,
+				      CONFIG_SYS_I2C_TMP451_ADDR,
+				      CONFIG_SYS_I2C_TMP451_ADDR_LEN,
+				      &dev);
+
+	if (!ret)
+		ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET,
+				   &r_therm_limit,
+				   sizeof(unsigned char));
+	return ret;
+}
+
+ static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
+ {
+ 	int ret;
+@@ -92,6 +115,12 @@ int spl_board_init_f(void)
+ 
+ 	pwm_device_init();
+ 
+	ret = init_tmp451_remote_therm_limit();
+	if (ret) {
+		debug("TMP451 remote THERM limit init failed: %d\n", ret);
+		goto end;
+	}
+
+ 	ret = spl_gemgxl_init();
+ 	if (ret) {
+ 		debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
+diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
+index 74cdb4ea..e843378c 100644
+--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
+@@ -68,3 +68,6 @@ CONFIG_SYSRESET=y
+ CONFIG_SYSRESET_SBI=y
+ CONFIG_CMD_POWEROFF=y
+ CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYS_TMP451_BUS_NUM=0
+CONFIG_SYS_I2C_TMP451_ADDR=0x4c
+CONFIG_SYS_I2C_TMP451_ADDR_LEN=1
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index b5707a15..8ea6f014 100644
+--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
+@@ -552,6 +552,20 @@ config SYS_I2C_EEPROM_ADDR
+ 
+ if I2C_EEPROM
+ 
+config SYS_TMP451_BUS_NUM
+	int "Bus number of TMP451 device"
+	default 0
+
+config SYS_I2C_TMP451_ADDR
+	hex "Chip address of the TMP451 device"
+	default 0
+
+config SYS_I2C_TMP451_ADDR_LEN
+	int "Length in bytes of the TMP451 memory array address"
+	default 1
+	help
+	  Note: This is NOT the chip address length!
+
+ config SYS_I2C_EEPROM_ADDR_OVERFLOW
+ 	hex "EEPROM Address Overflow"
+ 	default 0x0
+diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
+index 74150b7d..6a8eb1e6 100644
+--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
+@@ -13,6 +13,10 @@
+ 
+ #define CFG_SYS_SDRAM_BASE		0x80000000
+ 
+#define CONFIG_SYS_TMP451_BUS_NUM	0
+#define CONFIG_SYS_I2C_TMP451_ADDR	0x4c
+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN	0x1
+
+ /* Environment options */
+ 
+ #define BOOT_TARGET_DEVICES(func) \
+-- 
+2.40.1
+
--- a/1
+++ b/1
@ -7,6 +7,7 @@ beelink_gs1
 dragonboard410c
 dragonboard820c
 dragonboard845c
+eaidk-610-rk3399
 evb-rk3328
 evb-rk3399
 ficus-rk3399
--- a/5
+++ b/5
@ -0,0 +1,5 @@
+qemu-riscv64
+qemu-riscv64_smode
+qemu-riscv64_spl
+sifive_unleashed
+sifive_unmatched
--- a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
+++ b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
@ -1,6 +1,6 @@
-From a23687b77c1e0b5be7f0443e5fba9d9bb7514b6b Mon Sep 17 00:00:00 2001
+From 72400858605c085cf94a6cf5599269c8c39e3e72 Mon Sep 17 00:00:00 2001
 From: Peter Robinson <pbrobinson@gmail.com>
-Date: Sun, 1 Jan 2023 02:11:29 +0000
+Date: Tue, 14 Mar 2023 12:30:36 +0000
 Subject: [PATCH] rockchip: pinephone pro: add initial display support

 Add proposed upstream DT patches for display, disable edp,
@ -206,12 +206,12 @@ index 04403a76238..d0609d1b534 100644
 +	status = "okay";
 +};
 diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
-index eb979f6c051..25941abc93a 100644
+index 54f9b90536c..1982131c805 100644
 --- a/configs/pinephone-pro-rk3399_defconfig
 +++ b/configs/pinephone-pro-rk3399_defconfig
-@@ -99,6 +99,7 @@ CONFIG_USB_ETHER_RTL8152=y
- CONFIG_DISPLAY=y
+@@ -96,6 +96,7 @@ CONFIG_USB_ETHER_RTL8152=y
 CONFIG_VIDEO=y
+ CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 -CONFIG_DISPLAY_ROCKCHIP_EDP=y
 +CONFIG_DISPLAY_ROCKCHIP_MIPI=y
@ -232,5 +232,5 @@ index 211faf8fa89..7866e5266d2 100644
 #define FCLK_CM0S			190
 
 -- 
-2.39.1
+2.39.2

--- a/rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch
+++ b/rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch
@ -1,296 +0,0 @@
-From patchwork Wed Aug 10 12:39:26 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Antoine Mazeas <antoine@karthanis.net>
-X-Patchwork-Id: 1665242
-X-Patchwork-Delegate: matthias.bgg@gmail.com
-Return-Path: <u-boot-bounces@lists.denx.de>
-X-Original-To: incoming@patchwork.ozlabs.org
-Delivered-To: patchwork-incoming@bilbo.ozlabs.org
-Authentication-Results: bilbo.ozlabs.org;
-	dkim=pass (1024-bit key;
- unprotected) header.d=karthanis.net header.i=@karthanis.net
- header.a=rsa-sha256 header.s=20191114 header.b=mcrC/rnn;
-	dkim-atps=neutral
-Authentication-Results: ozlabs.org;
- spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
- (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
- envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
-Received: from phobos.denx.de (phobos.denx.de
- [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
-	(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
-	 key-exchange X25519 server-signature RSA-PSS (2048 bits))
-	(No client certificate requested)
-	by bilbo.ozlabs.org (Postfix) with ESMTPS id 4M2qkM6g8Vz9ryY
-	for <incoming@patchwork.ozlabs.org>; Wed, 10 Aug 2022 22:58:35 +1000 (AEST)
-Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
-	by phobos.denx.de (Postfix) with ESMTP id CB5EF842A3;
-	Wed, 10 Aug 2022 14:58:11 +0200 (CEST)
-Authentication-Results: phobos.denx.de;
- dmarc=pass (p=none dis=none) header.from=karthanis.net
-Authentication-Results: phobos.denx.de;
- spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
-Authentication-Results: phobos.denx.de;
-	dkim=pass (1024-bit key;
- unprotected) header.d=karthanis.net header.i=@karthanis.net
- header.b="mcrC/rnn";
-	dkim-atps=neutral
-Received: by phobos.denx.de (Postfix, from userid 109)
- id 4FB14841DC; Wed, 10 Aug 2022 14:40:46 +0200 (CEST)
-X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
-X-Spam-Level: 
-X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
- DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,
- T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2
-Received: from smtp-42a9.mail.infomaniak.ch (smtp-42a9.mail.infomaniak.ch
- [IPv6:2001:1600:3:17::42a9])
- (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))
- (No client certificate requested)
- by phobos.denx.de (Postfix) with ESMTPS id CCC6784084
- for <u-boot@lists.denx.de>; Wed, 10 Aug 2022 14:40:43 +0200 (CEST)
-Authentication-Results: phobos.denx.de;
- dmarc=pass (p=none dis=none) header.from=karthanis.net
-Authentication-Results: phobos.denx.de;
- spf=pass smtp.mailfrom=antoine@karthanis.net
-Received: from smtp-3-0001.mail.infomaniak.ch (unknown [10.4.36.108])
- by smtp-2-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4M2qKl3S6GzMqbyx;
- Wed, 10 Aug 2022 14:40:43 +0200 (CEST)
-Received: from localhost.localdomain (unknown [88.168.170.86])
- by smtp-3-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4M2qKk6qXKzlnSD1;
- Wed, 10 Aug 2022 14:40:42 +0200 (CEST)
-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=karthanis.net;
- s=20191114; t=1660135243;
- bh=YF4GTVv5pqqW0OMrNZFlf0WHnELr1KiKKA02ok/znf4=;
- h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
- b=mcrC/rnnUv3FXlrllL2s9lLTjUEnTuLbiINuyrIQWr2HG3AmCcD11F7n0AypUdePp
- 2XfG1PnZalJa2v3m6/DUWsz6B/cqmYo31h/6HpFeJ4g2i1pEZar7cC+9oScmbjJptV
- w2oDsFHzyK2oWHUMGFJ4N6bboD8kq3z4WLaH2vrQ=
-From: Antoine Mazeas <antoine@karthanis.net>
-To: u-boot@lists.denx.de
-Cc: Antoine Mazeas <antoine@karthanis.net>,
- Sjoerd Simons <sjoerd@collabora.com>
-Subject: [PATCH 1/2] rpi: Copy properties from firmware dtb to the loaded dtb
-Date: Wed, 10 Aug 2022 14:39:26 +0200
-Message-Id: <20220810123927.2567677-2-antoine@karthanis.net>
-X-Mailer: git-send-email 2.37.1
-In-Reply-To: <20220810123927.2567677-1-antoine@karthanis.net>
-References: <20220810123927.2567677-1-antoine@karthanis.net>
-MIME-Version: 1.0
-X-Mailman-Approved-At: Wed, 10 Aug 2022 14:58:03 +0200
-X-BeenThere: u-boot@lists.denx.de
-X-Mailman-Version: 2.1.39
-Precedence: list
-List-Id: U-Boot discussion <u-boot.lists.denx.de>
-List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
-List-Archive: <https://lists.denx.de/pipermail/u-boot/>
-List-Post: <mailto:u-boot@lists.denx.de>
-List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
-List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=subscribe>
-Errors-To: u-boot-bounces@lists.denx.de
-Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
-X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de
-X-Virus-Status: Clean
-
-The RPI firmware adjusts several property values in the dtb it passes
-to u-boot depending on the board/SoC revision. Inherit some of these
-when u-boot loads a dtb itself. Specificaly copy:
-
-* /model: The firmware provides a more specific string
-* /memreserve: The firmware defines a reserved range, better keep it
-* emmc2bus and pcie0 dma-ranges: The C0T revision of the bcm2711 Soc (as
-  present on rpi 400 and some rpi 4B boards) has different values for
-  these then the B0T revision. So these need to be adjusted to boot on
-  these boards
-* blconfig: The firmware defines the memory area where the blconfig
-  stored. Copy those over so it can be enabled.
-* /chosen/kaslr-seed: The firmware generates a kaslr seed, take advantage
-  of that.
-
-Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
---
- board/raspberrypi/rpi/rpi.c | 48 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
-diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
-index 17b8108cc8..28b6f52506 100644
--- a/board/raspberrypi/rpi/rpi.c
-+++ b/board/raspberrypi/rpi/rpi.c
-@@ -504,10 +504,58 @@ void *board_fdt_blob_setup(int *err)
- 	return (void *)fw_dtb_pointer;
- }
- 
-+int copy_property(void *dst, void *src, char *path, char *property)
-+{
-+	int dst_offset, src_offset;
-+	const fdt32_t *prop;
-+	int len;
-+
-+	src_offset = fdt_path_offset(src, path);
-+	dst_offset = fdt_path_offset(dst, path);
-+
-+	if (src_offset < 0 || dst_offset < 0)
-+		return -1;
-+
-+	prop = fdt_getprop(src, src_offset, property, &len);
-+	if (!prop)
-+		return -1;
-+
-+	return fdt_setprop(dst, dst_offset, property, prop, len);
-+}
-+
-+/* Copy tweaks from the firmware dtb to the loaded dtb */
-+void  update_fdt_from_fw(void *fdt, void *fw_fdt)
-+{
-+	/* Using dtb from firmware directly; leave it alone */
-+	if (fdt == fw_fdt)
-+		return;
-+
-+	/* The firmware provides a more precie model; so copy that */
-+	copy_property(fdt, fw_fdt, "/", "model");
-+
-+	/* memory reserve as suggested by the firmware */
-+	copy_property(fdt, fw_fdt, "/", "memreserve");
-+
-+	/* Adjust dma-ranges for the SD card and PCI bus as they can depend on
-+	 * the SoC revision
-+	 */
-+	copy_property(fdt, fw_fdt, "emmc2bus", "dma-ranges");
-+	copy_property(fdt, fw_fdt, "pcie0", "dma-ranges");
-+
-+	/* Bootloader configuration template exposes as nvmem */
-+	if (copy_property(fdt, fw_fdt, "blconfig", "reg") == 0)
-+		copy_property(fdt, fw_fdt, "blconfig", "status");
-+
-+	/* kernel address randomisation seed as provided by the firmware */
-+	copy_property(fdt, fw_fdt, "/chosen", "kaslr-seed");
-+}
-+
- int ft_board_setup(void *blob, struct bd_info *bd)
- {
- 	int node;
- 
-+	update_fdt_from_fw(blob, (void *)fw_dtb_pointer);
-+
- 	node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
- 	if (node < 0)
- 		fdt_simplefb_add_node(blob);
-
-From patchwork Wed Aug 10 12:39:27 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Antoine Mazeas <antoine@karthanis.net>
-X-Patchwork-Id: 1665243
-X-Patchwork-Delegate: matthias.bgg@gmail.com
-Return-Path: <u-boot-bounces@lists.denx.de>
-X-Original-To: incoming@patchwork.ozlabs.org
-Delivered-To: patchwork-incoming@bilbo.ozlabs.org
-Authentication-Results: bilbo.ozlabs.org;
-	dkim=pass (1024-bit key;
- unprotected) header.d=karthanis.net header.i=@karthanis.net
- header.a=rsa-sha256 header.s=20191114 header.b=3Vltv92i;
-	dkim-atps=neutral
-Authentication-Results: ozlabs.org;
- spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de
- (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;
- envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)
-Received: from phobos.denx.de (phobos.denx.de
- [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
-	(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
-	 key-exchange X25519 server-signature RSA-PSS (2048 bits))
-	(No client certificate requested)
-	by bilbo.ozlabs.org (Postfix) with ESMTPS id 4M2qkb5v6sz9ryY
-	for <incoming@patchwork.ozlabs.org>; Wed, 10 Aug 2022 22:58:47 +1000 (AEST)
-Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
-	by phobos.denx.de (Postfix) with ESMTP id 2E6C784564;
-	Wed, 10 Aug 2022 14:58:17 +0200 (CEST)
-Authentication-Results: phobos.denx.de;
- dmarc=pass (p=none dis=none) header.from=karthanis.net
-Authentication-Results: phobos.denx.de;
- spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
-Authentication-Results: phobos.denx.de;
-	dkim=pass (1024-bit key;
- unprotected) header.d=karthanis.net header.i=@karthanis.net
- header.b="3Vltv92i";
-	dkim-atps=neutral
-Received: by phobos.denx.de (Postfix, from userid 109)
- id 274CF8415B; Wed, 10 Aug 2022 14:40:48 +0200 (CEST)
-X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
-X-Spam-Level: 
-X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
- DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,
- T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2
-Received: from smtp-42a9.mail.infomaniak.ch (smtp-42a9.mail.infomaniak.ch
- [84.16.66.169])
- (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))
- (No client certificate requested)
- by phobos.denx.de (Postfix) with ESMTPS id DAC58841A4
- for <u-boot@lists.denx.de>; Wed, 10 Aug 2022 14:40:45 +0200 (CEST)
-Authentication-Results: phobos.denx.de;
- dmarc=pass (p=none dis=none) header.from=karthanis.net
-Authentication-Results: phobos.denx.de;
- spf=pass smtp.mailfrom=antoine@karthanis.net
-Received: from smtp-3-0001.mail.infomaniak.ch (unknown [10.4.36.108])
- by smtp-2-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4M2qKn4VzjzMqnFS;
- Wed, 10 Aug 2022 14:40:45 +0200 (CEST)
-Received: from localhost.localdomain (unknown [88.168.170.86])
- by smtp-3-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4M2qKn1TBqzlnSCc;
- Wed, 10 Aug 2022 14:40:45 +0200 (CEST)
-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=karthanis.net;
- s=20191114; t=1660135245;
- bh=f61vvBG7E2UozLHxeE7zghMr3kXQzBW+5PpzEyEGYJU=;
- h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
- b=3Vltv92i/KGKD06qHi+zyrqGwfJWUvdwHMojKKH7OqswhScJTxhUbGq6MnPrCqWsn
- QgB117zr++vQSy1jxV2vZIFLxMC3j8AZb4l3ktmU7FiPp7AUB6AqAzv+tUrYeS3nz4
- LQ0mJS4s1jk1k0WWAK3/WGdOyUAo8ZWw5oiBHUvk=
-From: Antoine Mazeas <antoine@karthanis.net>
-To: u-boot@lists.denx.de
-Cc: Antoine Mazeas <antoine@karthanis.net>
-Subject: [PATCH 2/2] rpi: Copy eth PHY address from fw DT to loaded DT
-Date: Wed, 10 Aug 2022 14:39:27 +0200
-Message-Id: <20220810123927.2567677-3-antoine@karthanis.net>
-X-Mailer: git-send-email 2.37.1
-In-Reply-To: <20220810123927.2567677-1-antoine@karthanis.net>
-References: <20220810123927.2567677-1-antoine@karthanis.net>
-MIME-Version: 1.0
-X-Mailman-Approved-At: Wed, 10 Aug 2022 14:58:03 +0200
-X-BeenThere: u-boot@lists.denx.de
-X-Mailman-Version: 2.1.39
-Precedence: list
-List-Id: U-Boot discussion <u-boot.lists.denx.de>
-List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
-List-Archive: <https://lists.denx.de/pipermail/u-boot/>
-List-Post: <mailto:u-boot@lists.denx.de>
-List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
-List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
- <mailto:u-boot-request@lists.denx.de?subject=subscribe>
-Errors-To: u-boot-bounces@lists.denx.de
-Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
-X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de
-X-Virus-Status: Clean
-
-Some Raspberry Pi 400 boards, specifically rev 1.1, have a different address for the ethernet PHY device than what is provided by the kernel DTB. The correct address is provided by the firmware, so we should carry it over into the loaded device tree so that ethernet works on such boards.
-
-Signed-off-by: Antoine Mazeas <antoine@karthanis.net>
---
- board/raspberrypi/rpi/rpi.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
-index 28b6f52506..793fd1aa30 100644
--- a/board/raspberrypi/rpi/rpi.c
-+++ b/board/raspberrypi/rpi/rpi.c
-@@ -548,6 +548,9 @@ void  update_fdt_from_fw(void *fdt, void *fw_fdt)
- 
- 	/* kernel address randomisation seed as provided by the firmware */
- 	copy_property(fdt, fw_fdt, "/chosen", "kaslr-seed");
-+
-+	/* address of the PHY device as provided by the firmware  */
-+	copy_property(fdt, fw_fdt, "ethernet0/mdio@e14/ethernet-phy@1", "reg");
- }
- 
- int ft_board_setup(void *blob, struct bd_info *bd)
--- a/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
+++ b/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
@ -1,7 +1,13 @@
-From f10f94831450671a77f61fe413b4a57459963860 Mon Sep 17 00:00:00 2001
+From 52b75976133683dc9fe66e8ad35127125f938bed Mon Sep 17 00:00:00 2001
 From: Peter Robinson <pbrobinson@gmail.com>
-Date: Mon, 10 Aug 2020 22:20:29 +0100
-Subject: [PATCH] rpi: Use firmware provided device tree
+Date: Tue, 28 Feb 2023 12:04:34 +0000
+Subject: [PATCH 2/2] rpi: Use OF_BOARD rather than OF_EMBED
+
+The use of OF_EMBED isn't recommended for standard use and the OF_BOARD
+is actually a better fit for the Raspberry Pi as the prior firmware
+provides a DT that can be used by U-Boot and the subsequent OS too, but
+it still allows the loading of a DT from disk as well if users wish
+to use the upstream kernel DT.

 Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
 ---
@ -10,14 +16,17 @@ Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
 configs/rpi_3_32b_defconfig    | 2 +-
 configs/rpi_3_b_plus_defconfig | 2 +-
 configs/rpi_3_defconfig        | 2 +-
+ configs/rpi_4_32b_defconfig    | 1 +
+ configs/rpi_4_defconfig        | 1 +
+ configs/rpi_arm64_defconfig    | 1 +
 configs/rpi_defconfig          | 2 +-
- 6 files changed, 6 insertions(+), 6 deletions(-)
+ 9 files changed, 9 insertions(+), 6 deletions(-)

 diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
-index bba5e12b12..0241f4c6d3 100644
+index 5249b29d76c..8c217848ca2 100644
 --- a/configs/rpi_0_w_defconfig
 +++ b/configs/rpi_0_w_defconfig
-@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
+@@ -23,7 +23,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
@ -27,10 +36,10 @@ index bba5e12b12..0241f4c6d3 100644
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
-index 1c2bbb29ce..9573e475f4 100644
+index 154284765f4..bfc5679fb7e 100644
 --- a/configs/rpi_2_defconfig
 +++ b/configs/rpi_2_defconfig
-@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
+@@ -24,7 +24,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
@ -40,10 +49,10 @@ index 1c2bbb29ce..9573e475f4 100644
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
-index b8a3d17f43..252df994e6 100644
+index ef1f25d2ad7..54cdcee980a 100644
 --- a/configs/rpi_3_32b_defconfig
 +++ b/configs/rpi_3_32b_defconfig
-@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y
+@@ -23,7 +23,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
@ -53,10 +62,10 @@ index b8a3d17f43..252df994e6 100644
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
-index 4c361438fa..3b2996a2f9 100644
+index 154615d78a1..3008c7a1c18 100644
 --- a/configs/rpi_3_b_plus_defconfig
 +++ b/configs/rpi_3_b_plus_defconfig
-@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y
+@@ -22,7 +22,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
@ -66,10 +75,10 @@ index 4c361438fa..3b2996a2f9 100644
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
-index 9b281a4f15..1e9ee6122e 100644
+index f0cf7f8e236..f7b9108ba00 100644
 --- a/configs/rpi_3_defconfig
 +++ b/configs/rpi_3_defconfig
-@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y
+@@ -22,7 +22,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
@ -78,11 +87,47 @@ index 9b281a4f15..1e9ee6122e 100644
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
+index 713b2ee231c..fa20ab767fe 100644
+--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
+@@ -24,6 +24,7 @@ CONFIG_CMD_MMC=y
+ CONFIG_CMD_PCI=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_FS_UUID=y
+CONFIG_OF_BOARD=y
+ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
+index 24f70b14fe8..741d4dbbbf4 100644
+--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
+@@ -24,6 +24,7 @@ CONFIG_CMD_MMC=y
+ CONFIG_CMD_PCI=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_FS_UUID=y
+CONFIG_OF_BOARD=y
+ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
+index 1d1ff12a58c..5e1195dd786 100644
+--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
+@@ -23,6 +23,7 @@ CONFIG_CMD_MMC=y
+ CONFIG_CMD_PCI=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_FS_UUID=y
+CONFIG_OF_BOARD=y
+ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+ CONFIG_TFTP_TSIZE=y
 diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
-index b5ad53c37b..223fc03275 100644
+index 28b92b14456..1504093eddf 100644
 --- a/configs/rpi_defconfig
 +++ b/configs/rpi_defconfig
-@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
+@@ -23,7 +23,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_FS_UUID=y
@ -92,5 +137,5 @@ index b5ad53c37b..223fc03275 100644
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 -- 
-2.26.2
+2.39.2

--- a/rpi-bcm2835_sdhost-firmware-managed-clock.patch
+++ b/rpi-bcm2835_sdhost-firmware-managed-clock.patch
@ -1,228 +0,0 @@
-From f3a870bfa075fb880f5e018a0a5ae6f27ca8be49 Mon Sep 17 00:00:00 2001
-From: Vincent Fazio <vfazio@xes-inc.com>
-Date: Mon, 13 Sep 2021 13:34:45 -0500
-Subject: [PATCH] mmc: bcm2835-host: let firmware manage the clock
-
-Newer firmware supports managing the sdhost clock divisor, so leverage
-this feature if it is available.
-
-SET_SDHOST_CLOCK is largely undocumented except for its usage within the
-Linux kernel, which this change is based on.
-
-https://github.com/raspberrypi/linux/commit/3cd16c39c718e2dda7885c4ed7a20118aed12524
-
-Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
---
- arch/arm/mach-bcm283x/include/mach/mbox.h | 18 ++++++++
- arch/arm/mach-bcm283x/include/mach/msg.h  | 10 +++++
- arch/arm/mach-bcm283x/msg.c               | 30 +++++++++++++
- drivers/mmc/bcm2835_sdhost.c              | 53 ++++++++++++++---------
- 4 files changed, 90 insertions(+), 21 deletions(-)
-
-diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
-index 7dcac583cc4..9b1943fcfc4 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
-+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
-@@ -252,6 +252,24 @@ struct bcm2835_mbox_tag_get_clock_rate {
- 	} body;
- };
- 
-+#define BCM2835_MBOX_TAG_SET_SDHOST_CLOCK	0x00038042
-+
-+struct bcm2835_mbox_tag_set_sdhost_clock {
-+	struct bcm2835_mbox_tag_hdr tag_hdr;
-+	union {
-+		struct {
-+			u32 rate_hz;
-+			u32 rate_1;
-+			u32 rate_2;
-+		} req;
-+		struct {
-+			u32 rate_hz;
-+			u32 rate_1;
-+			u32 rate_2;
-+		} resp;
-+	} body;
-+};
-+
- #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER	0x00040001
- 
- struct bcm2835_mbox_tag_allocate_buffer {
-diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h
-index e45c1bf010f..ab37abdb6c6 100644
--- a/arch/arm/mach-bcm283x/include/mach/msg.h
-+++ b/arch/arm/mach-bcm283x/include/mach/msg.h
-@@ -22,6 +22,16 @@ int bcm2835_power_on_module(u32 module);
-  */
- int bcm2835_get_mmc_clock(u32 clock_id);
- 
-+/**
-+ * bcm2835_set_sdhost_clock() - determine if firmware controls sdhost cdiv
-+ *
-+ * @rate_hz: Input clock frequency
-+ * @rate_1: Returns a clock frequency
-+ * @rate_2: Returns a clock frequency
-+ * @return 0 of OK, -EIO on error
-+ */
-+int bcm2835_set_sdhost_clock(u32 rate_hz, u32 *rate_1, u32 *rate_2);
-+
- /**
-  * bcm2835_get_video_size() - get the current display size
-  *
-diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
-index e2badfecb09..8c1c36a5f15 100644
--- a/arch/arm/mach-bcm283x/msg.c
-+++ b/arch/arm/mach-bcm283x/msg.c
-@@ -21,6 +21,12 @@ struct msg_get_clock_rate {
- 	u32 end_tag;
- };
- 
-+struct msg_set_sdhost_clock {
-+	struct bcm2835_mbox_hdr hdr;
-+	struct bcm2835_mbox_tag_set_sdhost_clock set_sdhost_clock;
-+	u32 end_tag;
-+};
-+
- struct msg_query {
- 	struct bcm2835_mbox_hdr hdr;
- 	struct bcm2835_mbox_tag_physical_w_h physical_w_h;
-@@ -111,6 +117,30 @@ int bcm2835_get_mmc_clock(u32 clock_id)
- 	return clock_rate;
- }
- 
-+int bcm2835_set_sdhost_clock(u32 rate_hz, u32 *rate_1, u32 *rate_2)
-+{
-+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_sdhost_clock, msg_sdhost_clk, 1);
-+	int ret;
-+
-+	BCM2835_MBOX_INIT_HDR(msg_sdhost_clk);
-+	BCM2835_MBOX_INIT_TAG(&msg_sdhost_clk->set_sdhost_clock, SET_SDHOST_CLOCK);
-+
-+	msg_sdhost_clk->set_sdhost_clock.body.req.rate_hz = rate_hz;
-+	msg_sdhost_clk->set_sdhost_clock.body.req.rate_1 = *rate_1;
-+	msg_sdhost_clk->set_sdhost_clock.body.req.rate_2 = *rate_2;
-+
-+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_sdhost_clk->hdr);
-+	if (ret) {
-+		printf("bcm2835: Could not query sdhost clock rate\n");
-+		return -EIO;
-+	}
-+
-+	*rate_1 = msg_sdhost_clk->set_sdhost_clock.body.resp.rate_1;
-+	*rate_2 = msg_sdhost_clk->set_sdhost_clock.body.resp.rate_2;
-+
-+	return 0;
-+}
-+
- int bcm2835_get_video_size(int *widthp, int *heightp)
- {
- 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_query, msg_query, 1);
-diff --git a/drivers/mmc/bcm2835_sdhost.c b/drivers/mmc/bcm2835_sdhost.c
-index 894dbdd6861..3a9cd6f1eb2 100644
--- a/drivers/mmc/bcm2835_sdhost.c
-+++ b/drivers/mmc/bcm2835_sdhost.c
-@@ -181,6 +181,7 @@ struct bcm2835_host {
- 	struct udevice		*dev;
- 	struct mmc		*mmc;
- 	struct bcm2835_plat	*plat;
-+	unsigned int 		firmware_sets_cdiv:1;
- };
- 
- static void bcm2835_dumpregs(struct bcm2835_host *host)
-@@ -233,7 +234,7 @@ static void bcm2835_reset_internal(struct bcm2835_host *host)
- 	msleep(20);
- 	host->clock = 0;
- 	writel(host->hcfg, host->ioaddr + SDHCFG);
-	writel(host->cdiv, host->ioaddr + SDCDIV);
-+	writel(SDCDIV_MAX_CDIV, host->ioaddr + SDCDIV);
- }
- 
- static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
-@@ -598,6 +599,7 @@ static int bcm2835_transmit(struct bcm2835_host *host)
- static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
- {
- 	int div;
-+	u32 clock_rate[2] = { 0 };
- 
- 	/* The SDCDIV register has 11 bits, and holds (div - 2).  But
- 	 * in data mode the max is 50MHz wihout a minimum, and only
-@@ -620,26 +622,34 @@ static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
- 	 * clock divisor at all times.
- 	 */
- 
-	if (clock < 100000) {
-		/* Can't stop the clock, but make it as slow as possible
-		 * to show willing
-		 */
-		host->cdiv = SDCDIV_MAX_CDIV;
-		writel(host->cdiv, host->ioaddr + SDCDIV);
-		return;
-	}
-+	if (host->firmware_sets_cdiv) {
-+		bcm2835_set_sdhost_clock(clock, &clock_rate[0], &clock_rate[1]);
-+		clock = max(clock_rate[0], clock_rate[1]);
-+	} else {
-+		if (clock < 100000) {
-+			/* Can't stop the clock, but make it as slow as possible
-+			* to show willing
-+			*/
-+			host->cdiv = SDCDIV_MAX_CDIV;
-+			writel(host->cdiv, host->ioaddr + SDCDIV);
-+			return;
-+		}
- 
-	div = host->max_clk / clock;
-	if (div < 2)
-		div = 2;
-	if ((host->max_clk / div) > clock)
-		div++;
-	div -= 2;
-+		div = host->max_clk / clock;
-+		if (div < 2)
-+			div = 2;
-+		if ((host->max_clk / div) > clock)
-+			div++;
-+		div -= 2;
- 
-	if (div > SDCDIV_MAX_CDIV)
-		div = SDCDIV_MAX_CDIV;
-+		if (div > SDCDIV_MAX_CDIV)
-+			div = SDCDIV_MAX_CDIV;
-+
-+		clock = host->max_clk / (div + 2);
-+		host->cdiv = div;
-+		writel(host->cdiv, host->ioaddr + SDCDIV);
-+	}
- 
-	clock = host->max_clk / (div + 2);
- 	host->mmc->clock = clock;
- 
- 	/* Calibrate some delays */
-@@ -647,9 +657,6 @@ static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
- 	host->ns_per_fifo_word = (1000000000 / clock) *
- 		((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
- 
-	host->cdiv = div;
-	writel(host->cdiv, host->ioaddr + SDCDIV);
-
- 	/* Set the timeout to 500ms */
- 	writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
- }
-@@ -759,6 +766,7 @@ static int bcm2835_probe(struct udevice *dev)
- 	struct bcm2835_host *host = dev_get_priv(dev);
- 	struct mmc *mmc = mmc_get_mmc_dev(dev);
- 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-+	u32 clock_rate[2] = { ~0 };
- 
- 	host->dev = dev;
- 	host->mmc = mmc;
-@@ -776,6 +784,9 @@ static int bcm2835_probe(struct udevice *dev)
- 
- 	host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
- 
-+	bcm2835_set_sdhost_clock(0, &clock_rate[0], &clock_rate[1]);
-+	host->firmware_sets_cdiv = (clock_rate[0] != ~0);
-+
- 	bcm2835_add_host(host);
- 
- 	dev_dbg(dev, "%s -> OK\n", __func__);
--- a/rpi-fallback-to-max-clock-for-mmc.patch
+++ b/rpi-fallback-to-max-clock-for-mmc.patch
@ -1,77 +0,0 @@
-From 71ba043e5c5575f3d86536acade70dab6599489b Mon Sep 17 00:00:00 2001
-From: Vincent Fazio <vfazio@xes-inc.com>
-Date: Mon, 13 Sep 2021 11:22:30 -0500
-Subject: [PATCH] arm: rpi: fallback to max clock rate for MMC clock
-
-In rpi-firmware 25e2b597ebfb2495eab4816a276758dcc6ea21f1 and later,
-the GET_CLOCK_RATE mailbox property was changed to return the last
-value set by SET_CLOCK_RATE.
-
-https://github.com/raspberrypi/firmware/issues/1619#issuecomment-917025502
-
-U-Boot does not call SET_CLOCK_RATE so bcm2835_get_mmc_clock will
-return zero and can cause degraded MMC performance.
-
-Calling SET_CLOCK_RATE fixes the frequency of the clock to a specific
-value and disables the firmware's clock scaling so is not an option.
-
-Instead, fallback to GET_MAX_CLOCK_RATE in bcm2835_get_mmc_clock if
-GET_CLOCK_RATE returns zero.
-
-Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
---
- arch/arm/mach-bcm283x/include/mach/mbox.h |  2 ++
- arch/arm/mach-bcm283x/msg.c               | 20 +++++++++++++++++++-
- 2 files changed, 21 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
-index 2ae2d3d97c3..7dcac583cc4 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
-+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
-@@ -224,6 +224,8 @@ struct bcm2835_mbox_tag_set_power_state {
- };
- 
- #define BCM2835_MBOX_TAG_GET_CLOCK_RATE	0x00030002
-+#define BCM2835_MBOX_TAG_GET_MAX_CLOCK_RATE	0x00030004
-+#define BCM2835_MBOX_TAG_GET_MIN_CLOCK_RATE	0x00030007
- 
- #define BCM2835_MBOX_CLOCK_ID_EMMC	1
- #define BCM2835_MBOX_CLOCK_ID_UART	2
-diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
-index 347aece3cd8..e2badfecb09 100644
--- a/arch/arm/mach-bcm283x/msg.c
-+++ b/arch/arm/mach-bcm283x/msg.c
-@@ -75,6 +75,7 @@ int bcm2835_get_mmc_clock(u32 clock_id)
- {
- 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1);
- 	int ret;
-+	u32 clock_rate = 0;
- 
- 	ret = bcm2835_power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
- 	if (ret)
-@@ -90,7 +91,24 @@ int bcm2835_get_mmc_clock(u32 clock_id)
- 		return -EIO;
- 	}
- 
-	return msg_clk->get_clock_rate.body.resp.rate_hz;
-+	clock_rate = msg_clk->get_clock_rate.body.resp.rate_hz;
-+
-+	if (clock_rate == 0)
-+	{
-+		BCM2835_MBOX_INIT_HDR(msg_clk);
-+		BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_MAX_CLOCK_RATE);
-+		msg_clk->get_clock_rate.body.req.clock_id = clock_id;
-+
-+		ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr);
-+		if (ret) {
-+			printf("bcm2835: Could not query max eMMC clock rate\n");
-+			return -EIO;
-+		}
-+
-+		clock_rate = msg_clk->get_clock_rate.body.resp.rate_hz;
-+	}
-+
-+	return clock_rate;
- }
- 
- int bcm2835_get_video_size(int *widthp, int *heightp)
--- a/2
+++ b/2
@ -1 +1 @@
-SHA512 (u-boot-2023.01.tar.bz2) = 417a28267eb7875820d08fafc7316f164663609378637539e71648b0b9b7d28796b6c381717f31b0ab6472805fefd32628ef7d1b2e7b9f3c51c8ad122993f679
+SHA512 (u-boot-2023.04.tar.bz2) = 31a44083af8084cd657c08233f485ff9503002bbaf95114c6135d483881fa14dc5a1b7ab42fd91f1fdd6b330556e76958d475280115018cb59c62b6ab4b508e6
--- a/uboot-tools.spec
+++ b/uboot-tools.spec
@ -1,13 +1,16 @@
-%global candidate rc1
+#global candidate rc0
 %if 0%{?rhel}
 %bcond_with toolsonly
 %else
 %bcond_without toolsonly
 %endif

+# Set it to "opensbi" (stable) or opensbi-unstable (unstable, git)
+%global opensbi opensbi-unstable
+
 Name:     uboot-tools
 Version:  2023.04
-Release:  0.1%{?candidate:.%{candidate}}%{?dist}
+Release:  1%{?candidate:.%{candidate}}.0.riscv64%{?dist}
 Summary:  U-Boot utilities
 License:  GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
 URL:      http://www.denx.de/wiki/U-Boot
@ -15,6 +18,7 @@ URL:      http://www.denx.de/wiki/U-Boot
 ExcludeArch: s390x
 Source0:  https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2
 Source1:  aarch64-boards
+Source2:  riscv64-boards

 # Fedoraisms patches
 # Needed to find DT on boot partition that's not the first partition
@ -24,11 +28,13 @@ Patch2:   smbios-Simplify-reporting-of-unknown-values.patch
 # Board fixes and enablement
 # RPi - uses RPI firmware device tree for HAT support
 Patch3:   rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
-Patch4:   rpi-fallback-to-max-clock-for-mmc.patch
-Patch5:   rpi-bcm2835_sdhost-firmware-managed-clock.patch
-Patch6:   rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch
 # Rockchips improvements
-Patch7:   rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
+Patch6:   rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
+
+# RISC-V (riscv64) patches
+Patch20:  0001-Improve-riscv-defconfigs.patch
+Patch21:  0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
+Patch22:  0003-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch

 BuildRequires:  bc
 BuildRequires:  bison
@ -49,9 +55,13 @@ BuildRequires:  swig
 %if %{with toolsonly}
 %ifarch aarch64
 BuildRequires:  arm-trusted-firmware-armv8
+BuildRequires:  python3-pyelftools
 %endif
 %endif
 Requires:       dtc
+%ifarch riscv64
+BuildRequires:  %{opensbi}
+%endif

 %description
 This package contains a few U-Boot utilities - mkimage for creating boot images
@ -66,12 +76,22 @@ BuildArch:   noarch
 %description -n uboot-images-armv8
 U-Boot firmware binaries for aarch64 boards
 %endif
+
+%ifarch riscv64
+%package     -n uboot-images-riscv64
+Summary:     u-boot bootloader images for riscv64 boards
+Requires:    uboot-tools
+BuildArch:   noarch
+
+%description -n uboot-images-riscv64
+u-boot bootloader binaries for riscv64 boards
+%endif
 %endif

 %prep
 %autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}}

-cp %SOURCE1 .
+cp %SOURCE1 %SOURCE2 .

 %build
 mkdir builds
@ -80,7 +100,11 @@ mkdir builds
 %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-all O=builds/

 %if %{with toolsonly}
-%ifarch aarch64
+%ifarch riscv64
+export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin
+%endif
+
+%ifarch aarch64 riscv64
 for board in $(cat %{_arch}-boards)
 do
  echo "Building board: $board"
@ -100,12 +124,13 @@ do
  rk3328=(evb-rk3328 nanopi-r2s-rk3328 rock64-rk3328 rock-pi-e-rk3328 roc-cc-rk3328)
  if [[ " ${rk3328[*]} " == *" $board "* ]]; then
    echo "Board: $board using rk3328"
-    cp /usr/share/arm-trusted-firmware/rk3328/* builds/$(echo $board)/
+    cp /usr/share/arm-trusted-firmware/rk3328/bl31.elf builds/$(echo $board)/atf-bl31
  fi
-  rk3399=(evb-rk3399 ficus-rk3399 firefly-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 leez-rk3399 nanopc-t4-rk3399 nanopi-m4-2gb-rk3399 nanopi-m4b-rk3399 nanopi-m4-rk3399 nanopi-neo4-rk3399 nanopi-r4s-rk3399 orangepi-rk3399 pinebook-pro-rk3399 pinephone-pro-rk3399 puma-rk3399 rock960-rk3399 rock-pi-4c-rk3399 rock-pi-4-rk3399 rock-pi-n10-rk3399pro rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399)
+  rk3399=(evb-rk3399 ficus-rk3399 firefly-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 leez-rk3399 nanopc-t4-rk3399 nanopi-m4-2gb-rk3399 nanopi-m4b-rk3399 nanopi-m4-rk3399 nanopi-neo4-rk3399 nanopi-r4s-rk3399 orangepi-rk3399 pinebook-pro-rk3399 pinephone-pro-rk3399 puma-rk3399 rock960-rk3399 rock-pi-4c-rk3399 rock-pi-4-rk3399 rock-pi-n10-rk3399pro rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399 eaidk-610-rk3399)
  if [[ " ${rk3399[*]} " == *" $board "* ]]; then
    echo "Board: $board using rk3399"
    cp /usr/share/arm-trusted-firmware/rk3399/* builds/$(echo $board)/
+    cp builds/$(echo $board)/bl31.elf builds/$(echo $board)/atf-bl31
  fi
  # End ATF

@ -150,6 +175,19 @@ done
 install -p -m 0644 builds/apple_m1/u-boot-nodtb.bin %{buildroot}%{_datadir}/uboot/apple_m1/u-boot-nodtb.bin
 %endif

+%ifarch riscv64
+for board in $(ls builds)
+do
+mkdir -p %{buildroot}%{_datadir}/uboot/$(echo $board)/
+ for file in u-boot.bin u-boot.dtb u-boot.img u-boot-nodtb.bin u-boot-dtb.bin u-boot.itb u-boot-dtb.img u-boot.its spl/u-boot-spl.bin spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb spl/u-boot-spl-dtb.bin
+ do
+  if [ -f builds/$(echo $board)/$(echo $file) ]; then
+    install -p -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/
+  fi
+ done
+done
+%endif
+
 # Bit of a hack to remove binaries we don't use as they're large
 %ifarch aarch64
 for board in $(ls builds)
@ -179,7 +217,7 @@ done
 %endif
 %endif

-for tool in dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc ifwitool img2srec kwboot mkeficapsule mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder ubsha1 xway-swap-bytes
+for tool in dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc ifwitool img2srec kwboot mkeficapsule mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder
 do
 install -p -m 0755 builds/tools/$tool %{buildroot}%{_bindir}
 done
@ -208,9 +246,31 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand
 %files -n uboot-images-armv8
 %{_datadir}/uboot/*
 %endif
+
+%ifarch riscv64
+%files -n uboot-images-riscv64
+%{_datadir}/uboot/*
+%endif
 %endif

 %changelog
+* Wed May 03 2023 David Abdurachmanov <davidlt@rivosinc.com> - 2023.04-1.0.riscv64
+- Add support for riscv64
+
+* Tue Apr 04 2023 Peter Robinson <pbrobinson@fedoraproject.org> - 2023.04-1
+- Update to 2023.04 GA
+
+* Tue Mar 28 2023 Peter Robinson <pbrobinson@fedoraproject.org> - 2023.04-0.4.rc5
+- Update to 2023.04 RC5
+- Drop upstreamed patches
+- Rockchip boot fixes
+
+* Tue Mar 14 2023 Peter Robinson <pbrobinson@fedoraproject.org> - 2023.04-0.3.rc4
+- Update to 2023.04 RC4
+
+* Fri Feb 17 2023 Peter Robinson <pbrobinson@fedoraproject.org> - 2023.04-0.2.rc2
+- Update to 2023.04 RC2
+
 * Tue Jan 31 2023 Peter Robinson <pbrobinson@fedoraproject.org> - 2023.04-0.1.rc1
 - Update to 2023.04 RC1
 - Drop bmp_logo tool
Author	SHA1	Message	Date
David Abdurachmanov	f890d0262b	Add support for riscv64 Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>	2023-05-03 11:03:58 +03:00
Peter Robinson	69626555b7	Merge branch 'rawhide' into f38	2023-04-06 07:57:20 +01:00
Peter Robinson	2a1c71298b	2023.04 GA	2023-04-05 23:03:46 +01:00
Peter Robinson	92806ecb85	2023.04 GA	2023-04-05 22:53:23 +01:00
Peter Robinson	33708bf7f4	2023.04 RC5	2023-04-02 22:33:04 +01:00
Peter Robinson	8e7afdbb87	2023.04 RC4	2023-03-14 17:19:11 +00:00
Peter Robinson	8a0d41132e	drop xway-swap-bytes	2023-02-20 11:01:34 +00:00
Peter Robinson	4adcd6c9bf	drop ubsha1	2023-02-20 10:19:35 +00:00
Peter Robinson	7a9f14f8e7	2023.04 RC2	2023-02-17 16:03:02 +00:00
Peter Robinson	de2eac07ba	upadte source hash	2023-01-31 13:11:34 +00:00