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Add support for riscv64

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Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
This commit is contained in:
David Abdurachmanov 2023-05-03 11:03:58 +03:00
parent 69626555b7
commit f890d0262b
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
5 changed files with 384 additions and 3 deletions
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102
0001-Improve-riscv-defconfigs.patch Normal file
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@ -0,0 +1,102 @@
From 71cc03c5c98c4d2dbf13061690f61394711ccc66 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <davidlt@rivosinc.com>
Date: Wed, 3 May 2023 07:33:11 +0000
Subject: [PATCH 1/3] Improve riscv defconfigs
- Enable "sbi" command.
- Enable SBI based reset and poweroff commands.
- Set max supported CPUs on QEMU targets to 32.
- Enable relocation and use firmware FDT/DTB (i.e. generated by QEMU) for QEMU targets.
Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
---
configs/qemu-riscv64_defconfig | 8 ++++++++
configs/qemu-riscv64_smode_defconfig | 5 +++++
configs/qemu-riscv64_spl_defconfig | 3 +++
configs/sifive_unleashed_defconfig | 5 +++++
configs/sifive_unmatched_defconfig | 5 +++++
include/configs/qemu-riscv.h | 2 --
6 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index d64f3400..09816973 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -23,3 +23,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_NR_CPUS=32
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x20000;"
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 53c2f489..c9bdc485 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -26,3 +26,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 9c8eb155..de65d4f0 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -28,3 +28,6 @@ CONFIG_DM_MTD=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_SYS_MAX_FLASH_BANKS=2
# CONFIG_BINMAN_FDT is not set
+CONFIG_NR_CPUS=32
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x20000;"
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index ae0f9b42..c4958785 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -41,3 +41,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index c24feb68..74cdb4ea 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -63,3 +63,8 @@ CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_CMD_SBI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_SBI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 20135f56..23db7b6f 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -35,8 +35,6 @@
"qemu "
#define CFG_EXTRA_ENV_SETTINGS \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x84000000\0" \
"kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
--
2.40.1

104
0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch Normal file
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@ -0,0 +1,104 @@
From 039f475da3e1e140ef5dd0c6d8dfb0676af0d39e Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Wed, 3 May 2023 07:34:48 +0000
Subject: [PATCH 2/3] board: sifive: spl: Initialized the PWM setting in the
SPL stage
LEDs and multiple fans can be controlled by SPL. This patch ensures
that all fans have been enabled in the SPL stage. In addition, the
LED's color will be set to yellow.
---
board/sifive/unmatched/Makefile | 1 +
board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++
board/sifive/unmatched/spl.c | 2 ++
3 files changed, 60 insertions(+)
create mode 100644 board/sifive/unmatched/pwm.c
diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
index 13453300..5df01982 100644
--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
@@ -9,3 +9,4 @@ obj-y += spl.o
else
obj-y += unmatched.o
endif
+obj-y += pwm.o
diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
new file mode 100644
index 00000000..e1cc0231
--- /dev/null
+++ b/board/sifive/unmatched/pwm.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021, SiFive Inc
+ *
+ * Authors:
+ * Vincent Chen <vincent.chen@sifive.com>
+ * David Abdurachmanov <david.abdurachmanov@sifive.com>
+ */
+
+#include <linux/io.h>
+#include <asm/arch/eeprom.h>
+
+struct pwm_sifive_regs {
+ unsigned int cfg; /* PWM configuration register */
+ unsigned int pad0; /* Reserved */
+ unsigned int cnt; /* PWM count register */
+ unsigned int pad1; /* Reserved */
+ unsigned int pwms; /* Scaled PWM count register */
+ unsigned int pad2; /* Reserved */
+ unsigned int pad3; /* Reserved */
+ unsigned int pad4; /* Reserved */
+ unsigned int cmp0; /* PWM 0 compare register */
+ unsigned int cmp1; /* PWM 1 compare register */
+ unsigned int cmp2; /* PWM 2 compare register */
+ unsigned int cmp3; /* PWM 3 compare register */
+};
+
+#define PWM0_BASE 0x10020000
+#define PWM1_BASE 0x10021000
+#define PWM_CFG_INIT 0x1000
+#define PWM_CMP_ENABLE_VAL 0x0
+#define PWM_CMP_DISABLE_VAL 0xffff
+
+void pwm_device_init(void)
+{
+ struct pwm_sifive_regs *pwm0, *pwm1;
+ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
+ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
+ /* Set the 3-color PWM LEDs to yellow in SPL */
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
+
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
+ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
+ so here sets the initial value of PWM_COMP0 as DISABLE */
+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
+ else
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+}
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 7c0beedc..f3a661a8 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -90,6 +90,8 @@ int spl_board_init_f(void)
goto end;
}
+ pwm_device_init();
+
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
--
2.40.1

123
0003-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch Normal file
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@ -0,0 +1,123 @@
From e1dcf7e7a3b5c0e76171ba0b7145af12693adcc4 Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Wed, 3 May 2023 07:46:41 +0000
Subject: [PATCH 3/3] board: sifive: spl: Set remote thermal of TMP451 to 85
deg C for the unmatched board
For TMP451 on the unmatched board, the default value of the remote
thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL.
---
board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++
configs/sifive_unmatched_defconfig | 3 +++
drivers/misc/Kconfig | 14 ++++++++++++++
include/configs/sifive-unmatched.h | 4 ++++
4 files changed, 50 insertions(+)
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index f3a661a8..05ba5916 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -10,6 +10,8 @@
#include <spl.h>
#include <misc.h>
#include <log.h>
+#include <config.h>
+#include <i2c.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
@@ -26,6 +28,27 @@
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
+#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19
+#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55
+
+static inline int init_tmp451_remote_therm_limit(void)
+{
+ struct udevice *dev;
+ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM,
+ CONFIG_SYS_I2C_TMP451_ADDR,
+ CONFIG_SYS_I2C_TMP451_ADDR_LEN,
+ &dev);
+
+ if (!ret)
+ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET,
+ &r_therm_limit,
+ sizeof(unsigned char));
+ return ret;
+}
+
static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
{
int ret;
@@ -92,6 +115,12 @@ int spl_board_init_f(void)
pwm_device_init();
+ ret = init_tmp451_remote_therm_limit();
+ if (ret) {
+ debug("TMP451 remote THERM limit init failed: %d\n", ret);
+ goto end;
+ }
+
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 74cdb4ea..e843378c 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -68,3 +68,6 @@ CONFIG_SYSRESET=y
CONFIG_SYSRESET_SBI=y
CONFIG_CMD_POWEROFF=y
CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYS_TMP451_BUS_NUM=0
+CONFIG_SYS_I2C_TMP451_ADDR=0x4c
+CONFIG_SYS_I2C_TMP451_ADDR_LEN=1
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index b5707a15..8ea6f014 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -552,6 +552,20 @@ config SYS_I2C_EEPROM_ADDR
if I2C_EEPROM
+config SYS_TMP451_BUS_NUM
+ int "Bus number of TMP451 device"
+ default 0
+
+config SYS_I2C_TMP451_ADDR
+ hex "Chip address of the TMP451 device"
+ default 0
+
+config SYS_I2C_TMP451_ADDR_LEN
+ int "Length in bytes of the TMP451 memory array address"
+ default 1
+ help
+ Note: This is NOT the chip address length!
+
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
default 0x0
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 74150b7d..6a8eb1e6 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -13,6 +13,10 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_TMP451_BUS_NUM 0
+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c
+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1
+
/* Environment options */
#define BOOT_TARGET_DEVICES(func) \
--
2.40.1

5
riscv64-boards Normal file
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@ -0,0 +1,5 @@
qemu-riscv64
qemu-riscv64_smode
qemu-riscv64_spl
sifive_unleashed
sifive_unmatched

53
uboot-tools.spec
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@ -5,9 +5,12 @@
%bcond_without toolsonly
%endif
# Set it to "opensbi" (stable) or opensbi-unstable (unstable, git)
%global opensbi opensbi-unstable
Name: uboot-tools
Version: 2023.04
Release: 1%{?candidate:.%{candidate}}%{?dist}
Release: 1%{?candidate:.%{candidate}}.0.riscv64%{?dist}
Summary: U-Boot utilities
License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
URL: http://www.denx.de/wiki/U-Boot
@ -15,6 +18,7 @@ URL: http://www.denx.de/wiki/U-Boot
ExcludeArch: s390x
Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2
Source1: aarch64-boards
Source2: riscv64-boards
# Fedoraisms patches
# Needed to find DT on boot partition that's not the first partition
@ -27,6 +31,11 @@ Patch3: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
# Rockchips improvements
Patch6: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
# RISC-V (riscv64) patches
Patch20: 0001-Improve-riscv-defconfigs.patch
Patch21: 0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
Patch22: 0003-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
BuildRequires: bc
BuildRequires: bison
BuildRequires: dtc
@ -50,6 +59,9 @@ BuildRequires: python3-pyelftools
%endif
%endif
Requires: dtc
%ifarch riscv64
BuildRequires: %{opensbi}
%endif
%description
This package contains a few U-Boot utilities - mkimage for creating boot images
@ -64,12 +76,22 @@ BuildArch: noarch
%description -n uboot-images-armv8
U-Boot firmware binaries for aarch64 boards
%endif
%ifarch riscv64
%package -n uboot-images-riscv64
Summary: u-boot bootloader images for riscv64 boards
Requires: uboot-tools
BuildArch: noarch
%description -n uboot-images-riscv64
u-boot bootloader binaries for riscv64 boards
%endif
%endif
%prep
%autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}}
cp %SOURCE1 .
cp %SOURCE1 %SOURCE2 .
%build
mkdir builds
@ -78,7 +100,11 @@ mkdir builds
%make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-all O=builds/
%if %{with toolsonly}
%ifarch aarch64
%ifarch riscv64
export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin
%endif
%ifarch aarch64 riscv64
for board in $(cat %{_arch}-boards)
do
echo "Building board: $board"
@ -149,6 +175,19 @@ done
install -p -m 0644 builds/apple_m1/u-boot-nodtb.bin %{buildroot}%{_datadir}/uboot/apple_m1/u-boot-nodtb.bin
%endif
%ifarch riscv64
for board in $(ls builds)
do
mkdir -p %{buildroot}%{_datadir}/uboot/$(echo $board)/
for file in u-boot.bin u-boot.dtb u-boot.img u-boot-nodtb.bin u-boot-dtb.bin u-boot.itb u-boot-dtb.img u-boot.its spl/u-boot-spl.bin spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb spl/u-boot-spl-dtb.bin
do
if [ -f builds/$(echo $board)/$(echo $file) ]; then
install -p -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/
fi
done
done
%endif
# Bit of a hack to remove binaries we don't use as they're large
%ifarch aarch64
for board in $(ls builds)
@ -207,9 +246,17 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand
%files -n uboot-images-armv8
%{_datadir}/uboot/*
%endif
%ifarch riscv64
%files -n uboot-images-riscv64
%{_datadir}/uboot/*
%endif
%endif
%changelog
* Wed May 03 2023 David Abdurachmanov <davidlt@rivosinc.com> - 2023.04-1.0.riscv64
- Add support for riscv64
* Tue Apr 04 2023 Peter Robinson <pbrobinson@fedoraproject.org> - 2023.04-1
- Update to 2023.04 GA