From f5a780f2f532b5aa4fb3bef2d23ef3bfd32c7ad1 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 23 Sep 2018 06:26:54 +0100 Subject: [PATCH] Update Rock960 patches, enable Rock960 Enterprise Edition (ficus) --- aarch64-boards | 1 + rk3399-Rock960-Ficus-board-support.patch | 2961 ++++++++++++++++++++++ rk3399-Rock960-board-support.patch | 772 ------ uboot-tools.spec | 5 +- 4 files changed, 2966 insertions(+), 773 deletions(-) create mode 100644 rk3399-Rock960-Ficus-board-support.patch delete mode 100644 rk3399-Rock960-board-support.patch diff --git a/aarch64-boards b/aarch64-boards index 054230c..5e876fe 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -6,6 +6,7 @@ dragonboard820c espresso7420 evb-rk3328 evb-rk3399 +ficus-rk3399 firefly-rk3399 geekbox hikey diff --git a/rk3399-Rock960-Ficus-board-support.patch b/rk3399-Rock960-Ficus-board-support.patch new file mode 100644 index 0000000..50a67da --- /dev/null +++ b/rk3399-Rock960-Ficus-board-support.patch @@ -0,0 +1,2961 @@ +From patchwork Fri Sep 21 00:22:12 2018 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v2, + 1/4] arm: dts: rockchip: add some common pin-settings to rk3399 +X-Patchwork-Submitter: Manivannan Sadhasivam +X-Patchwork-Id: 972789 +Message-Id: <20180921002215.2013-2-manivannan.sadhasivam@linaro.org> +To: sjg@chromium.org, + philipp.tomsich@theobroma-systems.com +Cc: tom@vamrs.com, Randy Li , amit.kucheria@linaro.org, + dev@vamrs.com, u-boot@lists.denx.de, + Manivannan Sadhasivam , stephen@vamrs.com +Date: Thu, 20 Sep 2018 17:22:12 -0700 +From: Manivannan Sadhasivam +List-Id: U-Boot discussion + +From: Randy Li + +Those pins would be used by many boards. + +Commit grabbed from Linux: + +commit b41023282d07b61a53e2c9b9508912b1e7ce7b4f +Author: Randy Li +Date: Thu Jun 21 21:32:10 2018 +0800 + + arm64: dts: rockchip: add some common pin-settings to rk3399 + + Those pins would be used by many boards. + + Signed-off-by: Randy Li + Signed-off-by: Heiko Stuebner + +Acked-by: Philipp Tomsich +Signed-off-by: Randy Li +Signed-off-by: Heiko Stuebner +Signed-off-by: Ezequiel Garcia +--- + +Changes in v2: None + + arch/arm/dts/rk3399.dtsi | 55 +++++++++++++++++++++++++++++++++++----- + 1 file changed, 49 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi +index 83c257b1228..8349451b03d 100644 +--- a/arch/arm/dts/rk3399.dtsi ++++ b/arch/arm/dts/rk3399.dtsi +@@ -1602,19 +1602,49 @@ + drive-strength = <12>; + }; + ++ pcfg_pull_none_13ma: pcfg-pull-none-13ma { ++ bias-disable; ++ drive-strength = <13>; ++ }; ++ ++ pcfg_pull_none_18ma: pcfg-pull-none-18ma { ++ bias-disable; ++ drive-strength = <18>; ++ }; ++ ++ pcfg_pull_none_20ma: pcfg-pull-none-20ma { ++ bias-disable; ++ drive-strength = <20>; ++ }; ++ ++ pcfg_pull_up_2ma: pcfg-pull-up-2ma { ++ bias-pull-up; ++ drive-strength = <2>; ++ }; ++ + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + ++ pcfg_pull_up_18ma: pcfg-pull-up-18ma { ++ bias-pull-up; ++ drive-strength = <18>; ++ }; ++ ++ pcfg_pull_up_20ma: pcfg-pull-up-20ma { ++ bias-pull-up; ++ drive-strength = <20>; ++ }; ++ + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + +- pcfg_pull_up_2ma: pcfg-pull-up-2ma { +- bias-pull-up; +- drive-strength = <2>; ++ pcfg_pull_down_8ma: pcfg-pull-down-8ma { ++ bias-pull-down; ++ drive-strength = <8>; + }; + + pcfg_pull_down_12ma: pcfg-pull-down-12ma { +@@ -1622,9 +1652,22 @@ + drive-strength = <12>; + }; + +- pcfg_pull_none_13ma: pcfg-pull-none-13ma { +- bias-disable; +- drive-strength = <13>; ++ pcfg_pull_down_18ma: pcfg-pull-down-18ma { ++ bias-pull-down; ++ drive-strength = <18>; ++ }; ++ ++ pcfg_pull_down_20ma: pcfg-pull-down-20ma { ++ bias-pull-down; ++ drive-strength = <20>; ++ }; ++ ++ pcfg_output_high: pcfg-output-high { ++ output-high; ++ }; ++ ++ pcfg_output_low: pcfg-output-low { ++ output-low; + }; + + clock { + +From patchwork Fri Sep 21 00:22:13 2018 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v2, + 2/4] rockchip: rk3399: Add common Rock960 family from Vamrs +X-Patchwork-Submitter: Manivannan Sadhasivam +X-Patchwork-Id: 972790 +Message-Id: <20180921002215.2013-3-manivannan.sadhasivam@linaro.org> +To: sjg@chromium.org, + philipp.tomsich@theobroma-systems.com +Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, + u-boot@lists.denx.de, + Manivannan Sadhasivam , + stephen@vamrs.com +Date: Thu, 20 Sep 2018 17:22:13 -0700 +From: Manivannan Sadhasivam +List-Id: U-Boot discussion + +Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs. +It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition) +96Boards. + +Below are some of the key differences between both Rock960 and Ficus +boards: + +1. Different host enable GPIO for USB +2. Different power and reset GPIO for PCI-E +3. No Ethernet port on Rock960 + +The common board support will be utilized by both boards. The device +tree has been organized in such a way that only the properties which +differ between both boards are placed in the board specific dts and +the reset of the nodes are placed in common dtsi file. + +Signed-off-by: Manivannan Sadhasivam +[Added instructions for SD card boot] +Signed-off-by: Ezequiel Garcia +--- + +Changes in v2: None + + arch/arm/dts/rk3399-rock960.dtsi | 506 ++++++++++++++++++++ + arch/arm/mach-rockchip/rk3399/Kconfig | 26 + + board/vamrs/rock960_rk3399/Kconfig | 15 + + board/vamrs/rock960_rk3399/MAINTAINERS | 6 + + board/vamrs/rock960_rk3399/Makefile | 6 + + board/vamrs/rock960_rk3399/README | 151 ++++++ + board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 ++ + include/configs/rock960_rk3399.h | 15 + + 8 files changed, 775 insertions(+) + create mode 100644 arch/arm/dts/rk3399-rock960.dtsi + create mode 100644 board/vamrs/rock960_rk3399/Kconfig + create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS + create mode 100644 board/vamrs/rock960_rk3399/Makefile + create mode 100644 board/vamrs/rock960_rk3399/README + create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c + create mode 100644 include/configs/rock960_rk3399.h + +diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi +new file mode 100644 +index 00000000000..51644d6d02d +--- /dev/null ++++ b/arch/arm/dts/rk3399-rock960.dtsi +@@ -0,0 +1,506 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2018 Linaro Ltd. ++ */ ++ ++#include ++#include ++#include "rk3399.dtsi" ++ ++/ { ++ vcc1v8_s0: vcc1v8-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_s0"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_drv>; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&host_vbus_drv>; ++ regulator-name = "vcc5v0_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 0>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ status = "okay"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc_sys>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc_sys>; ++ vcc10-supply = <&vcc_sys>; ++ vcc11-supply = <&vcc_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_hdmi: LDO_REG2 { ++ regulator-name = "vcca1v8_hdmi"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG3 { ++ regulator-name = "vcca_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sd: LDO_REG4 { ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc3v0_sd: LDO_REG5 { ++ regulator-name = "vcc3v0_sd"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca0v9_hdmi: LDO_REG7 { ++ regulator-name = "vcca0v9_hdmi"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++}; ++ ++&i2c4 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ ++ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ ++ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ ++ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ sdmmc { ++ sdmmc_bus1: sdmmc-bus1 { ++ rockchip,pins = ++ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = ++ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, ++ <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = ++ <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; ++ }; ++ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = ++ <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = ++ <1 17 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = ++ <1 14 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ clock-frequency = <100000000>; ++ clock-freq-min-max = <100000 100000000>; ++ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ sd-uhs-sdr104; ++ vqmmc-supply = <&vcc_sd>; ++ card-detect-delay = <800>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; +diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig +index 415466a49bb..8f18e33c76f 100644 +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -28,6 +28,31 @@ config TARGET_PUMA_RK3399 + * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI + * SPI, I2C, I2S, UART, GPIO, ... + ++config TARGET_ROCK960_RK3399 ++ bool "Vamrs Limited Rock960 board family" ++ help ++ Support for Rock960 board family by Vamrs Limited. This board ++ family consists of Rock960 (Consumer Edition) and Ficus ++ (Enterprise Edition) 96Boards. ++ ++ Common features implemented on both boards: ++ * Rockchip RK3399 SoC (2xCortex A72, 4xCortex A53, ARM Mali T860MP4) ++ * 16/32GB eMMC, uSD slot ++ * HDMI/DP/MIPI ++ * 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons ++ ++ Additional features of Rock960: ++ * 2GiB/4GiB LPDDR3 RAM ++ * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), ++ 1x USB 3.0 type C OTG ++ ++ Additional features of Ficus: ++ * 2GiB/4GiB DDR3 RAM ++ * Ethernet ++ * Dual SATA ++ * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), ++ 1x USB 3.0 type C OTG ++ + endchoice + + config SYS_SOC +@@ -38,5 +63,6 @@ config SYS_MALLOC_F_LEN + + source "board/rockchip/evb_rk3399/Kconfig" + source "board/theobroma-systems/puma_rk3399/Kconfig" ++source "board/vamrs/rock960_rk3399/Kconfig" + + endif +diff --git a/board/vamrs/rock960_rk3399/Kconfig b/board/vamrs/rock960_rk3399/Kconfig +new file mode 100644 +index 00000000000..cacc53f3780 +--- /dev/null ++++ b/board/vamrs/rock960_rk3399/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_ROCK960_RK3399 ++ ++config SYS_BOARD ++ default "rock960_rk3399" ++ ++config SYS_VENDOR ++ default "vamrs" ++ ++config SYS_CONFIG_NAME ++ default "rock960_rk3399" ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ ++endif +diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS +new file mode 100644 +index 00000000000..9f3fe75f4fb +--- /dev/null ++++ b/board/vamrs/rock960_rk3399/MAINTAINERS +@@ -0,0 +1,6 @@ ++ROCK960-RK3399 ++M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org ++S: Maintained ++F: board/rockchip/rock960_rk3399 ++F: include/configs/rock960_rk3399.h ++F: configs/rock960-rk3399_defconfig +diff --git a/board/vamrs/rock960_rk3399/Makefile b/board/vamrs/rock960_rk3399/Makefile +new file mode 100644 +index 00000000000..6c3e475b3a8 +--- /dev/null ++++ b/board/vamrs/rock960_rk3399/Makefile +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (C) 2018 Manivannan Sadhasivam ++# ++ ++obj-y += rock960-rk3399.o +diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README +new file mode 100644 +index 00000000000..f3389520b08 +--- /dev/null ++++ b/board/vamrs/rock960_rk3399/README +@@ -0,0 +1,151 @@ ++Contents ++======== ++ ++1. Introduction ++2. Get the Source and prebuild binary ++3. Compile the U-Boot ++4. Compile the rkdeveloptool ++5. Package the image ++ 5.1. Package the image for U-Boot SPL(option 1) ++ 5.2. Package the image for Rockchip miniloader(option 2) ++6. Bootloader storage options ++7. Flash the image to eMMC ++ 7.1. Flash the image with U-Boot SPL(option 1) ++ 7.2. Flash the image with Rockchip miniloader(option 2) ++8. Create a bootable SD/MMC ++9. And that is it ++ ++Introduction ++============ ++ ++Rock960 board family consists of Rock960 (Consumer Edition) and ++Ficus (Enterprise Edition) 96Boards featuring Rockchip RK3399 SoC. ++ ++Common features implemented on both boards: ++ * CPU: ARMv8 64bit Big-Little architecture, ++ * Big: dual-core Cortex-A72 ++ * Little: quad-core Cortex-A53 ++ * IRAM: 200KB ++ * eMMC: 16/32GB eMMC 5.1 ++ * PMU: RK808 ++ * SD/MMC ++ * Display: HDMI/DP/MIPI ++ * Low Speed Expansion Connector ++ * High Speed Expansion Connector ++ ++Additional features of Rock960: ++ * DRAM: 2GB/4GB LPDDR3 @ 1866MHz ++ * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), ++ 1x USB 3.0 type C OTG ++ ++Additional features of Ficus: ++ * DRAM: 2GB/4GB DDR3 @ 1600MHz ++ * Ethernet ++ * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), ++ 1x USB 3.0 type C OTG ++ ++Here is the step-by-step to boot to U-Boot on Rock960 boards. ++ ++Get the Source and prebuild binary ++================================== ++ ++ > git clone https://github.com/96rocks/rkbin.git ++ > git clone https://github.com/rockchip-linux/rkdeveloptool.git ++ ++Compile the U-Boot ++================== ++ ++ > cd ../u-boot ++ > export ARCH=arm64 ++ > export CROSS_COMPILE=aarch64-linux-gnu- ++ > make rock960-rk3399_defconfig ++ > make ++ > make u-boot.itb ++ ++Compile the rkdeveloptool ++========================= ++ ++Follow instructions in latest README ++ > cd ../rkdeveloptool ++ > autoreconf -i ++ > ./configure ++ > make ++ > sudo make install ++ ++Package the image ++================= ++ ++Package the image for U-Boot SPL(option 1) ++-------------------------------- ++ > cd .. ++ > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img ++ ++ Get idbspl.img in this step. ++ ++Package the image for Rockchip miniloader(option 2) ++------------------------------------------ ++ > cd ../rkbin ++ > ./tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img 0x200000 ++ ++ > ../u-boot/tools/mkimage -n rk3399 -T rksd -d rk3399_ddr_933MHz_v1.08.bin idbloader.img ++ > cat ./rk33/rk3399_miniloader_v1.06.bin >> idbloader.img ++ ++ Get uboot.img and idbloader.img in this step. ++ ++Bootloader storage options ++========================== ++ ++There are a few different storage options for the bootloader. ++This document explores two of these: eMMC and removable SD/MMC. ++ ++Flash the image to eMMC ++======================= ++ ++Flash the image with U-Boot SPL(option 1) ++------------------------------- ++Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: ++ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin ++ > rkdeveloptool wl 64 u-boot/idbspl.img ++ > rkdeveloptool wl 0x4000 u-boot/u-boot.itb ++ > rkdeveloptool rd ++ ++Flash the image with Rockchip miniloader(option 2) ++---------------------------------------- ++Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: ++ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin ++ > rkdeveloptool wl 0x40 idbloader.img ++ > rkdeveloptool wl 0x4000 uboot.img ++ > rkdeveloptool wl 0x6000 ./img/rk3399/trust.img ++ > rkdeveloptool rd ++ ++Create a bootable SD/MMC ++======================== ++ ++The idbspl.img contains the first stage, and the u-boot.img the second stage. ++As explained in the Rockchip partition table reference [1], the first stage ++(aka loader1) start sector is 64, and the second stage start sector is 16384. ++ ++Each sector is 512 bytes, which means the first stage offset is 32 KiB, ++and the second stage offset is 8 MiB. ++ ++Note: the second stage location is actually not as per the spec, ++but defined by the SPL. Mainline SPL defines an 8 MiB offset for the second ++stage. ++ ++Assuming the SD card is exposed by device /dev/mmcblk0, the commands ++to write the two stages are: ++ ++ > dd if=idbspl.img of=/dev/mmcblk0 bs=1k seek=32 ++ > dd if=u-boot.itb of=/dev/mmcblk0 bs=1k seek=8192 ++ ++Setting up the kernel and rootfs is beyond the scope of this document. ++ ++And that is it ++============== ++ ++You should be able to get U-Boot log in console/UART2(baurdrate 1500000) ++ ++For more detail, please reference [2]. ++ ++[1] http://opensource.rock-chips.com/wiki_Partitions ++[2] http://opensource.rock-chips.com/wiki_Boot_option +diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c +new file mode 100644 +index 00000000000..d3775b22191 +--- /dev/null ++++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c +@@ -0,0 +1,50 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018 Manivannan Sadhasivam ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int board_init(void) ++{ ++ int ret; ++ ++ ret = regulators_enable_boot_on(false); ++ if (ret) ++ debug("%s: Cannot enable boot on regulator\n", __func__); ++ ++ return 0; ++} ++ ++void spl_board_init(void) ++{ ++ struct udevice *pinctrl; ++ int ret; ++ ++ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); ++ if (ret) { ++ debug("%s: Cannot find pinctrl device\n", __func__); ++ goto err; ++ } ++ ++ /* Enable debug UART */ ++ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); ++ if (ret) { ++ debug("%s: Failed to set up console UART\n", __func__); ++ goto err; ++ } ++ ++ preloader_console_init(); ++ return; ++err: ++ printf("%s: Error %d\n", __func__, ret); ++ ++ /* No way to report error here */ ++ hang(); ++} +diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h +new file mode 100644 +index 00000000000..746d24cbff5 +--- /dev/null ++++ b/include/configs/rock960_rk3399.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2018 Manivannan Sadhasivam ++ */ ++ ++#ifndef __ROCK960_RK3399_H ++#define __ROCK960_RK3399_H ++ ++#include ++ ++#define CONFIG_SYS_MMC_ENV_DEV 1 ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++ ++#endif + +From patchwork Fri Sep 21 00:22:14 2018 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v2,3/4] rockchip: rk3399: Add Rock960 CE board support +X-Patchwork-Submitter: Manivannan Sadhasivam +X-Patchwork-Id: 972791 +Message-Id: <20180921002215.2013-4-manivannan.sadhasivam@linaro.org> +To: sjg@chromium.org, + philipp.tomsich@theobroma-systems.com +Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, + u-boot@lists.denx.de, + Manivannan Sadhasivam , + stephen@vamrs.com +Date: Thu, 20 Sep 2018 17:22:14 -0700 +From: Manivannan Sadhasivam +List-Id: U-Boot discussion + +Add board support for Rock960 CE board from Vamrs. This board utilizes +common Rock960 family support. + +Following peripherals are tested and known to work: +* USB 2.0 +* MMC + +This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which +is being used on the board. + +Signed-off-by: Manivannan Sadhasivam +--- + +Changes in v2: + +* Added missing config options for USB/uSD +* Fixed the commit description for DDR speed + + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-rock960.dts | 45 + + .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 +++++++++++++++++ + configs/rock960-rk3399_defconfig | 67 + + 4 files changed, 1649 insertions(+) + create mode 100644 arch/arm/dts/rk3399-rock960.dts + create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi + create mode 100644 configs/rock960-rk3399_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index ebfa2272627..9b891826b73 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk3399-puma-ddr1333.dtb \ + rk3399-puma-ddr1600.dtb \ + rk3399-puma-ddr1866.dtb \ ++ rk3399-rock960.dtb \ + rv1108-evb.dtb + dtb-$(CONFIG_ARCH_MESON) += \ + meson-gxbb-nanopi-k2.dtb \ +diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts +new file mode 100644 +index 00000000000..25c58b42611 +--- /dev/null ++++ b/arch/arm/dts/rk3399-rock960.dts +@@ -0,0 +1,45 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018 Manivannan Sadhasivam ++ */ ++ ++/dts-v1/; ++#include "rk3399-rock960.dtsi" ++#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" ++ ++/ { ++ model = "96boards Rock960"; ++ compatible = "vamrs,rock960", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; ++}; ++ ++&pinctrl { ++ pcie { ++ pcie_drv: pcie-drv { ++ rockchip,pins = ++ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb2 { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = ++ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&vcc3v3_pcie { ++ gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; ++}; ++ ++&vcc5v0_host { ++ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; ++}; +diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi +new file mode 100644 +index 00000000000..d14e833d228 +--- /dev/null ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi +@@ -0,0 +1,1536 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ * (C) Copyright 2018 Manivannan Sadhasivam ++ */ ++ ++&dmc { ++ rockchip,sdram-params = < ++ 0x1 ++ 0xa ++ 0x3 ++ 0x2 ++ 0x2 ++ 0x0 ++ 0xf ++ 0xf ++ 1 ++ 0x1d191519 ++ 0x14040808 ++ 0x00000002 ++ 0x00006226 ++ 0x00000054 ++ 0x00000000 ++ 0x1 ++ 0xa ++ 0x3 ++ 0x2 ++ 0x2 ++ 0x0 ++ 0xf ++ 0xf ++ 1 ++ 0x1d191519 ++ 0x14040808 ++ 0x00000002 ++ 0x00006226 ++ 0x00000054 ++ 0x00000000 ++ 800 ++ 6 ++ 2 ++ 9 ++ 1 ++ 0x00000700 ++ 0x00000000 ++ 0x00000000 ++ 0x00000000 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b/configs/rock960-rk3399_defconfig +new file mode 100644 +index 00000000000..9c6db64d7ec +--- /dev/null ++++ b/configs/rock960-rk3399_defconfig +@@ -0,0 +1,67 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 ++CONFIG_TARGET_ROCK960_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_BAUDRATE=1500000 ++CONFIG_SPL_STACK_R_ADDR=0x80000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" ++CONFIG_SYS_PROMPT="rock960 => " ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_PINCTRL_ROCKCHIP_RK3399=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_STORAGE=y ++CONFIG_USE_TINY_PRINTF=y ++CONFIG_ERRNO_STR=y + +From patchwork Fri Sep 21 00:22:15 2018 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v2,4/4] rockchip: rk3399: Add Ficus EE board support +X-Patchwork-Submitter: Manivannan Sadhasivam +X-Patchwork-Id: 972792 +Message-Id: <20180921002215.2013-5-manivannan.sadhasivam@linaro.org> +To: sjg@chromium.org, + philipp.tomsich@theobroma-systems.com +Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, + u-boot@lists.denx.de, + Manivannan Sadhasivam , + stephen@vamrs.com +Date: Thu, 20 Sep 2018 17:22:15 -0700 +From: Manivannan Sadhasivam +List-Id: U-Boot discussion + +Add board support for Ficus EE board from Vamrs. This board utilizes +common Rock960 family support. + +Following peripherals are tested and known to work: +* Gigabit Ethernet +* USB 2.0 +* MMC + +Signed-off-by: Ezequiel Garcia +[Reworked based on common Rock960 family support] +Signed-off-by: Manivannan Sadhasivam +--- + +Changes in v2: None + + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-ficus.dts | 78 ++++++++++++++++++++++++++++++++++ + configs/ficus-rk3399_defconfig | 71 +++++++++++++++++++++++++++++++ + 3 files changed, 150 insertions(+) + create mode 100644 arch/arm/dts/rk3399-ficus.dts + create mode 100644 configs/ficus-rk3399_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 9b891826b73..e2bd9822aa2 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk3288-veyron-minnie.dtb \ + rk3288-vyasa.dtb \ + rk3328-evb.dtb \ ++ rk3399-ficus.dtb \ + rk3368-lion.dtb \ + rk3368-sheep.dtb \ + rk3368-geekbox.dtb \ +diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts +new file mode 100644 +index 00000000000..de934cd61ab +--- /dev/null ++++ b/arch/arm/dts/rk3399-ficus.dts +@@ -0,0 +1,78 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2018 Collabora Ltd. ++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. ++ * ++ * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw ++ */ ++ ++/dts-v1/; ++#include "rk3399-rock960.dtsi" ++#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" ++ ++/ { ++ model = "96boards RK3399 Ficus"; ++ compatible = "vamrs,ficus", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc3v3_sys>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x28>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; ++}; ++ ++&pinctrl { ++ gmac { ++ rgmii_sleep_pins: rgmii-sleep-pins { ++ rockchip,pins = ++ <3 15 RK_FUNC_GPIO &pcfg_output_low>; ++ }; ++ }; ++ ++ pcie { ++ pcie_drv: pcie-drv { ++ rockchip,pins = ++ <1 24 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb2 { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = ++ <4 27 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&vcc3v3_pcie { ++ gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; ++}; ++ ++&vcc5v0_host { ++ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; ++}; +diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig +new file mode 100644 +index 00000000000..e890bc25238 +--- /dev/null ++++ b/configs/ficus-rk3399_defconfig +@@ -0,0 +1,71 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_ROCK960_RK3399=y ++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_STACK_R_ADDR=0x80000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_RGMII=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_PINCTRL_ROCKCHIP_RK3399=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_STORAGE=y ++CONFIG_USE_TINY_PRINTF=y ++CONFIG_ERRNO_STR=y diff --git a/rk3399-Rock960-board-support.patch b/rk3399-Rock960-board-support.patch deleted file mode 100644 index 0342d2d..0000000 --- a/rk3399-Rock960-board-support.patch +++ /dev/null @@ -1,772 +0,0 @@ -From patchwork Tue Aug 21 17:28:16 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,1/2] arm: dts: Add Rock960 devicetree support -X-Patchwork-Submitter: Manivannan Sadhasivam -X-Patchwork-Id: 960637 -Message-Id: <20180821172817.26463-2-manivannan.sadhasivam@linaro.org> -To: sjg@chromium.org, - philipp.tomsich@theobroma-systems.com -Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, - u-boot@lists.denx.de, - Manivannan Sadhasivam , - stephen@vamrs.com -Date: Tue, 21 Aug 2018 22:58:16 +0530 -From: Manivannan Sadhasivam -List-Id: U-Boot discussion - -Add devicetree support for Vamrs Limited Rock960. This board is one of -the 96Boards Consumer Edition platform. - -Signed-off-by: Manivannan Sadhasivam ---- - -Changes in v2: - -* Added missing DTB entry in arch/arm/dts/Makefile - - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-rock960.dts | 348 ++++++++++++++++++++++++++++++++ - 2 files changed, 349 insertions(+) - create mode 100644 arch/arm/dts/rk3399-rock960.dts - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index ebfa2272627..9b891826b73 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk3399-puma-ddr1333.dtb \ - rk3399-puma-ddr1600.dtb \ - rk3399-puma-ddr1866.dtb \ -+ rk3399-rock960.dtb \ - rv1108-evb.dtb - dtb-$(CONFIG_ARCH_MESON) += \ - meson-gxbb-nanopi-k2.dtb \ -diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts -new file mode 100644 -index 00000000000..8662548e642 ---- /dev/null -+++ b/arch/arm/dts/rk3399-rock960.dts -@@ -0,0 +1,348 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2018 Manivannan Sadhasivam -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include "rk3399.dtsi" -+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" -+ -+/ { -+ model = "Vamrs Limited Rock960 96Board"; -+ compatible = "rockchip,rk3399-rock960", "rockchip,rk3399"; -+ -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = \ -+ &sdhci, &sdmmc; -+ }; -+ -+ vccsys: vccsys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vccsys"; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_host0: vcc5v0-host0-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host0"; -+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc5v0_host1: vcc5v0-host1-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host1"; -+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc5v0_host2: vcc5v0-host2-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host2"; -+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vbus_typec: vbus-typec-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vbus_typec"; -+ gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-init-microvolt = <900000>; -+ }; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&pwm3 { -+ status = "okay"; -+}; -+ -+&saradc { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ u-boot,dm-pre-reloc; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ non-removable; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ i2c-scl-falling-time-ns = <50>; -+ i2c-scl-rising-time-ns = <100>; -+ u-boot,dm-pre-reloc; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc5v0_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vcc13-supply = <&vcc5v0_sys>; -+ vcc14-supply = <&vcc5v0_sys>; -+ vddio-supply = <&vcc_1v8>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG1 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_hdmi: LDO_REG2 { -+ regulator-name = "vcca1v8_hdmi"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG3 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-name = "vcc_sdio"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca1v8_mipi: LDO_REG5 { -+ regulator-name = "vcca1v8_mipi"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca0v9_hdmi: LDO_REG7 { -+ regulator-name = "vcca0v9_hdmi"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <0>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = -+ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; - -From patchwork Tue Aug 21 17:28:17 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,2/2] board: Add Vamrs Limited Rock960 board support -X-Patchwork-Submitter: Manivannan Sadhasivam -X-Patchwork-Id: 960641 -Message-Id: <20180821172817.26463-3-manivannan.sadhasivam@linaro.org> -To: sjg@chromium.org, - philipp.tomsich@theobroma-systems.com -Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, - u-boot@lists.denx.de, - Manivannan Sadhasivam , - stephen@vamrs.com -Date: Tue, 21 Aug 2018 22:58:17 +0530 -From: Manivannan Sadhasivam -List-Id: U-Boot discussion - -Add board support for Vamrs Limited Rock960 board, which is -one of the 96Boards Consumer Edition platform. - -Rock960 features: - * CPU: ARMv8 64bit Big-Little architecture, - * Big: dual-core Cortex-A72 - * Little: quad-core Cortex-A53 - * IRAM: 200KB - * DRAM: 2GB/4GB LPDDR3 @ 1866MHz - * eMMC: 16/32GB eMMC 5.1 - * PMU: RK808 - * SD/MMC - * USB: - * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only) and - 1x USB 3.0 type C OTG - * Display: - * 1x HDMI 2.0(Type A - full) up to 4Kx2K@60Hz, - 1x 4L - MIPI DSI up to 1080p@60Hz, - 1x DP 1.2(Type C) up to 4Kx2K@60 - * Camera: 2x 4-lane MIPI CSI - * PCI-E: 4- lane M.2 PCI-E 2.1 - * Low Speed Expansion Connector - * High Speed Expansion Connector - -Signed-off-by: Manivannan Sadhasivam ---- - -Changes in v2: None - - arch/arm/mach-rockchip/rk3399/Kconfig | 16 +++++ - board/vamrs/rock960_rk3399/Kconfig | 15 ++++ - board/vamrs/rock960_rk3399/MAINTAINERS | 6 ++ - board/vamrs/rock960_rk3399/Makefile | 6 ++ - board/vamrs/rock960_rk3399/README | 79 +++++++++++++++++++++ - board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 +++++++++++++ - configs/rock960-rk3399_defconfig | 62 ++++++++++++++++ - include/configs/rock960_rk3399.h | 15 ++++ - 8 files changed, 249 insertions(+) - create mode 100644 board/vamrs/rock960_rk3399/Kconfig - create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS - create mode 100644 board/vamrs/rock960_rk3399/Makefile - create mode 100644 board/vamrs/rock960_rk3399/README - create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c - create mode 100644 configs/rock960-rk3399_defconfig - create mode 100644 include/configs/rock960_rk3399.h - -diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig -index 415466a49bb..ce4605187e3 100644 ---- a/arch/arm/mach-rockchip/rk3399/Kconfig -+++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -28,6 +28,21 @@ config TARGET_PUMA_RK3399 - * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI - * SPI, I2C, I2S, UART, GPIO, ... - -+config TARGET_ROCK960_RK3399 -+ bool "Vamrs Limited Rock960 board" -+ help -+ Support for Rock960 board. This board complies with -+ 96Board Consumer Edition Specification. -+ -+ Features: -+ * Rockchip RK3399 SoC (2xCortex A72, 4xCortex A53, ARM Mali T860MP4) -+ * 2GiB/4GiB RAM -+ * 16/32GB eMMC, uSD slot -+ * WiFi, Bluetooth -+ * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG -+ * HDMI -+ * 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons -+ - endchoice - - config SYS_SOC -@@ -38,5 +53,6 @@ config SYS_MALLOC_F_LEN - - source "board/rockchip/evb_rk3399/Kconfig" - source "board/theobroma-systems/puma_rk3399/Kconfig" -+source "board/vamrs/rock960_rk3399/Kconfig" - - endif -diff --git a/board/vamrs/rock960_rk3399/Kconfig b/board/vamrs/rock960_rk3399/Kconfig -new file mode 100644 -index 00000000000..cacc53f3780 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_ROCK960_RK3399 -+ -+config SYS_BOARD -+ default "rock960_rk3399" -+ -+config SYS_VENDOR -+ default "vamrs" -+ -+config SYS_CONFIG_NAME -+ default "rock960_rk3399" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif -diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS -new file mode 100644 -index 00000000000..9f3fe75f4fb ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/MAINTAINERS -@@ -0,0 +1,6 @@ -+ROCK960-RK3399 -+M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org -+S: Maintained -+F: board/rockchip/rock960_rk3399 -+F: include/configs/rock960_rk3399.h -+F: configs/rock960-rk3399_defconfig -diff --git a/board/vamrs/rock960_rk3399/Makefile b/board/vamrs/rock960_rk3399/Makefile -new file mode 100644 -index 00000000000..6c3e475b3a8 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/Makefile -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# Copyright (C) 2018 Manivannan Sadhasivam -+# -+ -+obj-y += rock960-rk3399.o -diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README -new file mode 100644 -index 00000000000..be6b5cd1d34 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/README -@@ -0,0 +1,79 @@ -+Introduction -+============ -+ -+Rock960 is a 96Boards Consumer Edition platform featuring the Rockchip -+RK3399 SoC. -+ -+Rock960 features: -+ * CPU: ARMv8 64bit Big-Little architecture, -+ * Big: dual-core Cortex-A72 -+ * Little: quad-core Cortex-A53 -+ * IRAM: 200KB -+ * DRAM: 2GB/4GB LPDDR3 @ 1866MHz -+ * eMMC: 16/32GB eMMC 5.1 -+ * PMU: RK808 -+ * SD/MMC -+ * USB: -+ * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only) and -+ 1x USB 3.0 type C OTG -+ * Display: -+ * 1x HDMI 2.0(Type A - full) up to 4Kx2K@60Hz, -+ 1x 4L - MIPI DSI up to 1080p@60Hz, -+ 1x DP 1.2(Type C) up to 4Kx2K@60 -+ * Camera: 2x 4-lane MIPI CSI -+ * PCI-E: 4- lane M.2 PCI-E 2.1 -+ * Low Speed Expansion Connector -+ * High Speed Expansion Connector -+ -+Here is the step-by-step to boot to U-Boot on rk3399. -+ -+Get the Source and prebuild binary -+================================== -+ -+ > git clone https://github.com/96rocks/rkbin.git -+ > git clone https://github.com/rockchip-linux/rkdeveloptool.git -+ -+Compile the U-Boot -+================== -+ -+ > cd ../u-boot -+ > export ARCH=arm64 -+ > export CROSS_COMPILE=aarch64-linux-gnu- -+ > make rock960-rk3399_defconfig -+ > make -+ -+Compile the rkdeveloptool -+========================= -+ Follow instructions in latest README -+ > cd ../rkdeveloptool -+ > autoreconf -i -+ > ./configure -+ > make -+ > sudo make install -+ -+Package the image -+================= -+ -+Package the image for Rockchip miniloader -+------------------------------------------ -+ > cd ../rkbin -+ > ./tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img 0x200000 -+ -+ > ../u-boot/tools/mkimage -n rk3399 -T rksd -d rk3399_ddr_933MHz_v1.08.bin idbloader.img -+ > cat ./rk33/rk3399_miniloader_v1.06.bin >> idbloader.img -+ -+ Get uboot.img and idbloader.img in this step. -+ -+Flash the image to eMMC -+======================= -+ -+Flash the image with Rockchip miniloader -+---------------------------------------- -+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: -+ > rkdeveloptool db ./rk33/rk3399_loader_v1.08.106.bin -+ > rkdeveloptool wl 0x40 idbloader.img -+ > rkdeveloptool wl 0x4000 uboot.img -+ > rkdeveloptool wl 0x6000 ./img/rk3399/trust.img -+ > rkdeveloptool rd -+ -+You should be able to get U-Boot log in console/UART2(baurdrate 1500000) -diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c -new file mode 100644 -index 00000000000..d3775b22191 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2018 Manivannan Sadhasivam -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_init(void) -+{ -+ int ret; -+ -+ ret = regulators_enable_boot_on(false); -+ if (ret) -+ debug("%s: Cannot enable boot on regulator\n", __func__); -+ -+ return 0; -+} -+ -+void spl_board_init(void) -+{ -+ struct udevice *pinctrl; -+ int ret; -+ -+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); -+ if (ret) { -+ debug("%s: Cannot find pinctrl device\n", __func__); -+ goto err; -+ } -+ -+ /* Enable debug UART */ -+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); -+ if (ret) { -+ debug("%s: Failed to set up console UART\n", __func__); -+ goto err; -+ } -+ -+ preloader_console_init(); -+ return; -+err: -+ printf("%s: Error %d\n", __func__, ret); -+ -+ /* No way to report error here */ -+ hang(); -+} -diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -new file mode 100644 -index 00000000000..998c7a4b707 ---- /dev/null -+++ b/configs/rock960-rk3399_defconfig -@@ -0,0 +1,62 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 -+CONFIG_TARGET_ROCK960_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_BAUDRATE=1500000 -+CONFIG_SPL_STACK_R_ADDR=0x80000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" -+CONFIG_SYS_PROMPT="rock960 => " -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_SF=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_PINCTRL_ROCKCHIP_RK3399=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_SYSRESET=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_ERRNO_STR=y -diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h -new file mode 100644 -index 00000000000..746d24cbff5 ---- /dev/null -+++ b/include/configs/rock960_rk3399.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (C) 2018 Manivannan Sadhasivam -+ */ -+ -+#ifndef __ROCK960_RK3399_H -+#define __ROCK960_RK3399_H -+ -+#include -+ -+#define CONFIG_SYS_MMC_ENV_DEV 1 -+ -+#define SDRAM_BANK_SIZE (2UL << 30) -+ -+#endif diff --git a/uboot-tools.spec b/uboot-tools.spec index aa9b8b2..f590e80 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -25,7 +25,7 @@ Patch3: usb-kbd-fixes.patch Patch10: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch11: rockchip-make_fit_atf-fix-warning-unit_address_vs_reg.patch Patch12: rockchip-make_fit_atf-use-elf-entry-point.patch -Patch13: rk3399-Rock960-board-support.patch +Patch13: rk3399-Rock960-Ficus-board-support.patch Patch14: dragonboard-fixes.patch Patch15: tegra186-jetson-tx2-disable-onboard-emmc.patch Patch16: tegra-efi_loader-simplify-ifdefs.patch @@ -299,6 +299,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Sun Sep 23 2018 Peter Robinson +- Update Rock960 patches, enable Rock960 Enterprise Edition (ficus) + * Mon Sep 10 2018 Peter Robinson 2018.09-1 - 2018.09