diff --git a/aarch64-boards b/aarch64-boards index ab282d9..f8e2f3b 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -61,6 +61,7 @@ pinebook pinebook-pro-rk3399 pine_h64 pinephone +pinephone-pro-rk3399 pinetab poplar puma-rk3399 @@ -77,8 +78,8 @@ roc-pc-rk3399 rpi_3 rpi_4 rpi_arm64 -starqltechn sopine_baseboard +starqltechn tanix_tx6 teres_i turris_mox diff --git a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch index f06c063..30012ad 100644 --- a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch +++ b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch @@ -1,34 +1,38 @@ -From: Martijn Braam -Subject: [PATCH] rockchip: Add initial support for the PinePhone Pro -Date: Thu, 21 Oct 2021 19:18:43 +0200 +From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 31 Dec 2022 09:20:34 +0000 +Subject: [PATCH v2 0/2] Initial support for Pinephone Pro -This is a new device by PINE64 that's very similar to the Pinebook Pro -that's already supported. +This adds initial support for the PINE64 Pinephone Pro. It's a rebase +to upstream core rk3399 DT pieces, and the addition of the upstream +PPP DT from 6.2-rc1 and the U-Boot pieces are based on my work on +the Pinebook Pro. -Specification: -- Rockchip RK3399 -- 4GB Dual-Channel LPDDR4 -- 128GB eMMC -- mSD card slot -- AP6255 for 802.11ac WiFi and Bluetooth -- 6 inch 720*1440 DSI display -- Quectel EG25g usb modem -- Type-C port with alt-mode display (DP 1.2) and PD charging. +Changes v2: +- Drop the rk3399.dtsi sync for time being, causing issues around + clock/dram +- Sync the Pinephone DT to 6.2-rc1 +- Update for the CONFIG_SYS_TEXT_BASE -> CONFIG_TEXT_BASE change +- usb: ohci: Use a flexible array member for portstatus +- Rename CONFIG_DM_VIDEO to CONFIG_VIDEO +- Enable DM_REGULATOR_FAN53555 +- Don't initialize i2c before relocation -Signed-off-by: Martijn Braam ---- +Peter Robinson (2): + arm64: dts: rk3399: Add upstream Pinephone Pro dts + rockchip: Add initial support for the PINE64 Pinephone Pro arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++ - arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++ + arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++ + arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinephone-pro-rk3399/Kconfig | 15 + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + board/pine64/pinephone-pro-rk3399/Makefile | 1 + - .../pinephone-pro-rk3399.c | 57 ++ - configs/pinephone-pro-rk3399_defconfig | 92 ++++ - include/configs/pinephone-pro-rk3399.h | 23 + - 10 files changed, 769 insertions(+) + .../pinephone-pro-rk3399.c | 76 +++ + configs/pinephone-pro-rk3399_defconfig | 104 ++++ + include/configs/pinephone-pro-rk3399.h | 19 + + 10 files changed, 737 insertions(+) create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig @@ -37,12 +41,30 @@ Signed-off-by: Martijn Braam create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c create mode 100644 configs/pinephone-pro-rk3399_defconfig create mode 100644 include/configs/pinephone-pro-rk3399.h - + +-- +2.39.0 + +From 9976caacb35316cbe047ded58855d2ca1a54243b Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 31 Dec 2022 09:18:44 +0000 +Subject: [PATCH v2 1/2] arm64: dts: rk3399: Add upstream Pinephone Pro dts + +Initial support for the PinePhone Pro has now landed upstream in +Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++++++++++ + 2 files changed, 475 insertions(+) + create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts + diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index ed3d360bb1..3206370226 100644 +index 43951a7731e..8c1eec1025f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ +@@ -153,6 +153,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-r4s.dtb \ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ @@ -50,106 +72,115 @@ index ed3d360bb1..3206370226 100644 rk3399-puma-haikou.dtb \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ -diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -new file mode 100644 -index 0000000000..9d44db5978 ---- /dev/null -+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Peter Robinson -+ * Copyright (C) 2021 Martijn Braam -+ */ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+ -+/ { -+ aliases { -+ spi0 = &spi1; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+ -+ config { -+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ -+ }; -+}; -+ -+&i2c0 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rk818 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rng { -+ status = "okay"; -+}; -+ -+&sdhci { -+ max-frequency = <25000000>; -+ u-boot,dm-pre-reloc; -+}; -+ -+&sdmmc { -+ max-frequency = <20000000>; -+ u-boot,dm-pre-reloc; -+}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts new file mode 100644 -index 0000000000..3fe1845ced +index 00000000000..04403a76238 --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro.dts -@@ -0,0 +1,520 @@ +@@ -0,0 +1,474 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* -+ * Copyright (c) 2021 Martijn Braam ++ * Copyright (c) 2020 Martijn Braam ++ * Copyright (c) 2021 Kamil Trzciński ++ */ ++ ++/* ++ * PinePhone Pro datasheet: ++ * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf + */ + +/dts-v1/; ++#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { -+ model = "Pine64 PinePhone Pro"; ++ model = "Pine64 PinePhonePro"; + compatible = "pine64,pinephone-pro", "rockchip,rk3399"; ++ chassis-type = "handset"; ++ ++ aliases { ++ mmc0 = &sdio0; ++ mmc1 = &sdmmc; ++ mmc2 = &sdhci; ++ }; + + chosen { -+ stdout-path = "serial2:1500000n8"; ++ stdout-path = "serial2:115200n8"; + }; + -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; ++ gpio-keys { ++ compatible = "gpio-keys"; + pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn_pin>; ++ ++ key-power { ++ debounce-interval = <20>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "Power"; ++ linux,code = ; ++ wakeup-source; ++ }; + }; + -+ /* Power tree */ -+ /* Root power source */ -+ vcc_sysin: vcc-sysin { ++ vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; -+ regulator-name = "vcc_sysin"; ++ regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + }; + -+ /* Main 3.3v supply */ -+ vcc3v3_sys: vcc3v3-sys { ++ vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sysin>; ++ vin-supply = <&vcc_sys>; ++ }; + -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; ++ vcca1v8_s3: vcc1v8-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca1v8_s3"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc1v8_codec: vcc1v8-codec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc1v8_codec_en>; ++ regulator-name = "vcc1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ wifi_pwrseq: sdio-wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk818 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h_pin>; ++ /* ++ * Wait between power-on and SDIO access for CYP43455 ++ * POR circuit. ++ */ ++ post-power-on-delay-ms = <110>; ++ /* ++ * Wait between consecutive toggles for CYP43455 CBUCK ++ * regulator discharge. ++ */ ++ power-off-delay-us = <10000>; ++ ++ /* WL_REG_ON on module */ ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + @@ -181,11 +212,6 @@ index 0000000000..3fe1845ced + status = "okay"; +}; + -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; @@ -204,22 +230,22 @@ index 0000000000..3fe1845ced + rockchip,system-power-controller; + wakeup-source; + -+ vcc1-supply = <&vcc_sysin>; -+ vcc2-supply = <&vcc_sysin>; -+ vcc3-supply = <&vcc_sysin>; -+ vcc4-supply = <&vcc_sysin>; -+ vcc6-supply = <&vcc_sysin>; ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc_sysin>; ++ vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_cpu_l: DCDC_REG1 { -+ regulator-name = "vdd_cpu_1"; ++ regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; @@ -231,7 +257,7 @@ index 0000000000..3fe1845ced + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1350000>; ++ regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; @@ -255,52 +281,35 @@ index 0000000000..3fe1845ced + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca3v0_codec: LDO_REG1 { + regulator-name = "vcca3v0_codec"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + + vcca1v8_codec: LDO_REG3 { + regulator-name = "vcca1v8_codec"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + -+ vcc_power_on: LDO_REG4 { -+ regulator-name = "vcc_power_on"; ++ rk818_pwr_on: LDO_REG4 { ++ regulator-name = "rk818_pwr_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; + }; + }; + @@ -312,7 +321,6 @@ index 0000000000..3fe1845ced + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; + }; + }; + @@ -324,19 +332,13 @@ index 0000000000..3fe1845ced + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_dvp: LDO_REG7 { + regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + + vcc3v3_s3: LDO_REG8 { @@ -350,14 +352,10 @@ index 0000000000..3fe1845ced + }; + }; + -+ vcc_sd: LDO_REG9 { -+ regulator-name = "vcc_sd"; ++ vccio_sd: LDO_REG9 { ++ regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; + }; + + vcc3v3_s0: SWITCH_REG { @@ -368,22 +366,6 @@ index 0000000000..3fe1845ced + regulator-on-in-suspend; + }; + }; -+ -+ boost_otg: DCDC_BOOST { -+ regulator-name = "boost_otg"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <5000000>; -+ }; -+ }; -+ -+ otg_switch: OTG_SWITCH { -+ regulator-name = "otg_switch"; -+ }; + }; + }; + @@ -394,8 +376,8 @@ index 0000000000..3fe1845ced + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; @@ -412,8 +394,8 @@ index 0000000000..3fe1845ced + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; @@ -424,95 +406,47 @@ index 0000000000..3fe1845ced + }; +}; + -+&i2c1 { -+ i2c-scl-rising-time-ns = <300>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; ++&cluster0_opp { ++ opp04 { ++ status = "disabled"; ++ }; ++ ++ opp05 { ++ status = "disabled"; ++ }; +}; + -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; ++&cluster1_opp { ++ opp06 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <1100000 1100000 1150000>; ++ }; + -+&i2c4 { -+ i2c-scl-rising-time-ns = <600>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ status = "okay"; ++ opp07 { ++ status = "disabled"; + }; +}; + +&io_domains { -+ status = "okay"; -+ + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sd>; ++ sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; ++ status = "okay"; +}; + +&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; ++ pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ + buttons { -+ pwrbtn: pwrbtn { ++ pwrbtn_pin: pwrbtn-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + -+ fusb302x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ leds { -+ work_led_pin: work-led-pin { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ diy_led_pin: diy-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie_perst: pcie-perst { -+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_pwr_en: pcie-pwr-en { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -527,51 +461,40 @@ index 0000000000..3fe1845ced + }; + }; + -+ sdcard { -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ }; -+ + sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { ++ wifi_enable_h_pin: wifi-enable-h-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + -+ usb-typec { -+ vcc5v0_typec_en: vcc5v0_typec_en { -+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ sound { ++ vcc1v8_codec_en: vcc1v8-codec-en { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + -+ usb2 { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ wireless-bluetooth { ++ bt_wake_pin: bt-wake-pin { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_pin: bt-host-wake-pin { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_reset_pin: bt-reset-pin { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; ++ mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; @@ -582,13 +505,13 @@ index 0000000000..3fe1845ced +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; -+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v3_s3>; -+ vqmmc-supply = <&vcc_1v8>; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + @@ -600,51 +523,133 @@ index 0000000000..3fe1845ced +}; + +&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rk818 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ max-speed = <1500000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ }; ++}; ++ +&uart2 { + status = "okay"; +}; +-- +2.39.0 + +From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 28 Dec 2022 03:52:27 +0000 +Subject: [PATCH v2 2/2] rockchip: Add initial support for the PINE64 Pinephone + Pro + +The Pinephone Pro is another device by PINE64. It's closely related +to the Pinebook Pro of which this initial support is derived from. + +Specification: +- A variant of the Rockchip RK3399 +- A 6 inch 720*1440 DSI display +- Front and rear cameras +- Type-C interface with alt mode display (DP 1.2) and PD charging +- 4GB LPDDR4 RAM +- 128GB eMMC +- mSD card slot +- An AP6255 module for 802.11ac WiFi and Bluetooth 5 +- Quectel EG25-G 4G/LTE modem + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++++++ + arch/arm/mach-rockchip/rk3399/Kconfig | 8 ++ + board/pine64/pinephone-pro-rk3399/Kconfig | 15 +++ + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 ++ + board/pine64/pinephone-pro-rk3399/Makefile | 1 + + .../pinephone-pro-rk3399.c | 76 +++++++++++++ + configs/pinephone-pro-rk3399_defconfig | 104 ++++++++++++++++++ + include/configs/pinephone-pro-rk3399.h | 19 ++++ + 8 files changed, 262 insertions(+) + create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi + create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig + create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS + create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile + create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c + create mode 100644 configs/pinephone-pro-rk3399_defconfig + create mode 100644 include/configs/pinephone-pro-rk3399.h + +diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +new file mode 100644 +index 00000000000..1dad283ad05 +--- /dev/null ++++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2022 Peter Robinson ++ */ + -+&vopb { ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ }; ++ ++ config { ++ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ ++ }; ++}; ++ ++&rng { + status = "okay"; +}; + -+&vopb_mmu { -+ status = "okay"; ++&sdhci { ++ max-frequency = <25000000>; ++ u-boot,dm-pre-reloc; +}; + -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; ++&sdmmc { ++ max-frequency = <20000000>; ++ u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig -index 17628f9171..3ba603ca80 100644 +index b48feeb3466..d01063ac98b 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399 +@@ -39,6 +39,13 @@ config TARGET_PINEBOOK_PRO_RK3399 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, 1920*1080 screen and all the usual laptop features. +config TARGET_PINEPHONE_PRO_RK3399 + bool "PinePhone Pro" + help -+ PinePhone Pro is a phone based on the Rockchip rk3399 SoC -+ with 4Gb RAM, onboard eMMC, USB-C, a headphone jack, -+ 720x1440 screen and an external Quectel USB modem. ++ PinePhone Pro is a phone based on a variant of the Rockchip ++ rk3399 SoC with 4Gb RAM, onboard eMMC, USB-C, headphone jack, ++ 720x1440 screen and a Quectel 4G/LTE modem. + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help -@@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT +@@ -165,6 +172,7 @@ endif # BOOTCOUNT_LIMIT source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" @@ -654,7 +659,7 @@ index 17628f9171..3ba603ca80 100644 source "board/theobroma-systems/puma_rk3399/Kconfig" diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig new file mode 100644 -index 0000000000..13d6465ae6 +index 00000000000..13d6465ae6e --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Kconfig @@ -0,0 +1,15 @@ @@ -675,12 +680,12 @@ index 0000000000..13d6465ae6 +endif diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS new file mode 100644 -index 0000000000..9ca4fc4cbe +index 00000000000..c923ff1be32 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS @@ -0,0 +1,8 @@ +PINEPHONE_PRO -+M: Martijn Braam ++M: Peter Robinson +S: Maintained +F: board/pine64/rk3399-pinephone-pro/ +F: include/configs/rk3399-pinephone-pro.h @@ -689,21 +694,21 @@ index 0000000000..9ca4fc4cbe +F: configs/pinephone-pro-rk3399_defconfig diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile new file mode 100644 -index 0000000000..8d9203053e +index 00000000000..8d9203053e5 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Makefile @@ -0,0 +1 @@ +obj-y += pinephone-pro-rk3399.o diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c new file mode 100644 -index 0000000000..8efeb6ea3d +index 00000000000..eb639cd0d07 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -@@ -0,0 +1,57 @@ +@@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* -+ * (C) Copyright 2019 Vasily Khoruzhick -+ * (C) Copyright 2021 Martijn Braam ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ * (C) Copyright 2022 Peter Robinson + */ + +#include @@ -715,17 +720,39 @@ index 0000000000..8efeb6ea3d +#include +#include +#include ++#include + +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define PMUGRF_CON0_VSEL_SHIFT 8 + ++#ifndef CONFIG_SPL_BUILD ++int board_early_init_f(void) ++{ ++ struct udevice *regulator; ++ int ret; ++ ++ ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); ++ if (ret) { ++ pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); ++ goto out; ++ } ++ ++ ret = regulator_set_enable(regulator, true); ++ if (ret) ++ pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); ++ ++out: ++ return 0; ++} ++#endif ++ +#ifdef CONFIG_MISC_INIT_R +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); ++ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); @@ -751,42 +778,49 @@ index 0000000000..8efeb6ea3d + if (ret) + return ret; + -+ ret = rockchip_setup_macaddr(); -+ + return ret; +} -+ +#endif diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig new file mode 100644 -index 0000000000..2cf80f7d35 +index 00000000000..eb979f6c051 --- /dev/null +++ b/configs/pinephone-pro-rk3399_defconfig -@@ -0,0 +1,92 @@ +@@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_PINEPHONE_PRO_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" -+CONFIG_DEBUG_UART=y ++CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y ++CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x400000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y @@ -804,6 +838,7 @@ index 0000000000..2cf80f7d35 +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEYBOARD=y @@ -816,13 +851,14 @@ index 0000000000..2cf80f7d35 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_DM_ETH=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y ++CONFIG_DM_REGULATOR_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y @@ -849,23 +885,22 @@ index 0000000000..2cf80f7d35 +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y -+CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y ++CONFIG_VIDEO=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h new file mode 100644 -index 0000000000..fefa793fdd +index 00000000000..78017d6bcc3 --- /dev/null +++ b/include/configs/pinephone-pro-rk3399.h -@@ -0,0 +1,23 @@ +@@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd -+ * Copyright (C) 2020 Peter Robinson -+ * Copyright (C) 2021 Martijn Braam ++ * Copyright (C) 2022 Peter Robinson + */ + +#ifndef __PINEPHONE_PRO_RK3399_H @@ -880,89 +915,6 @@ index 0000000000..fefa793fdd + +#define SDRAM_BANK_SIZE (2UL << 30) + -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ +#endif ---- u-boot-2022.10/configs/pinephone-pro-rk3399_defconfig.orig 2022-10-12 16:14:17.050158119 +0100 -+++ u-boot-2022.10/configs/pinephone-pro-rk3399_defconfig 2022-10-12 16:14:28.525240728 +0100 -@@ -1,27 +1,37 @@ - CONFIG_ARM=y - CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 - CONFIG_ARCH_ROCKCHIP=y - CONFIG_SYS_TEXT_BASE=0x00200000 - CONFIG_NR_DRAM_BANKS=1 - CONFIG_ENV_SIZE=0x8000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" - CONFIG_ROCKCHIP_RK3399=y - CONFIG_TARGET_PINEPHONE_PRO_RK3399=y - CONFIG_DEBUG_UART_BASE=0xFF1A0000 - CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_SPL_SPI_FLASH_SUPPORT=y --CONFIG_SPL_SPI_SUPPORT=y --CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" --CONFIG_DEBUG_UART=y -+CONFIG_SPL_SPI=y - CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 - CONFIG_BOOTDELAY=3 - CONFIG_USE_PREBOOT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" - CONFIG_DISPLAY_BOARDINFO_LATE=y - CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x2e000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 - # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK=0x400000 - CONFIG_SPL_STACK_R=y - CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 --CONFIG_SPL_MTD_SUPPORT=y - CONFIG_SPL_SPI_LOAD=y - CONFIG_TPL=y - CONFIG_CMD_BOOTZ=y -@@ -39,6 +49,7 @@ - CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" - CONFIG_ENV_IS_IN_SPI_FLASH=y - CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SPL_DM_SEQ_ALIAS=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_DM_KEYBOARD=y -@@ -51,10 +62,10 @@ - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_SF_DEFAULT_BUS=1 - CONFIG_SF_DEFAULT_SPEED=20000000 - CONFIG_SPI_FLASH_GIGADEVICE=y - CONFIG_SPI_FLASH_WINBOND=y --CONFIG_DM_ETH=y - CONFIG_PHY_ROCKCHIP_INNO_USB2=y - CONFIG_PHY_ROCKCHIP_TYPEC=y - CONFIG_DM_PMIC_FAN53555=y -@@ -77,6 +88,7 @@ - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 - CONFIG_USB_DWC3=y - CONFIG_USB_DWC3_GENERIC=y - CONFIG_USB_KEYBOARD=y ---- u-boot-2022.10/include/configs/pinephone-pro-rk3399.h.orig 2022-10-12 16:14:51.881408874 +0100 -+++ u-boot-2022.10/include/configs/pinephone-pro-rk3399.h 2022-10-12 16:14:58.693457915 +0100 -@@ -17,7 +17,4 @@ - - #define SDRAM_BANK_SIZE (2UL << 30) - --#define CONFIG_USB_OHCI_NEW --#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -- - #endif +-- +2.39.0 diff --git a/uboot-tools.spec b/uboot-tools.spec index 09d8e3e..095727c 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -7,7 +7,7 @@ Name: uboot-tools Version: 2023.01 -Release: 0.3%{?candidate:.%{candidate}}%{?dist} +Release: 0.4%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -211,6 +211,9 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %endif %changelog +* Sat Dec 31 2022 Peter Robinson - 2023.01-0.4.rc4 +- Update PinePhone Pro to latest rev + * Tue Dec 20 2022 Peter Robinson - 2023.01-0.3.rc4 - Update to 2023.01 RC4