2020.04 RC5
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From patchwork Wed Mar 25 18:21:51 2020
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From: <tomcwarren3959@gmail.com>
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To: <u-boot@lists.denx.de>
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
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<twarren@nvidia.com>
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Subject: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
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Date: Wed, 25 Mar 2020 11:21:51 -0700
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Message-ID: <1585160511-15347-1-git-send-email-tomcwarren3959@gmail.com>
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X-Virus-Status: Clean
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||||||
From: Tom Warren <twarren@nvidia.com>
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The Jetson Nano Developer Kit is a Tegra X1-based development board. It
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is similar to Jetson TX1 but it is not pin compatible. It features 4GB
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of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
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used for storage.
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HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
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and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
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Ethernet controller provides onboard network connectivity. NVMe support
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has also been added. Env save is at the end of QSPI (4MB-8K).
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A 40-pin header on the board can be used to extend the capabilities and
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exposed interfaces of the Jetson Nano.
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Signed-off-by: Thierry Reding <treding@nvidia.com>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
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||||||
---
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retry send-email to see if it shows up in Patchwork
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arch/arm/dts/Makefile | 3 +-
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arch/arm/dts/tegra210-p3450-0000.dts | 147 +++++++++++++++++++++++++++++
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arch/arm/mach-tegra/board2.c | 25 +++++
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arch/arm/mach-tegra/tegra210/Kconfig | 7 ++
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board/nvidia/p3450-0000/Kconfig | 12 +++
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board/nvidia/p3450-0000/MAINTAINERS | 6 ++
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board/nvidia/p3450-0000/Makefile | 8 ++
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board/nvidia/p3450-0000/p3450-0000.c | 178 +++++++++++++++++++++++++++++++++++
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configs/p3450-0000_defconfig | 64 +++++++++++++
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include/configs/p3450-0000.h | 46 +++++++++
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10 files changed, 495 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts
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create mode 100644 board/nvidia/p3450-0000/Kconfig
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create mode 100644 board/nvidia/p3450-0000/MAINTAINERS
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create mode 100644 board/nvidia/p3450-0000/Makefile
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create mode 100644 board/nvidia/p3450-0000/p3450-0000.c
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create mode 100644 configs/p3450-0000_defconfig
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create mode 100644 include/configs/p3450-0000.h
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 9c593b2..820ee97 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-e2220-1170.dtb \
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tegra210-p2371-0000.dtb \
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tegra210-p2371-2180.dtb \
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- tegra210-p2571.dtb
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+ tegra210-p2571.dtb \
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+ tegra210-p3450-0000.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-3720-db.dtb \
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diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts
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new file mode 100644
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index 0000000..9ef744a
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--- /dev/null
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+++ b/arch/arm/dts/tegra210-p3450-0000.dts
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@@ -0,0 +1,147 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
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+ */
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+/dts-v1/;
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+
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+#include "tegra210.dtsi"
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+
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+/ {
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+ model = "NVIDIA Jetson Nano Developer Kit";
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+ compatible = "nvidia,p3450-0000", "nvidia,tegra210";
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+
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+ chosen {
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+ stdout-path = &uarta;
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+ };
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+
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+ aliases {
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+ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
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+ i2c0 = "/i2c@7000d000";
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+ i2c2 = "/i2c@7000c400";
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+ i2c3 = "/i2c@7000c500";
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+ i2c4 = "/i2c@7000c700";
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+ mmc0 = "/sdhci@700b0600";
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+ mmc1 = "/sdhci@700b0000";
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+ spi0 = "/spi@70410000";
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+ usb0 = "/usb@7d000000";
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+ };
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+
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+ memory {
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+ reg = <0x0 0x80000000 0x0 0xc0000000>;
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+ };
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+
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+ pcie@1003000 {
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+ status = "okay";
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+
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+ pci@1,0 {
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+ status = "okay";
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+ };
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+
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+ pci@2,0 {
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+ status = "okay";
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+
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+ ethernet@0,0 {
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+ reg = <0x000000 0 0 0 0>;
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+ local-mac-address = [ 00 00 00 00 00 00 ];
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+ };
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+ };
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+ };
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+
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+ serial@70006000 {
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+ status = "okay";
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+ };
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+
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+ padctl@7009f000 {
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+ pinctrl-0 = <&padctl_default>;
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+ pinctrl-names = "default";
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+
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+ padctl_default: pinmux {
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+ xusb {
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+ nvidia,lanes = "otg-1", "otg-2";
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+ nvidia,function = "xusb";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ usb3 {
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+ nvidia,lanes = "pcie-5", "pcie-6";
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+ nvidia,function = "usb3";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ pcie-x1 {
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+ nvidia,lanes = "pcie-0";
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+ nvidia,function = "pcie-x1";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ pcie-x4 {
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+ nvidia,lanes = "pcie-1", "pcie-2",
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+ "pcie-3", "pcie-4";
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+ nvidia,function = "pcie-x4";
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+ nvidia,iddq = <0>;
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+ };
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+
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+ sata {
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+ nvidia,lanes = "sata-0";
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+ nvidia,function = "sata";
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||||||
+ nvidia,iddq = <0>;
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||||||
+ };
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+ };
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+ };
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+
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||||||
+ sdhci@700b0000 {
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||||||
+ status = "okay";
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|
||||||
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
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|
||||||
+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
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|
||||||
+ bus-width = <4>;
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|
||||||
+ };
|
|
||||||
+
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|
||||||
+ sdhci@700b0600 {
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|
||||||
+ status = "okay";
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|
||||||
+ bus-width = <8>;
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|
||||||
+ non-removable;
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||||||
+ };
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|
||||||
+
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|
||||||
+ i2c@7000c400 {
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|
||||||
+ status = "okay";
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|
||||||
+ clock-frequency = <400000>;
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|
||||||
+ };
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|
||||||
+
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|
||||||
+ i2c@7000c500 {
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|
||||||
+ status = "okay";
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|
||||||
+ clock-frequency = <400000>;
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|
||||||
+ };
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|
||||||
+
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|
||||||
+ i2c@7000c700 {
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||||||
+ status = "okay";
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|
||||||
+ clock-frequency = <400000>;
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|
||||||
+ };
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|
||||||
+
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|
||||||
+ i2c@7000d000 {
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||||||
+ status = "okay";
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|
||||||
+ clock-frequency = <400000>;
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||||||
+ };
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||||||
+
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||||||
+ spi@70410000 {
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||||||
+ status = "okay";
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||||||
+ spi-max-frequency = <80000000>;
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||||||
+ };
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||||||
+
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||||||
+ usb@7d000000 {
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||||||
+ status = "okay";
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||||||
+ dr_mode = "peripheral";
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||||||
+ };
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||||||
+
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|
||||||
+ clocks {
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||||||
+ compatible = "simple-bus";
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||||||
+ #address-cells = <1>;
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||||||
+ #size-cells = <0>;
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||||||
+
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||||||
+ clk32k_in: clock@0 {
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||||||
+ compatible = "fixed-clock";
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|
||||||
+ reg = <0>;
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|
||||||
+ #clock-cells = <0>;
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||||||
+ clock-frequency = <32768>;
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||||||
+ };
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||||||
+ };
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||||||
+};
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||||||
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
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index 787ff97..224efc9 100644
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|
||||||
--- a/arch/arm/mach-tegra/board2.c
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+++ b/arch/arm/mach-tegra/board2.c
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||||||
@@ -217,6 +217,31 @@ int board_early_init_f(void)
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arch_timer_init();
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#endif
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|
|
||||||
+#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
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|
||||||
+ /*
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|
||||||
+ * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
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|
||||||
+ * We do this because earlier bootloaders have enabled power to
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||||||
+ * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
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||||||
+ * results in power being back-driven into the SD-card and SDMMC1
|
|
||||||
+ * HW, which is 'bad' as per the HW team.
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|
||||||
+ *
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|
||||||
+ * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
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|
||||||
+ * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
|
|
||||||
+ * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
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|
||||||
+ * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
|
|
||||||
+ * voltage turns off. Since the SDCard voltage is no longer there, the
|
|
||||||
+ * SDMMC CLK/DAT lines are backdriving into what essentially is a
|
|
||||||
+ * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
|
|
||||||
+ *
|
|
||||||
+ * Note that this can probably be removed when we change over to storing
|
|
||||||
+ * all BL components on QSPI on Nano, and U-Boot then becomes the first
|
|
||||||
+ * one to turn on SDMMC1 power. Another fix would be to have CBoot
|
|
||||||
+ * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
|
|
||||||
+ */
|
|
||||||
+ reset_set_enable(PERIPH_ID_SDMMC1, 1);
|
|
||||||
+ clock_set_enable(PERIPH_ID_SDMMC1, 0);
|
|
||||||
+#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
|
|
||||||
+
|
|
||||||
pinmux_init();
|
|
||||||
board_init_uart_f();
|
|
||||||
|
|
||||||
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
|
|
||||||
index 3637473..97ed8e0 100644
|
|
||||||
--- a/arch/arm/mach-tegra/tegra210/Kconfig
|
|
||||||
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
|
|
||||||
@@ -35,6 +35,12 @@ config TARGET_P2571
|
|
||||||
help
|
|
||||||
P2571 is a P2530 married to a P1963 I/O board
|
|
||||||
|
|
||||||
+config TARGET_P3450_0000
|
|
||||||
+ bool "NVIDIA Jetson Nano Developer Kit"
|
|
||||||
+ select BOARD_LATE_INIT
|
|
||||||
+ help
|
|
||||||
+ P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
|
|
||||||
+
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
config SYS_SOC
|
|
||||||
@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
|
|
||||||
source "board/nvidia/p2371-0000/Kconfig"
|
|
||||||
source "board/nvidia/p2371-2180/Kconfig"
|
|
||||||
source "board/nvidia/p2571/Kconfig"
|
|
||||||
+source "board/nvidia/p3450-0000/Kconfig"
|
|
||||||
|
|
||||||
endif
|
|
||||||
diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig
|
|
||||||
new file mode 100644
|
|
||||||
index 0000000..7a08cd8
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/board/nvidia/p3450-0000/Kconfig
|
|
||||||
@@ -0,0 +1,12 @@
|
|
||||||
+if TARGET_P3450_0000
|
|
||||||
+
|
|
||||||
+config SYS_BOARD
|
|
||||||
+ default "p3450-0000"
|
|
||||||
+
|
|
||||||
+config SYS_VENDOR
|
|
||||||
+ default "nvidia"
|
|
||||||
+
|
|
||||||
+config SYS_CONFIG_NAME
|
|
||||||
+ default "p3450-0000"
|
|
||||||
+
|
|
||||||
+endif
|
|
||||||
diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS
|
|
||||||
new file mode 100644
|
|
||||||
index 0000000..4070006
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/board/nvidia/p3450-0000/MAINTAINERS
|
|
||||||
@@ -0,0 +1,6 @@
|
|
||||||
+P3450-0000 BOARD
|
|
||||||
+M: Tom Warren <twarren@nvidia.com>
|
|
||||||
+S: Maintained
|
|
||||||
+F: board/nvidia/p3450-0000/
|
|
||||||
+F: include/configs/p3450-0000.h
|
|
||||||
+F: configs/p3450-0000_defconfig
|
|
||||||
diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile
|
|
||||||
new file mode 100644
|
|
||||||
index 0000000..993c506
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/board/nvidia/p3450-0000/Makefile
|
|
||||||
@@ -0,0 +1,8 @@
|
|
||||||
+#
|
|
||||||
+# (C) Copyright 2018
|
|
||||||
+# NVIDIA Corporation <www.nvidia.com>
|
|
||||||
+#
|
|
||||||
+# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
+#
|
|
||||||
+
|
|
||||||
+obj-y += p3450-0000.o
|
|
||||||
diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c
|
|
||||||
new file mode 100644
|
|
||||||
index 0000000..f4212ab
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/board/nvidia/p3450-0000/p3450-0000.c
|
|
||||||
@@ -0,0 +1,178 @@
|
|
||||||
+// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
+/*
|
|
||||||
+ * (C) Copyright 2018-2019
|
|
||||||
+ * NVIDIA Corporation <www.nvidia.com>
|
|
||||||
+ *
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+#include <common.h>
|
|
||||||
+#include <fdtdec.h>
|
|
||||||
+#include <i2c.h>
|
|
||||||
+#include <linux/libfdt.h>
|
|
||||||
+#include <pca953x.h>
|
|
||||||
+#include <asm/arch-tegra/cboot.h>
|
|
||||||
+#include <asm/arch/gpio.h>
|
|
||||||
+#include <asm/arch/pinmux.h>
|
|
||||||
+#include "../p2571/max77620_init.h"
|
|
||||||
+
|
|
||||||
+void pin_mux_mmc(void)
|
|
||||||
+{
|
|
||||||
+ struct udevice *dev;
|
|
||||||
+ uchar val;
|
|
||||||
+ int ret;
|
|
||||||
+
|
|
||||||
+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
|
|
||||||
+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
|
|
||||||
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
|
||||||
+ if (ret) {
|
|
||||||
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
|
||||||
+ return;
|
|
||||||
+ }
|
|
||||||
+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
|
||||||
+ val = 0xF2;
|
|
||||||
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
|
|
||||||
+ if (ret)
|
|
||||||
+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
|
||||||
+
|
|
||||||
+ /* Disable LDO4 discharge */
|
|
||||||
+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
|
|
||||||
+ if (ret) {
|
|
||||||
+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
|
|
||||||
+ } else {
|
|
||||||
+ val &= ~BIT(1); /* ADE */
|
|
||||||
+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
|
|
||||||
+ if (ret)
|
|
||||||
+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ /* Set MBLPD */
|
|
||||||
+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
|
|
||||||
+ if (ret) {
|
|
||||||
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
|
|
||||||
+ } else {
|
|
||||||
+ val |= BIT(6); /* MBLPD */
|
|
||||||
+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
|
|
||||||
+ if (ret)
|
|
||||||
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
|
|
||||||
+ }
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+#ifdef CONFIG_PCI_TEGRA
|
|
||||||
+int tegra_pcie_board_init(void)
|
|
||||||
+{
|
|
||||||
+ struct udevice *dev;
|
|
||||||
+ uchar val;
|
|
||||||
+ int ret;
|
|
||||||
+
|
|
||||||
+ /* Turn on MAX77620 LDO1 to 1.05V for PEX power */
|
|
||||||
+ debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
|
|
||||||
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
|
||||||
+ if (ret) {
|
|
||||||
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
|
||||||
+ return -1;
|
|
||||||
+ }
|
|
||||||
+ /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
|
||||||
+ val = 0xCA;
|
|
||||||
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
|
|
||||||
+ if (ret)
|
|
||||||
+ printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+#endif /* PCI */
|
|
||||||
+
|
|
||||||
+static void ft_mac_address_setup(void *fdt)
|
|
||||||
+{
|
|
||||||
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
|
|
||||||
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
|
|
||||||
+ const char *path;
|
|
||||||
+ int offset, err;
|
|
||||||
+
|
|
||||||
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
|
|
||||||
+ if (err < 0)
|
|
||||||
+ memset(local_mac, 0, ETH_ALEN);
|
|
||||||
+
|
|
||||||
+ path = fdt_get_alias(fdt, "ethernet");
|
|
||||||
+ if (!path)
|
|
||||||
+ return;
|
|
||||||
+
|
|
||||||
+ debug("ethernet alias found: %s\n", path);
|
|
||||||
+
|
|
||||||
+ offset = fdt_path_offset(fdt, path);
|
|
||||||
+ if (offset < 0) {
|
|
||||||
+ printf("ethernet alias points to absent node %s\n", path);
|
|
||||||
+ return;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ if (is_valid_ethaddr(local_mac)) {
|
|
||||||
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
|
|
||||||
+ ETH_ALEN);
|
|
||||||
+ if (!err)
|
|
||||||
+ debug("Local MAC address set: %pM\n", local_mac);
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
|
|
||||||
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
|
|
||||||
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
|
|
||||||
+ ETH_ALEN);
|
|
||||||
+ if (!err)
|
|
||||||
+ debug("MAC address set: %pM\n", mac);
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
|
|
||||||
+{
|
|
||||||
+ struct fdt_memory fb;
|
|
||||||
+ int err;
|
|
||||||
+
|
|
||||||
+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
|
|
||||||
+ if (err < 0) {
|
|
||||||
+ if (err != -FDT_ERR_NOTFOUND)
|
|
||||||
+ printf("failed to get carveout for %s: %d\n", node,
|
|
||||||
+ err);
|
|
||||||
+
|
|
||||||
+ return err;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
|
|
||||||
+ &fb);
|
|
||||||
+ if (err < 0) {
|
|
||||||
+ printf("failed to set carveout for %s: %d\n", node, err);
|
|
||||||
+ return err;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+static void ft_carveout_setup(void *fdt)
|
|
||||||
+{
|
|
||||||
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
|
|
||||||
+ static const char * const nodes[] = {
|
|
||||||
+ "/host1x@50000000/dc@54200000",
|
|
||||||
+ "/host1x@50000000/dc@54240000",
|
|
||||||
+ };
|
|
||||||
+ unsigned int i;
|
|
||||||
+ int err;
|
|
||||||
+
|
|
||||||
+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
|
|
||||||
+ printf("copying carveout for %s...\n", nodes[i]);
|
|
||||||
+
|
|
||||||
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
|
|
||||||
+ if (err < 0) {
|
|
||||||
+ if (err != -FDT_ERR_NOTFOUND)
|
|
||||||
+ printf("failed to copy carveout for %s: %d\n",
|
|
||||||
+ nodes[i], err);
|
|
||||||
+
|
|
||||||
+ continue;
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
+int ft_board_setup(void *fdt, bd_t *bd)
|
|
||||||
+{
|
|
||||||
+ ft_mac_address_setup(fdt);
|
|
||||||
+ ft_carveout_setup(fdt);
|
|
||||||
+
|
|
||||||
+ return 0;
|
|
||||||
+}
|
|
||||||
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
|
|
||||||
new file mode 100644
|
|
||||||
index 0000000..c861d13
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/configs/p3450-0000_defconfig
|
|
||||||
@@ -0,0 +1,64 @@
|
|
||||||
+CONFIG_ARM=y
|
|
||||||
+CONFIG_TEGRA=y
|
|
||||||
+CONFIG_SYS_TEXT_BASE=0x80080000
|
|
||||||
+CONFIG_TEGRA210=y
|
|
||||||
+CONFIG_TARGET_P3450_0000=y
|
|
||||||
+CONFIG_NR_DRAM_BANKS=2
|
|
||||||
+CONFIG_OF_SYSTEM_SETUP=y
|
|
||||||
+CONFIG_OF_BOARD_SETUP=y
|
|
||||||
+CONFIG_CONSOLE_MUX=y
|
|
||||||
+CONFIG_SYS_STDIO_DEREGISTER=y
|
|
||||||
+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
|
|
||||||
+# CONFIG_CMD_IMI is not set
|
|
||||||
+CONFIG_CMD_DFU=y
|
|
||||||
+# CONFIG_CMD_FLASH is not set
|
|
||||||
+CONFIG_CMD_GPIO=y
|
|
||||||
+CONFIG_CMD_I2C=y
|
|
||||||
+CONFIG_CMD_MMC=y
|
|
||||||
+CONFIG_CMD_PCI=y
|
|
||||||
+CONFIG_CMD_SF=y
|
|
||||||
+CONFIG_CMD_SPI=y
|
|
||||||
+CONFIG_CMD_USB=y
|
|
||||||
+CONFIG_CMD_USB_MASS_STORAGE=y
|
|
||||||
+# CONFIG_CMD_SETEXPR is not set
|
|
||||||
+# CONFIG_CMD_NFS is not set
|
|
||||||
+CONFIG_CMD_EXT4_WRITE=y
|
|
||||||
+CONFIG_OF_LIVE=y
|
|
||||||
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
|
|
||||||
+CONFIG_DFU_MMC=y
|
|
||||||
+CONFIG_DFU_RAM=y
|
|
||||||
+CONFIG_DFU_SF=y
|
|
||||||
+CONFIG_SYS_I2C_TEGRA=y
|
|
||||||
+CONFIG_SPI_FLASH=y
|
|
||||||
+CONFIG_SPI_FLASH_MACRONIX=y
|
|
||||||
+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
|
|
||||||
+CONFIG_SF_DEFAULT_MODE=0
|
|
||||||
+CONFIG_SF_DEFAULT_SPEED=24000000
|
|
||||||
+CONFIG_RTL8169=y
|
|
||||||
+CONFIG_PCI=y
|
|
||||||
+CONFIG_DM_PCI=y
|
|
||||||
+CONFIG_DM_PCI_COMPAT=y
|
|
||||||
+CONFIG_PCI_TEGRA=y
|
|
||||||
+CONFIG_SYS_NS16550=y
|
|
||||||
+CONFIG_TEGRA114_SPI=y
|
|
||||||
+CONFIG_TEGRA210_QSPI=y
|
|
||||||
+CONFIG_USB=y
|
|
||||||
+CONFIG_DM_USB=y
|
|
||||||
+CONFIG_USB_EHCI_HCD=y
|
|
||||||
+CONFIG_USB_EHCI_TEGRA=y
|
|
||||||
+CONFIG_USB_GADGET=y
|
|
||||||
+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
|
|
||||||
+CONFIG_USB_GADGET_VENDOR_NUM=0x0955
|
|
||||||
+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a
|
|
||||||
+CONFIG_CI_UDC=y
|
|
||||||
+CONFIG_USB_GADGET_DOWNLOAD=y
|
|
||||||
+CONFIG_USB_HOST_ETHER=y
|
|
||||||
+CONFIG_USB_ETHER_ASIX=y
|
|
||||||
+# CONFIG_ENV_IS_IN_MMC is not set
|
|
||||||
+CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|
||||||
+CONFIG_ENV_SIZE=0x2000
|
|
||||||
+CONFIG_ENV_SECT_SIZE=0x1000
|
|
||||||
+CONFIG_ENV_OFFSET=0xFFFFE000
|
|
||||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
|
||||||
+CONFIG_DISABLE_SDMMC1_EARLY=y
|
|
||||||
+CONFIG_NVME=y
|
|
||||||
diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
|
|
||||||
new file mode 100644
|
|
||||||
index 0000000..7f05beb
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/include/configs/p3450-0000.h
|
|
||||||
@@ -0,0 +1,46 @@
|
|
||||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
+/*
|
|
||||||
+ * (C) Copyright 2018-2019 NVIDIA Corporation.
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+#ifndef _P3450_0000_H
|
|
||||||
+#define _P3450_0000_H
|
|
||||||
+
|
|
||||||
+#include <linux/sizes.h>
|
|
||||||
+
|
|
||||||
+#include "tegra210-common.h"
|
|
||||||
+
|
|
||||||
+/* High-level configuration options */
|
|
||||||
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000"
|
|
||||||
+
|
|
||||||
+/* Board-specific serial config */
|
|
||||||
+#define CONFIG_TEGRA_ENABLE_UARTA
|
|
||||||
+
|
|
||||||
+/* Only MMC/PXE/DHCP for now, add USB back in later when supported */
|
|
||||||
+#define BOOT_TARGET_DEVICES(func) \
|
|
||||||
+ func(MMC, mmc, 1) \
|
|
||||||
+ func(MMC, mmc, 0) \
|
|
||||||
+ func(PXE, pxe, na) \
|
|
||||||
+ func(DHCP, dhcp, na)
|
|
||||||
+
|
|
||||||
+/* Environment at end of QSPI, in the VER partition */
|
|
||||||
+#define CONFIG_ENV_SPI_MAX_HZ 48000000
|
|
||||||
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
|
||||||
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
|
|
||||||
+
|
|
||||||
+#define CONFIG_PREBOOT
|
|
||||||
+
|
|
||||||
+#define BOARD_EXTRA_ENV_SETTINGS \
|
|
||||||
+ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
|
|
||||||
+ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
|
|
||||||
+ "source ${scriptaddr}; " \
|
|
||||||
+ "fi\0"
|
|
||||||
+
|
|
||||||
+/* General networking support */
|
|
||||||
+#include "tegra-common-usb-gadget.h"
|
|
||||||
+#include "tegra-common-post.h"
|
|
||||||
+
|
|
||||||
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
|
|
||||||
+#define COUNTER_FREQUENCY 19200000
|
|
||||||
+
|
|
||||||
+#endif /* _P3450_0000_H */
|
|
|
@ -1,130 +1,3 @@
|
||||||
From patchwork Thu Mar 26 22:20:43 2020
|
|
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|
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|
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|
|
||||||
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <vishruthj@nvidia.com>
|
|
||||||
Subject: [PATCH 1/3] ARM: tegra: p2771-0000: enable PIE relocation
|
|
||||||
Date: Thu, 26 Mar 2020 15:20:43 -0700
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|
||||||
From: Vishruth <vishruthj@nvidia.com>
|
|
||||||
|
|
||||||
U-Boot is configured to build as position independent executable. Enable
|
|
||||||
relocation of RELA section required to work with different load
|
|
||||||
addresses.
|
|
||||||
|
|
||||||
Signed-off-by: Vishruth <vishruthj@nvidia.com>
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
configs/p2771-0000-000_defconfig | 1 +
|
|
||||||
configs/p2771-0000-500_defconfig | 1 +
|
|
||||||
2 files changed, 2 insertions(+)
|
|
||||||
|
|
||||||
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
|
|
||||||
index 06f12e2..e347a77 100644
|
|
||||||
--- a/configs/p2771-0000-000_defconfig
|
|
||||||
+++ b/configs/p2771-0000-000_defconfig
|
|
||||||
@@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_DM_USB=y
|
|
||||||
+CONFIG_POSITION_INDEPENDENT=y
|
|
||||||
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
|
|
||||||
index 1a14a92..0803b26 100644
|
|
||||||
--- a/configs/p2771-0000-500_defconfig
|
|
||||||
+++ b/configs/p2771-0000-500_defconfig
|
|
||||||
@@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_DM_USB=y
|
|
||||||
+CONFIG_POSITION_INDEPENDENT=y
|
|
||||||
|
|
||||||
From patchwork Thu Mar 26 22:20:44 2020
|
From patchwork Thu Mar 26 22:20:44 2020
|
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MIME-Version: 1.0
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|
@ -245,150 +118,3 @@ index 25a6ed4..36cc726 100644
|
||||||
char *prop; /* property */
|
char *prop; /* property */
|
||||||
int nodeoffset; /* node offset from libfdt */
|
int nodeoffset; /* node offset from libfdt */
|
||||||
|
|
||||||
From patchwork Thu Mar 26 22:20:45 2020
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|
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Subject: [PATCH 3/3] ARM: tegra: p2371-2180: add I2C nodes to DT
|
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|
||||||
X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
|
|
||||||
X-Virus-Status: Clean
|
|
||||||
|
|
||||||
From: Stephen Warren <swarren@nvidia.com>
|
|
||||||
|
|
||||||
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
|
|
||||||
camera board EEPROM, etc. With this change, you can now probe all I2C devices
|
|
||||||
on a TX1 board.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
arch/arm/dts/tegra210-p2371-2180.dts | 18 ++++++++++++++++++
|
|
||||||
1 file changed, 18 insertions(+)
|
|
||||||
|
|
||||||
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts
|
|
||||||
index c2f497c..d982b5f 100644
|
|
||||||
--- a/arch/arm/dts/tegra210-p2371-2180.dts
|
|
||||||
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
|
|
||||||
@@ -12,6 +12,9 @@
|
|
||||||
|
|
||||||
aliases {
|
|
||||||
i2c0 = "/i2c@7000d000";
|
|
||||||
+ i2c2 = "/i2c@7000c400";
|
|
||||||
+ i2c3 = "/i2c@7000c500";
|
|
||||||
+ i2c5 = "/i2c@546c0c00";
|
|
||||||
mmc0 = "/sdhci@700b0600";
|
|
||||||
mmc1 = "/sdhci@700b0000";
|
|
||||||
usb0 = "/usb@7d000000";
|
|
||||||
@@ -33,6 +36,11 @@
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
+ i2c@546c0c00 {
|
|
||||||
+ status = "okay";
|
|
||||||
+ clock-frequency = <400000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
padctl@7009f000 {
|
|
||||||
pinctrl-0 = <&padctl_default>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
@@ -85,6 +93,16 @@
|
|
||||||
non-removable;
|
|
||||||
};
|
|
||||||
|
|
||||||
+ i2c@7000c400 {
|
|
||||||
+ status = "okay";
|
|
||||||
+ clock-frequency = <400000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ i2c@7000c500 {
|
|
||||||
+ status = "okay";
|
|
||||||
+ clock-frequency = <400000>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
i2c@7000d000 {
|
|
||||||
status = "okay";
|
|
||||||
clock-frequency = <400000>;
|
|
||||||
|
|
|
@ -1,461 +0,0 @@
|
||||||
From patchwork Thu Mar 26 22:30:21 2020
|
|
||||||
Content-Type: text/plain; charset="utf-8"
|
|
||||||
MIME-Version: 1.0
|
|
||||||
Content-Transfer-Encoding: 7bit
|
|
||||||
X-Patchwork-Submitter: Tom Warren <tomcwarren3959@gmail.com>
|
|
||||||
X-Patchwork-Id: 1262385
|
|
||||||
X-Patchwork-Delegate: twarren@nvidia.com
|
|
||||||
Return-Path: <u-boot-bounces@lists.denx.de>
|
|
||||||
X-Original-To: incoming@patchwork.ozlabs.org
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|
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Delivered-To: patchwork-incoming@bilbo.ozlabs.org
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|
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Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized)
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|
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smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61;
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|
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(No client certificate requested)
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|
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|
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|
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|
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|
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|
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X-PGP-Universal: processed;
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by hqpgpgate102.nvidia.com on Thu, 26 Mar 2020 15:30:34 -0700
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|
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|
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id <B5e7d2d090026>; Thu, 26 Mar 2020 15:30:33 -0700
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|
||||||
From: <tomcwarren3959@gmail.com>
|
|
||||||
To: <u-boot@lists.denx.de>
|
|
||||||
CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <jh80.chung@samsung.com>
|
|
||||||
Subject: [PATCH 1/2] mmc: t210: Add autocal and tap/trim updates for SDMMC1/3
|
|
||||||
Date: Thu, 26 Mar 2020 15:30:21 -0700
|
|
||||||
Message-ID: <1585261822-3420-2-git-send-email-tomcwarren3959@gmail.com>
|
|
||||||
X-Mailer: git-send-email 1.8.2.1.610.g562af5b
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|
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In-Reply-To: <1585261822-3420-1-git-send-email-tomcwarren3959@gmail.com>
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|
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References: <1585261822-3420-1-git-send-email-tomcwarren3959@gmail.com>
|
|
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|
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X-BeenThere: u-boot@lists.denx.de
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|
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|
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|
||||||
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|
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|
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|
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|
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|
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|
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X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de
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|
||||||
X-Virus-Status: Clean
|
|
||||||
|
|
||||||
From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
|
|
||||||
autocal values need to be set to condition the signals correctly before
|
|
||||||
talking to the SD-card. This is the same as what's being done in CBoot,
|
|
||||||
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
|
|
||||||
init, so needs to be repeated here. Also set autocal and tap/trim for
|
|
||||||
SDMMC3, although no T210 boards use it for SD-card at this time.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
Changes for v2:
|
|
||||||
- Added clocks.h include for TEGRA30 to fix T30 32-bit builds
|
|
||||||
|
|
||||||
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 +++++--
|
|
||||||
drivers/mmc/tegra_mmc.c | 84 ++++++++++++++++++++++++++---
|
|
||||||
2 files changed, 92 insertions(+), 12 deletions(-)
|
|
||||||
|
|
||||||
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
|
||||||
index a2b6f63..a8bfa46 100644
|
|
||||||
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
|
||||||
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
|
||||||
@@ -2,7 +2,7 @@
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2009 SAMSUNG Electronics
|
|
||||||
* Minkyu Kang <mk7.kang@samsung.com>
|
|
||||||
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
|
|
||||||
+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __TEGRA_MMC_H_
|
|
||||||
@@ -52,7 +52,7 @@ struct tegra_mmc {
|
|
||||||
unsigned char admaerr; /* offset 54h */
|
|
||||||
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
|
|
||||||
unsigned long admaaddr; /* offset 58h-5Fh */
|
|
||||||
- unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
|
|
||||||
+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
|
|
||||||
unsigned short slotintstatus; /* offset FCh */
|
|
||||||
unsigned short hcver; /* HOST Version */
|
|
||||||
unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
|
|
||||||
@@ -127,11 +127,23 @@ struct tegra_mmc {
|
|
||||||
|
|
||||||
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
|
|
||||||
|
|
||||||
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
|
|
||||||
+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
|
|
||||||
#define MEMCOMP_PADCTRL_VREF 7
|
|
||||||
-#define AUTO_CAL_ENABLED (1 << 29)
|
|
||||||
+#define AUTO_CAL_ENABLE (1 << 29)
|
|
||||||
+#if defined(CONFIG_TEGRA210)
|
|
||||||
+#define AUTO_CAL_ACTIVE (1 << 31)
|
|
||||||
+#define AUTO_CAL_START (1 << 31)
|
|
||||||
+#define AUTO_CAL_PD_OFFSET (0x7D << 8)
|
|
||||||
+#define AUTO_CAL_PU_OFFSET (0 << 0)
|
|
||||||
+#define IO_TRIM_BYPASS_MASK (1 << 2)
|
|
||||||
+#define TRIM_VAL_SHIFT 24
|
|
||||||
+#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
|
|
||||||
+#define TAP_VAL_SHIFT 16
|
|
||||||
+#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
|
|
||||||
+#else
|
|
||||||
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
|
|
||||||
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
|
|
||||||
+#endif
|
|
||||||
|
|
||||||
#endif /* __ASSEMBLY__ */
|
|
||||||
#endif /* __TEGRA_MMC_H_ */
|
|
||||||
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
|
|
||||||
index f022e93..73ac58c 100644
|
|
||||||
--- a/drivers/mmc/tegra_mmc.c
|
|
||||||
+++ b/drivers/mmc/tegra_mmc.c
|
|
||||||
@@ -3,7 +3,7 @@
|
|
||||||
* (C) Copyright 2009 SAMSUNG Electronics
|
|
||||||
* Minkyu Kang <mk7.kang@samsung.com>
|
|
||||||
* Jaehoon Chung <jh80.chung@samsung.com>
|
|
||||||
- * Portions Copyright 2011-2016 NVIDIA Corporation
|
|
||||||
+ * Portions Copyright 2011-2019 NVIDIA Corporation
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <bouncebuf.h>
|
|
||||||
@@ -15,6 +15,9 @@
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/arch-tegra/tegra_mmc.h>
|
|
||||||
#include <linux/err.h>
|
|
||||||
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
|
|
||||||
+#include <asm/arch/clock.h>
|
|
||||||
+#endif
|
|
||||||
|
|
||||||
struct tegra_mmc_plat {
|
|
||||||
struct mmc_config cfg;
|
|
||||||
@@ -30,6 +33,7 @@ struct tegra_mmc_priv {
|
|
||||||
struct gpio_desc wp_gpio; /* Write Protect GPIO */
|
|
||||||
unsigned int version; /* SDHCI spec. version */
|
|
||||||
unsigned int clock; /* Current clock (MHz) */
|
|
||||||
+ int mmc_id; /* peripheral id */
|
|
||||||
};
|
|
||||||
|
|
||||||
static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
|
|
||||||
@@ -446,16 +450,19 @@ static int tegra_mmc_set_ios(struct udevice *dev)
|
|
||||||
|
|
||||||
static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
|
|
||||||
{
|
|
||||||
-#if defined(CONFIG_TEGRA30)
|
|
||||||
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
|
|
||||||
u32 val;
|
|
||||||
+ u16 clk_con;
|
|
||||||
+ int timeout;
|
|
||||||
+ int id = priv->mmc_id;
|
|
||||||
|
|
||||||
- debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
|
|
||||||
+ debug("%s: sdmmc address = %p, id = %d\n", __func__,
|
|
||||||
+ priv->reg, id);
|
|
||||||
|
|
||||||
/* Set the pad drive strength for SDMMC1 or 3 only */
|
|
||||||
- if (priv->reg != (void *)0x78000000 &&
|
|
||||||
- priv->reg != (void *)0x78000400) {
|
|
||||||
+ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
|
|
||||||
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
|
|
||||||
- __func__);
|
|
||||||
+ __func__);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
@@ -464,11 +471,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
|
|
||||||
val |= MEMCOMP_PADCTRL_VREF;
|
|
||||||
writel(val, &priv->reg->sdmemcmppadctl);
|
|
||||||
|
|
||||||
+ /* Disable SD Clock Enable before running auto-cal as per TRM */
|
|
||||||
+ clk_con = readw(&priv->reg->clkcon);
|
|
||||||
+ debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
|
|
||||||
+ clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
|
|
||||||
+ writew(clk_con, &priv->reg->clkcon);
|
|
||||||
+
|
|
||||||
val = readl(&priv->reg->autocalcfg);
|
|
||||||
val &= 0xFFFF0000;
|
|
||||||
- val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
|
|
||||||
+ val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
|
|
||||||
writel(val, &priv->reg->autocalcfg);
|
|
||||||
-#endif
|
|
||||||
+ val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
|
|
||||||
+ writel(val, &priv->reg->autocalcfg);
|
|
||||||
+ debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
|
|
||||||
+ udelay(1);
|
|
||||||
+ timeout = 100; /* 10 mSec max (100*100uS) */
|
|
||||||
+ do {
|
|
||||||
+ val = readl(&priv->reg->autocalsts);
|
|
||||||
+ udelay(100);
|
|
||||||
+ } while ((val & AUTO_CAL_ACTIVE) && --timeout);
|
|
||||||
+ val = readl(&priv->reg->autocalsts);
|
|
||||||
+ debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
|
|
||||||
+ __func__, val, timeout);
|
|
||||||
+
|
|
||||||
+ /* Re-enable SD Clock Enable when auto-cal is done */
|
|
||||||
+ clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
|
|
||||||
+ writew(clk_con, &priv->reg->clkcon);
|
|
||||||
+ clk_con = readw(&priv->reg->clkcon);
|
|
||||||
+ debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
|
|
||||||
+
|
|
||||||
+ if (timeout == 0) {
|
|
||||||
+ printf("%s: Warning: Autocal timed out!\n", __func__);
|
|
||||||
+ /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+#if defined(CONFIG_TEGRA210)
|
|
||||||
+ u32 tap_value, trim_value;
|
|
||||||
+
|
|
||||||
+ /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
|
|
||||||
+ val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
|
|
||||||
+ val &= IO_TRIM_BYPASS_MASK;
|
|
||||||
+ if (id == PERIPH_ID_SDMMC1) {
|
|
||||||
+ tap_value = 4; /* default */
|
|
||||||
+ if (val)
|
|
||||||
+ tap_value = 3;
|
|
||||||
+ trim_value = 2;
|
|
||||||
+ } else { /* SDMMC3 */
|
|
||||||
+ tap_value = 3;
|
|
||||||
+ trim_value = 3;
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ val = readl(&priv->reg->venclkctl);
|
|
||||||
+ val &= ~TRIM_VAL_MASK;
|
|
||||||
+ val |= (trim_value << TRIM_VAL_SHIFT);
|
|
||||||
+ val &= ~TAP_VAL_MASK;
|
|
||||||
+ val |= (tap_value << TAP_VAL_SHIFT);
|
|
||||||
+ writel(val, &priv->reg->venclkctl);
|
|
||||||
+ debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
|
|
||||||
+#endif /* T210 */
|
|
||||||
+#endif /* T30/T210 */
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
|
|
||||||
@@ -514,6 +575,13 @@ static int tegra_mmc_init(struct udevice *dev)
|
|
||||||
unsigned int mask;
|
|
||||||
debug(" tegra_mmc_init called\n");
|
|
||||||
|
|
||||||
+#if defined(CONFIG_TEGRA210)
|
|
||||||
+ priv->mmc_id = clock_decode_periph_id(dev);
|
|
||||||
+ if (priv->mmc_id == PERIPH_ID_NONE) {
|
|
||||||
+ printf("%s: Missing/invalid peripheral ID\n", __func__);
|
|
||||||
+ return -EINVAL;
|
|
||||||
+ }
|
|
||||||
+#endif
|
|
||||||
tegra_mmc_reset(priv, mmc);
|
|
||||||
|
|
||||||
#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
|
|
||||||
|
|
||||||
From patchwork Thu Mar 26 22:30:22 2020
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|
|
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X-Patchwork-Id: 1262386
|
|
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <jh80.chung@samsung.com>
|
|
||||||
Subject: [PATCH 2/2] mmc: t210: Fix 'bad' SD-card clock when doing 400KHz
|
|
||||||
card detect
|
|
||||||
Date: Thu, 26 Mar 2020 15:30:22 -0700
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Message-ID: <1585261822-3420-3-git-send-email-tomcwarren3959@gmail.com>
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|
||||||
From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
According to the HW team, for some reason the normal clock select code
|
|
||||||
picks what appears to be a perfectly valid 375KHz SD card clock, based
|
|
||||||
on the CAR clock source and SDMMC1 controller register settings (CAR =
|
|
||||||
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
|
|
||||||
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
|
|
||||||
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
|
|
||||||
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
|
|
||||||
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
|
|
||||||
T210 when the requested clock is <= 400KHz. Note that as far as I can
|
|
||||||
tell, the other requests for clocks in the Tegra MMC driver result in
|
|
||||||
valid SD clocks.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
Changes for v2:
|
|
||||||
- None
|
|
||||||
|
|
||||||
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 +-
|
|
||||||
drivers/mmc/tegra_mmc.c | 18 ++++++++++++++++++
|
|
||||||
2 files changed, 19 insertions(+), 1 deletion(-)
|
|
||||||
|
|
||||||
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
|
||||||
index a8bfa46..70dcf4a 100644
|
|
||||||
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
|
||||||
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
|
||||||
@@ -130,9 +130,9 @@ struct tegra_mmc {
|
|
||||||
/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
|
|
||||||
#define MEMCOMP_PADCTRL_VREF 7
|
|
||||||
#define AUTO_CAL_ENABLE (1 << 29)
|
|
||||||
-#if defined(CONFIG_TEGRA210)
|
|
||||||
#define AUTO_CAL_ACTIVE (1 << 31)
|
|
||||||
#define AUTO_CAL_START (1 << 31)
|
|
||||||
+#if defined(CONFIG_TEGRA210)
|
|
||||||
#define AUTO_CAL_PD_OFFSET (0x7D << 8)
|
|
||||||
#define AUTO_CAL_PU_OFFSET (0 << 0)
|
|
||||||
#define IO_TRIM_BYPASS_MASK (1 << 2)
|
|
||||||
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
|
|
||||||
index 73ac58c..03110ba 100644
|
|
||||||
--- a/drivers/mmc/tegra_mmc.c
|
|
||||||
+++ b/drivers/mmc/tegra_mmc.c
|
|
||||||
@@ -376,6 +376,24 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
|
|
||||||
|
|
||||||
rate = clk_set_rate(&priv->clk, clock);
|
|
||||||
div = (rate + clock - 1) / clock;
|
|
||||||
+
|
|
||||||
+#if defined(CONFIG_TEGRA210)
|
|
||||||
+ if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
|
|
||||||
+ /* clock_adjust_periph_pll_div() chooses a 'bad' clock
|
|
||||||
+ * on SDMMC1 T210, so skip it here and force a clock
|
|
||||||
+ * that's been spec'd in the table in the TRM for
|
|
||||||
+ * card-detect (400KHz).
|
|
||||||
+ */
|
|
||||||
+ uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
|
|
||||||
+ CLOCK_ID_PERIPH, 24727273, NULL);
|
|
||||||
+ div = 62;
|
|
||||||
+
|
|
||||||
+ debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
|
|
||||||
+ __func__, effective_rate, div, clock);
|
|
||||||
+ } else
|
|
||||||
+ clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, clock,
|
|
||||||
+ &div);
|
|
||||||
+#endif
|
|
||||||
debug("div = %d\n", div);
|
|
||||||
|
|
||||||
writew(0, &priv->reg->clkcon);
|
|
|
@ -1,116 +0,0 @@
|
||||||
From patchwork Thu Mar 26 21:59:01 2020
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|
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|
|
||||||
X-Patchwork-Id: 1262368
|
|
||||||
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|
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From: <tomcwarren3959@gmail.com>
|
|
||||||
To: <u-boot@lists.denx.de>
|
|
||||||
CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <jagan@amarulasolutions.com>
|
|
||||||
Subject: [PATCH] mtd: spi: Add Macronix MX25U3235F device
|
|
||||||
Date: Thu, 26 Mar 2020 14:59:01 -0700
|
|
||||||
Message-ID: <1585259941-28879-1-git-send-email-tomcwarren3959@gmail.com>
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|
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|
|
||||||
From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
Add Macronix MX25U3235F flash device description.
|
|
||||||
This is a 4MiB part.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
drivers/mtd/spi/spi-nor-ids.c | 1 +
|
|
||||||
1 file changed, 1 insertion(+)
|
|
||||||
|
|
||||||
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
|
|
||||||
index 973b6f8..abdf560 100644
|
|
||||||
--- a/drivers/mtd/spi/spi-nor-ids.c
|
|
||||||
+++ b/drivers/mtd/spi/spi-nor-ids.c
|
|
||||||
@@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = {
|
|
||||||
{ INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
|
||||||
{ INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
|
|
||||||
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
|
|
||||||
+ { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
|
|
||||||
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
|
||||||
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
|
|
||||||
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
|
|
|
@ -1,310 +0,0 @@
|
||||||
From patchwork Thu Mar 26 22:59:13 2020
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From: <tomcwarren3959@gmail.com>
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To: <u-boot@lists.denx.de>
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <joe.hershberger@ni.com>
|
|
||||||
Subject: [PATCH 1/2] net: rt8169: WAR for DHCP not getting IP after kernel
|
|
||||||
boot/reboot
|
|
||||||
Date: Thu, 26 Mar 2020 15:59:13 -0700
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From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
This is a WAR for DHCP failure after rebooting from the L4T kernel. The
|
|
||||||
r8169.c kernel driver is setting bit 19 of the rt816x HW register 0xF0,
|
|
||||||
which goes by FuncEvent and MISC in various driver source/datasheets.
|
|
||||||
That bit is called RxDv_Gated_En in the r8169.c kernel driver. Clear it
|
|
||||||
here at the end of probe to ensure that U-Boot can get an IP assigned
|
|
||||||
via DHCP.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
drivers/net/rtl8169.c | 16 ++++++++++++++++
|
|
||||||
1 file changed, 16 insertions(+)
|
|
||||||
|
|
||||||
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
|
|
||||||
index 5ccdfdd..ff89e28 100644
|
|
||||||
--- a/drivers/net/rtl8169.c
|
|
||||||
+++ b/drivers/net/rtl8169.c
|
|
||||||
@@ -237,6 +237,9 @@ enum RTL8169_register_content {
|
|
||||||
|
|
||||||
/*_TBICSRBit*/
|
|
||||||
TBILinkOK = 0x02000000,
|
|
||||||
+
|
|
||||||
+ /* FuncEvent/Misc */
|
|
||||||
+ RxDv_Gated_En = 0x80000,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct {
|
|
||||||
@@ -1207,6 +1210,19 @@ static int rtl8169_eth_probe(struct udevice *dev)
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
+ /*
|
|
||||||
+ * WAR for DHCP failure after rebooting from kernel.
|
|
||||||
+ * Clear RxDv_Gated_En bit which was set by kernel driver.
|
|
||||||
+ * Without this, U-Boot can't get an IP via DHCP.
|
|
||||||
+ * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
|
|
||||||
+ * the r8169.c kernel driver.
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+ u32 val = RTL_R32(FuncEvent);
|
|
||||||
+ debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
|
|
||||||
+ val &= ~RxDv_Gated_En;
|
|
||||||
+ RTL_W32(FuncEvent, val);
|
|
||||||
+
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
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From patchwork Thu Mar 26 22:59:14 2020
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From: <tomcwarren3959@gmail.com>
|
|
||||||
To: <u-boot@lists.denx.de>
|
|
||||||
CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <joe.hershberger@ni.com>
|
|
||||||
Subject: [PATCH 2/2] tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all
|
|
||||||
Jetson boards
|
|
||||||
Date: Thu, 26 Mar 2020 15:59:14 -0700
|
|
||||||
Message-ID: <1585263554-10258-3-git-send-email-tomcwarren3959@gmail.com>
|
|
||||||
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|
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|
|
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|
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|
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|
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|
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|
||||||
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|
|
||||||
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|
|
||||||
X-Virus-Status: Clean
|
|
||||||
|
|
||||||
From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
This allows the user to set $serverip in the environment before
|
|
||||||
executing a DHCP request. If they do, U-Boot will use that IP rather
|
|
||||||
than using the IP in the DHCP response.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
Acked-by: Stephen Warren <swarren@nvidia.com>
|
|
||||||
---
|
|
||||||
configs/e2220-1170_defconfig | 1 +
|
|
||||||
configs/p2371-0000_defconfig | 1 +
|
|
||||||
configs/p2371-2180_defconfig | 1 +
|
|
||||||
configs/p2571_defconfig | 1 +
|
|
||||||
configs/p2771-0000-000_defconfig | 1 +
|
|
||||||
configs/p2771-0000-500_defconfig | 1 +
|
|
||||||
6 files changed, 6 insertions(+)
|
|
||||||
|
|
||||||
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
|
|
||||||
index 1639040..951ed1d 100644
|
|
||||||
--- a/configs/e2220-1170_defconfig
|
|
||||||
+++ b/configs/e2220-1170_defconfig
|
|
||||||
@@ -43,3 +43,4 @@ CONFIG_CI_UDC=y
|
|
||||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
|
||||||
CONFIG_USB_HOST_ETHER=y
|
|
||||||
CONFIG_USB_ETHER_ASIX=y
|
|
||||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
|
||||||
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
|
|
||||||
index 2070199..7081719 100644
|
|
||||||
--- a/configs/p2371-0000_defconfig
|
|
||||||
+++ b/configs/p2371-0000_defconfig
|
|
||||||
@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
|
|
||||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
|
||||||
CONFIG_USB_HOST_ETHER=y
|
|
||||||
CONFIG_USB_ETHER_ASIX=y
|
|
||||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
|
||||||
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
|
|
||||||
index 8c808ae..c70217c 100644
|
|
||||||
--- a/configs/p2371-2180_defconfig
|
|
||||||
+++ b/configs/p2371-2180_defconfig
|
|
||||||
@@ -52,3 +52,4 @@ CONFIG_CI_UDC=y
|
|
||||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
|
||||||
CONFIG_USB_HOST_ETHER=y
|
|
||||||
CONFIG_USB_ETHER_ASIX=y
|
|
||||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
|
||||||
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
|
|
||||||
index 721c5c5..43c24b8 100644
|
|
||||||
--- a/configs/p2571_defconfig
|
|
||||||
+++ b/configs/p2571_defconfig
|
|
||||||
@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
|
|
||||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
|
||||||
CONFIG_USB_HOST_ETHER=y
|
|
||||||
CONFIG_USB_ETHER_ASIX=y
|
|
||||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
|
||||||
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
|
|
||||||
index e347a77..8bf8419 100644
|
|
||||||
--- a/configs/p2771-0000-000_defconfig
|
|
||||||
+++ b/configs/p2771-0000-000_defconfig
|
|
||||||
@@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_DM_USB=y
|
|
||||||
CONFIG_POSITION_INDEPENDENT=y
|
|
||||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
|
||||||
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
|
|
||||||
index 0803b26..1f40333 100644
|
|
||||||
--- a/configs/p2771-0000-500_defconfig
|
|
||||||
+++ b/configs/p2771-0000-500_defconfig
|
|
||||||
@@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_DM_USB=y
|
|
||||||
CONFIG_POSITION_INDEPENDENT=y
|
|
||||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
|
|
@ -1,453 +0,0 @@
|
||||||
From patchwork Thu Mar 26 22:42:00 2020
|
|
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Content-Type: text/plain; charset="utf-8"
|
|
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|
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X-Patchwork-Submitter: Tom Warren <tomcwarren3959@gmail.com>
|
|
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X-Patchwork-Id: 1262404
|
|
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X-Patchwork-Delegate: twarren@nvidia.com
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From: <tomcwarren3959@gmail.com>
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To: <u-boot@lists.denx.de>
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|
||||||
CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <jagan@amarulasolutions.com>
|
|
||||||
Subject: [PATCH 1/3] qspi: t210: Fix claim_bus's use of the wrong bus/device
|
|
||||||
Date: Thu, 26 Mar 2020 15:42:00 -0700
|
|
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Message-ID: <1585262522-6127-2-git-send-email-tomcwarren3959@gmail.com>
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|
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From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
claim_bus() is passed a udevice *dev, which is the bus device's parent.
|
|
||||||
In this driver, claim_bus assumed it was the bus, which caused the
|
|
||||||
'priv' info pointer to be wrong, and periph_id was incorrect. This in
|
|
||||||
turn caused the periph clock call to assign the wrong clock (PLLM
|
|
||||||
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
|
|
||||||
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
|
|
||||||
working w/this errant clock, but it was moot as QSPI wasn't active
|
|
||||||
unless you probed it, and that wasn't happening until I posted a patch
|
|
||||||
to enable env save to QSPI for Nano (coming soon).
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
Changes in v2:
|
|
||||||
- None
|
|
||||||
|
|
||||||
drivers/spi/tegra210_qspi.c | 6 ++++--
|
|
||||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
|
||||||
|
|
||||||
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
|
|
||||||
index d82ecaa..2a77126 100644
|
|
||||||
--- a/drivers/spi/tegra210_qspi.c
|
|
||||||
+++ b/drivers/spi/tegra210_qspi.c
|
|
||||||
@@ -2,7 +2,8 @@
|
|
||||||
/*
|
|
||||||
* NVIDIA Tegra210 QSPI controller driver
|
|
||||||
*
|
|
||||||
- * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
|
|
||||||
+ * (C) Copyright 2015-2019 NVIDIA Corporation <www.nvidia.com>
|
|
||||||
+ *
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
@@ -137,8 +138,9 @@ static int tegra210_qspi_probe(struct udevice *bus)
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
-static int tegra210_qspi_claim_bus(struct udevice *bus)
|
|
||||||
+static int tegra210_qspi_claim_bus(struct udevice *dev)
|
|
||||||
{
|
|
||||||
+ struct udevice *bus = dev->parent;
|
|
||||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
|
||||||
struct qspi_regs *regs = priv->regs;
|
|
||||||
|
|
||||||
|
|
||||||
From patchwork Thu Mar 26 22:42:01 2020
|
|
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X-Patchwork-Id: 1262405
|
|
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
|
||||||
<twarren@nvidia.com>, <jagan@amarulasolutions.com>
|
|
||||||
Subject: [PATCH 2/3] qspi: t210: Fix QSPI clock and tap delays
|
|
||||||
Date: Thu, 26 Mar 2020 15:42:01 -0700
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Message-ID: <1585262522-6127-3-git-send-email-tomcwarren3959@gmail.com>
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||||||
From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
When claim_bus was setting the clock, it reset the QSPI controller,
|
|
||||||
which wipes out any tap delays set by previous bootloaders (nvtboot,
|
|
||||||
CBoot for example on Nano). Instead of doing that in claim_bus, which
|
|
||||||
gets called a lot, moved clock setting to probe(), and set tap delays
|
|
||||||
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
|
|
||||||
save works reliably again.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
Changes in v2:
|
|
||||||
- None
|
|
||||||
|
|
||||||
drivers/spi/tegra210_qspi.c | 19 ++++++++++++-------
|
|
||||||
1 file changed, 12 insertions(+), 7 deletions(-)
|
|
||||||
|
|
||||||
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
|
|
||||||
index 2a77126..4284ea9 100644
|
|
||||||
--- a/drivers/spi/tegra210_qspi.c
|
|
||||||
+++ b/drivers/spi/tegra210_qspi.c
|
|
||||||
@@ -42,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
#define QSPI_CMD1_BITLEN_SHIFT 0
|
|
||||||
|
|
||||||
/* COMMAND2 */
|
|
||||||
-#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
|
|
||||||
-#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
|
|
||||||
-#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
|
|
||||||
-#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
|
|
||||||
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
|
|
||||||
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
|
|
||||||
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
|
|
||||||
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
|
|
||||||
|
|
||||||
/* TRANSFER STATUS */
|
|
||||||
#define QSPI_XFER_STS_RDY BIT(30)
|
|
||||||
@@ -127,14 +127,22 @@ static int tegra210_qspi_probe(struct udevice *bus)
|
|
||||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
|
||||||
|
|
||||||
priv->regs = (struct qspi_regs *)plat->base;
|
|
||||||
+ struct qspi_regs *regs = priv->regs;
|
|
||||||
|
|
||||||
priv->last_transaction_us = timer_get_us();
|
|
||||||
priv->freq = plat->frequency;
|
|
||||||
priv->periph_id = plat->periph_id;
|
|
||||||
|
|
||||||
+ debug("%s: Freq = %u, id = %d\n", __func__, priv->freq, priv->periph_id);
|
|
||||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
|
||||||
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
|
|
||||||
|
|
||||||
+ /* Set tap delays here, clock change above resets QSPI controller */
|
|
||||||
+ u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
|
|
||||||
+ (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
|
|
||||||
+ writel(reg, ®s->command2);
|
|
||||||
+ debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2));
|
|
||||||
+
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
@@ -144,9 +152,6 @@ static int tegra210_qspi_claim_bus(struct udevice *dev)
|
|
||||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
|
||||||
struct qspi_regs *regs = priv->regs;
|
|
||||||
|
|
||||||
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
|
||||||
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
|
|
||||||
-
|
|
||||||
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
|
|
||||||
|
|
||||||
/* Set master mode and sw controlled CS */
|
|
||||||
|
|
||||||
From patchwork Thu Mar 26 22:42:02 2020
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MIME-Version: 1.0
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X-Patchwork-Submitter: Tom Warren <tomcwarren3959@gmail.com>
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X-Patchwork-Id: 1262406
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
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<twarren@nvidia.com>, <jagan@amarulasolutions.com>
|
|
||||||
Subject: [PATCH 3/3] qspi: t210: Use dev_read calls to get FDT data like
|
|
||||||
base, freq
|
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Date: Thu, 26 Mar 2020 15:42:02 -0700
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|
||||||
From: Tom Warren <twarren@nvidia.com>
|
|
||||||
|
|
||||||
This Tegra QSPI driver hadn't been brought up to date with how
|
|
||||||
DM drivers are fetching data from the FDT now, and was pulling
|
|
||||||
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
|
|
||||||
to work the same way it does in the tegra114 SPI driver, using
|
|
||||||
dev_read_ functions.
|
|
||||||
|
|
||||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
||||||
---
|
|
||||||
Changes in v2:
|
|
||||||
- New
|
|
||||||
|
|
||||||
drivers/spi/tegra210_qspi.c | 10 ++++------
|
|
||||||
1 file changed, 4 insertions(+), 6 deletions(-)
|
|
||||||
|
|
||||||
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
|
|
||||||
index 4284ea9..466d572 100644
|
|
||||||
--- a/drivers/spi/tegra210_qspi.c
|
|
||||||
+++ b/drivers/spi/tegra210_qspi.c
|
|
||||||
@@ -2,7 +2,7 @@
|
|
||||||
/*
|
|
||||||
* NVIDIA Tegra210 QSPI controller driver
|
|
||||||
*
|
|
||||||
- * (C) Copyright 2015-2019 NVIDIA Corporation <www.nvidia.com>
|
|
||||||
+ * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
@@ -97,10 +97,8 @@ struct tegra210_qspi_priv {
|
|
||||||
static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
|
|
||||||
{
|
|
||||||
struct tegra_spi_platdata *plat = bus->platdata;
|
|
||||||
- const void *blob = gd->fdt_blob;
|
|
||||||
- int node = dev_of_offset(bus);
|
|
||||||
|
|
||||||
- plat->base = devfdt_get_addr(bus);
|
|
||||||
+ plat->base = dev_read_addr(bus);
|
|
||||||
plat->periph_id = clock_decode_periph_id(bus);
|
|
||||||
|
|
||||||
if (plat->periph_id == PERIPH_ID_NONE) {
|
|
||||||
@@ -110,9 +108,9 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Use 500KHz as a suitable default */
|
|
||||||
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
|
||||||
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
|
|
||||||
500000);
|
|
||||||
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
|
|
||||||
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
|
|
||||||
"spi-deactivate-delay", 0);
|
|
||||||
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
|
|
||||||
__func__, plat->base, plat->periph_id, plat->frequency,
|
|
2
sources
2
sources
|
@ -1 +1 @@
|
||||||
SHA512 (u-boot-2020.04-rc4.tar.bz2) = 0e8acc06aae5e009122d06fa1cf89d2a428796bfd44b71907493e6c83480b71949e03cb432ebcd78df90fd1fbf21a1d586bb174ad90257b5e64ac41661f974b3
|
SHA512 (u-boot-2020.04-rc5.tar.bz2) = 4fed5a45e9ebfc931cb4f06bbdb9ec1a477ed7dff902b8e9013fc7e41a78e4448749b88c450ee5ce62b6756031ec250f11e9afbea01bab2702ac6e9bb22f4ad2
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,8 +1,8 @@
|
||||||
%global candidate rc4
|
%global candidate rc5
|
||||||
|
|
||||||
Name: uboot-tools
|
Name: uboot-tools
|
||||||
Version: 2020.04
|
Version: 2020.04
|
||||||
Release: 0.6%{?candidate:.%{candidate}}%{?dist}
|
Release: 0.7%{?candidate:.%{candidate}}%{?dist}
|
||||||
Summary: U-Boot utilities
|
Summary: U-Boot utilities
|
||||||
License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
|
License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
|
||||||
URL: http://www.denx.de/wiki/U-Boot
|
URL: http://www.denx.de/wiki/U-Boot
|
||||||
|
@ -27,16 +27,9 @@ Patch6: dragonboard-fixes.patch
|
||||||
Patch7: efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch
|
Patch7: efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch
|
||||||
|
|
||||||
# Tegra improvements
|
# Tegra improvements
|
||||||
Patch10: mtd-spi-Add-Macronix-MX25U3235F-device.patch
|
Patch10: Misc-fixes-for-Tegra.patch
|
||||||
Patch11: Misc-fixes-for-Tegra.patch
|
Patch11: arm-tegra-define-fdtfile-option-for-distro-boot.patch
|
||||||
Patch12: mmc-t210-fix-autocal-and-400KHz-clock.patch
|
Patch12: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch
|
||||||
Patch13: qspi-t210-fix-claim_bus-and-clock-tap-delays.patch
|
|
||||||
Patch14: net-tegra-Misc-network-fixes.patch
|
|
||||||
Patch15: t210-miscellaneous-patches.patch
|
|
||||||
# http://patchwork.ozlabs.org/patch/1261582/
|
|
||||||
Patch16: ARM-tegra-Add-NVIDIA-Jetson-Nano.patch
|
|
||||||
Patch17: arm-tegra-define-fdtfile-option-for-distro-boot.patch
|
|
||||||
Patch18: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch
|
|
||||||
|
|
||||||
# Rockchips improvements
|
# Rockchips improvements
|
||||||
Patch20: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch
|
Patch20: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch
|
||||||
|
@ -262,6 +255,9 @@ cp -p board/warp7/README builds/docs/README.warp7
|
||||||
%endif
|
%endif
|
||||||
|
|
||||||
%changelog
|
%changelog
|
||||||
|
* Tue Apr 7 2020 Peter Robinson <pbrobinson@fedoraproject.org> 2020.04-0.7-rc5
|
||||||
|
- 2020.04 RC5
|
||||||
|
|
||||||
* Tue Mar 31 2020 Peter Robinson <pbrobinson@fedoraproject.org> 2020.04-0.6-rc4
|
* Tue Mar 31 2020 Peter Robinson <pbrobinson@fedoraproject.org> 2020.04-0.6-rc4
|
||||||
- 2020.04 RC4
|
- 2020.04 RC4
|
||||||
- Updates for NVIDIA Jetson platforms
|
- Updates for NVIDIA Jetson platforms
|
||||||
|
|
Loading…
Reference in New Issue