From d8c86a078c240ecb97f9dbf2ad8fa00f59520ee6 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 7 Apr 2020 09:49:18 +0100 Subject: [PATCH] 2020.04 RC5 --- ARM-tegra-Add-NVIDIA-Jetson-Nano.patch | 710 ------ Misc-fixes-for-Tegra.patch | 274 --- mmc-t210-fix-autocal-and-400KHz-clock.patch | 461 ---- mtd-spi-Add-Macronix-MX25U3235F-device.patch | 116 - net-tegra-Misc-network-fixes.patch | 310 --- ...0-fix-claim_bus-and-clock-tap-delays.patch | 453 ---- sources | 2 +- t210-miscellaneous-patches.patch | 2026 ----------------- uboot-tools.spec | 20 +- 9 files changed, 9 insertions(+), 4363 deletions(-) delete mode 100644 ARM-tegra-Add-NVIDIA-Jetson-Nano.patch delete mode 100644 mmc-t210-fix-autocal-and-400KHz-clock.patch delete mode 100644 mtd-spi-Add-Macronix-MX25U3235F-device.patch delete mode 100644 net-tegra-Misc-network-fixes.patch delete mode 100644 qspi-t210-fix-claim_bus-and-clock-tap-delays.patch delete mode 100644 t210-miscellaneous-patches.patch diff --git a/ARM-tegra-Add-NVIDIA-Jetson-Nano.patch b/ARM-tegra-Add-NVIDIA-Jetson-Nano.patch deleted file mode 100644 index 9ac9e94..0000000 --- a/ARM-tegra-Add-NVIDIA-Jetson-Nano.patch +++ /dev/null @@ -1,710 +0,0 @@ -From patchwork Wed Mar 25 18:21:51 2020 -Content-Type: text/plain; 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Wed, 25 Mar 2020 11:22:07 -0700 -From: -To: -CC: , , , - -Subject: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support -Date: Wed, 25 Mar 2020 11:21:51 -0700 -Message-ID: <1585160511-15347-1-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -The Jetson Nano Developer Kit is a Tegra X1-based development board. It -is similar to Jetson TX1 but it is not pin compatible. It features 4GB -of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot -used for storage. - -HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 -and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI -Ethernet controller provides onboard network connectivity. NVMe support -has also been added. Env save is at the end of QSPI (4MB-8K). - -A 40-pin header on the board can be used to extend the capabilities and -exposed interfaces of the Jetson Nano. - -Signed-off-by: Thierry Reding -Signed-off-by: Tom Warren ---- -retry send-email to see if it shows up in Patchwork - - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/tegra210-p3450-0000.dts | 147 +++++++++++++++++++++++++++++ - arch/arm/mach-tegra/board2.c | 25 +++++ - arch/arm/mach-tegra/tegra210/Kconfig | 7 ++ - board/nvidia/p3450-0000/Kconfig | 12 +++ - board/nvidia/p3450-0000/MAINTAINERS | 6 ++ - board/nvidia/p3450-0000/Makefile | 8 ++ - board/nvidia/p3450-0000/p3450-0000.c | 178 +++++++++++++++++++++++++++++++++++ - configs/p3450-0000_defconfig | 64 +++++++++++++ - include/configs/p3450-0000.h | 46 +++++++++ - 10 files changed, 495 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts - create mode 100644 board/nvidia/p3450-0000/Kconfig - create mode 100644 board/nvidia/p3450-0000/MAINTAINERS - create mode 100644 board/nvidia/p3450-0000/Makefile - create mode 100644 board/nvidia/p3450-0000/p3450-0000.c - create mode 100644 configs/p3450-0000_defconfig - create mode 100644 include/configs/p3450-0000.h - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 9c593b2..820ee97 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ - tegra210-e2220-1170.dtb \ - tegra210-p2371-0000.dtb \ - tegra210-p2371-2180.dtb \ -- tegra210-p2571.dtb -+ tegra210-p2571.dtb \ -+ tegra210-p3450-0000.dtb - - dtb-$(CONFIG_ARCH_MVEBU) += \ - armada-3720-db.dtb \ -diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts -new file mode 100644 -index 0000000..9ef744a ---- /dev/null -+++ b/arch/arm/dts/tegra210-p3450-0000.dts -@@ -0,0 +1,147 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2019-2020 NVIDIA Corporation -+ */ -+/dts-v1/; -+ -+#include "tegra210.dtsi" -+ -+/ { -+ model = "NVIDIA Jetson Nano Developer Kit"; -+ compatible = "nvidia,p3450-0000", "nvidia,tegra210"; -+ -+ chosen { -+ stdout-path = &uarta; -+ }; -+ -+ aliases { -+ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; -+ i2c0 = "/i2c@7000d000"; -+ i2c2 = "/i2c@7000c400"; -+ i2c3 = "/i2c@7000c500"; -+ i2c4 = "/i2c@7000c700"; -+ mmc0 = "/sdhci@700b0600"; -+ mmc1 = "/sdhci@700b0000"; -+ spi0 = "/spi@70410000"; -+ usb0 = "/usb@7d000000"; -+ }; -+ -+ memory { -+ reg = <0x0 0x80000000 0x0 0xc0000000>; -+ }; -+ -+ pcie@1003000 { -+ status = "okay"; -+ -+ pci@1,0 { -+ status = "okay"; -+ }; -+ -+ pci@2,0 { -+ status = "okay"; -+ -+ ethernet@0,0 { -+ reg = <0x000000 0 0 0 0>; -+ local-mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ }; -+ }; -+ -+ serial@70006000 { -+ status = "okay"; -+ }; -+ -+ padctl@7009f000 { -+ pinctrl-0 = <&padctl_default>; -+ pinctrl-names = "default"; -+ -+ padctl_default: pinmux { -+ xusb { -+ nvidia,lanes = "otg-1", "otg-2"; -+ nvidia,function = "xusb"; -+ nvidia,iddq = <0>; -+ }; -+ -+ usb3 { -+ nvidia,lanes = "pcie-5", "pcie-6"; -+ nvidia,function = "usb3"; -+ nvidia,iddq = <0>; -+ }; -+ -+ pcie-x1 { -+ nvidia,lanes = "pcie-0"; -+ nvidia,function = "pcie-x1"; -+ nvidia,iddq = <0>; -+ }; -+ -+ pcie-x4 { -+ nvidia,lanes = "pcie-1", "pcie-2", -+ "pcie-3", "pcie-4"; -+ nvidia,function = "pcie-x4"; -+ nvidia,iddq = <0>; -+ }; -+ -+ sata { -+ nvidia,lanes = "sata-0"; -+ nvidia,function = "sata"; -+ nvidia,iddq = <0>; -+ }; -+ }; -+ }; -+ -+ sdhci@700b0000 { -+ status = "okay"; -+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; -+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; -+ bus-width = <4>; -+ }; -+ -+ sdhci@700b0600 { -+ status = "okay"; -+ bus-width = <8>; -+ non-removable; -+ }; -+ -+ i2c@7000c400 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ i2c@7000c500 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ i2c@7000c700 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ i2c@7000d000 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ spi@70410000 { -+ status = "okay"; -+ spi-max-frequency = <80000000>; -+ }; -+ -+ usb@7d000000 { -+ status = "okay"; -+ dr_mode = "peripheral"; -+ }; -+ -+ clocks { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clk32k_in: clock@0 { -+ compatible = "fixed-clock"; -+ reg = <0>; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ }; -+ }; -+}; -diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c -index 787ff97..224efc9 100644 ---- a/arch/arm/mach-tegra/board2.c -+++ b/arch/arm/mach-tegra/board2.c -@@ -217,6 +217,31 @@ int board_early_init_f(void) - arch_timer_init(); - #endif - -+#if defined(CONFIG_DISABLE_SDMMC1_EARLY) -+ /* -+ * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT. -+ * We do this because earlier bootloaders have enabled power to -+ * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init() -+ * results in power being back-driven into the SD-card and SDMMC1 -+ * HW, which is 'bad' as per the HW team. -+ * -+ * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in -+ * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT -+ * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off -+ * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard -+ * voltage turns off. Since the SDCard voltage is no longer there, the -+ * SDMMC CLK/DAT lines are backdriving into what essentially is a -+ * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V" -+ * -+ * Note that this can probably be removed when we change over to storing -+ * all BL components on QSPI on Nano, and U-Boot then becomes the first -+ * one to turn on SDMMC1 power. Another fix would be to have CBoot -+ * disable power/gate SDMMC1 off before handing off to U-Boot/kernel. -+ */ -+ reset_set_enable(PERIPH_ID_SDMMC1, 1); -+ clock_set_enable(PERIPH_ID_SDMMC1, 0); -+#endif /* CONFIG_DISABLE_SDMMC1_EARLY */ -+ - pinmux_init(); - board_init_uart_f(); - -diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig -index 3637473..97ed8e0 100644 ---- a/arch/arm/mach-tegra/tegra210/Kconfig -+++ b/arch/arm/mach-tegra/tegra210/Kconfig -@@ -35,6 +35,12 @@ config TARGET_P2571 - help - P2571 is a P2530 married to a P1963 I/O board - -+config TARGET_P3450_0000 -+ bool "NVIDIA Jetson Nano Developer Kit" -+ select BOARD_LATE_INIT -+ help -+ P3450-0000 is a P3448 CPU board married to a P3449 I/O board. -+ - endchoice - - config SYS_SOC -@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig" - source "board/nvidia/p2371-0000/Kconfig" - source "board/nvidia/p2371-2180/Kconfig" - source "board/nvidia/p2571/Kconfig" -+source "board/nvidia/p3450-0000/Kconfig" - - endif -diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig -new file mode 100644 -index 0000000..7a08cd8 ---- /dev/null -+++ b/board/nvidia/p3450-0000/Kconfig -@@ -0,0 +1,12 @@ -+if TARGET_P3450_0000 -+ -+config SYS_BOARD -+ default "p3450-0000" -+ -+config SYS_VENDOR -+ default "nvidia" -+ -+config SYS_CONFIG_NAME -+ default "p3450-0000" -+ -+endif -diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS -new file mode 100644 -index 0000000..4070006 ---- /dev/null -+++ b/board/nvidia/p3450-0000/MAINTAINERS -@@ -0,0 +1,6 @@ -+P3450-0000 BOARD -+M: Tom Warren -+S: Maintained -+F: board/nvidia/p3450-0000/ -+F: include/configs/p3450-0000.h -+F: configs/p3450-0000_defconfig -diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile -new file mode 100644 -index 0000000..993c506 ---- /dev/null -+++ b/board/nvidia/p3450-0000/Makefile -@@ -0,0 +1,8 @@ -+# -+# (C) Copyright 2018 -+# NVIDIA Corporation -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += p3450-0000.o -diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c -new file mode 100644 -index 0000000..f4212ab ---- /dev/null -+++ b/board/nvidia/p3450-0000/p3450-0000.c -@@ -0,0 +1,178 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 -+ * NVIDIA Corporation -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "../p2571/max77620_init.h" -+ -+void pin_mux_mmc(void) -+{ -+ struct udevice *dev; -+ uchar val; -+ int ret; -+ -+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ -+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); -+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); -+ if (ret) { -+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__); -+ return; -+ } -+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ -+ val = 0xF2; -+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -+ -+ /* Disable LDO4 discharge */ -+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); -+ if (ret) { -+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); -+ } else { -+ val &= ~BIT(1); /* ADE */ -+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); -+ } -+ -+ /* Set MBLPD */ -+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); -+ if (ret) { -+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); -+ } else { -+ val |= BIT(6); /* MBLPD */ -+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); -+ } -+} -+ -+#ifdef CONFIG_PCI_TEGRA -+int tegra_pcie_board_init(void) -+{ -+ struct udevice *dev; -+ uchar val; -+ int ret; -+ -+ /* Turn on MAX77620 LDO1 to 1.05V for PEX power */ -+ debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__); -+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); -+ if (ret) { -+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__); -+ return -1; -+ } -+ /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ -+ val = 0xCA; -+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1); -+ if (ret) -+ printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret); -+ -+ return 0; -+} -+#endif /* PCI */ -+ -+static void ft_mac_address_setup(void *fdt) -+{ -+ const void *cboot_fdt = (const void *)cboot_boot_x0; -+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; -+ const char *path; -+ int offset, err; -+ -+ err = cboot_get_ethaddr(cboot_fdt, local_mac); -+ if (err < 0) -+ memset(local_mac, 0, ETH_ALEN); -+ -+ path = fdt_get_alias(fdt, "ethernet"); -+ if (!path) -+ return; -+ -+ debug("ethernet alias found: %s\n", path); -+ -+ offset = fdt_path_offset(fdt, path); -+ if (offset < 0) { -+ printf("ethernet alias points to absent node %s\n", path); -+ return; -+ } -+ -+ if (is_valid_ethaddr(local_mac)) { -+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, -+ ETH_ALEN); -+ if (!err) -+ debug("Local MAC address set: %pM\n", local_mac); -+ } -+ -+ if (eth_env_get_enetaddr("ethaddr", mac)) { -+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) { -+ err = fdt_setprop(fdt, offset, "mac-address", mac, -+ ETH_ALEN); -+ if (!err) -+ debug("MAC address set: %pM\n", mac); -+ } -+ } -+} -+ -+static int ft_copy_carveout(void *dst, const void *src, const char *node) -+{ -+ struct fdt_memory fb; -+ int err; -+ -+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); -+ if (err < 0) { -+ if (err != -FDT_ERR_NOTFOUND) -+ printf("failed to get carveout for %s: %d\n", node, -+ err); -+ -+ return err; -+ } -+ -+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", -+ &fb); -+ if (err < 0) { -+ printf("failed to set carveout for %s: %d\n", node, err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static void ft_carveout_setup(void *fdt) -+{ -+ const void *cboot_fdt = (const void *)cboot_boot_x0; -+ static const char * const nodes[] = { -+ "/host1x@50000000/dc@54200000", -+ "/host1x@50000000/dc@54240000", -+ }; -+ unsigned int i; -+ int err; -+ -+ for (i = 0; i < ARRAY_SIZE(nodes); i++) { -+ printf("copying carveout for %s...\n", nodes[i]); -+ -+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); -+ if (err < 0) { -+ if (err != -FDT_ERR_NOTFOUND) -+ printf("failed to copy carveout for %s: %d\n", -+ nodes[i], err); -+ -+ continue; -+ } -+ } -+} -+ -+int ft_board_setup(void *fdt, bd_t *bd) -+{ -+ ft_mac_address_setup(fdt); -+ ft_carveout_setup(fdt); -+ -+ return 0; -+} -diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig -new file mode 100644 -index 0000000..c861d13 ---- /dev/null -+++ b/configs/p3450-0000_defconfig -@@ -0,0 +1,64 @@ -+CONFIG_ARM=y -+CONFIG_TEGRA=y -+CONFIG_SYS_TEXT_BASE=0x80080000 -+CONFIG_TEGRA210=y -+CONFIG_TARGET_P3450_0000=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_OF_BOARD_SETUP=y -+CONFIG_CONSOLE_MUX=y -+CONFIG_SYS_STDIO_DEREGISTER=y -+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " -+# CONFIG_CMD_IMI is not set -+CONFIG_CMD_DFU=y -+# CONFIG_CMD_FLASH is not set -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_SF=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_SETEXPR is not set -+# CONFIG_CMD_NFS is not set -+CONFIG_CMD_EXT4_WRITE=y -+CONFIG_OF_LIVE=y -+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" -+CONFIG_DFU_MMC=y -+CONFIG_DFU_RAM=y -+CONFIG_DFU_SF=y -+CONFIG_SYS_I2C_TEGRA=y -+CONFIG_SPI_FLASH=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_USE_4K_SECTORS=y -+CONFIG_SF_DEFAULT_MODE=0 -+CONFIG_SF_DEFAULT_SPEED=24000000 -+CONFIG_RTL8169=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_DM_PCI_COMPAT=y -+CONFIG_PCI_TEGRA=y -+CONFIG_SYS_NS16550=y -+CONFIG_TEGRA114_SPI=y -+CONFIG_TEGRA210_QSPI=y -+CONFIG_USB=y -+CONFIG_DM_USB=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_TEGRA=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" -+CONFIG_USB_GADGET_VENDOR_NUM=0x0955 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a -+CONFIG_CI_UDC=y -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+# CONFIG_ENV_IS_IN_MMC is not set -+CONFIG_ENV_IS_IN_SPI_FLASH=y -+CONFIG_ENV_SIZE=0x2000 -+CONFIG_ENV_SECT_SIZE=0x1000 -+CONFIG_ENV_OFFSET=0xFFFFE000 -+CONFIG_BOOTP_PREFER_SERVERIP=y -+CONFIG_DISABLE_SDMMC1_EARLY=y -+CONFIG_NVME=y -diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h -new file mode 100644 -index 0000000..7f05beb ---- /dev/null -+++ b/include/configs/p3450-0000.h -@@ -0,0 +1,46 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * (C) Copyright 2018-2019 NVIDIA Corporation. -+ */ -+ -+#ifndef _P3450_0000_H -+#define _P3450_0000_H -+ -+#include -+ -+#include "tegra210-common.h" -+ -+/* High-level configuration options */ -+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" -+ -+/* Board-specific serial config */ -+#define CONFIG_TEGRA_ENABLE_UARTA -+ -+/* Only MMC/PXE/DHCP for now, add USB back in later when supported */ -+#define BOOT_TARGET_DEVICES(func) \ -+ func(MMC, mmc, 1) \ -+ func(MMC, mmc, 0) \ -+ func(PXE, pxe, na) \ -+ func(DHCP, dhcp, na) -+ -+/* Environment at end of QSPI, in the VER partition */ -+#define CONFIG_ENV_SPI_MAX_HZ 48000000 -+#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -+#define CONFIG_SPI_FLASH_SIZE (4 << 20) -+ -+#define CONFIG_PREBOOT -+ -+#define BOARD_EXTRA_ENV_SETTINGS \ -+ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \ -+ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \ -+ "source ${scriptaddr}; " \ -+ "fi\0" -+ -+/* General networking support */ -+#include "tegra-common-usb-gadget.h" -+#include "tegra-common-post.h" -+ -+/* Crystal is 38.4MHz. clk_m runs at half that rate */ -+#define COUNTER_FREQUENCY 19200000 -+ -+#endif /* _P3450_0000_H */ diff --git a/Misc-fixes-for-Tegra.patch b/Misc-fixes-for-Tegra.patch index 355bbae..2c3223d 100644 --- a/Misc-fixes-for-Tegra.patch +++ b/Misc-fixes-for-Tegra.patch @@ -1,130 +1,3 @@ -From patchwork Thu Mar 26 22:20:43 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262377 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Thu, 26 Mar 2020 15:20:48 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 1/3] ARM: tegra: p2771-0000: enable PIE relocation -Date: Thu, 26 Mar 2020 15:20:43 -0700 -Message-ID: <1585261245-1740-2-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585261245-1740-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585261245-1740-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Vishruth - -U-Boot is configured to build as position independent executable. Enable -relocation of RELA section required to work with different load -addresses. - -Signed-off-by: Vishruth -Signed-off-by: Tom Warren ---- - configs/p2771-0000-000_defconfig | 1 + - configs/p2771-0000-500_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig -index 06f12e2..e347a77 100644 ---- a/configs/p2771-0000-000_defconfig -+++ b/configs/p2771-0000-000_defconfig -@@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y - CONFIG_SYS_NS16550=y - CONFIG_USB=y - CONFIG_DM_USB=y -+CONFIG_POSITION_INDEPENDENT=y -diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig -index 1a14a92..0803b26 100644 ---- a/configs/p2771-0000-500_defconfig -+++ b/configs/p2771-0000-500_defconfig -@@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y - CONFIG_SYS_NS16550=y - CONFIG_USB=y - CONFIG_DM_USB=y -+CONFIG_POSITION_INDEPENDENT=y - From patchwork Thu Mar 26 22:20:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 @@ -245,150 +118,3 @@ index 25a6ed4..36cc726 100644 char *prop; /* property */ int nodeoffset; /* node offset from libfdt */ -From patchwork Thu Mar 26 22:20:45 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262379 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pKGB4dynz9sPR - for ; - Fri, 27 Mar 2020 09:21:38 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 3DA5280199; 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-+ i2c2 = "/i2c@7000c400"; -+ i2c3 = "/i2c@7000c500"; -+ i2c5 = "/i2c@546c0c00"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; - usb0 = "/usb@7d000000"; -@@ -33,6 +36,11 @@ - }; - }; - -+ i2c@546c0c00 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ - padctl@7009f000 { - pinctrl-0 = <&padctl_default>; - pinctrl-names = "default"; -@@ -85,6 +93,16 @@ - non-removable; - }; - -+ i2c@7000c400 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ i2c@7000c500 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; diff --git a/mmc-t210-fix-autocal-and-400KHz-clock.patch b/mmc-t210-fix-autocal-and-400KHz-clock.patch deleted file mode 100644 index 622e570..0000000 --- a/mmc-t210-fix-autocal-and-400KHz-clock.patch +++ /dev/null @@ -1,461 +0,0 @@ -From patchwork Thu Mar 26 22:30:21 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262385 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; 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- Thu, 26 Mar 2020 15:30:34 -0700 -X-PGP-Universal: processed; - by hqpgpgate102.nvidia.com on Thu, 26 Mar 2020 15:30:34 -0700 -Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com - (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; - Thu, 26 Mar 2020 22:30:34 +0000 -Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com - (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via - Frontend Transport; Thu, 26 Mar 2020 22:30:34 +0000 -Received: from tom-lt2.nvidia.com (Not Verified[10.2.63.13]) by - rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) - id ; Thu, 26 Mar 2020 15:30:33 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 1/2] mmc: t210: Add autocal and tap/trim updates for SDMMC1/3 -Date: Thu, 26 Mar 2020 15:30:21 -0700 -Message-ID: <1585261822-3420-2-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585261822-3420-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585261822-3420-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and -autocal values need to be set to condition the signals correctly before -talking to the SD-card. This is the same as what's being done in CBoot, -but it gets reset when the SDMMC1 HW is soft-reset during SD driver -init, so needs to be repeated here. Also set autocal and tap/trim for -SDMMC3, although no T210 boards use it for SD-card at this time. - -Signed-off-by: Tom Warren ---- -Changes for v2: - - Added clocks.h include for TEGRA30 to fix T30 32-bit builds - - arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 +++++-- - drivers/mmc/tegra_mmc.c | 84 ++++++++++++++++++++++++++--- - 2 files changed, 92 insertions(+), 12 deletions(-) - -diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h -index a2b6f63..a8bfa46 100644 ---- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h -+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h -@@ -2,7 +2,7 @@ - /* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang -- * Portions Copyright (C) 2011-2012 NVIDIA Corporation -+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation - */ - - #ifndef __TEGRA_MMC_H_ -@@ -52,7 +52,7 @@ struct tegra_mmc { - unsigned char admaerr; /* offset 54h */ - unsigned char res4[3]; /* RESERVED, offset 55h-57h */ - unsigned long admaaddr; /* offset 58h-5Fh */ -- unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ -+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ - unsigned short slotintstatus; /* offset FCh */ - unsigned short hcver; /* HOST Version */ - unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ -@@ -127,11 +127,23 @@ struct tegra_mmc { - - #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) - --/* SDMMC1/3 settings from section 24.6 of T30 TRM */ -+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ - #define MEMCOMP_PADCTRL_VREF 7 --#define AUTO_CAL_ENABLED (1 << 29) -+#define AUTO_CAL_ENABLE (1 << 29) -+#if defined(CONFIG_TEGRA210) -+#define AUTO_CAL_ACTIVE (1 << 31) -+#define AUTO_CAL_START (1 << 31) -+#define AUTO_CAL_PD_OFFSET (0x7D << 8) -+#define AUTO_CAL_PU_OFFSET (0 << 0) -+#define IO_TRIM_BYPASS_MASK (1 << 2) -+#define TRIM_VAL_SHIFT 24 -+#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT) -+#define TAP_VAL_SHIFT 16 -+#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT) -+#else - #define AUTO_CAL_PD_OFFSET (0x70 << 8) - #define AUTO_CAL_PU_OFFSET (0x62 << 0) -+#endif - - #endif /* __ASSEMBLY__ */ - #endif /* __TEGRA_MMC_H_ */ -diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c -index f022e93..73ac58c 100644 ---- a/drivers/mmc/tegra_mmc.c -+++ b/drivers/mmc/tegra_mmc.c -@@ -3,7 +3,7 @@ - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang - * Jaehoon Chung -- * Portions Copyright 2011-2016 NVIDIA Corporation -+ * Portions Copyright 2011-2019 NVIDIA Corporation - */ - - #include -@@ -15,6 +15,9 @@ - #include - #include - #include -+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) -+#include -+#endif - - struct tegra_mmc_plat { - struct mmc_config cfg; -@@ -30,6 +33,7 @@ struct tegra_mmc_priv { - struct gpio_desc wp_gpio; /* Write Protect GPIO */ - unsigned int version; /* SDHCI spec. version */ - unsigned int clock; /* Current clock (MHz) */ -+ int mmc_id; /* peripheral id */ - }; - - static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, -@@ -446,16 +450,19 @@ static int tegra_mmc_set_ios(struct udevice *dev) - - static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) - { --#if defined(CONFIG_TEGRA30) -+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) - u32 val; -+ u16 clk_con; -+ int timeout; -+ int id = priv->mmc_id; - -- debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); -+ debug("%s: sdmmc address = %p, id = %d\n", __func__, -+ priv->reg, id); - - /* Set the pad drive strength for SDMMC1 or 3 only */ -- if (priv->reg != (void *)0x78000000 && -- priv->reg != (void *)0x78000400) { -+ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { - debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", -- __func__); -+ __func__); - return; - } - -@@ -464,11 +471,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) - val |= MEMCOMP_PADCTRL_VREF; - writel(val, &priv->reg->sdmemcmppadctl); - -+ /* Disable SD Clock Enable before running auto-cal as per TRM */ -+ clk_con = readw(&priv->reg->clkcon); -+ debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); -+ clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; -+ writew(clk_con, &priv->reg->clkcon); -+ - val = readl(&priv->reg->autocalcfg); - val &= 0xFFFF0000; -- val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; -+ val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET; - writel(val, &priv->reg->autocalcfg); --#endif -+ val |= AUTO_CAL_START | AUTO_CAL_ENABLE; -+ writel(val, &priv->reg->autocalcfg); -+ debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val); -+ udelay(1); -+ timeout = 100; /* 10 mSec max (100*100uS) */ -+ do { -+ val = readl(&priv->reg->autocalsts); -+ udelay(100); -+ } while ((val & AUTO_CAL_ACTIVE) && --timeout); -+ val = readl(&priv->reg->autocalsts); -+ debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n", -+ __func__, val, timeout); -+ -+ /* Re-enable SD Clock Enable when auto-cal is done */ -+ clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; -+ writew(clk_con, &priv->reg->clkcon); -+ clk_con = readw(&priv->reg->clkcon); -+ debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); -+ -+ if (timeout == 0) { -+ printf("%s: Warning: Autocal timed out!\n", __func__); -+ /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */ -+ } -+ -+#if defined(CONFIG_TEGRA210) -+ u32 tap_value, trim_value; -+ -+ /* Set tap/trim values for SDMMC1/3 @ <48MHz here */ -+ val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */ -+ val &= IO_TRIM_BYPASS_MASK; -+ if (id == PERIPH_ID_SDMMC1) { -+ tap_value = 4; /* default */ -+ if (val) -+ tap_value = 3; -+ trim_value = 2; -+ } else { /* SDMMC3 */ -+ tap_value = 3; -+ trim_value = 3; -+ } -+ -+ val = readl(&priv->reg->venclkctl); -+ val &= ~TRIM_VAL_MASK; -+ val |= (trim_value << TRIM_VAL_SHIFT); -+ val &= ~TAP_VAL_MASK; -+ val |= (tap_value << TAP_VAL_SHIFT); -+ writel(val, &priv->reg->venclkctl); -+ debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val); -+#endif /* T210 */ -+#endif /* T30/T210 */ - } - - static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) -@@ -514,6 +575,13 @@ static int tegra_mmc_init(struct udevice *dev) - unsigned int mask; - debug(" tegra_mmc_init called\n"); - -+#if defined(CONFIG_TEGRA210) -+ priv->mmc_id = clock_decode_periph_id(dev); -+ if (priv->mmc_id == PERIPH_ID_NONE) { -+ printf("%s: Missing/invalid peripheral ID\n", __func__); -+ return -EINVAL; -+ } -+#endif - tegra_mmc_reset(priv, mmc); - - #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK) - -From patchwork Thu Mar 26 22:30:22 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262386 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; 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- Thu, 26 Mar 2020 15:30:35 -0700 -X-PGP-Universal: processed; - by hqpgpgate101.nvidia.com on Thu, 26 Mar 2020 15:30:35 -0700 -Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com - (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; - Thu, 26 Mar 2020 22:30:35 +0000 -Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com - (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via - Frontend Transport; Thu, 26 Mar 2020 22:30:35 +0000 -Received: from tom-lt2.nvidia.com (Not Verified[10.2.63.13]) by - rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) - id ; Thu, 26 Mar 2020 15:30:34 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 2/2] mmc: t210: Fix 'bad' SD-card clock when doing 400KHz - card detect -Date: Thu, 26 Mar 2020 15:30:22 -0700 -Message-ID: <1585261822-3420-3-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585261822-3420-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585261822-3420-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -According to the HW team, for some reason the normal clock select code -picks what appears to be a perfectly valid 375KHz SD card clock, based -on the CAR clock source and SDMMC1 controller register settings (CAR = -408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register -divisor of 16 = 375KHz). But the resulting SD card clock, as measured by -the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the -values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR -clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on -T210 when the requested clock is <= 400KHz. Note that as far as I can -tell, the other requests for clocks in the Tegra MMC driver result in -valid SD clocks. - -Signed-off-by: Tom Warren ---- -Changes for v2: - - None - - arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 +- - drivers/mmc/tegra_mmc.c | 18 ++++++++++++++++++ - 2 files changed, 19 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h -index a8bfa46..70dcf4a 100644 ---- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h -+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h -@@ -130,9 +130,9 @@ struct tegra_mmc { - /* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ - #define MEMCOMP_PADCTRL_VREF 7 - #define AUTO_CAL_ENABLE (1 << 29) --#if defined(CONFIG_TEGRA210) - #define AUTO_CAL_ACTIVE (1 << 31) - #define AUTO_CAL_START (1 << 31) -+#if defined(CONFIG_TEGRA210) - #define AUTO_CAL_PD_OFFSET (0x7D << 8) - #define AUTO_CAL_PU_OFFSET (0 << 0) - #define IO_TRIM_BYPASS_MASK (1 << 2) -diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c -index 73ac58c..03110ba 100644 ---- a/drivers/mmc/tegra_mmc.c -+++ b/drivers/mmc/tegra_mmc.c -@@ -376,6 +376,24 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) - - rate = clk_set_rate(&priv->clk, clock); - div = (rate + clock - 1) / clock; -+ -+#if defined(CONFIG_TEGRA210) -+ if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) { -+ /* clock_adjust_periph_pll_div() chooses a 'bad' clock -+ * on SDMMC1 T210, so skip it here and force a clock -+ * that's been spec'd in the table in the TRM for -+ * card-detect (400KHz). -+ */ -+ uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id, -+ CLOCK_ID_PERIPH, 24727273, NULL); -+ div = 62; -+ -+ debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n", -+ __func__, effective_rate, div, clock); -+ } else -+ clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, clock, -+ &div); -+#endif - debug("div = %d\n", div); - - writew(0, &priv->reg->clkcon); diff --git a/mtd-spi-Add-Macronix-MX25U3235F-device.patch b/mtd-spi-Add-Macronix-MX25U3235F-device.patch deleted file mode 100644 index 117fe28..0000000 --- a/mtd-spi-Add-Macronix-MX25U3235F-device.patch +++ /dev/null @@ -1,116 +0,0 @@ -From patchwork Thu Mar 26 21:59:01 2020 -Content-Type: text/plain; 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Thu, 26 Mar 2020 14:59:00 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH] mtd: spi: Add Macronix MX25U3235F device -Date: Thu, 26 Mar 2020 14:59:01 -0700 -Message-ID: <1585259941-28879-1-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -Add Macronix MX25U3235F flash device description. -This is a 4MiB part. - -Signed-off-by: Tom Warren ---- - drivers/mtd/spi/spi-nor-ids.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c -index 973b6f8..abdf560 100644 ---- a/drivers/mtd/spi/spi-nor-ids.c -+++ b/drivers/mtd/spi/spi-nor-ids.c -@@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = { - { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, - { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, - { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, -+ { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, - { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, - { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, - { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, diff --git a/net-tegra-Misc-network-fixes.patch b/net-tegra-Misc-network-fixes.patch deleted file mode 100644 index d177516..0000000 --- a/net-tegra-Misc-network-fixes.patch +++ /dev/null @@ -1,310 +0,0 @@ -From patchwork Thu Mar 26 22:59:13 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262416 -X-Patchwork-Delegate: joe.hershberger@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pL643S8Tz9sSH - for ; - Fri, 27 Mar 2020 09:59:40 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 95C3581850; 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- spf=fail smtp.mailfrom=tomcwarren3959@gmail.com -Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by - hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) - id ; Thu, 26 Mar 2020 15:57:38 -0700 -Received: from hqmail.nvidia.com ([172.20.161.6]) - by hqpgpgate101.nvidia.com (PGP Universal service); - Thu, 26 Mar 2020 15:59:10 -0700 -X-PGP-Universal: processed; - by hqpgpgate101.nvidia.com on Thu, 26 Mar 2020 15:59:10 -0700 -Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com - (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; - Thu, 26 Mar 2020 22:59:09 +0000 -Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com - (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 - via Frontend Transport; Thu, 26 Mar 2020 22:59:10 +0000 -Received: from tom-lt2.nvidia.com (Not Verified[10.2.63.13]) by - hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) - id ; Thu, 26 Mar 2020 15:59:09 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 1/2] net: rt8169: WAR for DHCP not getting IP after kernel - boot/reboot -Date: Thu, 26 Mar 2020 15:59:13 -0700 -Message-ID: <1585263554-10258-2-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585263554-10258-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585263554-10258-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -This is a WAR for DHCP failure after rebooting from the L4T kernel. The -r8169.c kernel driver is setting bit 19 of the rt816x HW register 0xF0, -which goes by FuncEvent and MISC in various driver source/datasheets. -That bit is called RxDv_Gated_En in the r8169.c kernel driver. Clear it -here at the end of probe to ensure that U-Boot can get an IP assigned -via DHCP. - -Signed-off-by: Tom Warren ---- - drivers/net/rtl8169.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c -index 5ccdfdd..ff89e28 100644 ---- a/drivers/net/rtl8169.c -+++ b/drivers/net/rtl8169.c -@@ -237,6 +237,9 @@ enum RTL8169_register_content { - - /*_TBICSRBit*/ - TBILinkOK = 0x02000000, -+ -+ /* FuncEvent/Misc */ -+ RxDv_Gated_En = 0x80000, - }; - - static struct { -@@ -1207,6 +1210,19 @@ static int rtl8169_eth_probe(struct udevice *dev) - return ret; - } - -+ /* -+ * WAR for DHCP failure after rebooting from kernel. -+ * Clear RxDv_Gated_En bit which was set by kernel driver. -+ * Without this, U-Boot can't get an IP via DHCP. -+ * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from -+ * the r8169.c kernel driver. -+ */ -+ -+ u32 val = RTL_R32(FuncEvent); -+ debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val); -+ val &= ~RxDv_Gated_En; -+ RTL_W32(FuncEvent, val); -+ - return 0; - } - - -From patchwork Thu Mar 26 22:59:14 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262417 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pL6B04lDz9sSH - for ; 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Thu, 26 Mar 2020 15:59:10 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 2/2] tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all - Jetson boards -Date: Thu, 26 Mar 2020 15:59:14 -0700 -Message-ID: <1585263554-10258-3-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585263554-10258-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585263554-10258-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -This allows the user to set $serverip in the environment before -executing a DHCP request. If they do, U-Boot will use that IP rather -than using the IP in the DHCP response. - -Signed-off-by: Tom Warren -Acked-by: Stephen Warren ---- - configs/e2220-1170_defconfig | 1 + - configs/p2371-0000_defconfig | 1 + - configs/p2371-2180_defconfig | 1 + - configs/p2571_defconfig | 1 + - configs/p2771-0000-000_defconfig | 1 + - configs/p2771-0000-500_defconfig | 1 + - 6 files changed, 6 insertions(+) - -diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig -index 1639040..951ed1d 100644 ---- a/configs/e2220-1170_defconfig -+++ b/configs/e2220-1170_defconfig -@@ -43,3 +43,4 @@ CONFIG_CI_UDC=y - CONFIG_USB_GADGET_DOWNLOAD=y - CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_ASIX=y -+CONFIG_BOOTP_PREFER_SERVERIP=y -diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig -index 2070199..7081719 100644 ---- a/configs/p2371-0000_defconfig -+++ b/configs/p2371-0000_defconfig -@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y - CONFIG_USB_GADGET_DOWNLOAD=y - CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_ASIX=y -+CONFIG_BOOTP_PREFER_SERVERIP=y -diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig -index 8c808ae..c70217c 100644 ---- a/configs/p2371-2180_defconfig -+++ b/configs/p2371-2180_defconfig -@@ -52,3 +52,4 @@ CONFIG_CI_UDC=y - CONFIG_USB_GADGET_DOWNLOAD=y - CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_ASIX=y -+CONFIG_BOOTP_PREFER_SERVERIP=y -diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig -index 721c5c5..43c24b8 100644 ---- a/configs/p2571_defconfig -+++ b/configs/p2571_defconfig -@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y - CONFIG_USB_GADGET_DOWNLOAD=y - CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_ASIX=y -+CONFIG_BOOTP_PREFER_SERVERIP=y -diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig -index e347a77..8bf8419 100644 ---- a/configs/p2771-0000-000_defconfig -+++ b/configs/p2771-0000-000_defconfig -@@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_POSITION_INDEPENDENT=y -+CONFIG_BOOTP_PREFER_SERVERIP=y -diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig -index 0803b26..1f40333 100644 ---- a/configs/p2771-0000-500_defconfig -+++ b/configs/p2771-0000-500_defconfig -@@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_POSITION_INDEPENDENT=y -+CONFIG_BOOTP_PREFER_SERVERIP=y diff --git a/qspi-t210-fix-claim_bus-and-clock-tap-delays.patch b/qspi-t210-fix-claim_bus-and-clock-tap-delays.patch deleted file mode 100644 index 2257083..0000000 --- a/qspi-t210-fix-claim_bus-and-clock-tap-delays.patch +++ /dev/null @@ -1,453 +0,0 @@ -From patchwork Thu Mar 26 22:42:00 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262404 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pKkD6xnVz9sRR - for ; - Fri, 27 Mar 2020 09:42:28 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 798238183F; 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- spf=fail smtp.mailfrom=tomcwarren3959@gmail.com -Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by - hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) - id ; Thu, 26 Mar 2020 15:41:16 -0700 -Received: from hqmail.nvidia.com ([172.20.161.6]) - by hqpgpgate102.nvidia.com (PGP Universal service); - Thu, 26 Mar 2020 15:42:02 -0700 -X-PGP-Universal: processed; - by hqpgpgate102.nvidia.com on Thu, 26 Mar 2020 15:42:02 -0700 -Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com - (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; - Thu, 26 Mar 2020 22:42:01 +0000 -Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com - (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via - Frontend Transport; Thu, 26 Mar 2020 22:42:01 +0000 -Received: from tom-lt2.nvidia.com (Not Verified[10.2.63.13]) by - rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) - id ; Thu, 26 Mar 2020 15:42:01 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 1/3] qspi: t210: Fix claim_bus's use of the wrong bus/device -Date: Thu, 26 Mar 2020 15:42:00 -0700 -Message-ID: <1585262522-6127-2-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585262522-6127-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585262522-6127-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -claim_bus() is passed a udevice *dev, which is the bus device's parent. -In this driver, claim_bus assumed it was the bus, which caused the -'priv' info pointer to be wrong, and periph_id was incorrect. This in -turn caused the periph clock call to assign the wrong clock (PLLM -instead of PLLP0), which caused a kernel warning. I only saw the 'bad' -periph_id when enabling DEBUG due to an assert. Not sure how QSPI was -working w/this errant clock, but it was moot as QSPI wasn't active -unless you probed it, and that wasn't happening until I posted a patch -to enable env save to QSPI for Nano (coming soon). - -Signed-off-by: Tom Warren ---- - Changes in v2: - - None - - drivers/spi/tegra210_qspi.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c -index d82ecaa..2a77126 100644 ---- a/drivers/spi/tegra210_qspi.c -+++ b/drivers/spi/tegra210_qspi.c -@@ -2,7 +2,8 @@ - /* - * NVIDIA Tegra210 QSPI controller driver - * -- * (C) Copyright 2015 NVIDIA Corporation -+ * (C) Copyright 2015-2019 NVIDIA Corporation -+ * - */ - - #include -@@ -137,8 +138,9 @@ static int tegra210_qspi_probe(struct udevice *bus) - return 0; - } - --static int tegra210_qspi_claim_bus(struct udevice *bus) -+static int tegra210_qspi_claim_bus(struct udevice *dev) - { -+ struct udevice *bus = dev->parent; - struct tegra210_qspi_priv *priv = dev_get_priv(bus); - struct qspi_regs *regs = priv->regs; - - -From patchwork Thu Mar 26 22:42:01 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262405 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pKkQ1xG5z9sRR - for ; - Fri, 27 Mar 2020 09:42:38 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 0EBF581883; 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- spf=fail smtp.mailfrom=tomcwarren3959@gmail.com -Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by - hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) - id ; Thu, 26 Mar 2020 15:41:16 -0700 -Received: from hqmail.nvidia.com ([172.20.161.6]) - by hqpgpgate102.nvidia.com (PGP Universal service); - Thu, 26 Mar 2020 15:42:02 -0700 -X-PGP-Universal: processed; - by hqpgpgate102.nvidia.com on Thu, 26 Mar 2020 15:42:02 -0700 -Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com - (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; - Thu, 26 Mar 2020 22:42:02 +0000 -Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com - (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via - Frontend Transport; Thu, 26 Mar 2020 22:42:02 +0000 -Received: from tom-lt2.nvidia.com (Not Verified[10.2.63.13]) by - rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) - id ; Thu, 26 Mar 2020 15:42:02 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 2/3] qspi: t210: Fix QSPI clock and tap delays -Date: Thu, 26 Mar 2020 15:42:01 -0700 -Message-ID: <1585262522-6127-3-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585262522-6127-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585262522-6127-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -When claim_bus was setting the clock, it reset the QSPI controller, -which wipes out any tap delays set by previous bootloaders (nvtboot, -CBoot for example on Nano). Instead of doing that in claim_bus, which -gets called a lot, moved clock setting to probe(), and set tap delays -there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env -save works reliably again. - -Signed-off-by: Tom Warren ---- - Changes in v2: - - None - - drivers/spi/tegra210_qspi.c | 19 ++++++++++++------- - 1 file changed, 12 insertions(+), 7 deletions(-) - -diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c -index 2a77126..4284ea9 100644 ---- a/drivers/spi/tegra210_qspi.c -+++ b/drivers/spi/tegra210_qspi.c -@@ -42,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR; - #define QSPI_CMD1_BITLEN_SHIFT 0 - - /* COMMAND2 */ --#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) --#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) --#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) --#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) -+#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10 -+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10) -+#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0 -+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0) - - /* TRANSFER STATUS */ - #define QSPI_XFER_STS_RDY BIT(30) -@@ -127,14 +127,22 @@ static int tegra210_qspi_probe(struct udevice *bus) - struct tegra210_qspi_priv *priv = dev_get_priv(bus); - - priv->regs = (struct qspi_regs *)plat->base; -+ struct qspi_regs *regs = priv->regs; - - priv->last_transaction_us = timer_get_us(); - priv->freq = plat->frequency; - priv->periph_id = plat->periph_id; - -+ debug("%s: Freq = %u, id = %d\n", __func__, priv->freq, priv->periph_id); - /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); - -+ /* Set tap delays here, clock change above resets QSPI controller */ -+ u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) | -+ (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT); -+ writel(reg, ®s->command2); -+ debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2)); -+ - return 0; - } - -@@ -144,9 +152,6 @@ static int tegra210_qspi_claim_bus(struct udevice *dev) - struct tegra210_qspi_priv *priv = dev_get_priv(bus); - struct qspi_regs *regs = priv->regs; - -- /* Change SPI clock to correct frequency, PLLP_OUT0 source */ -- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); -- - debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); - - /* Set master mode and sw controlled CS */ - -From patchwork Thu Mar 26 22:42:02 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262406 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pKkb4wzBz9sRR - for ; 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Thu, 26 Mar 2020 15:42:02 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 3/3] qspi: t210: Use dev_read calls to get FDT data like - base, freq -Date: Thu, 26 Mar 2020 15:42:02 -0700 -Message-ID: <1585262522-6127-4-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585262522-6127-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585262522-6127-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -This Tegra QSPI driver hadn't been brought up to date with how -DM drivers are fetching data from the FDT now, and was pulling -in bogus data for base, max freq, etc. Fixed ofdata_to_platdata -to work the same way it does in the tegra114 SPI driver, using -dev_read_ functions. - -Signed-off-by: Tom Warren ---- - Changes in v2: - - New - - drivers/spi/tegra210_qspi.c | 10 ++++------ - 1 file changed, 4 insertions(+), 6 deletions(-) - -diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c -index 4284ea9..466d572 100644 ---- a/drivers/spi/tegra210_qspi.c -+++ b/drivers/spi/tegra210_qspi.c -@@ -2,7 +2,7 @@ - /* - * NVIDIA Tegra210 QSPI controller driver - * -- * (C) Copyright 2015-2019 NVIDIA Corporation -+ * (C) Copyright 2015-2020 NVIDIA Corporation - * - */ - -@@ -97,10 +97,8 @@ struct tegra210_qspi_priv { - static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) - { - struct tegra_spi_platdata *plat = bus->platdata; -- const void *blob = gd->fdt_blob; -- int node = dev_of_offset(bus); - -- plat->base = devfdt_get_addr(bus); -+ plat->base = dev_read_addr(bus); - plat->periph_id = clock_decode_periph_id(bus); - - if (plat->periph_id == PERIPH_ID_NONE) { -@@ -110,9 +108,9 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) - } - - /* Use 500KHz as a suitable default */ -- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", -+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", - 500000); -- plat->deactivate_delay_us = fdtdec_get_int(blob, node, -+ plat->deactivate_delay_us = dev_read_u32_default(bus, - "spi-deactivate-delay", 0); - debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", - __func__, plat->base, plat->periph_id, plat->frequency, diff --git a/sources b/sources index 4c62613..50992b8 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2020.04-rc4.tar.bz2) = 0e8acc06aae5e009122d06fa1cf89d2a428796bfd44b71907493e6c83480b71949e03cb432ebcd78df90fd1fbf21a1d586bb174ad90257b5e64ac41661f974b3 +SHA512 (u-boot-2020.04-rc5.tar.bz2) = 4fed5a45e9ebfc931cb4f06bbdb9ec1a477ed7dff902b8e9013fc7e41a78e4448749b88c450ee5ce62b6756031ec250f11e9afbea01bab2702ac6e9bb22f4ad2 diff --git a/t210-miscellaneous-patches.patch b/t210-miscellaneous-patches.patch deleted file mode 100644 index ec41c55..0000000 --- a/t210-miscellaneous-patches.patch +++ /dev/null @@ -1,2026 +0,0 @@ -From patchwork Thu Mar 26 23:10:09 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262431 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pLLj2Nttz9sSL - for ; - Fri, 27 Mar 2020 10:10:37 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 67ACD818A2; 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- spf=fail smtp.mailfrom=tomcwarren3959@gmail.com -Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by - hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) - id ; Thu, 26 Mar 2020 16:08:35 -0700 -Received: from hqmail.nvidia.com ([172.20.161.6]) - by hqpgpgate102.nvidia.com (PGP Universal service); - Thu, 26 Mar 2020 16:10:07 -0700 -X-PGP-Universal: processed; - by hqpgpgate102.nvidia.com on Thu, 26 Mar 2020 16:10:07 -0700 -Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com - (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; - Thu, 26 Mar 2020 23:10:07 +0000 -Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com - (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via - Frontend Transport; Thu, 26 Mar 2020 23:10:07 +0000 -Received: from tom-lt2.nvidia.com (Not Verified[10.2.63.13]) by - rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) - id ; Thu, 26 Mar 2020 16:10:06 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 1/3] t210: do not enable PLLE and UPHY PLL HW PWRSEQ -Date: Thu, 26 Mar 2020 16:10:09 -0700 -Message-ID: <1585264211-13739-2-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585264211-13739-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585264211-13739-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: JC Kuo - -This commit removes the programming sequence that enables PLLE and UPHY -PLL hardware power sequencers. Per TRM, boot software should enable PLLE -and UPHY PLLs in software controlled power-on state and should power -down PLL before jumping into kernel or the next stage boot software. - -Adds call to board_cleanup_before_linux to facilitate this. - -Signed-off-by: JC Kuo -Signed-off-by: Tom Warren -Acked-by: Stephen Warren ---- - arch/arm/cpu/armv8/cpu.c | 5 ++ - arch/arm/include/asm/arch-tegra/xusb-padctl.h | 1 + - arch/arm/mach-tegra/board2.c | 6 +++ - arch/arm/mach-tegra/tegra210/clock.c | 19 -------- - arch/arm/mach-tegra/tegra210/xusb-padctl.c | 68 +++++++++++++++++---------- - arch/arm/mach-tegra/xusb-padctl-dummy.c | 4 ++ - 6 files changed, 59 insertions(+), 44 deletions(-) - -diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c -index 2467e0b..3575203 100644 ---- a/arch/arm/cpu/armv8/cpu.c -+++ b/arch/arm/cpu/armv8/cpu.c -@@ -32,6 +32,8 @@ void sdelay(unsigned long loops) - "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc"); - } - -+void __weak board_cleanup_before_linux(void){} -+ - int cleanup_before_linux(void) - { - /* -@@ -40,6 +42,9 @@ int cleanup_before_linux(void) - * - * disable interrupt and turn off caches etc ... - */ -+ -+ board_cleanup_before_linux(); -+ - disable_interrupts(); - - /* -diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h -index deccdf4..7e14d81 100644 ---- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h -+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h -@@ -16,6 +16,7 @@ struct tegra_xusb_phy; - struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); - - void tegra_xusb_padctl_init(void); -+void tegra_xusb_padctl_exit(void); - int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); - int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); - int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); -diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c -index d3497a2..787ff97 100644 ---- a/arch/arm/mach-tegra/board2.c -+++ b/arch/arm/mach-tegra/board2.c -@@ -181,6 +181,12 @@ int board_init(void) - return nvidia_board_init(); - } - -+void board_cleanup_before_linux(void) -+{ -+ /* power down UPHY PLL */ -+ tegra_xusb_padctl_exit(); -+} -+ - #ifdef CONFIG_BOARD_EARLY_INIT_F - static void __gpio_early_init(void) - { -diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c -index b240860..f1b25e2 100644 ---- a/arch/arm/mach-tegra/tegra210/clock.c -+++ b/arch/arm/mach-tegra/tegra210/clock.c -@@ -1235,25 +1235,6 @@ int tegra_plle_enable(void) - value &= ~PLLE_SS_CNTL_INTERP_RESET; - writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL); - -- /* 7. Enable HW power sequencer for PLLE */ -- -- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); -- value &= ~PLLE_MISC_IDDQ_SWCTL; -- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC); -- -- value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); -- value &= ~PLLE_AUX_SS_SWCTL; -- value &= ~PLLE_AUX_ENABLE_SWCTL; -- value |= PLLE_AUX_SS_SEQ_INCLUDE; -- value |= PLLE_AUX_USE_LOCKDET; -- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); -- -- /* 8. Wait 1 us */ -- -- udelay(1); -- value |= PLLE_AUX_SEQ_ENABLE; -- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); -- - return 0; - } - -diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c -index ab6684f..64dc297 100644 ---- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c -+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c -@@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy) - return tegra_xusb_padctl_disable(phy->padctl); - } - -+#define XUSB_PADCTL_USB3_PAD_MUX 0x28 -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7) -+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8) -+ - #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 - #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20) - #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20) -@@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy) - value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; - padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); - -- value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); -- value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; -- value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; -- value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; -- value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; -- writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); -- -- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); -- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; -- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); -- -- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); -- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; -- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); -- -- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); -- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; -- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); -- -- udelay(1); -- -- value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); -- value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; -- writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); -- - debug("< %s()\n", __func__); - return 0; - } -@@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void) - ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata); - debug("%s: done, ret=%d\n", __func__, ret); - } -+ -+void tegra_xusb_padctl_exit(void) -+{ -+ u32 value; -+ -+ debug("> %s\n", __func__); -+ -+ value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX); -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6; -+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0; -+ padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX); -+ -+ value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); -+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; -+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; -+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3); -+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; -+ padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); -+ -+ reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1); -+ while (padctl.enable) -+ tegra_xusb_padctl_disable(&padctl); -+ -+ debug("< %s()\n", __func__); -+} -diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c -index 3ec27a2..f2d9030 100644 ---- a/arch/arm/mach-tegra/xusb-padctl-dummy.c -+++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c -@@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) - void __weak tegra_xusb_padctl_init(void) - { - } -+ -+void __weak tegra_xusb_padctl_exit(void) -+{ -+} - -From patchwork Thu Mar 26 23:10:10 2020 -Content-Type: text/plain; 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Adjust the load addresses to fix this for now. -Using the calculated_env addresses table from T186 U-Boot is a -better fix, but it isn't working correctly on T210 U-Boot right now, -so this will do until I can fix it. - -Signed-off-by: Tom Warren ---- - include/configs/tegra210-common.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h -index 1c53311..1b8e94b 100644 ---- a/include/configs/tegra210-common.h -+++ b/include/configs/tegra210-common.h -@@ -46,8 +46,8 @@ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -- "fdt_addr_r=0x82000000\0" \ -- "ramdisk_addr_r=0x82100000\0" -+ "fdt_addr_r=0x83000000\0" \ -+ "ramdisk_addr_r=0x83200000\0" - - /* For USB EHCI controller */ - #define CONFIG_EHCI_IS_TDI - -From patchwork Thu Mar 26 23:10:11 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Tom Warren -X-Patchwork-Id: 1262433 -X-Patchwork-Delegate: twarren@nvidia.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 48pLM80QC1z9sSL - for ; - Fri, 27 Mar 2020 10:10:59 +1100 (AEDT) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id F404281888; - Fri, 27 Mar 2020 00:10:56 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=gmail.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 9953D81888; Fri, 27 Mar 2020 00:10:33 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=0.0 required=5.0 tests=BAYES_00, - DKIM_ADSP_CUSTOM_MED, - FORGED_GMAIL_RCVD,FREEMAIL_FROM,NML_ADSP_CUSTOM_MED,SPF_HELO_NONE, - UPPERCASE_75_100,URIBL_BLOCKED autolearn=no autolearn_force=no - version=3.4.2 -Received: from hqnvemgate26.nvidia.com (hqnvemgate26.nvidia.com - [216.228.121.65]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 - bits)) (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id B819481843 - for ; Fri, 27 Mar 2020 00:10:10 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=gmail.com -Authentication-Results: phobos.denx.de; - spf=fail smtp.mailfrom=tomcwarren3959@gmail.com -Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by - hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) - id ; Thu, 26 Mar 2020 16:09:55 -0700 -Received: from hqmail.nvidia.com ([172.20.161.6]) - by hqpgpgate101.nvidia.com (PGP Universal service); - Thu, 26 Mar 2020 16:10:09 -0700 -X-PGP-Universal: processed; - by hqpgpgate101.nvidia.com on Thu, 26 Mar 2020 16:10:09 -0700 -Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com - (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; - Thu, 26 Mar 2020 23:10:08 +0000 -Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com - (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via - Frontend Transport; Thu, 26 Mar 2020 23:10:08 +0000 -Received: from tom-lt2.nvidia.com (Not Verified[10.2.63.13]) by - rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) - id ; Thu, 26 Mar 2020 16:10:08 -0700 -From: -To: -CC: , , , - , -Subject: [PATCH 3/3] t210: pinmux: Remove pinmux/GPIO init from T210 boards -Date: Thu, 26 Mar 2020 16:10:11 -0700 -Message-ID: <1585264211-13739-4-git-send-email-tomcwarren3959@gmail.com> -X-Mailer: git-send-email 1.8.2.1.610.g562af5b -In-Reply-To: <1585264211-13739-1-git-send-email-tomcwarren3959@gmail.com> -References: <1585264211-13739-1-git-send-email-tomcwarren3959@gmail.com> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Tom Warren - -T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB -tables. Remove pinmux/GPIO init tables & code from all T210-based builds -below: - -p2371-2180 aka TX1 -p2371-0000 -e2220-1170 -p2571 - -Signed-off-by: Tom Warren -Acked-by: Stephen Warren ---- - arch/arm/mach-tegra/tegra210/Makefile | 3 +- - arch/arm/mach-tegra/tegra210/pinmux.c | 194 -------------- - board/nvidia/e2220-1170/e2220-1170.c | 21 +- - board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 276 -------------------- - board/nvidia/p2371-0000/p2371-0000.c | 21 +- - board/nvidia/p2371-0000/pinmux-config-p2371-0000.h | 267 -------------------- - board/nvidia/p2371-2180/p2371-2180.c | 21 +- - board/nvidia/p2371-2180/pinmux-config-p2371-2180.h | 278 --------------------- - board/nvidia/p2571/p2571.c | 21 +- - board/nvidia/p2571/pinmux-config-p2571.h | 242 ------------------ - 10 files changed, 5 insertions(+), 1339 deletions(-) - delete mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c - delete mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h - delete mode 100644 board/nvidia/p2371-0000/pinmux-config-p2371-0000.h - delete mode 100644 board/nvidia/p2371-2180/pinmux-config-p2371-2180.h - delete mode 100644 board/nvidia/p2571/pinmux-config-p2571.h - -diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile -index b6012fc..cfcba5b 100644 ---- a/arch/arm/mach-tegra/tegra210/Makefile -+++ b/arch/arm/mach-tegra/tegra210/Makefile -@@ -1,5 +1,5 @@ - # --# (C) Copyright 2013-2015 -+# (C) Copyright 2013-2020 - # NVIDIA Corporation - # - # SPDX-License-Identifier: GPL-2.0+ -@@ -7,6 +7,5 @@ - - obj-y += clock.o - obj-y += funcmux.o --obj-y += pinmux.o - obj-y += xusb-padctl.o - obj-y += ../xusb-padctl-common.o -diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c -deleted file mode 100644 -index 6158099..0000000 ---- a/arch/arm/mach-tegra/tegra210/pinmux.c -+++ /dev/null -@@ -1,194 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ --/* -- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. -- */ -- --#include --#include --#include -- --#define PIN(pin, f0, f1, f2, f3) \ -- { \ -- .funcs = { \ -- PMUX_FUNC_##f0, \ -- PMUX_FUNC_##f1, \ -- PMUX_FUNC_##f2, \ -- PMUX_FUNC_##f3, \ -- }, \ -- } -- --#define PIN_RESERVED {} -- --static const struct pmux_pingrp_desc tegra210_pingroups[] = { -- /* pin, f0, f1, f2, f3 */ -- /* Offset 0x3000 */ -- PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), -- PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), -- PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), -- PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), -- PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), -- PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), -- PIN_RESERVED, -- /* Offset 0x301c */ -- PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), -- PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), -- PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), -- PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), -- PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), -- PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), -- PIN_RESERVED, -- /* Offset 0x3038 */ -- PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), -- PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), -- PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), -- PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), -- PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), -- PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), -- PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), -- PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), -- PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), -- PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), -- PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), -- PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), -- PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), -- PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), -- PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), -- PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), -- PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), -- PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), -- PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), -- PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), -- PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), -- PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), -- PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), -- PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), -- PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), -- PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), -- PIN_RESERVED, -- /* Offset 0x30a4 */ -- PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), -- PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), -- PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), -- PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), -- PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), -- PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), -- PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), -- PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), -- PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), -- PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), -- PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), -- PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), -- PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), -- PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), -- PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), -- PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), -- PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), -- PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), -- PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), -- PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), -- PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), -- PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), -- PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), -- PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), -- PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), -- PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), -- PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), -- PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), -- PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), -- PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), -- PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), -- PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), -- PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), -- PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), -- PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), -- PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), -- PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), -- PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), -- PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), -- PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), -- PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), -- PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), -- PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), -- PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), -- PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), -- PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), -- PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), -- PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), -- PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), -- PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), -- PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), -- PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), -- PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), -- PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), -- PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), -- PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), -- PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), -- PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), -- PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), -- PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), -- PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), -- PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), -- PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), -- PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), -- PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), -- PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), -- PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), -- PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), -- PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), -- PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), -- PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), -- PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), -- PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), -- PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), -- PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), -- PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), -- PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), -- PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), -- PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), -- PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), -- PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), -- PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), -- PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), -- PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), -- PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), -- PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), -- PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), -- PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), -- PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), -- PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), -- PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), -- PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), -- PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), -- PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), -- PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), -- PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), -- PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), -- PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), -- PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), --}; --const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; -diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c -index 8baaf2c..5aac040 100644 ---- a/board/nvidia/e2220-1170/e2220-1170.c -+++ b/board/nvidia/e2220-1170/e2220-1170.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * (C) Copyright 2013-2015 -+ * (C) Copyright 2013-2019 - * NVIDIA Corporation - */ - -@@ -9,7 +9,6 @@ - #include - #include - #include "../p2571/max77620_init.h" --#include "pinmux-config-e2220-1170.h" - - void pin_mux_mmc(void) - { -@@ -30,21 +29,3 @@ void pin_mux_mmc(void) - if (ret) - printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); - } -- --/* -- * Routine: pinmux_init -- * Description: Do individual peripheral pinmux configs -- */ --void pinmux_init(void) --{ -- pinmux_clear_tristate_input_clamping(); -- -- gpio_config_table(e2220_1170_gpio_inits, -- ARRAY_SIZE(e2220_1170_gpio_inits)); -- -- pinmux_config_pingrp_table(e2220_1170_pingrps, -- ARRAY_SIZE(e2220_1170_pingrps)); -- -- pinmux_config_drvgrp_table(e2220_1170_drvgrps, -- ARRAY_SIZE(e2220_1170_drvgrps)); --} -diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h -deleted file mode 100644 -index 14bbfbf..0000000 ---- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h -+++ /dev/null -@@ -1,276 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. -- */ -- --/* -- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! -- * -- * To generate this file, use the tegra-pinmux-scripts tool available from -- * https://github.com/NVIDIA/tegra-pinmux-scripts -- * Run "board-to-uboot.py e2220-1170". -- */ -- --#ifndef _PINMUX_CONFIG_E2220_1170_H_ --#define _PINMUX_CONFIG_E2220_1170_H_ -- --#define GPIO_INIT(_port, _gpio, _init) \ -- { \ -- .gpio = TEGRA_GPIO(_port, _gpio), \ -- .init = TEGRA_GPIO_INIT_##_init, \ -- } -- --static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { -- /* port, pin, init_val */ -- GPIO_INIT(A, 5, IN), -- GPIO_INIT(A, 6, IN), -- GPIO_INIT(B, 4, IN), -- GPIO_INIT(E, 6, IN), -- GPIO_INIT(G, 2, OUT0), -- GPIO_INIT(G, 3, OUT0), -- GPIO_INIT(H, 0, OUT0), -- GPIO_INIT(H, 1, OUT0), -- GPIO_INIT(H, 2, IN), -- GPIO_INIT(H, 3, OUT0), -- GPIO_INIT(H, 4, OUT0), -- GPIO_INIT(H, 5, IN), -- GPIO_INIT(H, 6, OUT0), -- GPIO_INIT(H, 7, OUT0), -- GPIO_INIT(I, 0, OUT0), -- GPIO_INIT(I, 1, IN), -- GPIO_INIT(I, 2, OUT0), -- GPIO_INIT(I, 3, OUT0), -- GPIO_INIT(K, 0, IN), -- GPIO_INIT(K, 1, OUT0), -- GPIO_INIT(K, 2, OUT0), -- GPIO_INIT(K, 3, OUT0), -- GPIO_INIT(K, 4, IN), -- GPIO_INIT(K, 5, OUT0), -- GPIO_INIT(K, 6, IN), -- GPIO_INIT(K, 7, OUT0), -- GPIO_INIT(L, 0, OUT0), -- GPIO_INIT(S, 4, OUT0), -- GPIO_INIT(S, 5, OUT0), -- GPIO_INIT(S, 6, OUT0), -- GPIO_INIT(S, 7, OUT0), -- GPIO_INIT(T, 0, OUT0), -- GPIO_INIT(T, 1, OUT0), -- GPIO_INIT(V, 1, OUT0), -- GPIO_INIT(V, 2, OUT0), -- GPIO_INIT(V, 3, IN), -- GPIO_INIT(V, 5, OUT0), -- GPIO_INIT(V, 6, OUT0), -- GPIO_INIT(X, 0, IN), -- GPIO_INIT(X, 1, IN), -- GPIO_INIT(X, 2, IN), -- GPIO_INIT(X, 3, IN), -- GPIO_INIT(X, 4, IN), -- GPIO_INIT(X, 5, IN), -- GPIO_INIT(X, 6, IN), -- GPIO_INIT(X, 7, IN), -- GPIO_INIT(Y, 0, IN), -- GPIO_INIT(Y, 1, IN), -- GPIO_INIT(Z, 0, IN), -- GPIO_INIT(Z, 4, OUT0), -- GPIO_INIT(BB, 2, OUT0), -- GPIO_INIT(BB, 3, OUT0), -- GPIO_INIT(BB, 4, IN), -- GPIO_INIT(CC, 1, IN), -- GPIO_INIT(CC, 5, OUT0), -- GPIO_INIT(CC, 6, IN), -- GPIO_INIT(CC, 7, OUT0), --}; -- --#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ -- { \ -- .pingrp = PMUX_PINGRP_##_pingrp, \ -- .func = PMUX_FUNC_##_mux, \ -- .pull = PMUX_PULL_##_pull, \ -- .tristate = PMUX_TRI_##_tri, \ -- .io = PMUX_PIN_##_io, \ -- .od = PMUX_PIN_OD_##_od, \ -- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ -- .lock = PMUX_PIN_LOCK_DEFAULT, \ -- } -- --static const struct pmux_pingrp_config e2220_1170_pingrps[] = { -- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ -- PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), -- PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), -- PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), -- PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), -- PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), --}; -- --#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ -- { \ -- .drvgrp = PMUX_DRVGRP_##_drvgrp, \ -- .slwf = _slwf, \ -- .slwr = _slwr, \ -- .drvup = _drvup, \ -- .drvdn = _drvdn, \ -- .lpmd = PMUX_LPMD_##_lpmd, \ -- .schmt = PMUX_SCHMT_##_schmt, \ -- .hsm = PMUX_HSM_##_hsm, \ -- } -- --static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { --}; -- --#endif /* PINMUX_CONFIG_E2220_1170_H */ -diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c -index e0c907b..5aac040 100644 ---- a/board/nvidia/p2371-0000/p2371-0000.c -+++ b/board/nvidia/p2371-0000/p2371-0000.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * (C) Copyright 2013-2015 -+ * (C) Copyright 2013-2019 - * NVIDIA Corporation - */ - -@@ -9,7 +9,6 @@ - #include - #include - #include "../p2571/max77620_init.h" --#include "pinmux-config-p2371-0000.h" - - void pin_mux_mmc(void) - { -@@ -30,21 +29,3 @@ void pin_mux_mmc(void) - if (ret) - printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); - } -- --/* -- * Routine: pinmux_init -- * Description: Do individual peripheral pinmux configs -- */ --void pinmux_init(void) --{ -- pinmux_clear_tristate_input_clamping(); -- -- gpio_config_table(p2371_0000_gpio_inits, -- ARRAY_SIZE(p2371_0000_gpio_inits)); -- -- pinmux_config_pingrp_table(p2371_0000_pingrps, -- ARRAY_SIZE(p2371_0000_pingrps)); -- -- pinmux_config_drvgrp_table(p2371_0000_drvgrps, -- ARRAY_SIZE(p2371_0000_drvgrps)); --} -diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h -deleted file mode 100644 -index aa5d7f9..0000000 ---- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h -+++ /dev/null -@@ -1,267 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. -- */ -- --/* -- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! -- * -- * To generate this file, use the tegra-pinmux-scripts tool available from -- * https://github.com/NVIDIA/tegra-pinmux-scripts -- * Run "board-to-uboot.py p2371-0000". -- */ -- --#ifndef _PINMUX_CONFIG_P2371_0000_H_ --#define _PINMUX_CONFIG_P2371_0000_H_ -- --#define GPIO_INIT(_port, _gpio, _init) \ -- { \ -- .gpio = TEGRA_GPIO(_port, _gpio), \ -- .init = TEGRA_GPIO_INIT_##_init, \ -- } -- --static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { -- /* port, pin, init_val */ -- GPIO_INIT(A, 5, IN), -- GPIO_INIT(E, 4, OUT0), -- GPIO_INIT(E, 6, IN), -- GPIO_INIT(G, 0, IN), -- GPIO_INIT(G, 3, OUT0), -- GPIO_INIT(H, 0, OUT0), -- GPIO_INIT(H, 2, IN), -- GPIO_INIT(H, 3, OUT0), -- GPIO_INIT(H, 4, OUT0), -- GPIO_INIT(H, 5, IN), -- GPIO_INIT(H, 6, OUT0), -- GPIO_INIT(H, 7, OUT0), -- GPIO_INIT(I, 0, OUT0), -- GPIO_INIT(I, 1, IN), -- GPIO_INIT(I, 2, OUT0), -- GPIO_INIT(I, 3, OUT0), -- GPIO_INIT(K, 4, IN), -- GPIO_INIT(K, 5, OUT0), -- GPIO_INIT(K, 6, IN), -- GPIO_INIT(K, 7, OUT0), -- GPIO_INIT(L, 0, OUT0), -- GPIO_INIT(S, 4, OUT0), -- GPIO_INIT(S, 5, OUT0), -- GPIO_INIT(S, 6, OUT0), -- GPIO_INIT(S, 7, OUT0), -- GPIO_INIT(T, 0, OUT0), -- GPIO_INIT(T, 1, OUT0), -- GPIO_INIT(V, 1, OUT0), -- GPIO_INIT(V, 2, OUT0), -- GPIO_INIT(V, 5, OUT0), -- GPIO_INIT(V, 6, OUT0), -- GPIO_INIT(V, 7, OUT1), -- GPIO_INIT(X, 0, IN), -- GPIO_INIT(X, 1, IN), -- GPIO_INIT(X, 2, IN), -- GPIO_INIT(X, 3, IN), -- GPIO_INIT(X, 4, IN), -- GPIO_INIT(X, 5, IN), -- GPIO_INIT(X, 6, IN), -- GPIO_INIT(X, 7, IN), -- GPIO_INIT(Y, 1, IN), -- GPIO_INIT(Z, 0, IN), -- GPIO_INIT(Z, 4, OUT0), -- GPIO_INIT(BB, 2, OUT0), -- GPIO_INIT(BB, 3, OUT0), -- GPIO_INIT(CC, 1, IN), -- GPIO_INIT(CC, 6, IN), -- GPIO_INIT(CC, 7, OUT0), --}; -- --#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ -- { \ -- .pingrp = PMUX_PINGRP_##_pingrp, \ -- .func = PMUX_FUNC_##_mux, \ -- .pull = PMUX_PULL_##_pull, \ -- .tristate = PMUX_TRI_##_tri, \ -- .io = PMUX_PIN_##_io, \ -- .od = PMUX_PIN_OD_##_od, \ -- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ -- .lock = PMUX_PIN_LOCK_DEFAULT, \ -- } -- --static const struct pmux_pingrp_config p2371_0000_pingrps[] = { -- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ -- PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), -- PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), -- PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -- PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), -- PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), --}; -- --#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ -- { \ -- .drvgrp = PMUX_DRVGRP_##_drvgrp, \ -- .slwf = _slwf, \ -- .slwr = _slwr, \ -- .drvup = _drvup, \ -- .drvdn = _drvdn, \ -- .lpmd = PMUX_LPMD_##_lpmd, \ -- .schmt = PMUX_SCHMT_##_schmt, \ -- .hsm = PMUX_HSM_##_hsm, \ -- } -- --static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = { --}; -- --#endif /* PINMUX_CONFIG_P2371_0000_H */ -diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c -index fa5288b..1756bbc 100644 ---- a/board/nvidia/p2371-2180/p2371-2180.c -+++ b/board/nvidia/p2371-2180/p2371-2180.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * (C) Copyright 2013-2015 -+ * (C) Copyright 2013-2019 - * NVIDIA Corporation - */ - -@@ -13,7 +13,6 @@ - #include - #include - #include "../p2571/max77620_init.h" --#include "pinmux-config-p2371-2180.h" - - void pin_mux_mmc(void) - { -@@ -57,24 +56,6 @@ void pin_mux_mmc(void) - } - } - --/* -- * Routine: pinmux_init -- * Description: Do individual peripheral pinmux configs -- */ --void pinmux_init(void) --{ -- pinmux_clear_tristate_input_clamping(); -- -- gpio_config_table(p2371_2180_gpio_inits, -- ARRAY_SIZE(p2371_2180_gpio_inits)); -- -- pinmux_config_pingrp_table(p2371_2180_pingrps, -- ARRAY_SIZE(p2371_2180_pingrps)); -- -- pinmux_config_drvgrp_table(p2371_2180_drvgrps, -- ARRAY_SIZE(p2371_2180_drvgrps)); --} -- - #ifdef CONFIG_PCI_TEGRA - int tegra_pcie_board_init(void) - { -diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h -deleted file mode 100644 -index d9abfa7..0000000 ---- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h -+++ /dev/null -@@ -1,278 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. -- */ -- --/* -- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! -- * -- * To generate this file, use the tegra-pinmux-scripts tool available from -- * https://github.com/NVIDIA/tegra-pinmux-scripts -- * Run "board-to-uboot.py p2371-2180". -- */ -- --#ifndef _PINMUX_CONFIG_P2371_2180_H_ --#define _PINMUX_CONFIG_P2371_2180_H_ -- --#define GPIO_INIT(_port, _gpio, _init) \ -- { \ -- .gpio = TEGRA_GPIO(_port, _gpio), \ -- .init = TEGRA_GPIO_INIT_##_init, \ -- } -- --static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { -- /* port, pin, init_val */ -- GPIO_INIT(A, 5, IN), -- GPIO_INIT(B, 0, IN), -- GPIO_INIT(B, 1, IN), -- GPIO_INIT(B, 2, IN), -- GPIO_INIT(B, 3, IN), -- GPIO_INIT(C, 0, IN), -- GPIO_INIT(C, 1, IN), -- GPIO_INIT(C, 2, IN), -- GPIO_INIT(C, 3, IN), -- GPIO_INIT(C, 4, IN), -- GPIO_INIT(E, 4, IN), -- GPIO_INIT(E, 5, IN), -- GPIO_INIT(E, 6, IN), -- GPIO_INIT(H, 0, OUT0), -- GPIO_INIT(H, 1, OUT0), -- GPIO_INIT(H, 2, IN), -- GPIO_INIT(H, 3, OUT0), -- GPIO_INIT(H, 4, OUT0), -- GPIO_INIT(H, 5, IN), -- GPIO_INIT(H, 6, IN), -- GPIO_INIT(H, 7, IN), -- GPIO_INIT(I, 0, OUT0), -- GPIO_INIT(I, 1, IN), -- GPIO_INIT(I, 2, OUT0), -- GPIO_INIT(K, 4, IN), -- GPIO_INIT(K, 5, OUT0), -- GPIO_INIT(K, 6, IN), -- GPIO_INIT(K, 7, IN), -- GPIO_INIT(L, 1, IN), -- GPIO_INIT(S, 4, OUT0), -- GPIO_INIT(S, 5, OUT0), -- GPIO_INIT(S, 6, OUT0), -- GPIO_INIT(S, 7, OUT0), -- GPIO_INIT(T, 0, OUT0), -- GPIO_INIT(T, 1, OUT0), -- GPIO_INIT(U, 2, IN), -- GPIO_INIT(U, 3, IN), -- GPIO_INIT(V, 1, OUT0), -- GPIO_INIT(V, 2, OUT0), -- GPIO_INIT(V, 3, IN), -- GPIO_INIT(V, 5, OUT0), -- GPIO_INIT(V, 6, OUT0), -- GPIO_INIT(X, 0, IN), -- GPIO_INIT(X, 1, IN), -- GPIO_INIT(X, 2, IN), -- GPIO_INIT(X, 3, IN), -- GPIO_INIT(X, 4, IN), -- GPIO_INIT(X, 5, IN), -- GPIO_INIT(X, 6, IN), -- GPIO_INIT(X, 7, IN), -- GPIO_INIT(Y, 0, IN), -- GPIO_INIT(Y, 1, IN), -- GPIO_INIT(Z, 0, IN), -- GPIO_INIT(Z, 2, IN), -- GPIO_INIT(Z, 3, OUT0), -- GPIO_INIT(BB, 0, IN), -- GPIO_INIT(BB, 2, OUT0), -- GPIO_INIT(BB, 3, IN), -- GPIO_INIT(CC, 1, IN), --}; -- --#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ -- { \ -- .pingrp = PMUX_PINGRP_##_pingrp, \ -- .func = PMUX_FUNC_##_mux, \ -- .pull = PMUX_PULL_##_pull, \ -- .tristate = PMUX_TRI_##_tri, \ -- .io = PMUX_PIN_##_io, \ -- .od = PMUX_PIN_OD_##_od, \ -- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ -- .lock = PMUX_PIN_LOCK_DEFAULT, \ -- } -- --static const struct pmux_pingrp_config p2371_2180_pingrps[] = { -- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ -- PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), -- PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH), -- PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_SCLK_PB3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_CLK_PE4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_DAT_PE5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_NFC_PH7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RTS_PU2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART1_CTS_PU3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(ALS_PROX_INT_PX3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -- PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), --}; -- --#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ -- { \ -- .drvgrp = PMUX_DRVGRP_##_drvgrp, \ -- .slwf = _slwf, \ -- .slwr = _slwr, \ -- .drvup = _drvup, \ -- .drvdn = _drvdn, \ -- .lpmd = PMUX_LPMD_##_lpmd, \ -- .schmt = PMUX_SCHMT_##_schmt, \ -- .hsm = PMUX_HSM_##_hsm, \ -- } -- --static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = { --}; -- --#endif /* PINMUX_CONFIG_P2371_2180_H */ -diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c -index dba3579..a9e4d21 100644 ---- a/board/nvidia/p2571/p2571.c -+++ b/board/nvidia/p2571/p2571.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * (C) Copyright 2013-2015 -+ * (C) Copyright 2013-2019 - * NVIDIA Corporation - */ - -@@ -10,7 +10,6 @@ - #include - #include - #include "max77620_init.h" --#include "pinmux-config-p2571.h" - - void pin_mux_mmc(void) - { -@@ -33,24 +32,6 @@ void pin_mux_mmc(void) - } - - /* -- * Routine: pinmux_init -- * Description: Do individual peripheral pinmux configs -- */ --void pinmux_init(void) --{ -- pinmux_clear_tristate_input_clamping(); -- -- gpio_config_table(p2571_gpio_inits, -- ARRAY_SIZE(p2571_gpio_inits)); -- -- pinmux_config_pingrp_table(p2571_pingrps, -- ARRAY_SIZE(p2571_pingrps)); -- -- pinmux_config_drvgrp_table(p2571_drvgrps, -- ARRAY_SIZE(p2571_drvgrps)); --} -- --/* - * Routine: start_cpu_fan - * Description: Enable/start PWM CPU fan on P2571 - */ -diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h -deleted file mode 100644 -index 04bb6ce..0000000 ---- a/board/nvidia/p2571/pinmux-config-p2571.h -+++ /dev/null -@@ -1,242 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. -- */ -- --/* -- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! -- * -- * To generate this file, use the tegra-pinmux-scripts tool available from -- * https://github.com/NVIDIA/tegra-pinmux-scripts -- * Run "board-to-uboot.py p2571". -- */ -- --#ifndef _PINMUX_CONFIG_P2571_H_ --#define _PINMUX_CONFIG_P2571_H_ -- --#define GPIO_INIT(_port, _gpio, _init) \ -- { \ -- .gpio = TEGRA_GPIO(_port, _gpio), \ -- .init = TEGRA_GPIO_INIT_##_init, \ -- } -- --static const struct tegra_gpio_config p2571_gpio_inits[] = { -- /* port, pin, init_val */ -- GPIO_INIT(A, 0, IN), -- GPIO_INIT(A, 5, IN), -- GPIO_INIT(D, 4, IN), -- GPIO_INIT(E, 4, OUT0), -- GPIO_INIT(G, 0, IN), -- GPIO_INIT(H, 0, OUT0), -- GPIO_INIT(H, 2, IN), -- GPIO_INIT(H, 3, OUT0), -- GPIO_INIT(H, 4, OUT0), -- GPIO_INIT(H, 5, IN), -- GPIO_INIT(I, 0, OUT0), -- GPIO_INIT(I, 1, IN), -- GPIO_INIT(V, 1, OUT0), -- GPIO_INIT(V, 6, OUT1), -- GPIO_INIT(X, 4, IN), -- GPIO_INIT(X, 6, IN), -- GPIO_INIT(X, 7, IN), -- GPIO_INIT(Y, 1, IN), -- GPIO_INIT(Z, 0, IN), -- GPIO_INIT(Z, 4, OUT0), -- GPIO_INIT(BB, 2, OUT0), -- GPIO_INIT(CC, 1, IN), -- GPIO_INIT(CC, 3, IN), --}; -- --#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ -- { \ -- .pingrp = PMUX_PINGRP_##_pingrp, \ -- .func = PMUX_FUNC_##_mux, \ -- .pull = PMUX_PULL_##_pull, \ -- .tristate = PMUX_TRI_##_tri, \ -- .io = PMUX_PIN_##_io, \ -- .od = PMUX_PIN_OD_##_od, \ -- .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ -- .lock = PMUX_PIN_LOCK_DEFAULT, \ -- } -- --static const struct pmux_pingrp_config p2571_pingrps[] = { -- /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ -- PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -- PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -- PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -- PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -- PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), -- PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), -- PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), -- PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), -- PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), -- PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), --}; -- --#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ -- { \ -- .drvgrp = PMUX_DRVGRP_##_drvgrp, \ -- .slwf = _slwf, \ -- .slwr = _slwr, \ -- .drvup = _drvup, \ -- .drvdn = _drvdn, \ -- .lpmd = PMUX_LPMD_##_lpmd, \ -- .schmt = PMUX_SCHMT_##_schmt, \ -- .hsm = PMUX_HSM_##_hsm, \ -- } -- --static const struct pmux_drvgrp_config p2571_drvgrps[] = { --}; -- --#endif /* PINMUX_CONFIG_P2571_H */ diff --git a/uboot-tools.spec b/uboot-tools.spec index 40ebdd3..2002614 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc4 +%global candidate rc5 Name: uboot-tools Version: 2020.04 -Release: 0.6%{?candidate:.%{candidate}}%{?dist} +Release: 0.7%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -27,16 +27,9 @@ Patch6: dragonboard-fixes.patch Patch7: efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch # Tegra improvements -Patch10: mtd-spi-Add-Macronix-MX25U3235F-device.patch -Patch11: Misc-fixes-for-Tegra.patch -Patch12: mmc-t210-fix-autocal-and-400KHz-clock.patch -Patch13: qspi-t210-fix-claim_bus-and-clock-tap-delays.patch -Patch14: net-tegra-Misc-network-fixes.patch -Patch15: t210-miscellaneous-patches.patch -# http://patchwork.ozlabs.org/patch/1261582/ -Patch16: ARM-tegra-Add-NVIDIA-Jetson-Nano.patch -Patch17: arm-tegra-define-fdtfile-option-for-distro-boot.patch -Patch18: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch +Patch10: Misc-fixes-for-Tegra.patch +Patch11: arm-tegra-define-fdtfile-option-for-distro-boot.patch +Patch12: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch # Rockchips improvements Patch20: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch @@ -262,6 +255,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Tue Apr 7 2020 Peter Robinson 2020.04-0.7-rc5 +- 2020.04 RC5 + * Tue Mar 31 2020 Peter Robinson 2020.04-0.6-rc4 - 2020.04 RC4 - Updates for NVIDIA Jetson platforms