diff --git a/ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch b/ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch index 2f662b1..70bb946 100644 --- a/ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch +++ b/ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch @@ -1,2462 +1,3 @@ -From patchwork Mon Mar 18 23:24:08 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,01/15] ARM: tegra: Use common header for PMU declarations -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058145 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-2-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:08 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -There's no need to replicate the pmu.h header file for every Tegra SoC -generation. Use a single header that is shared across generations. - -Signed-off-by: Thierry Reding ---- - .../include/asm/{arch-tegra20 => arch-tegra}/pmu.h | 6 +++--- - arch/arm/include/asm/arch-tegra114/pmu.h | 12 ------------ - arch/arm/include/asm/arch-tegra124/pmu.h | 13 ------------- - arch/arm/include/asm/arch-tegra210/pmu.h | 13 ------------- - arch/arm/include/asm/arch-tegra30/pmu.h | 12 ------------ - arch/arm/mach-tegra/board2.c | 2 +- - arch/arm/mach-tegra/emc.c | 2 +- - 7 files changed, 5 insertions(+), 55 deletions(-) - rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/pmu.h (73%) - delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h - delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h - delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h - delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h - -diff --git a/arch/arm/include/asm/arch-tegra20/pmu.h b/arch/arm/include/asm/arch-tegra/pmu.h -similarity index 73% -rename from arch/arm/include/asm/arch-tegra20/pmu.h -rename to arch/arm/include/asm/arch-tegra/pmu.h -index 18766dfed2bb..e850875d3166 100644 ---- a/arch/arm/include/asm/arch-tegra20/pmu.h -+++ b/arch/arm/include/asm/arch-tegra/pmu.h -@@ -4,10 +4,10 @@ - * NVIDIA Corporation - */ - --#ifndef _ARCH_PMU_H_ --#define _ARCH_PMU_H_ -+#ifndef _TEGRA_PMU_H_ -+#define _TEGRA_PMU_H_ - - /* Set core and CPU voltages to nominal levels */ - int pmu_set_nominal(void); - --#endif /* _ARCH_PMU_H_ */ -+#endif /* _TEGRA_PMU_H_ */ -diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h -deleted file mode 100644 -index 1e571ee7b317..000000000000 ---- a/arch/arm/include/asm/arch-tegra114/pmu.h -+++ /dev/null -@@ -1,12 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 */ --/* -- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -- */ -- --#ifndef _TEGRA114_PMU_H_ --#define _TEGRA114_PMU_H_ -- --/* Set core and CPU voltages to nominal levels */ --int pmu_set_nominal(void); -- --#endif /* _TEGRA114_PMU_H_ */ -diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h -deleted file mode 100644 -index c38393edefda..000000000000 ---- a/arch/arm/include/asm/arch-tegra124/pmu.h -+++ /dev/null -@@ -1,13 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * (C) Copyright 2010-2013 -- * NVIDIA Corporation -- */ -- --#ifndef _TEGRA124_PMU_H_ --#define _TEGRA124_PMU_H_ -- --/* Set core and CPU voltages to nominal levels */ --int pmu_set_nominal(void); -- --#endif /* _TEGRA124_PMU_H_ */ -diff --git a/arch/arm/include/asm/arch-tegra210/pmu.h b/arch/arm/include/asm/arch-tegra210/pmu.h -deleted file mode 100644 -index 6ea36aa41876..000000000000 ---- a/arch/arm/include/asm/arch-tegra210/pmu.h -+++ /dev/null -@@ -1,13 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * (C) Copyright 2010-2015 -- * NVIDIA Corporation -- */ -- --#ifndef _TEGRA210_PMU_H_ --#define _TEGRA210_PMU_H_ -- --/* Set core and CPU voltages to nominal levels */ --int pmu_set_nominal(void); -- --#endif /* _TEGRA210_PMU_H_ */ -diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h -deleted file mode 100644 -index a823f0fbfc61..000000000000 ---- a/arch/arm/include/asm/arch-tegra30/pmu.h -+++ /dev/null -@@ -1,12 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 */ --/* -- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -- */ -- --#ifndef _TEGRA30_PMU_H_ --#define _TEGRA30_PMU_H_ -- --/* Set core and CPU voltages to nominal levels */ --int pmu_set_nominal(void); -- --#endif /* _TEGRA30_PMU_H_ */ -diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c -index 12257a42b51b..b8d5ef0322cb 100644 ---- a/arch/arm/mach-tegra/board2.c -+++ b/arch/arm/mach-tegra/board2.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -24,7 +25,6 @@ - #include - #include - #include --#include - #include - #ifdef CONFIG_TEGRA_CLOCK_SCALING - #include -diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c -index 6697909d9a3e..66628933b653 100644 ---- a/arch/arm/mach-tegra/emc.c -+++ b/arch/arm/mach-tegra/emc.c -@@ -8,10 +8,10 @@ - #include - #include - #include --#include - #include - #include - #include -+#include - #include - - DECLARE_GLOBAL_DATA_PTR; - -From patchwork Mon Mar 18 23:24:09 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,02/15] ARM: tegra: Guard clock code with a Kconfig symbol -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058147 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-3-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:09 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Clock code is not relevant on all Tegra SoC generations, so guard it -with a Kconfig symbol that can be selected by the generations that need -it. - -This is in preparation for unifying Tegra186 code with the code used on -older generations. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/Kconfig | 5 +++++ - arch/arm/mach-tegra/Makefile | 2 +- - arch/arm/mach-tegra/board.c | 2 ++ - arch/arm/mach-tegra/board2.c | 12 ++++++++++-- - 4 files changed, 18 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig -index 86b1cd11f752..ee078fec9adc 100644 ---- a/arch/arm/mach-tegra/Kconfig -+++ b/arch/arm/mach-tegra/Kconfig -@@ -12,6 +12,9 @@ config SPL_LIBGENERIC_SUPPORT - config SPL_SERIAL_SUPPORT - default y - -+config TEGRA_CLKRST -+ bool -+ - config TEGRA_IVC - bool "Tegra IVC protocol" - help -@@ -55,6 +58,7 @@ config TEGRA_ARMV7_COMMON - select SPL - select SPL_BOARD_INIT if SPL - select SUPPORT_SPL -+ select TEGRA_CLKRST - select TEGRA_COMMON - select TEGRA_GPIO - select TEGRA_NO_BPMP -@@ -100,6 +104,7 @@ config TEGRA124 - config TEGRA210 - bool "Tegra210 family" - select TEGRA_ARMV8_COMMON -+ select TEGRA_CLKRST - select TEGRA_GPIO - select TEGRA_NO_BPMP - -diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile -index d4b4666fb1e2..0e812818d7a2 100644 ---- a/arch/arm/mach-tegra/Makefile -+++ b/arch/arm/mach-tegra/Makefile -@@ -16,7 +16,7 @@ endif - obj-y += ap.o - obj-y += board.o board2.o - obj-y += cache.o --obj-y += clock.o -+obj-$(CONFIG_TEGRA_CLKRST) += clock.o - obj-y += pinmux-common.o - obj-y += powergate.o - obj-y += xusb-padctl-dummy.o -diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c -index f8fc042a1dcc..ecd5001de4c5 100644 ---- a/arch/arm/mach-tegra/board.c -+++ b/arch/arm/mach-tegra/board.c -@@ -9,7 +9,9 @@ - #include - #include - #include -+#if IS_ENABLED(CONFIG_TEGRA_CLKRST) - #include -+#endif - #include - #include - #include -diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c -index b8d5ef0322cb..b94077221f77 100644 ---- a/arch/arm/mach-tegra/board2.c -+++ b/arch/arm/mach-tegra/board2.c -@@ -22,7 +22,9 @@ - #include - #include - #include -+#if IS_ENABLED(CONFIG_TEGRA_CLKRST) - #include -+#endif - #include - #include - #include -@@ -109,8 +111,10 @@ int board_init(void) - __maybe_unused int board_id; - - /* Do clocks and UART first so that printf() works */ -+#if IS_ENABLED(CONFIG_TEGRA_CLKRST) - clock_init(); - clock_verify(); -+#endif - - tegra_gpu_config(); - -@@ -181,8 +185,10 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); - - int board_early_init_f(void) - { -+#if IS_ENABLED(CONFIG_TEGRA_CLKRST) - if (!clock_early_init_done()) - clock_early_init(); -+#endif - - #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) - #define USBCMD_FS2 (1 << 15) -@@ -193,10 +199,12 @@ int board_early_init_f(void) - #endif - - /* Do any special system timer/TSC setup */ --#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) -+#if IS_ENABLED(CONFIG_TEGRA_CLKRST) -+# if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) - if (!tegra_cpu_is_non_secure()) --#endif -+# endif - arch_timer_init(); -+#endif - - pinmux_init(); - board_init_uart_f(); - -From patchwork Mon Mar 18 23:24:10 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, v2, - 03/15] ARM: tegra: Guard GP pad control code with a Kconfig symbol -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058148 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-4-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:10 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -The GP pad control code is not relevant on all Tegra SoC generations, so -guard it with a Kconfig symbol that can be selected by the generations -that need it. - -This is in preparation for unifying Tegra186 code with the code used on -older generations. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/Kconfig | 5 +++++ - arch/arm/mach-tegra/Makefile | 2 +- - arch/arm/mach-tegra/cache.c | 2 ++ - 3 files changed, 8 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig -index ee078fec9adc..265051b18aaf 100644 ---- a/arch/arm/mach-tegra/Kconfig -+++ b/arch/arm/mach-tegra/Kconfig -@@ -15,6 +15,9 @@ config SPL_SERIAL_SUPPORT - config TEGRA_CLKRST - bool - -+config TEGRA_GP_PADCTRL -+ bool -+ - config TEGRA_IVC - bool "Tegra IVC protocol" - help -@@ -61,6 +64,7 @@ config TEGRA_ARMV7_COMMON - select TEGRA_CLKRST - select TEGRA_COMMON - select TEGRA_GPIO -+ select TEGRA_GP_PADCTRL - select TEGRA_NO_BPMP - - config TEGRA_ARMV8_COMMON -@@ -106,6 +110,7 @@ config TEGRA210 - select TEGRA_ARMV8_COMMON - select TEGRA_CLKRST - select TEGRA_GPIO -+ select TEGRA_GP_PADCTRL - select TEGRA_NO_BPMP - - config TEGRA186 -diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile -index 0e812818d7a2..69f802c01b45 100644 ---- a/arch/arm/mach-tegra/Makefile -+++ b/arch/arm/mach-tegra/Makefile -@@ -13,7 +13,7 @@ else - obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o - endif - --obj-y += ap.o -+obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o - obj-y += board.o board2.o - obj-y += cache.o - obj-$(CONFIG_TEGRA_CLKRST) += clock.o -diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c -index be414e4e4aca..d7063490e222 100644 ---- a/arch/arm/mach-tegra/cache.c -+++ b/arch/arm/mach-tegra/cache.c -@@ -8,7 +8,9 @@ - #include - #include - #include -+#if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL) - #include -+#endif - - #ifndef CONFIG_ARM64 - void config_cache(void) - -From patchwork Mon Mar 18 23:24:11 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, v2, - 04/15] ARM: tegra: Guard memory controller code with a Kconfig symbol -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058146 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-5-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:11 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Memory controller code is not relevant on all Tegra SoC generations, so -guard it with a Kconfig symbol that can be selected by the generations -that need it. - -This is in preparation for unifying Tegra186 code with the code used on -older generations. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/Kconfig | 5 +++++ - arch/arm/mach-tegra/board.c | 7 +++++++ - 2 files changed, 12 insertions(+) - -diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig -index 265051b18aaf..5763c4ae3cd1 100644 ---- a/arch/arm/mach-tegra/Kconfig -+++ b/arch/arm/mach-tegra/Kconfig -@@ -26,6 +26,9 @@ config TEGRA_IVC - U-Boot, it is typically used for communication between the main CPU - and various auxiliary processors. - -+config TEGRA_MC -+ bool -+ - config TEGRA_COMMON - bool "Tegra common options" - select BINMAN -@@ -65,6 +68,7 @@ config TEGRA_ARMV7_COMMON - select TEGRA_COMMON - select TEGRA_GPIO - select TEGRA_GP_PADCTRL -+ select TEGRA_MC - select TEGRA_NO_BPMP - - config TEGRA_ARMV8_COMMON -@@ -111,6 +115,7 @@ config TEGRA210 - select TEGRA_CLKRST - select TEGRA_GPIO - select TEGRA_GP_PADCTRL -+ select TEGRA_MC - select TEGRA_NO_BPMP - - config TEGRA186 -diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c -index ecd5001de4c5..7ef5a67edd1f 100644 ---- a/arch/arm/mach-tegra/board.c -+++ b/arch/arm/mach-tegra/board.c -@@ -13,7 +13,9 @@ - #include - #endif - #include -+#if IS_ENABLED(CONFIG_TEGRA_MC) - #include -+#endif - #include - #include - #include -@@ -68,6 +70,7 @@ bool tegra_cpu_is_non_secure(void) - } - #endif - -+#if IS_ENABLED(CONFIG_TEGRA_MC) - /* Read the RAM size directly from the memory controller */ - static phys_size_t query_sdram_size(void) - { -@@ -117,11 +120,15 @@ static phys_size_t query_sdram_size(void) - - return size_bytes; - } -+#endif - - int dram_init(void) - { -+#if IS_ENABLED(CONFIG_TEGRA_MC) - /* We do not initialise DRAM here. We just query the size */ - gd->ram_size = query_sdram_size(); -+#endif -+ - return 0; - } - - -From patchwork Mon Mar 18 23:24:12 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, v2, - 05/15] ARM: tegra: Guard pin controller code with a Kconfig symbol -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058156 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-6-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:12 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Pin controller code is not relevant on all Tegra SoC generations, so -guard it with a Kconfig symbol that can be selected by the generations -that need it. - -This is in preparation for unifying Tegra186 code with the code used on -older generations. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/Kconfig | 5 +++++ - arch/arm/mach-tegra/Makefile | 2 +- - arch/arm/mach-tegra/board.c | 6 ++++++ - arch/arm/mach-tegra/board2.c | 2 ++ - 4 files changed, 14 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig -index 5763c4ae3cd1..be20ac2e804e 100644 ---- a/arch/arm/mach-tegra/Kconfig -+++ b/arch/arm/mach-tegra/Kconfig -@@ -29,6 +29,9 @@ config TEGRA_IVC - config TEGRA_MC - bool - -+config TEGRA_PINCTRL -+ bool -+ - config TEGRA_COMMON - bool "Tegra common options" - select BINMAN -@@ -70,6 +73,7 @@ config TEGRA_ARMV7_COMMON - select TEGRA_GP_PADCTRL - select TEGRA_MC - select TEGRA_NO_BPMP -+ select TEGRA_PINCTRL - - config TEGRA_ARMV8_COMMON - bool "Tegra 64-bit common options" -@@ -117,6 +121,7 @@ config TEGRA210 - select TEGRA_GP_PADCTRL - select TEGRA_MC - select TEGRA_NO_BPMP -+ select TEGRA_PINCTRL - - config TEGRA186 - bool "Tegra186 family" -diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile -index 69f802c01b45..395e0191a458 100644 ---- a/arch/arm/mach-tegra/Makefile -+++ b/arch/arm/mach-tegra/Makefile -@@ -17,7 +17,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o - obj-y += board.o board2.o - obj-y += cache.o - obj-$(CONFIG_TEGRA_CLKRST) += clock.o --obj-y += pinmux-common.o -+obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o - obj-y += powergate.o - obj-y += xusb-padctl-dummy.o - endif -diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c -index 7ef5a67edd1f..b65bdde5a78d 100644 ---- a/arch/arm/mach-tegra/board.c -+++ b/arch/arm/mach-tegra/board.c -@@ -12,7 +12,9 @@ - #if IS_ENABLED(CONFIG_TEGRA_CLKRST) - #include - #endif -+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) - #include -+#endif - #if IS_ENABLED(CONFIG_TEGRA_MC) - #include - #endif -@@ -132,6 +134,7 @@ int dram_init(void) - return 0; - } - -+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) - static int uart_configs[] = { - #if defined(CONFIG_TEGRA20) - #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) -@@ -199,9 +202,11 @@ static void setup_uarts(int uart_ids) - } - } - } -+#endif - - void board_init_uart_f(void) - { -+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) - int uart_ids = 0; /* bit mask of which UART ids to enable */ - - #ifdef CONFIG_TEGRA_ENABLE_UARTA -@@ -220,6 +225,7 @@ void board_init_uart_f(void) - uart_ids |= UARTE; - #endif - setup_uarts(uart_ids); -+#endif - } - - #if !CONFIG_IS_ENABLED(OF_CONTROL) -diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c -index b94077221f77..ce1c9346959d 100644 ---- a/arch/arm/mach-tegra/board2.c -+++ b/arch/arm/mach-tegra/board2.c -@@ -25,8 +25,10 @@ - #if IS_ENABLED(CONFIG_TEGRA_CLKRST) - #include - #endif -+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) - #include - #include -+#endif - #include - #ifdef CONFIG_TEGRA_CLOCK_SCALING - #include - -From patchwork Mon Mar 18 23:24:13 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, v2, - 06/15] ARM: tegra: Guard powergate code with a Kconfig symbol -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058150 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-7-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:13 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Powergate code is not relevant on all Tegra SoC generations, so guard it -with a Kconfig symbol that can be selected by the generations that need -it. - -This is in preparation for unifying Tegra186 code with the code used on -older generations. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/Kconfig | 5 +++++ - arch/arm/mach-tegra/Makefile | 2 +- - 2 files changed, 6 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig -index be20ac2e804e..db9198348d3f 100644 ---- a/arch/arm/mach-tegra/Kconfig -+++ b/arch/arm/mach-tegra/Kconfig -@@ -32,6 +32,9 @@ config TEGRA_MC - config TEGRA_PINCTRL - bool - -+config TEGRA_PMC -+ bool -+ - config TEGRA_COMMON - bool "Tegra common options" - select BINMAN -@@ -74,6 +77,7 @@ config TEGRA_ARMV7_COMMON - select TEGRA_MC - select TEGRA_NO_BPMP - select TEGRA_PINCTRL -+ select TEGRA_PMC - - config TEGRA_ARMV8_COMMON - bool "Tegra 64-bit common options" -@@ -122,6 +126,7 @@ config TEGRA210 - select TEGRA_MC - select TEGRA_NO_BPMP - select TEGRA_PINCTRL -+ select TEGRA_PMC - - config TEGRA186 - bool "Tegra186 family" -diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile -index 395e0191a458..517be21ee5f5 100644 ---- a/arch/arm/mach-tegra/Makefile -+++ b/arch/arm/mach-tegra/Makefile -@@ -18,7 +18,7 @@ obj-y += board.o board2.o - obj-y += cache.o - obj-$(CONFIG_TEGRA_CLKRST) += clock.o - obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o --obj-y += powergate.o -+obj-$(CONFIG_TEGRA_PMC) += powergate.o - obj-y += xusb-padctl-dummy.o - endif - - -From patchwork Mon Mar 18 23:24:14 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,07/15] ARM: tegra: Fix save_boot_params() prototype -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058149 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-8-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:14 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -The save_boot_params() function takes as its first four arguments the -first four registers. On 32-bit ARM these are r0, r1, r2 and r3, all of -which are 32 bits wide. However, on 64-bit ARM thene registers are x0, -x1, x2 and x3, all of which are 64 bits wide. In order to allow reusing -the save_boot_params() implementation on 64-bit ARM, change it to take -unsigned long parameters rather than the fixed size 32-bit integers. -This ensures that the correct values are passed. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/board.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c -index b65bdde5a78d..59d2f347485d 100644 ---- a/arch/arm/mach-tegra/board.c -+++ b/arch/arm/mach-tegra/board.c -@@ -42,7 +42,8 @@ enum { - static bool from_spl __attribute__ ((section(".data"))); - - #ifndef CONFIG_SPL_BUILD --void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) -+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, -+ unsigned long r3) - { - from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; - save_boot_params_ret(); - -From patchwork Mon Mar 18 23:24:15 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, v2, - 08/15] ARM: tegra: Allow boards to override boot target devices -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058152 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-9-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:15 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Boards may not support all the boot target devices in the default list -for Tegra devices. Allow a board to override the list and default to the -standard list only if the board hasn't specified one itself. - -Signed-off-by: Thierry Reding ---- - include/configs/tegra-common-post.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h -index e54428ba43e2..9685ee5059ab 100644 ---- a/include/configs/tegra-common-post.h -+++ b/include/configs/tegra-common-post.h -@@ -21,12 +21,14 @@ - #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ - - #ifndef CONFIG_SPL_BUILD -+#ifndef BOOT_TARGET_DEVICES - #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -+#endif - #include - #else - #define BOOTENV - -From patchwork Mon Mar 18 23:24:16 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,09/15] ARM: tegra: Support TZ-only access to PMC -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058153 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-10-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:16 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Some devices may restrict access to the PMC to TrustZone software only. -Non-TZ software can detect this and use SMC calls to the firmware that -runs in the TrustZone to perform accesses to PMC registers. - -Note that this also fixes reset_cpu() and the enterrcm command on -Tegra186 where they were previously trying to access the PMC at a wrong -physical address. - -Based on work by Kalyani Chidambaram and Tom -Warren . - -Signed-off-by: Thierry Reding ---- - arch/arm/include/asm/arch-tegra/pmc.h | 20 +++++- - arch/arm/include/asm/arch-tegra/tegra.h | 6 ++ - arch/arm/mach-tegra/Kconfig | 5 ++ - arch/arm/mach-tegra/Makefile | 4 +- - arch/arm/mach-tegra/clock.c | 13 ++-- - arch/arm/mach-tegra/cmd_enterrcm.c | 6 +- - arch/arm/mach-tegra/cpu.c | 20 +++--- - arch/arm/mach-tegra/lowlevel_init.S | 39 ----------- - arch/arm/mach-tegra/pmc.c | 92 +++++++++++++++++++++++++ - arch/arm/mach-tegra/powergate.c | 11 +-- - 10 files changed, 151 insertions(+), 65 deletions(-) - delete mode 100644 arch/arm/mach-tegra/lowlevel_init.S - create mode 100644 arch/arm/mach-tegra/pmc.c - -diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h -index 34bbe75d5fdb..1524bf291164 100644 ---- a/arch/arm/include/asm/arch-tegra/pmc.h -+++ b/arch/arm/include/asm/arch-tegra/pmc.h -@@ -1,6 +1,6 @@ - /* SPDX-License-Identifier: GPL-2.0+ */ - /* -- * (C) Copyright 2010-2015 -+ * (C) Copyright 2010-2019 - * NVIDIA Corporation - */ - -@@ -388,4 +388,22 @@ struct pmc_ctlr { - /* APBDEV_PMC_CNTRL2_0 0x440 */ - #define HOLD_CKE_LOW_EN (1 << 12) - -+/* PMC read/write functions */ -+u32 tegra_pmc_readl(unsigned long offset); -+void tegra_pmc_writel(u32 value, unsigned long offset); -+ -+#define PMC_CNTRL 0x0 -+#define PMC_CNTRL_MAIN_RST BIT(4) -+ -+#if IS_ENABLED(CONFIG_TEGRA186) -+# define PMC_SCRATCH0 0x32000 -+#else -+# define PMC_SCRATCH0 0x00050 -+#endif -+ -+/* for secure PMC */ -+#define TEGRA_SMC_PMC 0xc2fffe00 -+#define TEGRA_SMC_PMC_READ 0xaa -+#define TEGRA_SMC_PMC_WRITE 0xbb -+ - #endif /* PMC_H */ -diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h -index 7ae0129e2db3..7a4e0972fb76 100644 ---- a/arch/arm/include/asm/arch-tegra/tegra.h -+++ b/arch/arm/include/asm/arch-tegra/tegra.h -@@ -30,7 +30,13 @@ - #define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) - #define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) - #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) -+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ -+ defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \ -+ defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210) - #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -+#else -+#define NV_PA_PMC_BASE 0xc360000 -+#endif - #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) - #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) - #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ -diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig -index db9198348d3f..28914a34a1b5 100644 ---- a/arch/arm/mach-tegra/Kconfig -+++ b/arch/arm/mach-tegra/Kconfig -@@ -35,6 +35,10 @@ config TEGRA_PINCTRL - config TEGRA_PMC - bool - -+config TEGRA_PMC_SECURE -+ bool -+ depends on TEGRA_PMC -+ - config TEGRA_COMMON - bool "Tegra common options" - select BINMAN -@@ -127,6 +131,7 @@ config TEGRA210 - select TEGRA_NO_BPMP - select TEGRA_PINCTRL - select TEGRA_PMC -+ select TEGRA_PMC_SECURE - - config TEGRA186 - bool "Tegra186 family" -diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile -index 517be21ee5f5..f8bc65aa8b18 100644 ---- a/arch/arm/mach-tegra/Makefile -+++ b/arch/arm/mach-tegra/Makefile -@@ -1,6 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0+ - # --# (C) Copyright 2010-2015 Nvidia Corporation. -+# (C) Copyright 2010-2019 Nvidia Corporation. - # - # (C) Copyright 2000-2008 - # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -@@ -27,11 +27,11 @@ obj-y += dt-setup.o - obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o - obj-$(CONFIG_TEGRA_GPU) += gpu.o - obj-$(CONFIG_TEGRA_IVC) += ivc.o --obj-y += lowlevel_init.o - ifndef CONFIG_SPL_BUILD - obj-$(CONFIG_ARMV7_PSCI) += psci.o - endif - obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o -+obj-y += pmc.o - - obj-$(CONFIG_TEGRA20) += tegra20/ - obj-$(CONFIG_TEGRA30) += tegra30/ -diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c -index 096330748f2b..c9cd4e6aaeb7 100644 ---- a/arch/arm/mach-tegra/clock.c -+++ b/arch/arm/mach-tegra/clock.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0 - /* -- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. -+ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. - */ - - /* Tegra SoC common clock control functions */ -@@ -814,11 +814,16 @@ void tegra30_set_up_pllp(void) - - int clock_external_output(int clk_id) - { -- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; -+ u32 val; - - if (clk_id >= 1 && clk_id <= 3) { -- setbits_le32(&pmc->pmc_clk_out_cntrl, -- 1 << (2 + (clk_id - 1) * 8)); -+ val = tegra_pmc_readl(offsetof(struct pmc_ctlr, -+ pmc_clk_out_cntrl)); -+ val |= 1 << (2 + (clk_id - 1) * 8); -+ tegra_pmc_writel(val, -+ offsetof(struct pmc_ctlr, -+ pmc_clk_out_cntrl)); -+ - } else { - printf("%s: Unknown output clock id %d\n", __func__, clk_id); - return -EINVAL; -diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c -index 4e6beb3e5bb4..4a889f0e3422 100644 ---- a/arch/arm/mach-tegra/cmd_enterrcm.c -+++ b/arch/arm/mach-tegra/cmd_enterrcm.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. -+ * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved. - * - * Derived from code (arch/arm/lib/reset.c) that is: - * -@@ -31,12 +31,10 @@ - static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) - { -- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; -- - puts("Entering RCM...\n"); - udelay(50000); - -- pmc->pmc_scratch0 = 2; -+ tegra_pmc_writel(2, PMC_SCRATCH0); - disable_interrupts(); - reset_cpu(0); - -diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c -index 1b6ad074ed8f..3d140760e68f 100644 ---- a/arch/arm/mach-tegra/cpu.c -+++ b/arch/arm/mach-tegra/cpu.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0 - /* -- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. -+ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. - */ - - #include -@@ -299,21 +299,19 @@ void enable_cpu_clock(int enable) - - static int is_cpu_powered(void) - { -- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; -- -- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; -+ return (tegra_pmc_readl(offsetof(struct pmc_ctlr, -+ pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0; - } - - static void remove_cpu_io_clamps(void) - { -- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - u32 reg; - debug("%s entry\n", __func__); - - /* Remove the clamps on the CPU I/O signals */ -- reg = readl(&pmc->pmc_remove_clamping); -+ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping)); - reg |= CPU_CLMP; -- writel(reg, &pmc->pmc_remove_clamping); -+ tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping)); - - /* Give I/O signals time to stabilize */ - udelay(IO_STABILIZATION_DELAY); -@@ -321,17 +319,19 @@ static void remove_cpu_io_clamps(void) - - void powerup_cpu(void) - { -- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - u32 reg; - int timeout = IO_STABILIZATION_DELAY; - debug("%s entry\n", __func__); - - if (!is_cpu_powered()) { - /* Toggle the CPU power state (OFF -> ON) */ -- reg = readl(&pmc->pmc_pwrgate_toggle); -+ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, -+ pmc_pwrgate_toggle)); - reg &= PARTID_CP; - reg |= START_CP; -- writel(reg, &pmc->pmc_pwrgate_toggle); -+ tegra_pmc_writel(reg, -+ offsetof(struct pmc_ctlr, -+ pmc_pwrgate_toggle)); - - /* Wait for the power to come up */ - while (!is_cpu_powered()) { -diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S -deleted file mode 100644 -index 626f1b642745..000000000000 ---- a/arch/arm/mach-tegra/lowlevel_init.S -+++ /dev/null -@@ -1,39 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * SoC-specific setup info -- * -- * (C) Copyright 2010,2011 -- * NVIDIA Corporation -- */ -- --#include --#include -- --#ifdef CONFIG_ARM64 -- .align 5 --ENTRY(reset_cpu) -- /* get address for global reset register */ -- ldr x1, =PRM_RSTCTRL -- ldr w3, [x1] -- /* force reset */ -- orr w3, w3, #0x10 -- str w3, [x1] -- mov w0, w0 --1: -- b 1b --ENDPROC(reset_cpu) --#else -- .align 5 --ENTRY(reset_cpu) -- ldr r1, rstctl @ get addr for global reset -- @ reg -- ldr r3, [r1] -- orr r3, r3, #0x10 -- str r3, [r1] @ force reset -- mov r0, r0 --_loop_forever: -- b _loop_forever --rstctl: -- .word PRM_RSTCTRL --ENDPROC(reset_cpu) --#endif -diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c -new file mode 100644 -index 000000000000..afd3c54179c1 ---- /dev/null -+++ b/arch/arm/mach-tegra/pmc.c -@@ -0,0 +1,92 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. -+ */ -+ -+#include -+ -+#include -+ -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) -+static bool tegra_pmc_detect_tz_only(void) -+{ -+ static bool initialized = false; -+ static bool is_tz_only = false; -+ u32 value, saved; -+ -+ if (!initialized) { -+ saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); -+ value = saved ^ 0xffffffff; -+ -+ if (value == 0xffffffff) -+ value = 0xdeadbeef; -+ -+ /* write pattern and read it back */ -+ writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0); -+ value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); -+ -+ /* if we read all-zeroes, access is restricted to TZ only */ -+ if (value == 0) { -+ debug("access to PMC is restricted to TZ\n"); -+ is_tz_only = true; -+ } else { -+ /* restore original value */ -+ writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0); -+ } -+ -+ initialized = true; -+ } -+ -+ return is_tz_only; -+} -+#endif -+ -+uint32_t tegra_pmc_readl(unsigned long offset) -+{ -+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) -+ if (tegra_pmc_detect_tz_only()) { -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, -+ 0, 0, 0, &res); -+ if (res.a0) -+ printf("%s(): SMC failed: %lu\n", __func__, res.a0); -+ -+ return res.a1; -+ } -+#endif -+ -+ return readl(NV_PA_PMC_BASE + offset); -+} -+ -+void tegra_pmc_writel(u32 value, unsigned long offset) -+{ -+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) -+ if (tegra_pmc_detect_tz_only()) { -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, -+ value, 0, 0, 0, 0, &res); -+ if (res.a0) -+ printf("%s(): SMC failed: %lu\n", __func__, res.a0); -+ -+ return; -+ } -+#endif -+ -+ writel(value, NV_PA_PMC_BASE + offset); -+} -+ -+void reset_cpu(ulong addr) -+{ -+ u32 value; -+ -+ value = tegra_pmc_readl(PMC_CNTRL); -+ value |= PMC_CNTRL_MAIN_RST; -+ tegra_pmc_writel(value, PMC_CNTRL); -+} -diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c -index e45f0961b242..761c9ef19e3b 100644 ---- a/arch/arm/mach-tegra/powergate.c -+++ b/arch/arm/mach-tegra/powergate.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0 - /* -- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. -+ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. - */ - - #include -@@ -11,6 +11,7 @@ - - #include - #include -+#include - - #define PWRGATE_TOGGLE 0x30 - #define PWRGATE_TOGGLE_START (1 << 8) -@@ -24,18 +25,18 @@ static int tegra_powergate_set(enum tegra_powergate id, bool state) - u32 value, mask = state ? (1 << id) : 0, old_mask; - unsigned long start, timeout = 25; - -- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); -+ value = tegra_pmc_readl(PWRGATE_STATUS); - old_mask = value & (1 << id); - - if (mask == old_mask) - return 0; - -- writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE); -+ tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); - - start = get_timer(0); - - while (get_timer(start) < timeout) { -- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); -+ value = tegra_pmc_readl(PWRGATE_STATUS); - if ((value & (1 << id)) == mask) - return 0; - } -@@ -69,7 +70,7 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) - else - value = 1 << id; - -- writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING); -+ tegra_pmc_writel(value, REMOVE_CLAMPING); - - return 0; - } - -From patchwork Mon Mar 18 23:24:17 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, v2, - 10/15] ARM: tegra: Workaround UDC boot issues only if necessary -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058157 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-11-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:17 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Resetting the USB device controller on boot is only necessary if the SoC -actually has a UDC controller and U-Boot enables support for it. All the -Tegra boards support UDC via the ChipIdea UDC driver, so make the UDC on -boot workaround depend on the ChipIdea UDC driver. - -This prevents a crash on Tegra186 which does not have the ChipIdea UDC. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig -index 28914a34a1b5..faa73559fd42 100644 ---- a/arch/arm/mach-tegra/Kconfig -+++ b/arch/arm/mach-tegra/Kconfig -@@ -148,6 +148,7 @@ endchoice - - config TEGRA_DISCONNECT_UDC_ON_BOOT - bool "Disconnect USB device mode controller on boot" -+ depends on CI_UDC - default y - help - When loading U-Boot into RAM over USB protocols using tools such as - -From patchwork Mon Mar 18 23:24:18 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,11/15] ARM: tegra: Restore DRAM bank count -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058154 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-12-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:18 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") reduced -the number of DRAM banks supported by U-Boot from 1026 to 8 on P2771-000 -boards. - -However, as explained in commit a9819b9e33bd ("ARM: tegra: p2771-000: -increase max DRAM bank count"), the platform can have a large number of -unusable chunks of memory (up to 1024), so a total of 1026 DRAM banks -are needed to describe the worst-case situation. - -In practice the number of DRAM banks needed will typically be much -lower, but we should be prepared to properly deal with the worst case. - -Signed-off-by: Thierry Reding ---- - configs/p2771-0000-000_defconfig | 2 +- - configs/p2771-0000-500_defconfig | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig -index ac85efa37b3b..ad0802067e73 100644 ---- a/configs/p2771-0000-000_defconfig -+++ b/configs/p2771-0000-000_defconfig -@@ -2,7 +2,7 @@ CONFIG_ARM=y - CONFIG_TEGRA=y - CONFIG_SYS_TEXT_BASE=0x80080000 - CONFIG_TEGRA186=y --CONFIG_NR_DRAM_BANKS=8 -+CONFIG_NR_DRAM_BANKS=1026 - CONFIG_OF_SYSTEM_SETUP=y - CONFIG_CONSOLE_MUX=y - CONFIG_SYS_STDIO_DEREGISTER=y -diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig -index df4d914d85cf..459b67fd195f 100644 ---- a/configs/p2771-0000-500_defconfig -+++ b/configs/p2771-0000-500_defconfig -@@ -2,7 +2,7 @@ CONFIG_ARM=y - CONFIG_TEGRA=y - CONFIG_SYS_TEXT_BASE=0x80080000 - CONFIG_TEGRA186=y --CONFIG_NR_DRAM_BANKS=8 -+CONFIG_NR_DRAM_BANKS=1026 - CONFIG_OF_SYSTEM_SETUP=y - CONFIG_CONSOLE_MUX=y - CONFIG_SYS_STDIO_DEREGISTER=y - -From patchwork Mon Mar 18 23:24:19 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,12/15] ARM: tegra: Unify Tegra186 builds -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058151 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-13-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:19 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -Tegra186 build are currently dealt with in very special ways, which is -because Tegra186 is fundamentally different in many respects. It is no -longer necessary to do many of the low-level programming because early -boot firmware will already have taken care of it. - -Unfortunately, separating Tegra186 builds from the rest in this way -makes it difficult to share code with prior generations of Tegra. With -all of the low-level programming code behind Kconfig guards, the build -for Tegra186 can again be unified. - -As a side-effect, and partial reason for this change, other Tegra SoC -generations can now make use of the code that deals with taking over a -boot from earlier bootloaders. This used to be nvtboot, but has been -replaced by cboot nowadays. Rename the files and functions related to -this to avoid confusion. The implemented protocols are unchanged. - -Signed-off-by: Thierry Reding ---- - arch/arm/include/asm/arch-tegra/cboot.h | 39 ++++ - arch/arm/mach-tegra/Makefile | 4 +- - arch/arm/mach-tegra/board.c | 23 ++ - arch/arm/mach-tegra/board186.c | 32 --- - arch/arm/mach-tegra/board2.c | 21 ++ - .../{tegra186/nvtboot_board.c => cboot.c} | 202 ++++++++++++++++-- - .../{tegra186/nvtboot_ll.S => cboot_ll.S} | 12 +- - arch/arm/mach-tegra/tegra186/Makefile | 4 - - arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 172 --------------- - board/nvidia/p2771-0000/p2771-0000.c | 10 +- - 10 files changed, 279 insertions(+), 240 deletions(-) - create mode 100644 arch/arm/include/asm/arch-tegra/cboot.h - delete mode 100644 arch/arm/mach-tegra/board186.c - rename arch/arm/mach-tegra/{tegra186/nvtboot_board.c => cboot.c} (55%) - rename arch/arm/mach-tegra/{tegra186/nvtboot_ll.S => cboot_ll.S} (57%) - delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_mem.c - -diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h -new file mode 100644 -index 000000000000..b3441ec178b3 ---- /dev/null -+++ b/arch/arm/include/asm/arch-tegra/cboot.h -@@ -0,0 +1,39 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (c) 2019 NVIDIA Corporation. All rights reserved. -+ */ -+ -+#ifndef _TEGRA_CBOOT_H_ -+#define _TEGRA_CBOOT_H_ -+ -+#ifdef CONFIG_ARM64 -+extern unsigned long cboot_boot_x0; -+ -+void cboot_save_boot_params(unsigned long x0, unsigned long x1, -+ unsigned long x2, unsigned long x3); -+int cboot_dram_init(void); -+int cboot_dram_init_banksize(void); -+ulong cboot_get_usable_ram_top(ulong total_size); -+#else -+static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, -+ unsigned long x2, unsigned long x3) -+{ -+} -+ -+static inline int cboot_dram_init(void) -+{ -+ return -ENOSYS; -+} -+ -+static inline int cboot_dram_init_banksize(void) -+{ -+ return -ENOSYS; -+} -+ -+static inline ulong cboot_get_usable_ram_top(ulong total_size) -+{ -+ return 0; -+} -+#endif -+ -+#endif -diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile -index f8bc65aa8b18..41ba674edff4 100644 ---- a/arch/arm/mach-tegra/Makefile -+++ b/arch/arm/mach-tegra/Makefile -@@ -5,7 +5,6 @@ - # (C) Copyright 2000-2008 - # Wolfgang Denk, DENX Software Engineering, wd@denx.de. - --ifndef CONFIG_TEGRA186 - ifdef CONFIG_SPL_BUILD - obj-y += spl.o - obj-y += cpu.o -@@ -20,9 +19,8 @@ obj-$(CONFIG_TEGRA_CLKRST) += clock.o - obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o - obj-$(CONFIG_TEGRA_PMC) += powergate.o - obj-y += xusb-padctl-dummy.o --endif - --obj-$(CONFIG_ARM64) += arm64-mmu.o -+obj-$(CONFIG_ARM64) += arm64-mmu.o cboot_ll.o cboot.o - obj-y += dt-setup.o - obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o - obj-$(CONFIG_TEGRA_GPU) += gpu.o -diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c -index 59d2f347485d..c3ba00811e83 100644 ---- a/arch/arm/mach-tegra/board.c -+++ b/arch/arm/mach-tegra/board.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -46,6 +47,21 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, - unsigned long r3) - { - from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; -+ -+ /* -+ * The logic for this is somewhat indirect. The purpose of the marker -+ * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot -+ * was loaded from a read-only instance of itself, which is something -+ * that can happen in secure boot setups. So basically the presence -+ * of the marker is an indication that U-Boot was loaded by one such -+ * special variant of U-Boot. Conversely, the absence of the marker -+ * indicates that this instance of U-Boot was loaded by something -+ * other than a special U-Boot. This could be SPL, but it could just -+ * as well be one of any number of other first stage bootloaders. -+ */ -+ if (from_spl) -+ cboot_save_boot_params(r0, r1, r2, r3); -+ - save_boot_params_ret(); - } - #endif -@@ -127,6 +143,13 @@ static phys_size_t query_sdram_size(void) - - int dram_init(void) - { -+ int err; -+ -+ /* try to initialize DRAM from cboot DTB first */ -+ err = cboot_dram_init(); -+ if (err == 0) -+ return 0; -+ - #if IS_ENABLED(CONFIG_TEGRA_MC) - /* We do not initialise DRAM here. We just query the size */ - gd->ram_size = query_sdram_size(); -diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c -deleted file mode 100644 -index 80b55707e90f..000000000000 ---- a/arch/arm/mach-tegra/board186.c -+++ /dev/null -@@ -1,32 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ --/* -- * Copyright (c) 2016, NVIDIA CORPORATION. -- */ -- --#include --#include -- --int board_early_init_f(void) --{ -- return 0; --} -- --__weak int tegra_board_init(void) --{ -- return 0; --} -- --int board_init(void) --{ -- return tegra_board_init(); --} -- --__weak int tegra_soc_board_init_late(void) --{ -- return 0; --} -- --int board_late_init(void) --{ -- return tegra_soc_board_init_late(); --} -diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c -index ce1c9346959d..bbc487aa3bf6 100644 ---- a/arch/arm/mach-tegra/board2.c -+++ b/arch/arm/mach-tegra/board2.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -51,6 +52,7 @@ __weak void pin_mux_mmc(void) {} - __weak void gpio_early_init_uart(void) {} - __weak void pin_mux_display(void) {} - __weak void start_cpu_fan(void) {} -+__weak void cboot_late_init(void) {} - - #if defined(CONFIG_TEGRA_NAND) - __weak void pin_mux_nand(void) -@@ -243,6 +245,7 @@ int board_late_init(void) - } - #endif - start_cpu_fan(); -+ cboot_late_init(); - - return 0; - } -@@ -337,6 +340,15 @@ static ulong usable_ram_size_below_4g(void) - */ - int dram_init_banksize(void) - { -+ int err; -+ -+ /* try to compute DRAM bank size based on cboot DTB first */ -+ err = cboot_dram_init_banksize(); -+ if (err == 0) -+ return err; -+ -+ /* fall back to default DRAM bank size computation */ -+ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); - -@@ -370,5 +382,14 @@ int dram_init_banksize(void) - */ - ulong board_get_usable_ram_top(ulong total_size) - { -+ ulong ram_top; -+ -+ /* try to get top of usable RAM based on cboot DTB first */ -+ ram_top = cboot_get_usable_ram_top(total_size); -+ if (ram_top > 0) -+ return ram_top; -+ -+ /* fall back to default usable RAM computation */ -+ - return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); - } -diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_board.c b/arch/arm/mach-tegra/cboot.c -similarity index 55% -rename from arch/arm/mach-tegra/tegra186/nvtboot_board.c -rename to arch/arm/mach-tegra/cboot.c -index 83c0e931ea24..2bca98c92898 100644 ---- a/arch/arm/mach-tegra/tegra186/nvtboot_board.c -+++ b/arch/arm/mach-tegra/cboot.c -@@ -3,14 +3,182 @@ - * Copyright (c) 2016-2018, NVIDIA CORPORATION. - */ - --#include - #include - #include - #include -+#include -+ -+#include -+ - #include -+#include - #include - --extern unsigned long nvtboot_boot_x0; -+/* -+ * Size of a region that's large enough to hold the relocated U-Boot and all -+ * other allocations made around it (stack, heap, page tables, etc.) -+ * In practice, running "bdinfo" at the shell prompt, the stack reaches about -+ * 5MB from the address selected for ram_top as of the time of writing, -+ * so a 16MB region should be plenty. -+ */ -+#define MIN_USABLE_RAM_SIZE SZ_16M -+/* -+ * The amount of space we expect to require for stack usage. Used to validate -+ * that all reservations fit into the region selected for the relocation target -+ */ -+#define MIN_USABLE_STACK_SIZE SZ_1M -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+extern struct mm_region tegra_mem_map[]; -+ -+/* -+ * These variables are written to before relocation, and hence cannot be -+ * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. -+ * The section attribute forces this into .data and avoids this issue. This -+ * also has the nice side-effect of the content being valid after relocation. -+ */ -+ -+/* The number of valid entries in ram_banks[] */ -+static int ram_bank_count __attribute__((section(".data"))); -+ -+/* -+ * The usable top-of-RAM for U-Boot. This is both: -+ * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. -+ * b) At the end of a region that has enough space to hold the relocated U-Boot -+ * and all other allocations made around it (stack, heap, page tables, etc.) -+ */ -+static u64 ram_top __attribute__((section(".data"))); -+/* The base address of the region of RAM that ends at ram_top */ -+static u64 region_base __attribute__((section(".data"))); -+ -+int cboot_dram_init(void) -+{ -+ unsigned int na, ns; -+ const void *cboot_blob = (void *)cboot_boot_x0; -+ int node, len, i; -+ const u32 *prop; -+ -+ if (!cboot_blob) -+ return -EINVAL; -+ -+ na = fdtdec_get_uint(cboot_blob, 0, "#address-cells", 2); -+ ns = fdtdec_get_uint(cboot_blob, 0, "#size-cells", 2); -+ -+ node = fdt_path_offset(cboot_blob, "/memory"); -+ if (node < 0) { -+ pr_err("Can't find /memory node in cboot DTB"); -+ hang(); -+ } -+ prop = fdt_getprop(cboot_blob, node, "reg", &len); -+ if (!prop) { -+ pr_err("Can't find /memory/reg property in cboot DTB"); -+ hang(); -+ } -+ -+ /* Calculate the true # of base/size pairs to read */ -+ len /= 4; /* Convert bytes to number of cells */ -+ len /= (na + ns); /* Convert cells to number of banks */ -+ if (len > CONFIG_NR_DRAM_BANKS) -+ len = CONFIG_NR_DRAM_BANKS; -+ -+ /* Parse the /memory node, and save useful entries */ -+ gd->ram_size = 0; -+ ram_bank_count = 0; -+ for (i = 0; i < len; i++) { -+ u64 bank_start, bank_end, bank_size, usable_bank_size; -+ -+ /* Extract raw memory region data from DTB */ -+ bank_start = fdt_read_number(prop, na); -+ prop += na; -+ bank_size = fdt_read_number(prop, ns); -+ prop += ns; -+ gd->ram_size += bank_size; -+ bank_end = bank_start + bank_size; -+ debug("Bank %d: %llx..%llx (+%llx)\n", i, -+ bank_start, bank_end, bank_size); -+ -+ /* -+ * Align the bank to MMU section size. This is not strictly -+ * necessary, since the translation table construction code -+ * handles page granularity without issue. However, aligning -+ * the MMU entries reduces the size and number of levels in the -+ * page table, so is worth it. -+ */ -+ bank_start = ROUND(bank_start, SZ_2M); -+ bank_end = bank_end & ~(SZ_2M - 1); -+ bank_size = bank_end - bank_start; -+ debug(" aligned: %llx..%llx (+%llx)\n", -+ bank_start, bank_end, bank_size); -+ if (bank_end <= bank_start) -+ continue; -+ -+ /* Record data used to create MMU translation tables */ -+ ram_bank_count++; -+ /* Index below is deliberately 1-based to skip MMIO entry */ -+ tegra_mem_map[ram_bank_count].virt = bank_start; -+ tegra_mem_map[ram_bank_count].phys = bank_start; -+ tegra_mem_map[ram_bank_count].size = bank_size; -+ tegra_mem_map[ram_bank_count].attrs = -+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; -+ -+ /* Determine best bank to relocate U-Boot into */ -+ if (bank_end > SZ_4G) -+ bank_end = SZ_4G; -+ debug(" end %llx (usable)\n", bank_end); -+ usable_bank_size = bank_end - bank_start; -+ debug(" size %llx (usable)\n", usable_bank_size); -+ if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && -+ (bank_end > ram_top)) { -+ ram_top = bank_end; -+ region_base = bank_start; -+ debug("ram top now %llx\n", ram_top); -+ } -+ } -+ -+ /* Ensure memory map contains the desired sentinel entry */ -+ tegra_mem_map[ram_bank_count + 1].virt = 0; -+ tegra_mem_map[ram_bank_count + 1].phys = 0; -+ tegra_mem_map[ram_bank_count + 1].size = 0; -+ tegra_mem_map[ram_bank_count + 1].attrs = 0; -+ -+ /* Error out if a relocation target couldn't be found */ -+ if (!ram_top) { -+ pr_err("Can't find a usable RAM top"); -+ hang(); -+ } -+ -+ return 0; -+} -+ -+int cboot_dram_init_banksize(void) -+{ -+ int i; -+ -+ if (ram_bank_count == 0) -+ return -EINVAL; -+ -+ if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { -+ pr_err("Reservations exceed chosen region size"); -+ hang(); -+ } -+ -+ for (i = 0; i < ram_bank_count; i++) { -+ gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; -+ gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; -+ } -+ -+#ifdef CONFIG_PCI -+ gd->pci_ram_top = ram_top; -+#endif -+ -+ return 0; -+} -+ -+ulong cboot_get_usable_ram_top(ulong total_size) -+{ -+ return ram_top; -+} - - /* - * The following few functions run late during the boot process and dynamically -@@ -23,8 +191,6 @@ extern unsigned long nvtboot_boot_x0; - * list of RAM banks into some private data structure before running. - */ - --extern struct mm_region tegra_mem_map[]; -- - static char *gen_varname(const char *var, const char *ext) - { - size_t len_var = strlen(var); -@@ -235,7 +401,7 @@ static void set_calculated_env_vars(void) - dump_ram_banks(); - #endif - -- reserve_ram(nvtboot_boot_x0, fdt_totalsize(nvtboot_boot_x0)); -+ reserve_ram(cboot_boot_x0, fdt_totalsize(cboot_boot_x0)); - - #ifdef DEBUG - printf("RAM after reserving cboot DTB:\n"); -@@ -262,7 +428,7 @@ static void set_calculated_env_vars(void) - debug("%s: var: %s\n", __func__, var); - set_calculated_env_var(var); - #ifdef DEBUG -- printf("RAM banks affter allocating %s:\n", var); -+ printf("RAM banks after allocating %s:\n", var); - dump_ram_banks(); - #endif - } -@@ -274,9 +440,9 @@ static int set_fdt_addr(void) - { - int ret; - -- ret = env_set_hex("fdt_addr", nvtboot_boot_x0); -+ ret = env_set_hex("fdtaddr", cboot_boot_x0); - if (ret) { -- printf("Failed to set fdt_addr to point at DTB: %d\n", ret); -+ printf("Failed to set fdtaddr to point at DTB: %d\n", ret); - return ret; - } - -@@ -284,12 +450,12 @@ static int set_fdt_addr(void) - } - - /* -- * Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's -+ * Attempt to use /chosen/nvidia,ethernet-mac in the cboot DTB to U-Boot's - * ethaddr environment variable if possible. - */ --static int set_ethaddr_from_nvtboot(void) -+static int set_ethaddr_from_cboot(void) - { -- const void *nvtboot_blob = (void *)nvtboot_boot_x0; -+ const void *cboot_blob = (void *)cboot_boot_x0; - int ret, node, len; - const u32 *prop; - -@@ -297,27 +463,27 @@ static int set_ethaddr_from_nvtboot(void) - if (env_get("ethaddr")) - return 0; - -- node = fdt_path_offset(nvtboot_blob, "/chosen"); -+ node = fdt_path_offset(cboot_blob, "/chosen"); - if (node < 0) { -- printf("Can't find /chosen node in nvtboot DTB\n"); -+ printf("Can't find /chosen node in cboot DTB\n"); - return node; - } -- prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len); -+ prop = fdt_getprop(cboot_blob, node, "nvidia,ethernet-mac", &len); - if (!prop) { -- printf("Can't find nvidia,ether-mac property in nvtboot DTB\n"); -+ printf("Can't find nvidia,ether-mac property in cboot DTB\n"); - return -ENOENT; - } - - ret = env_set("ethaddr", (void *)prop); - if (ret) { -- printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret); -+ printf("Failed to set ethaddr from cboot DTB: %d\n", ret); - return ret; - } - - return 0; - } - --int tegra_soc_board_init_late(void) -+int cboot_late_init(void) - { - set_calculated_env_vars(); - /* -@@ -326,7 +492,7 @@ int tegra_soc_board_init_late(void) - */ - set_fdt_addr(); - /* Ignore errors here; not all cases care about Ethernet addresses */ -- set_ethaddr_from_nvtboot(); -+ set_ethaddr_from_cboot(); - - return 0; - } -diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/cboot_ll.S -similarity index 57% -rename from arch/arm/mach-tegra/tegra186/nvtboot_ll.S -rename to arch/arm/mach-tegra/cboot_ll.S -index aa7a863d9702..4c9ddacc2b39 100644 ---- a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S -+++ b/arch/arm/mach-tegra/cboot_ll.S -@@ -1,6 +1,6 @@ - /* SPDX-License-Identifier: GPL-2.0+ */ - /* -- * Save nvtboot-related boot-time CPU state -+ * Save cboot-related boot-time CPU state - * - * (C) Copyright 2015-2016 NVIDIA Corporation - */ -@@ -9,12 +9,12 @@ - #include - - .align 8 --.globl nvtboot_boot_x0 --nvtboot_boot_x0: -+.globl cboot_boot_x0 -+cboot_boot_x0: - .dword 0 - --ENTRY(save_boot_params) -- adr x8, nvtboot_boot_x0 -+ENTRY(cboot_save_boot_params) -+ adr x8, cboot_boot_x0 - str x0, [x8] - b save_boot_params_ret --ENDPROC(save_boot_params) -+ENDPROC(cboot_save_boot_params) -diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile -index 56f3378ecea3..3a2405027704 100644 ---- a/arch/arm/mach-tegra/tegra186/Makefile -+++ b/arch/arm/mach-tegra/tegra186/Makefile -@@ -2,8 +2,4 @@ - # - # SPDX-License-Identifier: GPL-2.0 - --obj-y += ../board186.o - obj-y += cache.o --obj-y += nvtboot_board.o --obj-y += nvtboot_ll.o --obj-y += nvtboot_mem.o -diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c -deleted file mode 100644 -index 62142821a595..000000000000 ---- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c -+++ /dev/null -@@ -1,172 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ --/* -- * Copyright (c) 2016-2018, NVIDIA CORPORATION. -- */ -- --#include --#include --#include --#include --#include --#include -- --/* -- * Size of a region that's large enough to hold the relocated U-Boot and all -- * other allocations made around it (stack, heap, page tables, etc.) -- * In practice, running "bdinfo" at the shell prompt, the stack reaches about -- * 5MB from the address selected for ram_top as of the time of writing, -- * so a 16MB region should be plenty. -- */ --#define MIN_USABLE_RAM_SIZE SZ_16M --/* -- * The amount of space we expect to require for stack usage. Used to validate -- * that all reservations fit into the region selected for the relocation target -- */ --#define MIN_USABLE_STACK_SIZE SZ_1M -- --DECLARE_GLOBAL_DATA_PTR; -- --extern unsigned long nvtboot_boot_x0; --extern struct mm_region tegra_mem_map[]; -- --/* -- * These variables are written to before relocation, and hence cannot be -- * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. -- * The section attribute forces this into .data and avoids this issue. This -- * also has the nice side-effect of the content being valid after relocation. -- */ -- --/* The number of valid entries in ram_banks[] */ --static int ram_bank_count __attribute__((section(".data"))); -- --/* -- * The usable top-of-RAM for U-Boot. This is both: -- * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. -- * b) At the end of a region that has enough space to hold the relocated U-Boot -- * and all other allocations made around it (stack, heap, page tables, etc.) -- */ --static u64 ram_top __attribute__((section(".data"))); --/* The base address of the region of RAM that ends at ram_top */ --static u64 region_base __attribute__((section(".data"))); -- --int dram_init(void) --{ -- unsigned int na, ns; -- const void *nvtboot_blob = (void *)nvtboot_boot_x0; -- int node, len, i; -- const u32 *prop; -- -- na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); -- ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); -- -- node = fdt_path_offset(nvtboot_blob, "/memory"); -- if (node < 0) { -- pr_err("Can't find /memory node in nvtboot DTB"); -- hang(); -- } -- prop = fdt_getprop(nvtboot_blob, node, "reg", &len); -- if (!prop) { -- pr_err("Can't find /memory/reg property in nvtboot DTB"); -- hang(); -- } -- -- /* Calculate the true # of base/size pairs to read */ -- len /= 4; /* Convert bytes to number of cells */ -- len /= (na + ns); /* Convert cells to number of banks */ -- if (len > CONFIG_NR_DRAM_BANKS) -- len = CONFIG_NR_DRAM_BANKS; -- -- /* Parse the /memory node, and save useful entries */ -- gd->ram_size = 0; -- ram_bank_count = 0; -- for (i = 0; i < len; i++) { -- u64 bank_start, bank_end, bank_size, usable_bank_size; -- -- /* Extract raw memory region data from DTB */ -- bank_start = fdt_read_number(prop, na); -- prop += na; -- bank_size = fdt_read_number(prop, ns); -- prop += ns; -- gd->ram_size += bank_size; -- bank_end = bank_start + bank_size; -- debug("Bank %d: %llx..%llx (+%llx)\n", i, -- bank_start, bank_end, bank_size); -- -- /* -- * Align the bank to MMU section size. This is not strictly -- * necessary, since the translation table construction code -- * handles page granularity without issue. However, aligning -- * the MMU entries reduces the size and number of levels in the -- * page table, so is worth it. -- */ -- bank_start = ROUND(bank_start, SZ_2M); -- bank_end = bank_end & ~(SZ_2M - 1); -- bank_size = bank_end - bank_start; -- debug(" aligned: %llx..%llx (+%llx)\n", -- bank_start, bank_end, bank_size); -- if (bank_end <= bank_start) -- continue; -- -- /* Record data used to create MMU translation tables */ -- ram_bank_count++; -- /* Index below is deliberately 1-based to skip MMIO entry */ -- tegra_mem_map[ram_bank_count].virt = bank_start; -- tegra_mem_map[ram_bank_count].phys = bank_start; -- tegra_mem_map[ram_bank_count].size = bank_size; -- tegra_mem_map[ram_bank_count].attrs = -- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; -- -- /* Determine best bank to relocate U-Boot into */ -- if (bank_end > SZ_4G) -- bank_end = SZ_4G; -- debug(" end %llx (usable)\n", bank_end); -- usable_bank_size = bank_end - bank_start; -- debug(" size %llx (usable)\n", usable_bank_size); -- if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && -- (bank_end > ram_top)) { -- ram_top = bank_end; -- region_base = bank_start; -- debug("ram top now %llx\n", ram_top); -- } -- } -- -- /* Ensure memory map contains the desired sentinel entry */ -- tegra_mem_map[ram_bank_count + 1].virt = 0; -- tegra_mem_map[ram_bank_count + 1].phys = 0; -- tegra_mem_map[ram_bank_count + 1].size = 0; -- tegra_mem_map[ram_bank_count + 1].attrs = 0; -- -- /* Error out if a relocation target couldn't be found */ -- if (!ram_top) { -- pr_err("Can't find a usable RAM top"); -- hang(); -- } -- -- return 0; --} -- --int dram_init_banksize(void) --{ -- int i; -- -- if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { -- pr_err("Reservations exceed chosen region size"); -- hang(); -- } -- -- for (i = 0; i < ram_bank_count; i++) { -- gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; -- gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; -- } -- --#ifdef CONFIG_PCI -- gd->pci_ram_top = ram_top; --#endif -- -- return 0; --} -- --ulong board_get_usable_ram_top(ulong total_size) --{ -- return ram_top; --} -diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c -index 496e8a02111e..6f88010c18c3 100644 ---- a/board/nvidia/p2771-0000/p2771-0000.c -+++ b/board/nvidia/p2771-0000/p2771-0000.c -@@ -7,7 +7,7 @@ - #include - #include "../p2571/max77620_init.h" - --int tegra_board_init(void) -+void pin_mux_mmc(void) - { - struct udevice *dev; - uchar val; -@@ -18,19 +18,18 @@ int tegra_board_init(void) - ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); - if (ret) { - printf("%s: Cannot find MAX77620 I2C chip\n", __func__); -- return ret; -+ return; - } - /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ - val = 0xF2; - ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1); - if (ret) { - printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); -- return ret; -+ return; - } -- -- return 0; - } - -+#ifdef CONFIG_PCI_TEGRA - int tegra_pcie_board_init(void) - { - struct udevice *dev; -@@ -52,3 +51,4 @@ int tegra_pcie_board_init(void) - - return 0; - } -+#endif - -From patchwork Mon Mar 18 23:24:20 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, v2, - 13/15] ARM: tegra: Implement cboot_save_boot_params() in C -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058159 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-14-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:20 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -This is easier to deal with and works just as well for this simple -function. - -Signed-off-by: Thierry Reding ---- - arch/arm/mach-tegra/Makefile | 2 +- - arch/arm/mach-tegra/cboot.c | 12 ++++++++++++ - arch/arm/mach-tegra/cboot_ll.S | 20 -------------------- - 3 files changed, 13 insertions(+), 21 deletions(-) - delete mode 100644 arch/arm/mach-tegra/cboot_ll.S - -diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile -index 41ba674edff4..7165d70a60da 100644 ---- a/arch/arm/mach-tegra/Makefile -+++ b/arch/arm/mach-tegra/Makefile -@@ -20,7 +20,7 @@ obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o - obj-$(CONFIG_TEGRA_PMC) += powergate.o - obj-y += xusb-padctl-dummy.o - --obj-$(CONFIG_ARM64) += arm64-mmu.o cboot_ll.o cboot.o -+obj-$(CONFIG_ARM64) += arm64-mmu.o cboot.o - obj-y += dt-setup.o - obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o - obj-$(CONFIG_TEGRA_GPU) += gpu.o -diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c -index 2bca98c92898..8708c4ec9727 100644 ---- a/arch/arm/mach-tegra/cboot.c -+++ b/arch/arm/mach-tegra/cboot.c -@@ -52,6 +52,18 @@ static u64 ram_top __attribute__((section(".data"))); - /* The base address of the region of RAM that ends at ram_top */ - static u64 region_base __attribute__((section(".data"))); - -+/* -+ * Explicitly put this in the .data section because it is written before the -+ * .bss section is zeroed out but it needs to persist. -+ */ -+unsigned long cboot_boot_x0 __attribute__((section(".data"))); -+ -+void cboot_save_boot_params(unsigned long x0, unsigned long x1, -+ unsigned long x2, unsigned long x3) -+{ -+ cboot_boot_x0 = x0; -+} -+ - int cboot_dram_init(void) - { - unsigned int na, ns; -diff --git a/arch/arm/mach-tegra/cboot_ll.S b/arch/arm/mach-tegra/cboot_ll.S -deleted file mode 100644 -index 4c9ddacc2b39..000000000000 ---- a/arch/arm/mach-tegra/cboot_ll.S -+++ /dev/null -@@ -1,20 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * Save cboot-related boot-time CPU state -- * -- * (C) Copyright 2015-2016 NVIDIA Corporation -- */ -- --#include --#include -- --.align 8 --.globl cboot_boot_x0 --cboot_boot_x0: -- .dword 0 -- --ENTRY(cboot_save_boot_params) -- adr x8, cboot_boot_x0 -- str x0, [x8] -- b save_boot_params_ret --ENDPROC(cboot_save_boot_params) - -From patchwork Mon Mar 18 23:24:21 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,14/15] ARM: tegra: Implement cboot_get_ethaddr() -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1058160 -X-Patchwork-Delegate: twarren@nvidia.com -Message-Id: <20190318232422.24404-15-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Tue, 19 Mar 2019 00:24:21 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -This function will attempt to look up an ethernet address in the DTB -that was passed in from cboot. It does so by first trying to locate the -primary ethernet device for the board (identified by the "ethernet" -alias) and if found, reads the "local-mac-address" property. If the -"ethernet" alias does not exist, or if it points to a device tree node -that doesn't exist, or if the device tree node that it points to does -not have a "local-mac-address" property or if the value is invalid, it -will fall back to the legacy mechanism of looking for the MAC address -stored in the "nvidia,ethernet-mac" property of the "/chosen" node. - -Signed-off-by: Thierry Reding ---- -Changes in v2: -- make dummy static inline to avoid duplicate definitions ---- - arch/arm/include/asm/arch-tegra/cboot.h | 6 ++ - arch/arm/mach-tegra/cboot.c | 78 ++++++++++++++++++++----- - 2 files changed, 69 insertions(+), 15 deletions(-) - -diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h -index b3441ec178b3..021c24617575 100644 ---- a/arch/arm/include/asm/arch-tegra/cboot.h -+++ b/arch/arm/include/asm/arch-tegra/cboot.h -@@ -14,6 +14,7 @@ void cboot_save_boot_params(unsigned long x0, unsigned long x1, - int cboot_dram_init(void); - int cboot_dram_init_banksize(void); - ulong cboot_get_usable_ram_top(ulong total_size); -+int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]); - #else - static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, - unsigned long x2, unsigned long x3) -@@ -34,6 +35,11 @@ static inline ulong cboot_get_usable_ram_top(ulong total_size) - { - return 0; - } -+ -+static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) -+{ -+ return -ENOSYS; -+} - #endif - - #endif -diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c -index 8708c4ec9727..c7a38d258cce 100644 ---- a/arch/arm/mach-tegra/cboot.c -+++ b/arch/arm/mach-tegra/cboot.c -@@ -4,6 +4,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -465,46 +466,93 @@ static int set_fdt_addr(void) - * Attempt to use /chosen/nvidia,ethernet-mac in the cboot DTB to U-Boot's - * ethaddr environment variable if possible. - */ --static int set_ethaddr_from_cboot(void) -+static int cboot_get_ethaddr_legacy(const void *fdt, uint8_t mac[ETH_ALEN]) - { -- const void *cboot_blob = (void *)cboot_boot_x0; -- int ret, node, len; -- const u32 *prop; -- -- /* Already a valid address in the environment? If so, keep it */ -- if (env_get("ethaddr")) -- return 0; -+ const char *prop; -+ int node, len; - -- node = fdt_path_offset(cboot_blob, "/chosen"); -+ node = fdt_path_offset(fdt, "/chosen"); - if (node < 0) { - printf("Can't find /chosen node in cboot DTB\n"); - return node; - } -- prop = fdt_getprop(cboot_blob, node, "nvidia,ethernet-mac", &len); -+ -+ prop = fdt_getprop(fdt, node, "nvidia,ethernet-mac", &len); - if (!prop) { - printf("Can't find nvidia,ether-mac property in cboot DTB\n"); - return -ENOENT; - } - -- ret = env_set("ethaddr", (void *)prop); -- if (ret) { -- printf("Failed to set ethaddr from cboot DTB: %d\n", ret); -- return ret; -+ eth_parse_enetaddr(prop, mac); -+ -+ if (!is_valid_ethaddr(mac)) { -+ printf("Invalid MAC address: %s\n", prop); -+ return -EINVAL; - } - -+ debug("Legacy MAC address: %pM\n", mac); -+ - return 0; - } - -+int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) -+{ -+ int node, len, err = 0; -+ const uchar *prop; -+ const char *path; -+ -+ path = fdt_get_alias(fdt, "ethernet"); -+ if (!path) { -+ err = -ENOENT; -+ goto out; -+ } -+ -+ debug("ethernet alias found: %s\n", path); -+ -+ node = fdt_path_offset(fdt, path); -+ if (node < 0) { -+ err = -ENOENT; -+ goto out; -+ } -+ -+ prop = fdt_getprop(fdt, node, "local-mac-address", &len); -+ if (!prop) { -+ err = -ENOENT; -+ goto out; -+ } -+ -+ if (len != ETH_ALEN) { -+ err = -EINVAL; -+ goto out; -+ } -+ -+ debug("MAC address: %pM\n", prop); -+ memcpy(mac, prop, ETH_ALEN); -+ -+out: -+ if (err < 0) -+ err = cboot_get_ethaddr_legacy(fdt, mac); -+ -+ return err; -+} -+ - int cboot_late_init(void) - { -+ const void *fdt = (const void *)cboot_boot_x0; -+ uint8_t mac[ETH_ALEN]; -+ int err; -+ - set_calculated_env_vars(); - /* - * Ignore errors here; the value may not be used depending on - * extlinux.conf or boot script content. - */ - set_fdt_addr(); -+ - /* Ignore errors here; not all cases care about Ethernet addresses */ -- set_ethaddr_from_cboot(); -+ err = cboot_get_ethaddr(fdt, mac); -+ if (!err) -+ eth_env_set_enetaddr("ethaddr", mac); - - return 0; - } - From patchwork Mon Mar 18 23:24:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 diff --git a/ARM-tegra-Add-support-for-framebuffer-carveouts.patch b/ARM-tegra-Add-support-for-framebuffer-carveouts.patch new file mode 100644 index 0000000..3e1dc09 --- /dev/null +++ b/ARM-tegra-Add-support-for-framebuffer-carveouts.patch @@ -0,0 +1,1685 @@ +From patchwork Thu Mar 21 18:09:58 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,01/13] libfdt: Add phandle generation helper +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060358 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-2-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:09:58 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +The new fdt_generate_phandle() function can be used to generate a new, +unused phandle given a specific device tree blob. The implementation is +somewhat naive in that it simply walks the entire device tree to find +the highest phandle value and then returns a phandle value one higher +than that. A more clever implementation might try to find holes in the +current set of phandle values and fill them. But this implementation is +relatively simple and works reliably. + +Also add a test that validates that phandles generated by this new API +are indeed unique. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- +Changes in v3: +- update to latest upstream commit + + lib/libfdt/fdt_ro.c | 31 +++++++++++++++++++++++++++++++ + scripts/dtc/libfdt/fdt_ro.c | 31 +++++++++++++++++++++++++++++++ + scripts/dtc/libfdt/libfdt.h | 19 +++++++++++++++++++ + scripts/dtc/libfdt/libfdt_env.h | 1 + + 4 files changed, 82 insertions(+) + +diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c +index b6ca4e0b0c30..693de9aa5ad8 100644 +--- a/lib/libfdt/fdt_ro.c ++++ b/lib/libfdt/fdt_ro.c +@@ -73,6 +73,37 @@ uint32_t fdt_get_max_phandle(const void *fdt) + return 0; + } + ++int fdt_generate_phandle(const void *fdt, uint32_t *phandle) ++{ ++ uint32_t max = 0; ++ int offset = -1; ++ ++ while (true) { ++ uint32_t value; ++ ++ offset = fdt_next_node(fdt, offset, NULL); ++ if (offset < 0) { ++ if (offset == -FDT_ERR_NOTFOUND) ++ break; ++ ++ return offset; ++ } ++ ++ value = fdt_get_phandle(fdt, offset); ++ ++ if (value > max) ++ max = value; ++ } ++ ++ if (max == FDT_MAX_PHANDLE) ++ return -FDT_ERR_NOPHANDLES; ++ ++ if (phandle) ++ *phandle = max + 1; ++ ++ return 0; ++} ++ + int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) + { + FDT_CHECK_HEADER(fdt); +diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c +index dfb3236da388..dc499884e4d1 100644 +--- a/scripts/dtc/libfdt/fdt_ro.c ++++ b/scripts/dtc/libfdt/fdt_ro.c +@@ -115,6 +115,37 @@ uint32_t fdt_get_max_phandle(const void *fdt) + return 0; + } + ++int fdt_generate_phandle(const void *fdt, uint32_t *phandle) ++{ ++ uint32_t max = 0; ++ int offset = -1; ++ ++ while (true) { ++ uint32_t value; ++ ++ offset = fdt_next_node(fdt, offset, NULL); ++ if (offset < 0) { ++ if (offset == -FDT_ERR_NOTFOUND) ++ break; ++ ++ return offset; ++ } ++ ++ value = fdt_get_phandle(fdt, offset); ++ ++ if (value > max) ++ max = value; ++ } ++ ++ if (max == FDT_MAX_PHANDLE) ++ return -FDT_ERR_NOPHANDLES; ++ ++ if (phandle) ++ *phandle = max + 1; ++ ++ return 0; ++} ++ + int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) + { + FDT_CHECK_HEADER(fdt); +diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h +index fd73688f9e9f..cf86ddba8811 100644 +--- a/scripts/dtc/libfdt/libfdt.h ++++ b/scripts/dtc/libfdt/libfdt.h +@@ -139,6 +139,10 @@ + + #define FDT_ERR_MAX 17 + ++/* constants */ ++#define FDT_MAX_PHANDLE 0xfffffffe ++ /* Valid values for phandles range from 1 to 2^32-2. */ ++ + /**********************************************************************/ + /* Low-level functions (you probably don't need these) */ + /**********************************************************************/ +@@ -313,6 +317,21 @@ const char *fdt_string(const void *fdt, int stroffset); + */ + uint32_t fdt_get_max_phandle(const void *fdt); + ++/** ++ * fdt_generate_phandle - return a new, unused phandle for a device tree blob ++ * @fdt: pointer to the device tree blob ++ * @phandle: return location for the new phandle ++ * ++ * Walks the device tree blob and looks for the highest phandle value. On ++ * success, the new, unused phandle value (one higher than the previously ++ * highest phandle value in the device tree blob) will be returned in the ++ * @phandle parameter. ++ * ++ * Returns: ++ * 0 on success or a negative error-code on failure ++ */ ++int fdt_generate_phandle(const void *fdt, uint32_t *phandle); ++ + /** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob +diff --git a/scripts/dtc/libfdt/libfdt_env.h b/scripts/dtc/libfdt/libfdt_env.h +index bd2474628775..3ff9e2863075 100644 +--- a/scripts/dtc/libfdt/libfdt_env.h ++++ b/scripts/dtc/libfdt/libfdt_env.h +@@ -52,6 +52,7 @@ + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + ++#include + #include + #include + #include + +From patchwork Thu Mar 21 18:09:59 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,02/13] fdtdec: Add cpu_to_fdt_{addr, size}() macros +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060376 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-3-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:09:59 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +These macros are useful for converting the endianness of variables of +type fdt_addr_t and fdt_size_t. + +Reviewed-by: Simon Glass +Signed-off-by: Thierry Reding +--- +Changes in v2: +- add Reviewed-by from Simon + + include/fdtdec.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/include/fdtdec.h b/include/fdtdec.h +index b7e35cd87c55..a965c33157c9 100644 +--- a/include/fdtdec.h ++++ b/include/fdtdec.h +@@ -27,11 +27,15 @@ typedef phys_size_t fdt_size_t; + #define FDT_ADDR_T_NONE (-1U) + #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) + #define fdt_size_to_cpu(reg) be64_to_cpu(reg) ++#define cpu_to_fdt_addr(reg) cpu_to_be64(reg) ++#define cpu_to_fdt_size(reg) cpu_to_be64(reg) + typedef fdt64_t fdt_val_t; + #else + #define FDT_ADDR_T_NONE (-1U) + #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) + #define fdt_size_to_cpu(reg) be32_to_cpu(reg) ++#define cpu_to_fdt_addr(reg) cpu_to_be32(reg) ++#define cpu_to_fdt_size(reg) cpu_to_be32(reg) + typedef fdt32_t fdt_val_t; + #endif + + +From patchwork Thu Mar 21 18:10:00 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,03/13] fdtdec: Add fdt_{addr, size}_unpack() helpers +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060360 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-4-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:00 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +These helpers can be used to unpack variables of type fdt_addr_t and +fdt_size_t into a pair of 32-bit variables. This is useful in cases +where such variables need to be written to properties (such as "reg") +of a device tree node where they need to be split into cells. + +Signed-off-by: Thierry Reding +--- +Changes in v2: +- new patch + + include/fdtdec.h | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/include/fdtdec.h b/include/fdtdec.h +index a965c33157c9..a0ba57c6318b 100644 +--- a/include/fdtdec.h ++++ b/include/fdtdec.h +@@ -23,6 +23,31 @@ + */ + typedef phys_addr_t fdt_addr_t; + typedef phys_size_t fdt_size_t; ++ ++static inline fdt32_t fdt_addr_unpack(fdt_addr_t addr, fdt32_t *upper) ++{ ++ if (upper) ++#ifdef CONFIG_PHYS_64BIT ++ *upper = addr >> 32; ++#else ++ *upper = 0; ++#endif ++ ++ return addr; ++} ++ ++static inline fdt32_t fdt_size_unpack(fdt_size_t size, fdt32_t *upper) ++{ ++ if (upper) ++#ifdef CONFIG_PHYS_64BIT ++ *upper = size >> 32; ++#else ++ *upper = 0; ++#endif ++ ++ return size; ++} ++ + #ifdef CONFIG_PHYS_64BIT + #define FDT_ADDR_T_NONE (-1U) + #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) + +From patchwork Thu Mar 21 18:10:01 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,04/13] fdtdec: Implement fdtdec_set_phandle() +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060366 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-5-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:01 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +This function can be used to set a phandle for a given node. + +Signed-off-by: Thierry Reding +--- +Changes in v2: +- don't emit deprecated linux,phandle property + + include/fdtdec.h | 11 +++++++++++ + lib/fdtdec.c | 7 +++++++ + 2 files changed, 18 insertions(+) + +diff --git a/include/fdtdec.h b/include/fdtdec.h +index a0ba57c6318b..55600026c488 100644 +--- a/include/fdtdec.h ++++ b/include/fdtdec.h +@@ -981,6 +981,17 @@ int fdtdec_setup_mem_size_base(void); + */ + int fdtdec_setup_memory_banksize(void); + ++/** ++ * fdtdec_set_phandle() - sets the phandle of a given node ++ * ++ * @param blob FDT blob ++ * @param node offset in the FDT blob of the node whose phandle is to ++ * be set ++ * @param phandle phandle to set for the given node ++ * @return 0 on success or a negative error code on failure ++ */ ++int fdtdec_set_phandle(void *blob, int node, uint32_t phandle); ++ + /** + * Set up the device tree ready for use + */ +diff --git a/lib/fdtdec.c b/lib/fdtdec.c +index 09a7e133a539..00db90e3cdfd 100644 +--- a/lib/fdtdec.c ++++ b/lib/fdtdec.c +@@ -1243,6 +1243,13 @@ __weak void *board_fdt_blob_setup(void) + } + #endif + ++int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) ++{ ++ fdt32_t value = cpu_to_fdt32(phandle); ++ ++ return fdt_setprop(blob, node, "phandle", &value, sizeof(value)); ++} ++ + int fdtdec_setup(void) + { + #if CONFIG_IS_ENABLED(OF_CONTROL) + +From patchwork Thu Mar 21 18:10:02 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,05/13] fdtdec: Implement fdtdec_add_reserved_memory() +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060362 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-6-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:02 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +This function can be used to add subnodes in the /reserved-memory node. + +Reviewed-by: Simon Glass +Signed-off-by: Thierry Reding +--- +Changes in v3: +- use fdt_generate_phandle() instead of fdtdec_generate_phandle() +- add device tree bindings for /reserved-memory +- add examples to code comments + +Changes in v2: +- split fdt_{addr,size}_unpack() helpers into separate patch +- use name@x,y notation only if the upper cell is > 0 +- use debug() instead of printf() to save code size +- properly compute number of cells in reg property +- fix carveout size computations, was off by one +- use #size-cells where appropriate + + .../reserved-memory/reserved-memory.txt | 136 ++++++++++++++++++ + include/fdtdec.h | 48 +++++++ + lib/fdtdec.c | 131 +++++++++++++++++ + 3 files changed, 315 insertions(+) + create mode 100644 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + +diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +new file mode 100644 +index 000000000000..bac4afa3b197 +--- /dev/null ++++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +@@ -0,0 +1,136 @@ ++*** Reserved memory regions *** ++ ++Reserved memory is specified as a node under the /reserved-memory node. ++The operating system shall exclude reserved memory from normal usage ++one can create child nodes describing particular reserved (excluded from ++normal use) memory regions. Such memory regions are usually designed for ++the special usage by various device drivers. ++ ++Parameters for each memory region can be encoded into the device tree ++with the following nodes: ++ ++/reserved-memory node ++--------------------- ++#address-cells, #size-cells (required) - standard definition ++ - Should use the same values as the root node ++ranges (required) - standard definition ++ - Should be empty ++ ++/reserved-memory/ child nodes ++----------------------------- ++Each child of the reserved-memory node specifies one or more regions of ++reserved memory. Each child node may either use a 'reg' property to ++specify a specific range of reserved memory, or a 'size' property with ++optional constraints to request a dynamically allocated block of memory. ++ ++Following the generic-names recommended practice, node names should ++reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). Unit ++address (@
) should be appended to the name if the node is a ++static allocation. ++ ++Properties: ++Requires either a) or b) below. ++a) static allocation ++ reg (required) - standard definition ++b) dynamic allocation ++ size (required) - length based on parent's #size-cells ++ - Size in bytes of memory to reserve. ++ alignment (optional) - length based on parent's #size-cells ++ - Address boundary for alignment of allocation. ++ alloc-ranges (optional) - prop-encoded-array (address, length pairs). ++ - Specifies regions of memory that are ++ acceptable to allocate from. ++ ++If both reg and size are present, then the reg property takes precedence ++and size is ignored. ++ ++Additional properties: ++compatible (optional) - standard definition ++ - may contain the following strings: ++ - shared-dma-pool: This indicates a region of memory meant to be ++ used as a shared pool of DMA buffers for a set of devices. It can ++ be used by an operating system to instantiate the necessary pool ++ management subsystem if necessary. ++ - vendor specific string in the form ,[-] ++no-map (optional) - empty property ++ - Indicates the operating system must not create a virtual mapping ++ of the region as part of its standard mapping of system memory, ++ nor permit speculative access to it under any circumstances other ++ than under the control of the device driver using the region. ++reusable (optional) - empty property ++ - The operating system can use the memory in this region with the ++ limitation that the device driver(s) owning the region need to be ++ able to reclaim it back. Typically that means that the operating ++ system can use that region to store volatile or cached data that ++ can be otherwise regenerated or migrated elsewhere. ++ ++Linux implementation note: ++- If a "linux,cma-default" property is present, then Linux will use the ++ region for the default pool of the contiguous memory allocator. ++ ++- If a "linux,dma-default" property is present, then Linux will use the ++ region for the default pool of the consistent DMA allocator. ++ ++Device node references to reserved memory ++----------------------------------------- ++Regions in the /reserved-memory node may be referenced by other device ++nodes by adding a memory-region property to the device node. ++ ++memory-region (optional) - phandle, specifier pairs to children of /reserved-memory ++ ++Example ++------- ++This example defines 3 contiguous regions are defined for Linux kernel: ++one default of all device drivers (named linux,cma@72000000 and 64MiB in size), ++one dedicated to the framebuffer device (named framebuffer@78000000, 8MiB), and ++one for multimedia processing (named multimedia-memory@77000000, 64MiB). ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /* global autoconfigured region for contiguous allocations */ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x4000000>; ++ alignment = <0x2000>; ++ linux,cma-default; ++ }; ++ ++ display_reserved: framebuffer@78000000 { ++ reg = <0x78000000 0x800000>; ++ }; ++ ++ multimedia_reserved: multimedia@77000000 { ++ compatible = "acme,multimedia-memory"; ++ reg = <0x77000000 0x4000000>; ++ }; ++ }; ++ ++ /* ... */ ++ ++ fb0: video@12300000 { ++ memory-region = <&display_reserved>; ++ /* ... */ ++ }; ++ ++ scaler: scaler@12500000 { ++ memory-region = <&multimedia_reserved>; ++ /* ... */ ++ }; ++ ++ codec: codec@12600000 { ++ memory-region = <&multimedia_reserved>; ++ /* ... */ ++ }; ++}; +diff --git a/include/fdtdec.h b/include/fdtdec.h +index 55600026c488..b54ed38fb362 100644 +--- a/include/fdtdec.h ++++ b/include/fdtdec.h +@@ -992,6 +992,54 @@ int fdtdec_setup_memory_banksize(void); + */ + int fdtdec_set_phandle(void *blob, int node, uint32_t phandle); + ++/** ++ * fdtdec_add_reserved_memory() - add or find a reserved-memory node ++ * ++ * If a reserved-memory node already exists for the given carveout, a phandle ++ * for that node will be returned. Otherwise a new node will be created and a ++ * phandle corresponding to it will be returned. ++ * ++ * See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt ++ * for details on how to use reserved memory regions. ++ * ++ * As an example, consider the following code snippet: ++ * ++ * struct fdt_memory fb = { ++ * .start = 0x92cb3000, ++ * .end = 0x934b2fff, ++ * }; ++ * uint32_t phandle; ++ * ++ * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle); ++ * ++ * This results in the following subnode being added to the top-level ++ * /reserved-memory node: ++ * ++ * reserved-memory { ++ * #address-cells = <0x00000002>; ++ * #size-cells = <0x00000002>; ++ * ranges; ++ * ++ * framebuffer@92cb3000 { ++ * reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>; ++ * phandle = <0x0000004d>; ++ * }; ++ * }; ++ * ++ * If the top-level /reserved-memory node does not exist, it will be created. ++ * The phandle returned from the function call can be used to reference this ++ * reserved memory region from other nodes. ++ * ++ * @param blob FDT blob ++ * @param basename base name of the node to create ++ * @param carveout information about the carveout region ++ * @param phandlep return location for the phandle of the carveout region ++ * @return 0 on success or a negative error code on failure ++ */ ++int fdtdec_add_reserved_memory(void *blob, const char *basename, ++ const struct fdt_memory *carveout, ++ uint32_t *phandlep); ++ + /** + * Set up the device tree ready for use + */ +diff --git a/lib/fdtdec.c b/lib/fdtdec.c +index 00db90e3cdfd..be54ad5bd092 100644 +--- a/lib/fdtdec.c ++++ b/lib/fdtdec.c +@@ -1250,6 +1250,137 @@ int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) + return fdt_setprop(blob, node, "phandle", &value, sizeof(value)); + } + ++static int fdtdec_init_reserved_memory(void *blob) ++{ ++ int na, ns, node, err; ++ fdt32_t value; ++ ++ /* inherit #address-cells and #size-cells from the root node */ ++ na = fdt_address_cells(blob, 0); ++ ns = fdt_size_cells(blob, 0); ++ ++ node = fdt_add_subnode(blob, 0, "reserved-memory"); ++ if (node < 0) ++ return node; ++ ++ err = fdt_setprop(blob, node, "ranges", NULL, 0); ++ if (err < 0) ++ return err; ++ ++ value = cpu_to_fdt32(ns); ++ ++ err = fdt_setprop(blob, node, "#size-cells", &value, sizeof(value)); ++ if (err < 0) ++ return err; ++ ++ value = cpu_to_fdt32(na); ++ ++ err = fdt_setprop(blob, node, "#address-cells", &value, sizeof(value)); ++ if (err < 0) ++ return err; ++ ++ return node; ++} ++ ++int fdtdec_add_reserved_memory(void *blob, const char *basename, ++ const struct fdt_memory *carveout, ++ uint32_t *phandlep) ++{ ++ fdt32_t cells[4] = {}, *ptr = cells; ++ uint32_t upper, lower, phandle; ++ int parent, node, na, ns, err; ++ char name[64]; ++ ++ /* create an empty /reserved-memory node if one doesn't exist */ ++ parent = fdt_path_offset(blob, "/reserved-memory"); ++ if (parent < 0) { ++ parent = fdtdec_init_reserved_memory(blob); ++ if (parent < 0) ++ return parent; ++ } ++ ++ /* only 1 or 2 #address-cells and #size-cells are supported */ ++ na = fdt_address_cells(blob, parent); ++ if (na < 1 || na > 2) ++ return -FDT_ERR_BADNCELLS; ++ ++ ns = fdt_size_cells(blob, parent); ++ if (ns < 1 || ns > 2) ++ return -FDT_ERR_BADNCELLS; ++ ++ /* find a matching node and return the phandle to that */ ++ fdt_for_each_subnode(node, blob, parent) { ++ const char *name = fdt_get_name(blob, node, NULL); ++ phys_addr_t addr, size; ++ ++ addr = fdtdec_get_addr_size(blob, node, "reg", &size); ++ if (addr == FDT_ADDR_T_NONE) { ++ debug("failed to read address/size for %s\n", name); ++ continue; ++ } ++ ++ if (addr == carveout->start && (addr + size) == carveout->end) { ++ *phandlep = fdt_get_phandle(blob, node); ++ return 0; ++ } ++ } ++ ++ /* ++ * Unpack the start address and generate the name of the new node ++ * base on the basename and the unit-address. ++ */ ++ lower = fdt_addr_unpack(carveout->start, &upper); ++ ++ if (na > 1 && upper > 0) ++ snprintf(name, sizeof(name), "%s@%x,%x", basename, upper, ++ lower); ++ else { ++ if (upper > 0) { ++ debug("address %08x:%08x exceeds addressable space\n", ++ upper, lower); ++ return -FDT_ERR_BADVALUE; ++ } ++ ++ snprintf(name, sizeof(name), "%s@%x", basename, lower); ++ } ++ ++ node = fdt_add_subnode(blob, parent, name); ++ if (node < 0) ++ return node; ++ ++ err = fdt_generate_phandle(blob, &phandle); ++ if (err < 0) ++ return err; ++ ++ err = fdtdec_set_phandle(blob, node, phandle); ++ if (err < 0) ++ return err; ++ ++ /* store one or two address cells */ ++ if (na > 1) ++ *ptr++ = cpu_to_fdt32(upper); ++ ++ *ptr++ = cpu_to_fdt32(lower); ++ ++ /* store one or two size cells */ ++ lower = fdt_size_unpack(carveout->end - carveout->start + 1, &upper); ++ ++ if (ns > 1) ++ *ptr++ = cpu_to_fdt32(upper); ++ ++ *ptr++ = cpu_to_fdt32(lower); ++ ++ err = fdt_setprop(blob, node, "reg", cells, (na + ns) * sizeof(*cells)); ++ if (err < 0) ++ return err; ++ ++ /* return the phandle for the new node for the caller to use */ ++ if (phandlep) ++ *phandlep = phandle; ++ ++ return 0; ++} ++ + int fdtdec_setup(void) + { + #if CONFIG_IS_ENABLED(OF_CONTROL) + +From patchwork Thu Mar 21 18:10:03 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,06/13] fdtdec: Implement carveout support functions +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060373 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-7-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:03 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +The fdtdec_get_carveout() and fdtdec_set_carveout() function can be used +to read a carveout from a given node or add a carveout to a given node +using the standard device tree bindings (involving reserved-memory nodes +and the memory-region property). + +Reviewed-by: Simon Glass +Signed-off-by: Thierry Reding +--- +Changes in v3: +- add examples to code comments + +Changes in v2: +- use debug() instead of printf() to save code size +- fix carveout size computations, was off by one +- use fdtdec_get_addr_size_auto_noparent() + + include/fdtdec.h | 81 ++++++++++++++++++++++++++++++++++++++++++++ + lib/fdtdec.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 168 insertions(+) + +diff --git a/include/fdtdec.h b/include/fdtdec.h +index b54ed38fb362..13b743f59ab1 100644 +--- a/include/fdtdec.h ++++ b/include/fdtdec.h +@@ -1030,6 +1030,8 @@ int fdtdec_set_phandle(void *blob, int node, uint32_t phandle); + * The phandle returned from the function call can be used to reference this + * reserved memory region from other nodes. + * ++ * See fdtdec_set_carveout() for a more elaborate example. ++ * + * @param blob FDT blob + * @param basename base name of the node to create + * @param carveout information about the carveout region +@@ -1040,6 +1042,85 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, + const struct fdt_memory *carveout, + uint32_t *phandlep); + ++/** ++ * fdtdec_get_carveout() - reads a carveout from an FDT ++ * ++ * Reads information about a carveout region from an FDT. The carveout is a ++ * referenced by its phandle that is read from a given property in a given ++ * node. ++ * ++ * @param blob FDT blob ++ * @param node name of a node ++ * @param name name of the property in the given node that contains ++ * the phandle for the carveout ++ * @param index index of the phandle for which to read the carveout ++ * @param carveout return location for the carveout information ++ * @return 0 on success or a negative error code on failure ++ */ ++int fdtdec_get_carveout(const void *blob, const char *node, const char *name, ++ unsigned int index, struct fdt_memory *carveout); ++ ++/** ++ * fdtdec_set_carveout() - sets a carveout region for a given node ++ * ++ * Sets a carveout region for a given node. If a reserved-memory node already ++ * exists for the carveout, the phandle for that node will be reused. If no ++ * such node exists, a new one will be created and a phandle to it stored in ++ * a specified property of the given node. ++ * ++ * As an example, consider the following code snippet: ++ * ++ * const char *node = "/host1x@50000000/dc@54240000"; ++ * struct fdt_memory fb = { ++ * .start = 0x92cb3000, ++ * .end = 0x934b2fff, ++ * }; ++ * ++ * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", &fb); ++ * ++ * dc@54200000 is a display controller and was set up by the bootloader to ++ * scan out the framebuffer specified by "fb". This would cause the following ++ * reserved memory region to be added: ++ * ++ * reserved-memory { ++ * #address-cells = <0x00000002>; ++ * #size-cells = <0x00000002>; ++ * ranges; ++ * ++ * framebuffer@92cb3000 { ++ * reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>; ++ * phandle = <0x0000004d>; ++ * }; ++ * }; ++ * ++ * A "memory-region" property will also be added to the node referenced by the ++ * offset parameter. ++ * ++ * host1x@50000000 { ++ * ... ++ * ++ * dc@54240000 { ++ * ... ++ * memory-region = <0x0000004d>; ++ * ... ++ * }; ++ * ++ * ... ++ * }; ++ * ++ * @param blob FDT blob ++ * @param node name of the node to add the carveout to ++ * @param prop_name name of the property in which to store the phandle of ++ * the carveout ++ * @param index index of the phandle to store ++ * @param name base name of the reserved-memory node to create ++ * @param carveout information about the carveout to add ++ * @return 0 on success or a negative error code on failure ++ */ ++int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, ++ unsigned int index, const char *name, ++ const struct fdt_memory *carveout); ++ + /** + * Set up the device tree ready for use + */ +diff --git a/lib/fdtdec.c b/lib/fdtdec.c +index be54ad5bd092..bd05ab90fce1 100644 +--- a/lib/fdtdec.c ++++ b/lib/fdtdec.c +@@ -1381,6 +1381,93 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, + return 0; + } + ++int fdtdec_get_carveout(const void *blob, const char *node, const char *name, ++ unsigned int index, struct fdt_memory *carveout) ++{ ++ const fdt32_t *prop; ++ uint32_t phandle; ++ int offset, len; ++ fdt_size_t size; ++ ++ offset = fdt_path_offset(blob, node); ++ if (offset < 0) ++ return offset; ++ ++ prop = fdt_getprop(blob, offset, name, &len); ++ if (!prop) { ++ debug("failed to get %s for %s\n", name, node); ++ return -FDT_ERR_NOTFOUND; ++ } ++ ++ if ((len % sizeof(phandle)) != 0) { ++ debug("invalid phandle property\n"); ++ return -FDT_ERR_BADPHANDLE; ++ } ++ ++ if (len < (sizeof(phandle) * (index + 1))) { ++ debug("invalid phandle index\n"); ++ return -FDT_ERR_BADPHANDLE; ++ } ++ ++ phandle = fdt32_to_cpu(prop[index]); ++ ++ offset = fdt_node_offset_by_phandle(blob, phandle); ++ if (offset < 0) { ++ debug("failed to find node for phandle %u\n", phandle); ++ return offset; ++ } ++ ++ carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset, ++ "reg", 0, &size, ++ true); ++ if (carveout->start == FDT_ADDR_T_NONE) { ++ debug("failed to read address/size from \"reg\" property\n"); ++ return -FDT_ERR_NOTFOUND; ++ } ++ ++ carveout->end = carveout->start + size - 1; ++ ++ return 0; ++} ++ ++int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, ++ unsigned int index, const char *name, ++ const struct fdt_memory *carveout) ++{ ++ uint32_t phandle; ++ int err, offset; ++ fdt32_t value; ++ ++ /* XXX implement support for multiple phandles */ ++ if (index > 0) { ++ debug("invalid index %u\n", index); ++ return -FDT_ERR_BADOFFSET; ++ } ++ ++ err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle); ++ if (err < 0) { ++ debug("failed to add reserved memory: %d\n", err); ++ return err; ++ } ++ ++ offset = fdt_path_offset(blob, node); ++ if (offset < 0) { ++ debug("failed to find offset for node %s: %d\n", node, offset); ++ return offset; ++ } ++ ++ value = cpu_to_fdt32(phandle); ++ ++ err = fdt_setprop(blob, offset, prop_name, &value, sizeof(value)); ++ if (err < 0) { ++ debug("failed to set %s property for node %s: %d\n", prop_name, ++ node, err); ++ return err; ++ } ++ ++ return 0; ++} ++ + int fdtdec_setup(void) + { + #if CONFIG_IS_ENABLED(OF_CONTROL) + +From patchwork Thu Mar 21 18:10:04 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,07/13] fdtdec: Add Kconfig symbol for tests +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060374 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-8-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:04 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Runtime tests are provided as a test_fdtdec command implementation. Add +a Kconfig symbol that allows this command to be built so that the tests +can be used. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- +Changes in v2: +- new patch + + lib/Kconfig | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/lib/Kconfig b/lib/Kconfig +index 366d164cd760..b1fccf7e8dff 100644 +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -423,4 +423,8 @@ source lib/efi/Kconfig + source lib/efi_loader/Kconfig + source lib/optee/Kconfig + ++config TEST_FDTDEC ++ bool "enable fdtdec test" ++ depends on OF_LIBFDT ++ + endmenu + +From patchwork Thu Mar 21 18:10:05 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,08/13] fdtdec: test: Fix build warning +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060368 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-9-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:05 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Hide the declaration of the "fd" variable When not building a DEBUG +configuration, to avoid the variable being unused. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- +Changes in v2: +- new patch + + lib/fdtdec_test.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c +index a82e27de942f..065fed278cf3 100644 +--- a/lib/fdtdec_test.c ++++ b/lib/fdtdec_test.c +@@ -79,7 +79,9 @@ static int make_fdt(void *fdt, int size, const char *aliases, + { + char name[20], value[20]; + const char *s; ++#if defined(DEBUG) && defined(CONFIG_SANDBOX) + int fd; ++#endif + + CHECK(fdt_create(fdt, size)); + CHECK(fdt_finish_reservemap(fdt)); + +From patchwork Thu Mar 21 18:10:06 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,09/13] fdtdec: test: Use compound statement macros +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060361 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-10-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:06 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +This eliminates the need for intermediate helper functions and allow the +macros to return a value so that it can be used subsequently. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- +Changes in v2: +- new patch + + lib/fdtdec_test.c | 64 ++++++++++++++++------------------------------- + 1 file changed, 22 insertions(+), 42 deletions(-) + +diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c +index 065fed278cf3..928950918413 100644 +--- a/lib/fdtdec_test.c ++++ b/lib/fdtdec_test.c +@@ -15,48 +15,28 @@ + /* The size of our test fdt blob */ + #define FDT_SIZE (16 * 1024) + +-/** +- * Check if an operation failed, and if so, print an error +- * +- * @param oper_name Name of operation +- * @param err Error code to check +- * +- * @return 0 if ok, -1 if there was an error +- */ +-static int fdt_checkerr(const char *oper_name, int err) +-{ +- if (err) { +- printf("%s: %s: %s\n", __func__, oper_name, fdt_strerror(err)); +- return -1; +- } +- +- return 0; +-} +- +-/** +- * Check the result of an operation and if incorrect, print an error +- * +- * @param oper_name Name of operation +- * @param expected Expected value +- * @param value Actual value +- * +- * @return 0 if ok, -1 if there was an error +- */ +-static int checkval(const char *oper_name, int expected, int value) +-{ +- if (expected != value) { +- printf("%s: %s: expected %d, but returned %d\n", __func__, +- oper_name, expected, value); +- return -1; +- } +- +- return 0; +-} ++#define CHECK(op) ({ \ ++ int err = op; \ ++ if (err < 0) { \ ++ printf("%s: %s: %s\n", __func__, #op, \ ++ fdt_strerror(err)); \ ++ return err; \ ++ } \ ++ \ ++ err; \ ++ }) ++ ++#define CHECKVAL(op, expected) ({ \ ++ int err = op; \ ++ if (err != expected) { \ ++ printf("%s: %s: expected %d, but returned %d\n",\ ++ __func__, #op, expected, err); \ ++ return err; \ ++ } \ ++ \ ++ err; \ ++ }) + +-#define CHECK(op) if (fdt_checkerr(#op, op)) return -1 +-#define CHECKVAL(op, expected) \ +- if (checkval(#op, expected, op)) \ +- return -1 + #define CHECKOK(op) CHECKVAL(op, 0) + + /* maximum number of nodes / aliases to generate */ +@@ -138,7 +118,7 @@ static int run_test(const char *aliases, const char *nodes, const char *expect) + CHECKVAL(make_fdt(blob, FDT_SIZE, aliases, nodes), 0); + CHECKVAL(fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_UNKNOWN, +- list, ARRAY_SIZE(list)), strlen(expect)); ++ list, ARRAY_SIZE(list)), (int)strlen(expect)); + + /* Check we got the right ones */ + for (i = 0, s = expect; *s; s++, i++) { + +From patchwork Thu Mar 21 18:10:07 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,10/13] fdtdec: test: Add carveout tests +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060375 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-11-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:07 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Implement carveout tests for 32-bit and 64-bit builds. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- +Changes in v2: +- new patch + + lib/fdtdec_test.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 152 insertions(+) + +diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c +index 928950918413..f6defe16c5a6 100644 +--- a/lib/fdtdec_test.c ++++ b/lib/fdtdec_test.c +@@ -141,6 +141,156 @@ static int run_test(const char *aliases, const char *nodes, const char *expect) + return 0; + } + ++static int make_fdt_carveout_device(void *fdt, uint32_t na, uint32_t ns) ++{ ++ const char *basename = "/display"; ++ struct fdt_memory carveout = { ++#ifdef CONFIG_PHYS_64BIT ++ .start = 0x180000000, ++ .end = 0x18fffffff, ++#else ++ .start = 0x80000000, ++ .end = 0x8fffffff, ++#endif ++ }; ++ fdt32_t cells[4], *ptr = cells; ++ uint32_t upper, lower; ++ char name[32]; ++ int offset; ++ ++ /* store one or two address cells */ ++ lower = fdt_addr_unpack(carveout.start, &upper); ++ ++ if (na > 1 && upper > 0) ++ snprintf(name, sizeof(name), "%s@%x,%x", basename, upper, ++ lower); ++ else ++ snprintf(name, sizeof(name), "%s@%x", basename, lower); ++ ++ if (na > 1) ++ *ptr++ = cpu_to_fdt32(upper); ++ ++ *ptr++ = cpu_to_fdt32(lower); ++ ++ /* store one or two size cells */ ++ lower = fdt_size_unpack(carveout.end - carveout.start + 1, &upper); ++ ++ if (ns > 1) ++ *ptr++ = cpu_to_fdt32(upper); ++ ++ *ptr++ = cpu_to_fdt32(lower); ++ ++ offset = CHECK(fdt_add_subnode(fdt, 0, name + 1)); ++ CHECK(fdt_setprop(fdt, offset, "reg", cells, (na + ns) * sizeof(*cells))); ++ ++ return fdtdec_set_carveout(fdt, name, "memory-region", 0, ++ "framebuffer", &carveout); ++} ++ ++static int check_fdt_carveout(void *fdt, uint32_t address_cells, ++ uint32_t size_cells) ++{ ++#ifdef CONFIG_PHYS_64BIT ++ const char *name = "/display@1,80000000"; ++ const struct fdt_memory expected = { ++ .start = 0x180000000, ++ .end = 0x18fffffff, ++ }; ++#else ++ const char *name = "/display@80000000"; ++ const struct fdt_memory expected = { ++ .start = 0x80000000, ++ .end = 0x8fffffff, ++ }; ++#endif ++ struct fdt_memory carveout; ++ ++ printf("carveout: %pap-%pap na=%u ns=%u: ", &expected.start, ++ &expected.end, address_cells, size_cells); ++ ++ CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout)); ++ ++ if ((carveout.start != expected.start) || ++ (carveout.end != expected.end)) { ++ printf("carveout: %pap-%pap, expected %pap-%pap\n", ++ &carveout.start, &carveout.end, ++ &expected.start, &expected.end); ++ return 1; ++ } ++ ++ printf("pass\n"); ++ return 0; ++} ++ ++static int make_fdt_carveout(void *fdt, int size, uint32_t address_cells, ++ uint32_t size_cells) ++{ ++ fdt32_t na = cpu_to_fdt32(address_cells); ++ fdt32_t ns = cpu_to_fdt32(size_cells); ++#if defined(DEBUG) && defined(CONFIG_SANDBOX) ++ char filename[512]; ++ int fd; ++#endif ++ int err; ++ ++ CHECK(fdt_create(fdt, size)); ++ CHECK(fdt_finish_reservemap(fdt)); ++ CHECK(fdt_begin_node(fdt, "")); ++ CHECK(fdt_property(fdt, "#address-cells", &na, sizeof(na))); ++ CHECK(fdt_property(fdt, "#size-cells", &ns, sizeof(ns))); ++ CHECK(fdt_end_node(fdt)); ++ CHECK(fdt_finish(fdt)); ++ CHECK(fdt_pack(fdt)); ++ ++ CHECK(fdt_open_into(fdt, fdt, FDT_SIZE)); ++ ++ err = make_fdt_carveout_device(fdt, address_cells, size_cells); ++ ++#if defined(DEBUG) && defined(CONFIG_SANDBOX) ++ snprintf(filename, sizeof(filename), "/tmp/fdtdec-carveout-%u-%u.dtb", ++ address_cells, size_cells); ++ ++ fd = os_open(filename, OS_O_CREAT | OS_O_WRONLY); ++ if (fd < 0) { ++ printf("could not open .dtb file to write\n"); ++ goto out; ++ } ++ ++ os_write(fd, fdt, size); ++ os_close(fd); ++ ++out: ++#endif ++ return err; ++} ++ ++static int check_carveout(void) ++{ ++ void *fdt; ++ ++ fdt = malloc(FDT_SIZE); ++ if (!fdt) { ++ printf("%s: out of memory\n", __func__); ++ return 1; ++ } ++ ++#ifndef CONFIG_PHYS_64BIT ++ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 1), 0); ++ CHECKOK(check_fdt_carveout(fdt, 1, 1)); ++ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 2), 0); ++ CHECKOK(check_fdt_carveout(fdt, 1, 2)); ++#else ++ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 1), -FDT_ERR_BADVALUE); ++ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 1, 2), -FDT_ERR_BADVALUE); ++#endif ++ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 2, 1), 0); ++ CHECKOK(check_fdt_carveout(fdt, 2, 1)); ++ CHECKVAL(make_fdt_carveout(fdt, FDT_SIZE, 2, 2), 0); ++ CHECKOK(check_fdt_carveout(fdt, 2, 2)); ++ ++ return 0; ++} ++ + static int do_test_fdtdec(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) + { +@@ -182,6 +332,8 @@ static int do_test_fdtdec(cmd_tbl_t *cmdtp, int flag, int argc, + CHECKOK(run_test("2a 1a 0a", "a", " a")); + CHECKOK(run_test("0a 1a 2a", "a", "a")); + ++ CHECKOK(check_carveout()); ++ + printf("Test passed\n"); + return 0; + } + +From patchwork Thu Mar 21 18:10:08 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,11/13] sandbox: Enable fdtdec tests +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060364 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-12-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:08 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Enable fdtdec tests on sandbox configurations so that they can be run to +validate the fdtdec implementation. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- +Changes in v2: +- new patch + + configs/sandbox64_defconfig | 1 + + configs/sandbox_defconfig | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig +index da4bdced3105..c04ecd915ae7 100644 +--- a/configs/sandbox64_defconfig ++++ b/configs/sandbox64_defconfig +@@ -194,6 +194,7 @@ CONFIG_CMD_DHRYSTONE=y + CONFIG_TPM=y + CONFIG_LZ4=y + CONFIG_ERRNO_STR=y ++CONFIG_TEST_FDTDEC=y + CONFIG_UNIT_TEST=y + CONFIG_UT_TIME=y + CONFIG_UT_DM=y +diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig +index 193e41896cb7..bb508a8d02e2 100644 +--- a/configs/sandbox_defconfig ++++ b/configs/sandbox_defconfig +@@ -215,6 +215,7 @@ CONFIG_CMD_DHRYSTONE=y + CONFIG_TPM=y + CONFIG_LZ4=y + CONFIG_ERRNO_STR=y ++CONFIG_TEST_FDTDEC=y + CONFIG_UNIT_TEST=y + CONFIG_UT_TIME=y + CONFIG_UT_DM=y + +From patchwork Thu Mar 21 18:10:09 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,12/13] p2371-2180: Add support for framebuffer carveouts +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060367 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-13-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:09 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +If early firmware initialized the display hardware and the display +controllers are scanning out a framebuffer (e.g. a splash screen), make +sure to pass information about the memory location of that framebuffer +to the kernel before booting to avoid the kernel from using that memory +for the buddy allocator. + +This same mechanism can also be used in the kernel to set up early SMMU +mappings and avoid SMMU faults caused by the display controller reading +from memory for which it has no mapping. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- + board/nvidia/p2371-2180/p2371-2180.c | 47 ++++++++++++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c +index a444d692d7ea..4985302d6bc2 100644 +--- a/board/nvidia/p2371-2180/p2371-2180.c ++++ b/board/nvidia/p2371-2180/p2371-2180.c +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -138,9 +139,55 @@ static void ft_mac_address_setup(void *fdt) + } + } + ++static int ft_copy_carveout(void *dst, const void *src, const char *node) ++{ ++ struct fdt_memory fb; ++ int err; ++ ++ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); ++ if (err < 0) { ++ if (err != -FDT_ERR_NOTFOUND) ++ printf("failed to get carveout for %s: %d\n", node, ++ err); ++ ++ return err; ++ } ++ ++ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", ++ &fb); ++ if (err < 0) { ++ printf("failed to set carveout for %s: %d\n", node, err); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void ft_carveout_setup(void *fdt) ++{ ++ const void *cboot_fdt = (const void *)cboot_boot_x0; ++ static const char * const nodes[] = { ++ "/host1x@50000000/dc@54200000", ++ "/host1x@50000000/dc@54240000", ++ }; ++ unsigned int i; ++ int err; ++ ++ for (i = 0; i < ARRAY_SIZE(nodes); i++) { ++ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); ++ if (err < 0) { ++ if (err != -FDT_ERR_NOTFOUND) ++ printf("failed to copy carveout for %s: %d\n", ++ nodes[i], err); ++ continue; ++ } ++ } ++} ++ + int ft_board_setup(void *fdt, bd_t *bd) + { + ft_mac_address_setup(fdt); ++ ft_carveout_setup(fdt); + + return 0; + } + +From patchwork Thu Mar 21 18:10:10 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,13/13] p2771-0000: Add support for framebuffer carveouts +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060363 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321181010.27005-14-thierry.reding@gmail.com> +To: Tom Warren , + Simon Glass +Cc: u-boot@lists.denx.de, Stephen Warren +Date: Thu, 21 Mar 2019 19:10:10 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +If early firmware initialized the display hardware and the display +controllers are scanning out a framebuffer (e.g. a splash screen), make +sure to pass information about the memory location of that framebuffer +to the kernel before booting to avoid the kernel from using that memory +for the buddy allocator. + +This same mechanism can also be used in the kernel to set up early SMMU +mappings and avoid SMMU faults caused by the display controller reading +from memory for which it has no mapping. + +Signed-off-by: Thierry Reding +Reviewed-by: Simon Glass +--- + board/nvidia/p2771-0000/p2771-0000.c | 66 ++++++++++++++++++++++++++-- + 1 file changed, 62 insertions(+), 4 deletions(-) + +diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c +index fe22067f6571..d294c7ae0136 100644 +--- a/board/nvidia/p2771-0000/p2771-0000.c ++++ b/board/nvidia/p2771-0000/p2771-0000.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -56,7 +57,7 @@ int tegra_pcie_board_init(void) + } + #endif + +-int ft_board_setup(void *fdt, bd_t *bd) ++static void ft_mac_address_setup(void *fdt) + { + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; +@@ -69,13 +70,15 @@ int ft_board_setup(void *fdt, bd_t *bd) + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) +- return 0; ++ return; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); +- if (offset < 0) +- return 0; ++ if (offset < 0) { ++ printf("ethernet alias points to absent node %s\n", path); ++ return; ++ } + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, +@@ -92,6 +95,61 @@ int ft_board_setup(void *fdt, bd_t *bd) + debug("MAC address set: %pM\n", mac); + } + } ++} ++ ++static int ft_copy_carveout(void *dst, const void *src, const char *node) ++{ ++ struct fdt_memory fb; ++ int err; ++ ++ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); ++ if (err < 0) { ++ if (err != -FDT_ERR_NOTFOUND) ++ printf("failed to get carveout for %s: %d\n", node, ++ err); ++ ++ return err; ++ } ++ ++ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", ++ &fb); ++ if (err < 0) { ++ printf("failed to set carveout for %s: %d\n", node, err); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void ft_carveout_setup(void *fdt) ++{ ++ const void *cboot_fdt = (const void *)cboot_boot_x0; ++ static const char * const nodes[] = { ++ "/host1x@13e00000/display-hub@15200000/display@15200000", ++ "/host1x@13e00000/display-hub@15200000/display@15210000", ++ "/host1x@13e00000/display-hub@15200000/display@15220000", ++ }; ++ unsigned int i; ++ int err; ++ ++ for (i = 0; i < ARRAY_SIZE(nodes); i++) { ++ printf("copying carveout for %s...\n", nodes[i]); ++ ++ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); ++ if (err < 0) { ++ if (err != -FDT_ERR_NOTFOUND) ++ printf("failed to copy carveout for %s: %d\n", ++ nodes[i], err); ++ ++ continue; ++ } ++ } ++} ++ ++int ft_board_setup(void *fdt, bd_t *bd) ++{ ++ ft_mac_address_setup(fdt); ++ ft_carveout_setup(fdt); + + return 0; + } diff --git a/ARM-tegra-Miscellaneous-improvements.patch b/ARM-tegra-Miscellaneous-improvements.patch new file mode 100644 index 0000000..61790a1 --- /dev/null +++ b/ARM-tegra-Miscellaneous-improvements.patch @@ -0,0 +1,2949 @@ +From patchwork Thu Mar 21 18:01:00 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,01/19] ARM: tegra: Use common header for PMU declarations +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060337 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-2-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:00 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +There's no need to replicate the pmu.h header file for every Tegra SoC +generation. Use a single header that is shared across generations. + +Signed-off-by: Thierry Reding +--- + .../include/asm/{arch-tegra20 => arch-tegra}/pmu.h | 6 +++--- + arch/arm/include/asm/arch-tegra114/pmu.h | 12 ------------ + arch/arm/include/asm/arch-tegra124/pmu.h | 13 ------------- + arch/arm/include/asm/arch-tegra210/pmu.h | 13 ------------- + arch/arm/include/asm/arch-tegra30/pmu.h | 12 ------------ + arch/arm/mach-tegra/board2.c | 2 +- + arch/arm/mach-tegra/emc.c | 2 +- + 7 files changed, 5 insertions(+), 55 deletions(-) + rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/pmu.h (73%) + delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h + delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h + delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h + delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h + +diff --git a/arch/arm/include/asm/arch-tegra20/pmu.h b/arch/arm/include/asm/arch-tegra/pmu.h +similarity index 73% +rename from arch/arm/include/asm/arch-tegra20/pmu.h +rename to arch/arm/include/asm/arch-tegra/pmu.h +index 18766dfed2bb..e850875d3166 100644 +--- a/arch/arm/include/asm/arch-tegra20/pmu.h ++++ b/arch/arm/include/asm/arch-tegra/pmu.h +@@ -4,10 +4,10 @@ + * NVIDIA Corporation + */ + +-#ifndef _ARCH_PMU_H_ +-#define _ARCH_PMU_H_ ++#ifndef _TEGRA_PMU_H_ ++#define _TEGRA_PMU_H_ + + /* Set core and CPU voltages to nominal levels */ + int pmu_set_nominal(void); + +-#endif /* _ARCH_PMU_H_ */ ++#endif /* _TEGRA_PMU_H_ */ +diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h +deleted file mode 100644 +index 1e571ee7b317..000000000000 +--- a/arch/arm/include/asm/arch-tegra114/pmu.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +- */ +- +-#ifndef _TEGRA114_PMU_H_ +-#define _TEGRA114_PMU_H_ +- +-/* Set core and CPU voltages to nominal levels */ +-int pmu_set_nominal(void); +- +-#endif /* _TEGRA114_PMU_H_ */ +diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h +deleted file mode 100644 +index c38393edefda..000000000000 +--- a/arch/arm/include/asm/arch-tegra124/pmu.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2010-2013 +- * NVIDIA Corporation +- */ +- +-#ifndef _TEGRA124_PMU_H_ +-#define _TEGRA124_PMU_H_ +- +-/* Set core and CPU voltages to nominal levels */ +-int pmu_set_nominal(void); +- +-#endif /* _TEGRA124_PMU_H_ */ +diff --git a/arch/arm/include/asm/arch-tegra210/pmu.h b/arch/arm/include/asm/arch-tegra210/pmu.h +deleted file mode 100644 +index 6ea36aa41876..000000000000 +--- a/arch/arm/include/asm/arch-tegra210/pmu.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * (C) Copyright 2010-2015 +- * NVIDIA Corporation +- */ +- +-#ifndef _TEGRA210_PMU_H_ +-#define _TEGRA210_PMU_H_ +- +-/* Set core and CPU voltages to nominal levels */ +-int pmu_set_nominal(void); +- +-#endif /* _TEGRA210_PMU_H_ */ +diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h +deleted file mode 100644 +index a823f0fbfc61..000000000000 +--- a/arch/arm/include/asm/arch-tegra30/pmu.h ++++ /dev/null +@@ -1,12 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. +- */ +- +-#ifndef _TEGRA30_PMU_H_ +-#define _TEGRA30_PMU_H_ +- +-/* Set core and CPU voltages to nominal levels */ +-int pmu_set_nominal(void); +- +-#endif /* _TEGRA30_PMU_H_ */ +diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c +index 12257a42b51b..b8d5ef0322cb 100644 +--- a/arch/arm/mach-tegra/board2.c ++++ b/arch/arm/mach-tegra/board2.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -24,7 +25,6 @@ + #include + #include + #include +-#include + #include + #ifdef CONFIG_TEGRA_CLOCK_SCALING + #include +diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c +index 6697909d9a3e..66628933b653 100644 +--- a/arch/arm/mach-tegra/emc.c ++++ b/arch/arm/mach-tegra/emc.c +@@ -8,10 +8,10 @@ + #include + #include + #include +-#include + #include + #include + #include ++#include + #include + + DECLARE_GLOBAL_DATA_PTR; + +From patchwork Thu Mar 21 18:01:01 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,02/19] ARM: tegra: Guard clock code with a Kconfig symbol +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060347 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-3-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:01 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Clock code is not relevant on all Tegra SoC generations, so guard it +with a Kconfig symbol that can be selected by the generations that need +it. + +This is in preparation for unifying Tegra186 code with the code used on +older generations. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Kconfig | 5 +++++ + arch/arm/mach-tegra/Makefile | 2 +- + arch/arm/mach-tegra/board.c | 2 ++ + arch/arm/mach-tegra/board2.c | 12 ++++++++++-- + 4 files changed, 18 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index 86b1cd11f752..ee078fec9adc 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -12,6 +12,9 @@ config SPL_LIBGENERIC_SUPPORT + config SPL_SERIAL_SUPPORT + default y + ++config TEGRA_CLKRST ++ bool ++ + config TEGRA_IVC + bool "Tegra IVC protocol" + help +@@ -55,6 +58,7 @@ config TEGRA_ARMV7_COMMON + select SPL + select SPL_BOARD_INIT if SPL + select SUPPORT_SPL ++ select TEGRA_CLKRST + select TEGRA_COMMON + select TEGRA_GPIO + select TEGRA_NO_BPMP +@@ -100,6 +104,7 @@ config TEGRA124 + config TEGRA210 + bool "Tegra210 family" + select TEGRA_ARMV8_COMMON ++ select TEGRA_CLKRST + select TEGRA_GPIO + select TEGRA_NO_BPMP + +diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile +index d4b4666fb1e2..0e812818d7a2 100644 +--- a/arch/arm/mach-tegra/Makefile ++++ b/arch/arm/mach-tegra/Makefile +@@ -16,7 +16,7 @@ endif + obj-y += ap.o + obj-y += board.o board2.o + obj-y += cache.o +-obj-y += clock.o ++obj-$(CONFIG_TEGRA_CLKRST) += clock.o + obj-y += pinmux-common.o + obj-y += powergate.o + obj-y += xusb-padctl-dummy.o +diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c +index f8fc042a1dcc..ecd5001de4c5 100644 +--- a/arch/arm/mach-tegra/board.c ++++ b/arch/arm/mach-tegra/board.c +@@ -9,7 +9,9 @@ + #include + #include + #include ++#if IS_ENABLED(CONFIG_TEGRA_CLKRST) + #include ++#endif + #include + #include + #include +diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c +index b8d5ef0322cb..b94077221f77 100644 +--- a/arch/arm/mach-tegra/board2.c ++++ b/arch/arm/mach-tegra/board2.c +@@ -22,7 +22,9 @@ + #include + #include + #include ++#if IS_ENABLED(CONFIG_TEGRA_CLKRST) + #include ++#endif + #include + #include + #include +@@ -109,8 +111,10 @@ int board_init(void) + __maybe_unused int board_id; + + /* Do clocks and UART first so that printf() works */ ++#if IS_ENABLED(CONFIG_TEGRA_CLKRST) + clock_init(); + clock_verify(); ++#endif + + tegra_gpu_config(); + +@@ -181,8 +185,10 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); + + int board_early_init_f(void) + { ++#if IS_ENABLED(CONFIG_TEGRA_CLKRST) + if (!clock_early_init_done()) + clock_early_init(); ++#endif + + #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) + #define USBCMD_FS2 (1 << 15) +@@ -193,10 +199,12 @@ int board_early_init_f(void) + #endif + + /* Do any special system timer/TSC setup */ +-#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) ++#if IS_ENABLED(CONFIG_TEGRA_CLKRST) ++# if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) + if (!tegra_cpu_is_non_secure()) +-#endif ++# endif + arch_timer_init(); ++#endif + + pinmux_init(); + board_init_uart_f(); + +From patchwork Thu Mar 21 18:01:02 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 03/19] ARM: tegra: Guard GP pad control code with a Kconfig symbol +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060338 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-4-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:02 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +The GP pad control code is not relevant on all Tegra SoC generations, so +guard it with a Kconfig symbol that can be selected by the generations +that need it. + +This is in preparation for unifying Tegra186 code with the code used on +older generations. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Kconfig | 5 +++++ + arch/arm/mach-tegra/Makefile | 2 +- + arch/arm/mach-tegra/cache.c | 2 ++ + 3 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index ee078fec9adc..265051b18aaf 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -15,6 +15,9 @@ config SPL_SERIAL_SUPPORT + config TEGRA_CLKRST + bool + ++config TEGRA_GP_PADCTRL ++ bool ++ + config TEGRA_IVC + bool "Tegra IVC protocol" + help +@@ -61,6 +64,7 @@ config TEGRA_ARMV7_COMMON + select TEGRA_CLKRST + select TEGRA_COMMON + select TEGRA_GPIO ++ select TEGRA_GP_PADCTRL + select TEGRA_NO_BPMP + + config TEGRA_ARMV8_COMMON +@@ -106,6 +110,7 @@ config TEGRA210 + select TEGRA_ARMV8_COMMON + select TEGRA_CLKRST + select TEGRA_GPIO ++ select TEGRA_GP_PADCTRL + select TEGRA_NO_BPMP + + config TEGRA186 +diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile +index 0e812818d7a2..69f802c01b45 100644 +--- a/arch/arm/mach-tegra/Makefile ++++ b/arch/arm/mach-tegra/Makefile +@@ -13,7 +13,7 @@ else + obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o + endif + +-obj-y += ap.o ++obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o + obj-y += board.o board2.o + obj-y += cache.o + obj-$(CONFIG_TEGRA_CLKRST) += clock.o +diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c +index be414e4e4aca..d7063490e222 100644 +--- a/arch/arm/mach-tegra/cache.c ++++ b/arch/arm/mach-tegra/cache.c +@@ -8,7 +8,9 @@ + #include + #include + #include ++#if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL) + #include ++#endif + + #ifndef CONFIG_ARM64 + void config_cache(void) + +From patchwork Thu Mar 21 18:01:03 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 04/19] ARM: tegra: Guard memory controller code with a Kconfig symbol +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060339 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-5-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:03 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Memory controller code is not relevant on all Tegra SoC generations, so +guard it with a Kconfig symbol that can be selected by the generations +that need it. + +This is in preparation for unifying Tegra186 code with the code used on +older generations. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Kconfig | 5 +++++ + arch/arm/mach-tegra/board.c | 7 +++++++ + 2 files changed, 12 insertions(+) + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index 265051b18aaf..5763c4ae3cd1 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -26,6 +26,9 @@ config TEGRA_IVC + U-Boot, it is typically used for communication between the main CPU + and various auxiliary processors. + ++config TEGRA_MC ++ bool ++ + config TEGRA_COMMON + bool "Tegra common options" + select BINMAN +@@ -65,6 +68,7 @@ config TEGRA_ARMV7_COMMON + select TEGRA_COMMON + select TEGRA_GPIO + select TEGRA_GP_PADCTRL ++ select TEGRA_MC + select TEGRA_NO_BPMP + + config TEGRA_ARMV8_COMMON +@@ -111,6 +115,7 @@ config TEGRA210 + select TEGRA_CLKRST + select TEGRA_GPIO + select TEGRA_GP_PADCTRL ++ select TEGRA_MC + select TEGRA_NO_BPMP + + config TEGRA186 +diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c +index ecd5001de4c5..7ef5a67edd1f 100644 +--- a/arch/arm/mach-tegra/board.c ++++ b/arch/arm/mach-tegra/board.c +@@ -13,7 +13,9 @@ + #include + #endif + #include ++#if IS_ENABLED(CONFIG_TEGRA_MC) + #include ++#endif + #include + #include + #include +@@ -68,6 +70,7 @@ bool tegra_cpu_is_non_secure(void) + } + #endif + ++#if IS_ENABLED(CONFIG_TEGRA_MC) + /* Read the RAM size directly from the memory controller */ + static phys_size_t query_sdram_size(void) + { +@@ -117,11 +120,15 @@ static phys_size_t query_sdram_size(void) + + return size_bytes; + } ++#endif + + int dram_init(void) + { ++#if IS_ENABLED(CONFIG_TEGRA_MC) + /* We do not initialise DRAM here. We just query the size */ + gd->ram_size = query_sdram_size(); ++#endif ++ + return 0; + } + + +From patchwork Thu Mar 21 18:01:04 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 05/19] ARM: tegra: Guard pin controller code with a Kconfig symbol +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060345 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-6-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:04 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Pin controller code is not relevant on all Tegra SoC generations, so +guard it with a Kconfig symbol that can be selected by the generations +that need it. + +This is in preparation for unifying Tegra186 code with the code used on +older generations. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Kconfig | 5 +++++ + arch/arm/mach-tegra/Makefile | 2 +- + arch/arm/mach-tegra/board.c | 6 ++++++ + arch/arm/mach-tegra/board2.c | 2 ++ + 4 files changed, 14 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index 5763c4ae3cd1..be20ac2e804e 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -29,6 +29,9 @@ config TEGRA_IVC + config TEGRA_MC + bool + ++config TEGRA_PINCTRL ++ bool ++ + config TEGRA_COMMON + bool "Tegra common options" + select BINMAN +@@ -70,6 +73,7 @@ config TEGRA_ARMV7_COMMON + select TEGRA_GP_PADCTRL + select TEGRA_MC + select TEGRA_NO_BPMP ++ select TEGRA_PINCTRL + + config TEGRA_ARMV8_COMMON + bool "Tegra 64-bit common options" +@@ -117,6 +121,7 @@ config TEGRA210 + select TEGRA_GP_PADCTRL + select TEGRA_MC + select TEGRA_NO_BPMP ++ select TEGRA_PINCTRL + + config TEGRA186 + bool "Tegra186 family" +diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile +index 69f802c01b45..395e0191a458 100644 +--- a/arch/arm/mach-tegra/Makefile ++++ b/arch/arm/mach-tegra/Makefile +@@ -17,7 +17,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o + obj-y += board.o board2.o + obj-y += cache.o + obj-$(CONFIG_TEGRA_CLKRST) += clock.o +-obj-y += pinmux-common.o ++obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o + obj-y += powergate.o + obj-y += xusb-padctl-dummy.o + endif +diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c +index 7ef5a67edd1f..b65bdde5a78d 100644 +--- a/arch/arm/mach-tegra/board.c ++++ b/arch/arm/mach-tegra/board.c +@@ -12,7 +12,9 @@ + #if IS_ENABLED(CONFIG_TEGRA_CLKRST) + #include + #endif ++#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) + #include ++#endif + #if IS_ENABLED(CONFIG_TEGRA_MC) + #include + #endif +@@ -132,6 +134,7 @@ int dram_init(void) + return 0; + } + ++#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) + static int uart_configs[] = { + #if defined(CONFIG_TEGRA20) + #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) +@@ -199,9 +202,11 @@ static void setup_uarts(int uart_ids) + } + } + } ++#endif + + void board_init_uart_f(void) + { ++#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) + int uart_ids = 0; /* bit mask of which UART ids to enable */ + + #ifdef CONFIG_TEGRA_ENABLE_UARTA +@@ -220,6 +225,7 @@ void board_init_uart_f(void) + uart_ids |= UARTE; + #endif + setup_uarts(uart_ids); ++#endif + } + + #if !CONFIG_IS_ENABLED(OF_CONTROL) +diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c +index b94077221f77..ce1c9346959d 100644 +--- a/arch/arm/mach-tegra/board2.c ++++ b/arch/arm/mach-tegra/board2.c +@@ -25,8 +25,10 @@ + #if IS_ENABLED(CONFIG_TEGRA_CLKRST) + #include + #endif ++#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) + #include + #include ++#endif + #include + #ifdef CONFIG_TEGRA_CLOCK_SCALING + #include + +From patchwork Thu Mar 21 18:01:05 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 06/19] ARM: tegra: Guard powergate code with a Kconfig symbol +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060355 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-7-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:05 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Powergate code is not relevant on all Tegra SoC generations, so guard it +with a Kconfig symbol that can be selected by the generations that need +it. + +This is in preparation for unifying Tegra186 code with the code used on +older generations. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Kconfig | 5 +++++ + arch/arm/mach-tegra/Makefile | 2 +- + 2 files changed, 6 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index be20ac2e804e..db9198348d3f 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -32,6 +32,9 @@ config TEGRA_MC + config TEGRA_PINCTRL + bool + ++config TEGRA_PMC ++ bool ++ + config TEGRA_COMMON + bool "Tegra common options" + select BINMAN +@@ -74,6 +77,7 @@ config TEGRA_ARMV7_COMMON + select TEGRA_MC + select TEGRA_NO_BPMP + select TEGRA_PINCTRL ++ select TEGRA_PMC + + config TEGRA_ARMV8_COMMON + bool "Tegra 64-bit common options" +@@ -122,6 +126,7 @@ config TEGRA210 + select TEGRA_MC + select TEGRA_NO_BPMP + select TEGRA_PINCTRL ++ select TEGRA_PMC + + config TEGRA186 + bool "Tegra186 family" +diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile +index 395e0191a458..517be21ee5f5 100644 +--- a/arch/arm/mach-tegra/Makefile ++++ b/arch/arm/mach-tegra/Makefile +@@ -18,7 +18,7 @@ obj-y += board.o board2.o + obj-y += cache.o + obj-$(CONFIG_TEGRA_CLKRST) += clock.o + obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o +-obj-y += powergate.o ++obj-$(CONFIG_TEGRA_PMC) += powergate.o + obj-y += xusb-padctl-dummy.o + endif + + +From patchwork Thu Mar 21 18:01:06 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,07/19] ARM: tegra: Fix save_boot_params() prototype +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060346 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-8-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:06 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +The save_boot_params() function takes as its first four arguments the +first four registers. On 32-bit ARM these are r0, r1, r2 and r3, all of +which are 32 bits wide. However, on 64-bit ARM thene registers are x0, +x1, x2 and x3, all of which are 64 bits wide. In order to allow reusing +the save_boot_params() implementation on 64-bit ARM, change it to take +unsigned long parameters rather than the fixed size 32-bit integers. +This ensures that the correct values are passed. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/board.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c +index b65bdde5a78d..59d2f347485d 100644 +--- a/arch/arm/mach-tegra/board.c ++++ b/arch/arm/mach-tegra/board.c +@@ -42,7 +42,8 @@ enum { + static bool from_spl __attribute__ ((section(".data"))); + + #ifndef CONFIG_SPL_BUILD +-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) ++void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, ++ unsigned long r3) + { + from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; + save_boot_params_ret(); + +From patchwork Thu Mar 21 18:01:07 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 08/19] ARM: tegra: Allow boards to override boot target devices +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060348 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-9-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:07 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Boards may not support all the boot target devices in the default list +for Tegra devices. Allow a board to override the list and default to the +standard list only if the board hasn't specified one itself. + +Signed-off-by: Thierry Reding +--- + include/configs/tegra-common-post.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h +index e54428ba43e2..9685ee5059ab 100644 +--- a/include/configs/tegra-common-post.h ++++ b/include/configs/tegra-common-post.h +@@ -21,12 +21,14 @@ + #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ + + #ifndef CONFIG_SPL_BUILD ++#ifndef BOOT_TARGET_DEVICES + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) ++#endif + #include + #else + #define BOOTENV + +From patchwork Thu Mar 21 18:01:08 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,09/19] ARM: tegra: Support TZ-only access to PMC +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060350 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-10-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:08 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Some devices may restrict access to the PMC to TrustZone software only. +Non-TZ software can detect this and use SMC calls to the firmware that +runs in the TrustZone to perform accesses to PMC registers. + +Note that this also fixes reset_cpu() and the enterrcm command on +Tegra186 where they were previously trying to access the PMC at a wrong +physical address. + +Based on work by Kalyani Chidambaram and Tom +Warren . + +Signed-off-by: Thierry Reding +--- + arch/arm/include/asm/arch-tegra/pmc.h | 20 +++++- + arch/arm/include/asm/arch-tegra/tegra.h | 6 ++ + arch/arm/mach-tegra/Kconfig | 5 ++ + arch/arm/mach-tegra/Makefile | 4 +- + arch/arm/mach-tegra/clock.c | 13 ++-- + arch/arm/mach-tegra/cmd_enterrcm.c | 6 +- + arch/arm/mach-tegra/cpu.c | 20 +++--- + arch/arm/mach-tegra/lowlevel_init.S | 39 ----------- + arch/arm/mach-tegra/pmc.c | 92 +++++++++++++++++++++++++ + arch/arm/mach-tegra/powergate.c | 11 +-- + 10 files changed, 151 insertions(+), 65 deletions(-) + delete mode 100644 arch/arm/mach-tegra/lowlevel_init.S + create mode 100644 arch/arm/mach-tegra/pmc.c + +diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h +index 34bbe75d5fdb..1524bf291164 100644 +--- a/arch/arm/include/asm/arch-tegra/pmc.h ++++ b/arch/arm/include/asm/arch-tegra/pmc.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + /* +- * (C) Copyright 2010-2015 ++ * (C) Copyright 2010-2019 + * NVIDIA Corporation + */ + +@@ -388,4 +388,22 @@ struct pmc_ctlr { + /* APBDEV_PMC_CNTRL2_0 0x440 */ + #define HOLD_CKE_LOW_EN (1 << 12) + ++/* PMC read/write functions */ ++u32 tegra_pmc_readl(unsigned long offset); ++void tegra_pmc_writel(u32 value, unsigned long offset); ++ ++#define PMC_CNTRL 0x0 ++#define PMC_CNTRL_MAIN_RST BIT(4) ++ ++#if IS_ENABLED(CONFIG_TEGRA186) ++# define PMC_SCRATCH0 0x32000 ++#else ++# define PMC_SCRATCH0 0x00050 ++#endif ++ ++/* for secure PMC */ ++#define TEGRA_SMC_PMC 0xc2fffe00 ++#define TEGRA_SMC_PMC_READ 0xaa ++#define TEGRA_SMC_PMC_WRITE 0xbb ++ + #endif /* PMC_H */ +diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h +index 7ae0129e2db3..7a4e0972fb76 100644 +--- a/arch/arm/include/asm/arch-tegra/tegra.h ++++ b/arch/arm/include/asm/arch-tegra/tegra.h +@@ -30,7 +30,13 @@ + #define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) + #define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) + #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) ++#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ ++ defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \ ++ defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210) + #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) ++#else ++#define NV_PA_PMC_BASE 0xc360000 ++#endif + #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) + #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) + #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index db9198348d3f..28914a34a1b5 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -35,6 +35,10 @@ config TEGRA_PINCTRL + config TEGRA_PMC + bool + ++config TEGRA_PMC_SECURE ++ bool ++ depends on TEGRA_PMC ++ + config TEGRA_COMMON + bool "Tegra common options" + select BINMAN +@@ -127,6 +131,7 @@ config TEGRA210 + select TEGRA_NO_BPMP + select TEGRA_PINCTRL + select TEGRA_PMC ++ select TEGRA_PMC_SECURE + + config TEGRA186 + bool "Tegra186 family" +diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile +index 517be21ee5f5..f8bc65aa8b18 100644 +--- a/arch/arm/mach-tegra/Makefile ++++ b/arch/arm/mach-tegra/Makefile +@@ -1,6 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0+ + # +-# (C) Copyright 2010-2015 Nvidia Corporation. ++# (C) Copyright 2010-2019 Nvidia Corporation. + # + # (C) Copyright 2000-2008 + # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +@@ -27,11 +27,11 @@ obj-y += dt-setup.o + obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o + obj-$(CONFIG_TEGRA_GPU) += gpu.o + obj-$(CONFIG_TEGRA_IVC) += ivc.o +-obj-y += lowlevel_init.o + ifndef CONFIG_SPL_BUILD + obj-$(CONFIG_ARMV7_PSCI) += psci.o + endif + obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o ++obj-y += pmc.o + + obj-$(CONFIG_TEGRA20) += tegra20/ + obj-$(CONFIG_TEGRA30) += tegra30/ +diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c +index 096330748f2b..c9cd4e6aaeb7 100644 +--- a/arch/arm/mach-tegra/clock.c ++++ b/arch/arm/mach-tegra/clock.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. ++ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. + */ + + /* Tegra SoC common clock control functions */ +@@ -814,11 +814,16 @@ void tegra30_set_up_pllp(void) + + int clock_external_output(int clk_id) + { +- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; ++ u32 val; + + if (clk_id >= 1 && clk_id <= 3) { +- setbits_le32(&pmc->pmc_clk_out_cntrl, +- 1 << (2 + (clk_id - 1) * 8)); ++ val = tegra_pmc_readl(offsetof(struct pmc_ctlr, ++ pmc_clk_out_cntrl)); ++ val |= 1 << (2 + (clk_id - 1) * 8); ++ tegra_pmc_writel(val, ++ offsetof(struct pmc_ctlr, ++ pmc_clk_out_cntrl)); ++ + } else { + printf("%s: Unknown output clock id %d\n", __func__, clk_id); + return -EINVAL; +diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c +index 4e6beb3e5bb4..4a889f0e3422 100644 +--- a/arch/arm/mach-tegra/cmd_enterrcm.c ++++ b/arch/arm/mach-tegra/cmd_enterrcm.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* +- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. ++ * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved. + * + * Derived from code (arch/arm/lib/reset.c) that is: + * +@@ -31,12 +31,10 @@ + static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) + { +- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; +- + puts("Entering RCM...\n"); + udelay(50000); + +- pmc->pmc_scratch0 = 2; ++ tegra_pmc_writel(2, PMC_SCRATCH0); + disable_interrupts(); + reset_cpu(0); + +diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c +index 1b6ad074ed8f..3d140760e68f 100644 +--- a/arch/arm/mach-tegra/cpu.c ++++ b/arch/arm/mach-tegra/cpu.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. ++ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. + */ + + #include +@@ -299,21 +299,19 @@ void enable_cpu_clock(int enable) + + static int is_cpu_powered(void) + { +- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; +- +- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; ++ return (tegra_pmc_readl(offsetof(struct pmc_ctlr, ++ pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0; + } + + static void remove_cpu_io_clamps(void) + { +- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + debug("%s entry\n", __func__); + + /* Remove the clamps on the CPU I/O signals */ +- reg = readl(&pmc->pmc_remove_clamping); ++ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping)); + reg |= CPU_CLMP; +- writel(reg, &pmc->pmc_remove_clamping); ++ tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping)); + + /* Give I/O signals time to stabilize */ + udelay(IO_STABILIZATION_DELAY); +@@ -321,17 +319,19 @@ static void remove_cpu_io_clamps(void) + + void powerup_cpu(void) + { +- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + int timeout = IO_STABILIZATION_DELAY; + debug("%s entry\n", __func__); + + if (!is_cpu_powered()) { + /* Toggle the CPU power state (OFF -> ON) */ +- reg = readl(&pmc->pmc_pwrgate_toggle); ++ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, ++ pmc_pwrgate_toggle)); + reg &= PARTID_CP; + reg |= START_CP; +- writel(reg, &pmc->pmc_pwrgate_toggle); ++ tegra_pmc_writel(reg, ++ offsetof(struct pmc_ctlr, ++ pmc_pwrgate_toggle)); + + /* Wait for the power to come up */ + while (!is_cpu_powered()) { +diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S +deleted file mode 100644 +index 626f1b642745..000000000000 +--- a/arch/arm/mach-tegra/lowlevel_init.S ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * SoC-specific setup info +- * +- * (C) Copyright 2010,2011 +- * NVIDIA Corporation +- */ +- +-#include +-#include +- +-#ifdef CONFIG_ARM64 +- .align 5 +-ENTRY(reset_cpu) +- /* get address for global reset register */ +- ldr x1, =PRM_RSTCTRL +- ldr w3, [x1] +- /* force reset */ +- orr w3, w3, #0x10 +- str w3, [x1] +- mov w0, w0 +-1: +- b 1b +-ENDPROC(reset_cpu) +-#else +- .align 5 +-ENTRY(reset_cpu) +- ldr r1, rstctl @ get addr for global reset +- @ reg +- ldr r3, [r1] +- orr r3, r3, #0x10 +- str r3, [r1] @ force reset +- mov r0, r0 +-_loop_forever: +- b _loop_forever +-rstctl: +- .word PRM_RSTCTRL +-ENDPROC(reset_cpu) +-#endif +diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c +new file mode 100644 +index 000000000000..afd3c54179c1 +--- /dev/null ++++ b/arch/arm/mach-tegra/pmc.c +@@ -0,0 +1,92 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. ++ */ ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) ++static bool tegra_pmc_detect_tz_only(void) ++{ ++ static bool initialized = false; ++ static bool is_tz_only = false; ++ u32 value, saved; ++ ++ if (!initialized) { ++ saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); ++ value = saved ^ 0xffffffff; ++ ++ if (value == 0xffffffff) ++ value = 0xdeadbeef; ++ ++ /* write pattern and read it back */ ++ writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0); ++ value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); ++ ++ /* if we read all-zeroes, access is restricted to TZ only */ ++ if (value == 0) { ++ debug("access to PMC is restricted to TZ\n"); ++ is_tz_only = true; ++ } else { ++ /* restore original value */ ++ writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0); ++ } ++ ++ initialized = true; ++ } ++ ++ return is_tz_only; ++} ++#endif ++ ++uint32_t tegra_pmc_readl(unsigned long offset) ++{ ++#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) ++ if (tegra_pmc_detect_tz_only()) { ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, ++ 0, 0, 0, &res); ++ if (res.a0) ++ printf("%s(): SMC failed: %lu\n", __func__, res.a0); ++ ++ return res.a1; ++ } ++#endif ++ ++ return readl(NV_PA_PMC_BASE + offset); ++} ++ ++void tegra_pmc_writel(u32 value, unsigned long offset) ++{ ++#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) ++ if (tegra_pmc_detect_tz_only()) { ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, ++ value, 0, 0, 0, 0, &res); ++ if (res.a0) ++ printf("%s(): SMC failed: %lu\n", __func__, res.a0); ++ ++ return; ++ } ++#endif ++ ++ writel(value, NV_PA_PMC_BASE + offset); ++} ++ ++void reset_cpu(ulong addr) ++{ ++ u32 value; ++ ++ value = tegra_pmc_readl(PMC_CNTRL); ++ value |= PMC_CNTRL_MAIN_RST; ++ tegra_pmc_writel(value, PMC_CNTRL); ++} +diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c +index e45f0961b242..761c9ef19e3b 100644 +--- a/arch/arm/mach-tegra/powergate.c ++++ b/arch/arm/mach-tegra/powergate.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. ++ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. + */ + + #include +@@ -11,6 +11,7 @@ + + #include + #include ++#include + + #define PWRGATE_TOGGLE 0x30 + #define PWRGATE_TOGGLE_START (1 << 8) +@@ -24,18 +25,18 @@ static int tegra_powergate_set(enum tegra_powergate id, bool state) + u32 value, mask = state ? (1 << id) : 0, old_mask; + unsigned long start, timeout = 25; + +- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); ++ value = tegra_pmc_readl(PWRGATE_STATUS); + old_mask = value & (1 << id); + + if (mask == old_mask) + return 0; + +- writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE); ++ tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); + + start = get_timer(0); + + while (get_timer(start) < timeout) { +- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); ++ value = tegra_pmc_readl(PWRGATE_STATUS); + if ((value & (1 << id)) == mask) + return 0; + } +@@ -69,7 +70,7 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) + else + value = 1 << id; + +- writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING); ++ tegra_pmc_writel(value, REMOVE_CLAMPING); + + return 0; + } + +From patchwork Thu Mar 21 18:01:09 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 10/19] ARM: tegra: Workaround UDC boot issues only if necessary +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060352 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-11-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:09 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Resetting the USB device controller on boot is only necessary if the SoC +actually has a UDC controller and U-Boot enables support for it. All the +Tegra boards support UDC via the ChipIdea UDC driver, so make the UDC on +boot workaround depend on the ChipIdea UDC driver. + +This prevents a crash on Tegra186 which does not have the ChipIdea UDC. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index 28914a34a1b5..faa73559fd42 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -148,6 +148,7 @@ endchoice + + config TEGRA_DISCONNECT_UDC_ON_BOOT + bool "Disconnect USB device mode controller on boot" ++ depends on CI_UDC + default y + help + When loading U-Boot into RAM over USB protocols using tools such as + +From patchwork Thu Mar 21 18:01:10 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,11/19] ARM: tegra: Restore DRAM bank count +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060341 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-12-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:10 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") reduced +the number of DRAM banks supported by U-Boot from 1026 to 8 on P2771-000 +boards. + +However, as explained in commit a9819b9e33bd ("ARM: tegra: p2771-000: +increase max DRAM bank count"), the platform can have a large number of +unusable chunks of memory (up to 1024), so a total of 1026 DRAM banks +are needed to describe the worst-case situation. + +In practice the number of DRAM banks needed will typically be much +lower, but we should be prepared to properly deal with the worst case. + +Signed-off-by: Thierry Reding +--- + configs/p2771-0000-000_defconfig | 2 +- + configs/p2771-0000-500_defconfig | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig +index ac85efa37b3b..ad0802067e73 100644 +--- a/configs/p2771-0000-000_defconfig ++++ b/configs/p2771-0000-000_defconfig +@@ -2,7 +2,7 @@ CONFIG_ARM=y + CONFIG_TEGRA=y + CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA186=y +-CONFIG_NR_DRAM_BANKS=8 ++CONFIG_NR_DRAM_BANKS=1026 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y +diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig +index df4d914d85cf..459b67fd195f 100644 +--- a/configs/p2771-0000-500_defconfig ++++ b/configs/p2771-0000-500_defconfig +@@ -2,7 +2,7 @@ CONFIG_ARM=y + CONFIG_TEGRA=y + CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA186=y +-CONFIG_NR_DRAM_BANKS=8 ++CONFIG_NR_DRAM_BANKS=1026 + CONFIG_OF_SYSTEM_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y + +From patchwork Thu Mar 21 18:01:11 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,12/19] ARM: tegra: Unify Tegra186 builds +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060344 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-13-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:11 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Tegra186 build are currently dealt with in very special ways, which is +because Tegra186 is fundamentally different in many respects. It is no +longer necessary to do many of the low-level programming because early +boot firmware will already have taken care of it. + +Unfortunately, separating Tegra186 builds from the rest in this way +makes it difficult to share code with prior generations of Tegra. With +all of the low-level programming code behind Kconfig guards, the build +for Tegra186 can again be unified. + +As a side-effect, and partial reason for this change, other Tegra SoC +generations can now make use of the code that deals with taking over a +boot from earlier bootloaders. This used to be nvtboot, but has been +replaced by cboot nowadays. Rename the files and functions related to +this to avoid confusion. The implemented protocols are unchanged. + +Signed-off-by: Thierry Reding +--- +Changes in v3: +- load cboot DTB address to fdt_addr instead of fdtaddr + + arch/arm/include/asm/arch-tegra/cboot.h | 39 ++++ + arch/arm/mach-tegra/Makefile | 4 +- + arch/arm/mach-tegra/board.c | 23 ++ + arch/arm/mach-tegra/board186.c | 32 --- + arch/arm/mach-tegra/board2.c | 21 ++ + .../{tegra186/nvtboot_board.c => cboot.c} | 200 ++++++++++++++++-- + .../{tegra186/nvtboot_ll.S => cboot_ll.S} | 12 +- + arch/arm/mach-tegra/tegra186/Makefile | 4 - + arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 172 --------------- + board/nvidia/p2771-0000/p2771-0000.c | 10 +- + 10 files changed, 278 insertions(+), 239 deletions(-) + create mode 100644 arch/arm/include/asm/arch-tegra/cboot.h + delete mode 100644 arch/arm/mach-tegra/board186.c + rename arch/arm/mach-tegra/{tegra186/nvtboot_board.c => cboot.c} (56%) + rename arch/arm/mach-tegra/{tegra186/nvtboot_ll.S => cboot_ll.S} (57%) + delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_mem.c + +diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h +new file mode 100644 +index 000000000000..b3441ec178b3 +--- /dev/null ++++ b/arch/arm/include/asm/arch-tegra/cboot.h +@@ -0,0 +1,39 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2019 NVIDIA Corporation. All rights reserved. ++ */ ++ ++#ifndef _TEGRA_CBOOT_H_ ++#define _TEGRA_CBOOT_H_ ++ ++#ifdef CONFIG_ARM64 ++extern unsigned long cboot_boot_x0; ++ ++void cboot_save_boot_params(unsigned long x0, unsigned long x1, ++ unsigned long x2, unsigned long x3); ++int cboot_dram_init(void); ++int cboot_dram_init_banksize(void); ++ulong cboot_get_usable_ram_top(ulong total_size); ++#else ++static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, ++ unsigned long x2, unsigned long x3) ++{ ++} ++ ++static inline int cboot_dram_init(void) ++{ ++ return -ENOSYS; ++} ++ ++static inline int cboot_dram_init_banksize(void) ++{ ++ return -ENOSYS; ++} ++ ++static inline ulong cboot_get_usable_ram_top(ulong total_size) ++{ ++ return 0; ++} ++#endif ++ ++#endif +diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile +index f8bc65aa8b18..41ba674edff4 100644 +--- a/arch/arm/mach-tegra/Makefile ++++ b/arch/arm/mach-tegra/Makefile +@@ -5,7 +5,6 @@ + # (C) Copyright 2000-2008 + # Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +-ifndef CONFIG_TEGRA186 + ifdef CONFIG_SPL_BUILD + obj-y += spl.o + obj-y += cpu.o +@@ -20,9 +19,8 @@ obj-$(CONFIG_TEGRA_CLKRST) += clock.o + obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o + obj-$(CONFIG_TEGRA_PMC) += powergate.o + obj-y += xusb-padctl-dummy.o +-endif + +-obj-$(CONFIG_ARM64) += arm64-mmu.o ++obj-$(CONFIG_ARM64) += arm64-mmu.o cboot_ll.o cboot.o + obj-y += dt-setup.o + obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o + obj-$(CONFIG_TEGRA_GPU) += gpu.o +diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c +index 59d2f347485d..c3ba00811e83 100644 +--- a/arch/arm/mach-tegra/board.c ++++ b/arch/arm/mach-tegra/board.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -46,6 +47,21 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) + { + from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; ++ ++ /* ++ * The logic for this is somewhat indirect. The purpose of the marker ++ * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot ++ * was loaded from a read-only instance of itself, which is something ++ * that can happen in secure boot setups. So basically the presence ++ * of the marker is an indication that U-Boot was loaded by one such ++ * special variant of U-Boot. Conversely, the absence of the marker ++ * indicates that this instance of U-Boot was loaded by something ++ * other than a special U-Boot. This could be SPL, but it could just ++ * as well be one of any number of other first stage bootloaders. ++ */ ++ if (from_spl) ++ cboot_save_boot_params(r0, r1, r2, r3); ++ + save_boot_params_ret(); + } + #endif +@@ -127,6 +143,13 @@ static phys_size_t query_sdram_size(void) + + int dram_init(void) + { ++ int err; ++ ++ /* try to initialize DRAM from cboot DTB first */ ++ err = cboot_dram_init(); ++ if (err == 0) ++ return 0; ++ + #if IS_ENABLED(CONFIG_TEGRA_MC) + /* We do not initialise DRAM here. We just query the size */ + gd->ram_size = query_sdram_size(); +diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c +deleted file mode 100644 +index 80b55707e90f..000000000000 +--- a/arch/arm/mach-tegra/board186.c ++++ /dev/null +@@ -1,32 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (c) 2016, NVIDIA CORPORATION. +- */ +- +-#include +-#include +- +-int board_early_init_f(void) +-{ +- return 0; +-} +- +-__weak int tegra_board_init(void) +-{ +- return 0; +-} +- +-int board_init(void) +-{ +- return tegra_board_init(); +-} +- +-__weak int tegra_soc_board_init_late(void) +-{ +- return 0; +-} +- +-int board_late_init(void) +-{ +- return tegra_soc_board_init_late(); +-} +diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c +index ce1c9346959d..bbc487aa3bf6 100644 +--- a/arch/arm/mach-tegra/board2.c ++++ b/arch/arm/mach-tegra/board2.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -51,6 +52,7 @@ __weak void pin_mux_mmc(void) {} + __weak void gpio_early_init_uart(void) {} + __weak void pin_mux_display(void) {} + __weak void start_cpu_fan(void) {} ++__weak void cboot_late_init(void) {} + + #if defined(CONFIG_TEGRA_NAND) + __weak void pin_mux_nand(void) +@@ -243,6 +245,7 @@ int board_late_init(void) + } + #endif + start_cpu_fan(); ++ cboot_late_init(); + + return 0; + } +@@ -337,6 +340,15 @@ static ulong usable_ram_size_below_4g(void) + */ + int dram_init_banksize(void) + { ++ int err; ++ ++ /* try to compute DRAM bank size based on cboot DTB first */ ++ err = cboot_dram_init_banksize(); ++ if (err == 0) ++ return err; ++ ++ /* fall back to default DRAM bank size computation */ ++ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); + +@@ -370,5 +382,14 @@ int dram_init_banksize(void) + */ + ulong board_get_usable_ram_top(ulong total_size) + { ++ ulong ram_top; ++ ++ /* try to get top of usable RAM based on cboot DTB first */ ++ ram_top = cboot_get_usable_ram_top(total_size); ++ if (ram_top > 0) ++ return ram_top; ++ ++ /* fall back to default usable RAM computation */ ++ + return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); + } +diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_board.c b/arch/arm/mach-tegra/cboot.c +similarity index 56% +rename from arch/arm/mach-tegra/tegra186/nvtboot_board.c +rename to arch/arm/mach-tegra/cboot.c +index 83c0e931ea24..95a097584ac6 100644 +--- a/arch/arm/mach-tegra/tegra186/nvtboot_board.c ++++ b/arch/arm/mach-tegra/cboot.c +@@ -3,14 +3,182 @@ + * Copyright (c) 2016-2018, NVIDIA CORPORATION. + */ + +-#include + #include + #include + #include ++#include ++ ++#include ++ + #include ++#include + #include + +-extern unsigned long nvtboot_boot_x0; ++/* ++ * Size of a region that's large enough to hold the relocated U-Boot and all ++ * other allocations made around it (stack, heap, page tables, etc.) ++ * In practice, running "bdinfo" at the shell prompt, the stack reaches about ++ * 5MB from the address selected for ram_top as of the time of writing, ++ * so a 16MB region should be plenty. ++ */ ++#define MIN_USABLE_RAM_SIZE SZ_16M ++/* ++ * The amount of space we expect to require for stack usage. Used to validate ++ * that all reservations fit into the region selected for the relocation target ++ */ ++#define MIN_USABLE_STACK_SIZE SZ_1M ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++extern struct mm_region tegra_mem_map[]; ++ ++/* ++ * These variables are written to before relocation, and hence cannot be ++ * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. ++ * The section attribute forces this into .data and avoids this issue. This ++ * also has the nice side-effect of the content being valid after relocation. ++ */ ++ ++/* The number of valid entries in ram_banks[] */ ++static int ram_bank_count __attribute__((section(".data"))); ++ ++/* ++ * The usable top-of-RAM for U-Boot. This is both: ++ * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. ++ * b) At the end of a region that has enough space to hold the relocated U-Boot ++ * and all other allocations made around it (stack, heap, page tables, etc.) ++ */ ++static u64 ram_top __attribute__((section(".data"))); ++/* The base address of the region of RAM that ends at ram_top */ ++static u64 region_base __attribute__((section(".data"))); ++ ++int cboot_dram_init(void) ++{ ++ unsigned int na, ns; ++ const void *cboot_blob = (void *)cboot_boot_x0; ++ int node, len, i; ++ const u32 *prop; ++ ++ if (!cboot_blob) ++ return -EINVAL; ++ ++ na = fdtdec_get_uint(cboot_blob, 0, "#address-cells", 2); ++ ns = fdtdec_get_uint(cboot_blob, 0, "#size-cells", 2); ++ ++ node = fdt_path_offset(cboot_blob, "/memory"); ++ if (node < 0) { ++ pr_err("Can't find /memory node in cboot DTB"); ++ hang(); ++ } ++ prop = fdt_getprop(cboot_blob, node, "reg", &len); ++ if (!prop) { ++ pr_err("Can't find /memory/reg property in cboot DTB"); ++ hang(); ++ } ++ ++ /* Calculate the true # of base/size pairs to read */ ++ len /= 4; /* Convert bytes to number of cells */ ++ len /= (na + ns); /* Convert cells to number of banks */ ++ if (len > CONFIG_NR_DRAM_BANKS) ++ len = CONFIG_NR_DRAM_BANKS; ++ ++ /* Parse the /memory node, and save useful entries */ ++ gd->ram_size = 0; ++ ram_bank_count = 0; ++ for (i = 0; i < len; i++) { ++ u64 bank_start, bank_end, bank_size, usable_bank_size; ++ ++ /* Extract raw memory region data from DTB */ ++ bank_start = fdt_read_number(prop, na); ++ prop += na; ++ bank_size = fdt_read_number(prop, ns); ++ prop += ns; ++ gd->ram_size += bank_size; ++ bank_end = bank_start + bank_size; ++ debug("Bank %d: %llx..%llx (+%llx)\n", i, ++ bank_start, bank_end, bank_size); ++ ++ /* ++ * Align the bank to MMU section size. This is not strictly ++ * necessary, since the translation table construction code ++ * handles page granularity without issue. However, aligning ++ * the MMU entries reduces the size and number of levels in the ++ * page table, so is worth it. ++ */ ++ bank_start = ROUND(bank_start, SZ_2M); ++ bank_end = bank_end & ~(SZ_2M - 1); ++ bank_size = bank_end - bank_start; ++ debug(" aligned: %llx..%llx (+%llx)\n", ++ bank_start, bank_end, bank_size); ++ if (bank_end <= bank_start) ++ continue; ++ ++ /* Record data used to create MMU translation tables */ ++ ram_bank_count++; ++ /* Index below is deliberately 1-based to skip MMIO entry */ ++ tegra_mem_map[ram_bank_count].virt = bank_start; ++ tegra_mem_map[ram_bank_count].phys = bank_start; ++ tegra_mem_map[ram_bank_count].size = bank_size; ++ tegra_mem_map[ram_bank_count].attrs = ++ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; ++ ++ /* Determine best bank to relocate U-Boot into */ ++ if (bank_end > SZ_4G) ++ bank_end = SZ_4G; ++ debug(" end %llx (usable)\n", bank_end); ++ usable_bank_size = bank_end - bank_start; ++ debug(" size %llx (usable)\n", usable_bank_size); ++ if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && ++ (bank_end > ram_top)) { ++ ram_top = bank_end; ++ region_base = bank_start; ++ debug("ram top now %llx\n", ram_top); ++ } ++ } ++ ++ /* Ensure memory map contains the desired sentinel entry */ ++ tegra_mem_map[ram_bank_count + 1].virt = 0; ++ tegra_mem_map[ram_bank_count + 1].phys = 0; ++ tegra_mem_map[ram_bank_count + 1].size = 0; ++ tegra_mem_map[ram_bank_count + 1].attrs = 0; ++ ++ /* Error out if a relocation target couldn't be found */ ++ if (!ram_top) { ++ pr_err("Can't find a usable RAM top"); ++ hang(); ++ } ++ ++ return 0; ++} ++ ++int cboot_dram_init_banksize(void) ++{ ++ int i; ++ ++ if (ram_bank_count == 0) ++ return -EINVAL; ++ ++ if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { ++ pr_err("Reservations exceed chosen region size"); ++ hang(); ++ } ++ ++ for (i = 0; i < ram_bank_count; i++) { ++ gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; ++ gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; ++ } ++ ++#ifdef CONFIG_PCI ++ gd->pci_ram_top = ram_top; ++#endif ++ ++ return 0; ++} ++ ++ulong cboot_get_usable_ram_top(ulong total_size) ++{ ++ return ram_top; ++} + + /* + * The following few functions run late during the boot process and dynamically +@@ -23,8 +191,6 @@ extern unsigned long nvtboot_boot_x0; + * list of RAM banks into some private data structure before running. + */ + +-extern struct mm_region tegra_mem_map[]; +- + static char *gen_varname(const char *var, const char *ext) + { + size_t len_var = strlen(var); +@@ -235,7 +401,7 @@ static void set_calculated_env_vars(void) + dump_ram_banks(); + #endif + +- reserve_ram(nvtboot_boot_x0, fdt_totalsize(nvtboot_boot_x0)); ++ reserve_ram(cboot_boot_x0, fdt_totalsize(cboot_boot_x0)); + + #ifdef DEBUG + printf("RAM after reserving cboot DTB:\n"); +@@ -262,7 +428,7 @@ static void set_calculated_env_vars(void) + debug("%s: var: %s\n", __func__, var); + set_calculated_env_var(var); + #ifdef DEBUG +- printf("RAM banks affter allocating %s:\n", var); ++ printf("RAM banks after allocating %s:\n", var); + dump_ram_banks(); + #endif + } +@@ -274,7 +440,7 @@ static int set_fdt_addr(void) + { + int ret; + +- ret = env_set_hex("fdt_addr", nvtboot_boot_x0); ++ ret = env_set_hex("fdt_addr", cboot_boot_x0); + if (ret) { + printf("Failed to set fdt_addr to point at DTB: %d\n", ret); + return ret; +@@ -284,12 +450,12 @@ static int set_fdt_addr(void) + } + + /* +- * Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's ++ * Attempt to use /chosen/nvidia,ethernet-mac in the cboot DTB to U-Boot's + * ethaddr environment variable if possible. + */ +-static int set_ethaddr_from_nvtboot(void) ++static int set_ethaddr_from_cboot(void) + { +- const void *nvtboot_blob = (void *)nvtboot_boot_x0; ++ const void *cboot_blob = (void *)cboot_boot_x0; + int ret, node, len; + const u32 *prop; + +@@ -297,27 +463,27 @@ static int set_ethaddr_from_nvtboot(void) + if (env_get("ethaddr")) + return 0; + +- node = fdt_path_offset(nvtboot_blob, "/chosen"); ++ node = fdt_path_offset(cboot_blob, "/chosen"); + if (node < 0) { +- printf("Can't find /chosen node in nvtboot DTB\n"); ++ printf("Can't find /chosen node in cboot DTB\n"); + return node; + } +- prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len); ++ prop = fdt_getprop(cboot_blob, node, "nvidia,ethernet-mac", &len); + if (!prop) { +- printf("Can't find nvidia,ether-mac property in nvtboot DTB\n"); ++ printf("Can't find nvidia,ether-mac property in cboot DTB\n"); + return -ENOENT; + } + + ret = env_set("ethaddr", (void *)prop); + if (ret) { +- printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret); ++ printf("Failed to set ethaddr from cboot DTB: %d\n", ret); + return ret; + } + + return 0; + } + +-int tegra_soc_board_init_late(void) ++int cboot_late_init(void) + { + set_calculated_env_vars(); + /* +@@ -326,7 +492,7 @@ int tegra_soc_board_init_late(void) + */ + set_fdt_addr(); + /* Ignore errors here; not all cases care about Ethernet addresses */ +- set_ethaddr_from_nvtboot(); ++ set_ethaddr_from_cboot(); + + return 0; + } +diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/cboot_ll.S +similarity index 57% +rename from arch/arm/mach-tegra/tegra186/nvtboot_ll.S +rename to arch/arm/mach-tegra/cboot_ll.S +index aa7a863d9702..4c9ddacc2b39 100644 +--- a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S ++++ b/arch/arm/mach-tegra/cboot_ll.S +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + /* +- * Save nvtboot-related boot-time CPU state ++ * Save cboot-related boot-time CPU state + * + * (C) Copyright 2015-2016 NVIDIA Corporation + */ +@@ -9,12 +9,12 @@ + #include + + .align 8 +-.globl nvtboot_boot_x0 +-nvtboot_boot_x0: ++.globl cboot_boot_x0 ++cboot_boot_x0: + .dword 0 + +-ENTRY(save_boot_params) +- adr x8, nvtboot_boot_x0 ++ENTRY(cboot_save_boot_params) ++ adr x8, cboot_boot_x0 + str x0, [x8] + b save_boot_params_ret +-ENDPROC(save_boot_params) ++ENDPROC(cboot_save_boot_params) +diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile +index 56f3378ecea3..3a2405027704 100644 +--- a/arch/arm/mach-tegra/tegra186/Makefile ++++ b/arch/arm/mach-tegra/tegra186/Makefile +@@ -2,8 +2,4 @@ + # + # SPDX-License-Identifier: GPL-2.0 + +-obj-y += ../board186.o + obj-y += cache.o +-obj-y += nvtboot_board.o +-obj-y += nvtboot_ll.o +-obj-y += nvtboot_mem.o +diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c +deleted file mode 100644 +index 62142821a595..000000000000 +--- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c ++++ /dev/null +@@ -1,172 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (c) 2016-2018, NVIDIA CORPORATION. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-/* +- * Size of a region that's large enough to hold the relocated U-Boot and all +- * other allocations made around it (stack, heap, page tables, etc.) +- * In practice, running "bdinfo" at the shell prompt, the stack reaches about +- * 5MB from the address selected for ram_top as of the time of writing, +- * so a 16MB region should be plenty. +- */ +-#define MIN_USABLE_RAM_SIZE SZ_16M +-/* +- * The amount of space we expect to require for stack usage. Used to validate +- * that all reservations fit into the region selected for the relocation target +- */ +-#define MIN_USABLE_STACK_SIZE SZ_1M +- +-DECLARE_GLOBAL_DATA_PTR; +- +-extern unsigned long nvtboot_boot_x0; +-extern struct mm_region tegra_mem_map[]; +- +-/* +- * These variables are written to before relocation, and hence cannot be +- * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. +- * The section attribute forces this into .data and avoids this issue. This +- * also has the nice side-effect of the content being valid after relocation. +- */ +- +-/* The number of valid entries in ram_banks[] */ +-static int ram_bank_count __attribute__((section(".data"))); +- +-/* +- * The usable top-of-RAM for U-Boot. This is both: +- * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. +- * b) At the end of a region that has enough space to hold the relocated U-Boot +- * and all other allocations made around it (stack, heap, page tables, etc.) +- */ +-static u64 ram_top __attribute__((section(".data"))); +-/* The base address of the region of RAM that ends at ram_top */ +-static u64 region_base __attribute__((section(".data"))); +- +-int dram_init(void) +-{ +- unsigned int na, ns; +- const void *nvtboot_blob = (void *)nvtboot_boot_x0; +- int node, len, i; +- const u32 *prop; +- +- na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); +- ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); +- +- node = fdt_path_offset(nvtboot_blob, "/memory"); +- if (node < 0) { +- pr_err("Can't find /memory node in nvtboot DTB"); +- hang(); +- } +- prop = fdt_getprop(nvtboot_blob, node, "reg", &len); +- if (!prop) { +- pr_err("Can't find /memory/reg property in nvtboot DTB"); +- hang(); +- } +- +- /* Calculate the true # of base/size pairs to read */ +- len /= 4; /* Convert bytes to number of cells */ +- len /= (na + ns); /* Convert cells to number of banks */ +- if (len > CONFIG_NR_DRAM_BANKS) +- len = CONFIG_NR_DRAM_BANKS; +- +- /* Parse the /memory node, and save useful entries */ +- gd->ram_size = 0; +- ram_bank_count = 0; +- for (i = 0; i < len; i++) { +- u64 bank_start, bank_end, bank_size, usable_bank_size; +- +- /* Extract raw memory region data from DTB */ +- bank_start = fdt_read_number(prop, na); +- prop += na; +- bank_size = fdt_read_number(prop, ns); +- prop += ns; +- gd->ram_size += bank_size; +- bank_end = bank_start + bank_size; +- debug("Bank %d: %llx..%llx (+%llx)\n", i, +- bank_start, bank_end, bank_size); +- +- /* +- * Align the bank to MMU section size. This is not strictly +- * necessary, since the translation table construction code +- * handles page granularity without issue. However, aligning +- * the MMU entries reduces the size and number of levels in the +- * page table, so is worth it. +- */ +- bank_start = ROUND(bank_start, SZ_2M); +- bank_end = bank_end & ~(SZ_2M - 1); +- bank_size = bank_end - bank_start; +- debug(" aligned: %llx..%llx (+%llx)\n", +- bank_start, bank_end, bank_size); +- if (bank_end <= bank_start) +- continue; +- +- /* Record data used to create MMU translation tables */ +- ram_bank_count++; +- /* Index below is deliberately 1-based to skip MMIO entry */ +- tegra_mem_map[ram_bank_count].virt = bank_start; +- tegra_mem_map[ram_bank_count].phys = bank_start; +- tegra_mem_map[ram_bank_count].size = bank_size; +- tegra_mem_map[ram_bank_count].attrs = +- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; +- +- /* Determine best bank to relocate U-Boot into */ +- if (bank_end > SZ_4G) +- bank_end = SZ_4G; +- debug(" end %llx (usable)\n", bank_end); +- usable_bank_size = bank_end - bank_start; +- debug(" size %llx (usable)\n", usable_bank_size); +- if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && +- (bank_end > ram_top)) { +- ram_top = bank_end; +- region_base = bank_start; +- debug("ram top now %llx\n", ram_top); +- } +- } +- +- /* Ensure memory map contains the desired sentinel entry */ +- tegra_mem_map[ram_bank_count + 1].virt = 0; +- tegra_mem_map[ram_bank_count + 1].phys = 0; +- tegra_mem_map[ram_bank_count + 1].size = 0; +- tegra_mem_map[ram_bank_count + 1].attrs = 0; +- +- /* Error out if a relocation target couldn't be found */ +- if (!ram_top) { +- pr_err("Can't find a usable RAM top"); +- hang(); +- } +- +- return 0; +-} +- +-int dram_init_banksize(void) +-{ +- int i; +- +- if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { +- pr_err("Reservations exceed chosen region size"); +- hang(); +- } +- +- for (i = 0; i < ram_bank_count; i++) { +- gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; +- gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; +- } +- +-#ifdef CONFIG_PCI +- gd->pci_ram_top = ram_top; +-#endif +- +- return 0; +-} +- +-ulong board_get_usable_ram_top(ulong total_size) +-{ +- return ram_top; +-} +diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c +index 496e8a02111e..6f88010c18c3 100644 +--- a/board/nvidia/p2771-0000/p2771-0000.c ++++ b/board/nvidia/p2771-0000/p2771-0000.c +@@ -7,7 +7,7 @@ + #include + #include "../p2571/max77620_init.h" + +-int tegra_board_init(void) ++void pin_mux_mmc(void) + { + struct udevice *dev; + uchar val; +@@ -18,19 +18,18 @@ int tegra_board_init(void) + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); +- return ret; ++ return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +- return ret; ++ return; + } +- +- return 0; + } + ++#ifdef CONFIG_PCI_TEGRA + int tegra_pcie_board_init(void) + { + struct udevice *dev; +@@ -52,3 +51,4 @@ int tegra_pcie_board_init(void) + + return 0; + } ++#endif + +From patchwork Thu Mar 21 18:01:12 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 13/19] ARM: tegra: Implement cboot_save_boot_params() in C +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060342 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-14-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:12 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +This is easier to deal with and works just as well for this simple +function. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Makefile | 2 +- + arch/arm/mach-tegra/cboot.c | 12 ++++++++++++ + arch/arm/mach-tegra/cboot_ll.S | 20 -------------------- + 3 files changed, 13 insertions(+), 21 deletions(-) + delete mode 100644 arch/arm/mach-tegra/cboot_ll.S + +diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile +index 41ba674edff4..7165d70a60da 100644 +--- a/arch/arm/mach-tegra/Makefile ++++ b/arch/arm/mach-tegra/Makefile +@@ -20,7 +20,7 @@ obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o + obj-$(CONFIG_TEGRA_PMC) += powergate.o + obj-y += xusb-padctl-dummy.o + +-obj-$(CONFIG_ARM64) += arm64-mmu.o cboot_ll.o cboot.o ++obj-$(CONFIG_ARM64) += arm64-mmu.o cboot.o + obj-y += dt-setup.o + obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o + obj-$(CONFIG_TEGRA_GPU) += gpu.o +diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c +index 95a097584ac6..acf33b4c4e0c 100644 +--- a/arch/arm/mach-tegra/cboot.c ++++ b/arch/arm/mach-tegra/cboot.c +@@ -52,6 +52,18 @@ static u64 ram_top __attribute__((section(".data"))); + /* The base address of the region of RAM that ends at ram_top */ + static u64 region_base __attribute__((section(".data"))); + ++/* ++ * Explicitly put this in the .data section because it is written before the ++ * .bss section is zeroed out but it needs to persist. ++ */ ++unsigned long cboot_boot_x0 __attribute__((section(".data"))); ++ ++void cboot_save_boot_params(unsigned long x0, unsigned long x1, ++ unsigned long x2, unsigned long x3) ++{ ++ cboot_boot_x0 = x0; ++} ++ + int cboot_dram_init(void) + { + unsigned int na, ns; +diff --git a/arch/arm/mach-tegra/cboot_ll.S b/arch/arm/mach-tegra/cboot_ll.S +deleted file mode 100644 +index 4c9ddacc2b39..000000000000 +--- a/arch/arm/mach-tegra/cboot_ll.S ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Save cboot-related boot-time CPU state +- * +- * (C) Copyright 2015-2016 NVIDIA Corporation +- */ +- +-#include +-#include +- +-.align 8 +-.globl cboot_boot_x0 +-cboot_boot_x0: +- .dword 0 +- +-ENTRY(cboot_save_boot_params) +- adr x8, cboot_boot_x0 +- str x0, [x8] +- b save_boot_params_ret +-ENDPROC(cboot_save_boot_params) + +From patchwork Thu Mar 21 18:01:13 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,14/19] ARM: tegra: Implement cboot_get_ethaddr() +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060340 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-15-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:13 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +This function will attempt to look up an ethernet address in the DTB +that was passed in from cboot. It does so by first trying to locate the +primary ethernet device for the board (identified by the "ethernet" +alias) and if found, reads the "local-mac-address" property. If the +"ethernet" alias does not exist, or if it points to a device tree node +that doesn't exist, or if the device tree node that it points to does +not have a "local-mac-address" property or if the value is invalid, it +will fall back to the legacy mechanism of looking for the MAC address +stored in the "nvidia,ethernet-mac" property of the "/chosen" node. + +Signed-off-by: Thierry Reding +--- +Changes in v2: +- make dummy static inline to avoid duplicate definitions + + arch/arm/include/asm/arch-tegra/cboot.h | 6 ++ + arch/arm/mach-tegra/cboot.c | 78 ++++++++++++++++++++----- + 2 files changed, 69 insertions(+), 15 deletions(-) + +diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h +index b3441ec178b3..021c24617575 100644 +--- a/arch/arm/include/asm/arch-tegra/cboot.h ++++ b/arch/arm/include/asm/arch-tegra/cboot.h +@@ -14,6 +14,7 @@ void cboot_save_boot_params(unsigned long x0, unsigned long x1, + int cboot_dram_init(void); + int cboot_dram_init_banksize(void); + ulong cboot_get_usable_ram_top(ulong total_size); ++int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]); + #else + static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, + unsigned long x2, unsigned long x3) +@@ -34,6 +35,11 @@ static inline ulong cboot_get_usable_ram_top(ulong total_size) + { + return 0; + } ++ ++static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) ++{ ++ return -ENOSYS; ++} + #endif + + #endif +diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c +index acf33b4c4e0c..9735380bda59 100644 +--- a/arch/arm/mach-tegra/cboot.c ++++ b/arch/arm/mach-tegra/cboot.c +@@ -4,6 +4,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -465,46 +466,93 @@ static int set_fdt_addr(void) + * Attempt to use /chosen/nvidia,ethernet-mac in the cboot DTB to U-Boot's + * ethaddr environment variable if possible. + */ +-static int set_ethaddr_from_cboot(void) ++static int cboot_get_ethaddr_legacy(const void *fdt, uint8_t mac[ETH_ALEN]) + { +- const void *cboot_blob = (void *)cboot_boot_x0; +- int ret, node, len; +- const u32 *prop; +- +- /* Already a valid address in the environment? If so, keep it */ +- if (env_get("ethaddr")) +- return 0; ++ const char *prop; ++ int node, len; + +- node = fdt_path_offset(cboot_blob, "/chosen"); ++ node = fdt_path_offset(fdt, "/chosen"); + if (node < 0) { + printf("Can't find /chosen node in cboot DTB\n"); + return node; + } +- prop = fdt_getprop(cboot_blob, node, "nvidia,ethernet-mac", &len); ++ ++ prop = fdt_getprop(fdt, node, "nvidia,ethernet-mac", &len); + if (!prop) { + printf("Can't find nvidia,ether-mac property in cboot DTB\n"); + return -ENOENT; + } + +- ret = env_set("ethaddr", (void *)prop); +- if (ret) { +- printf("Failed to set ethaddr from cboot DTB: %d\n", ret); +- return ret; ++ eth_parse_enetaddr(prop, mac); ++ ++ if (!is_valid_ethaddr(mac)) { ++ printf("Invalid MAC address: %s\n", prop); ++ return -EINVAL; + } + ++ debug("Legacy MAC address: %pM\n", mac); ++ + return 0; + } + ++int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) ++{ ++ int node, len, err = 0; ++ const uchar *prop; ++ const char *path; ++ ++ path = fdt_get_alias(fdt, "ethernet"); ++ if (!path) { ++ err = -ENOENT; ++ goto out; ++ } ++ ++ debug("ethernet alias found: %s\n", path); ++ ++ node = fdt_path_offset(fdt, path); ++ if (node < 0) { ++ err = -ENOENT; ++ goto out; ++ } ++ ++ prop = fdt_getprop(fdt, node, "local-mac-address", &len); ++ if (!prop) { ++ err = -ENOENT; ++ goto out; ++ } ++ ++ if (len != ETH_ALEN) { ++ err = -EINVAL; ++ goto out; ++ } ++ ++ debug("MAC address: %pM\n", prop); ++ memcpy(mac, prop, ETH_ALEN); ++ ++out: ++ if (err < 0) ++ err = cboot_get_ethaddr_legacy(fdt, mac); ++ ++ return err; ++} ++ + int cboot_late_init(void) + { ++ const void *fdt = (const void *)cboot_boot_x0; ++ uint8_t mac[ETH_ALEN]; ++ int err; ++ + set_calculated_env_vars(); + /* + * Ignore errors here; the value may not be used depending on + * extlinux.conf or boot script content. + */ + set_fdt_addr(); ++ + /* Ignore errors here; not all cases care about Ethernet addresses */ +- set_ethaddr_from_cboot(); ++ err = cboot_get_ethaddr(fdt, mac); ++ if (!err) ++ eth_env_set_enetaddr("ethaddr", mac); + + return 0; + } + +From patchwork Thu Mar 21 18:01:14 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v3, + 15/19] ARM: tegra: Enable position independent build for 64-bit +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060357 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-16-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:14 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Note that U-Boot is always chainloaded from cboot starting with L4T +release 28. cboot always loads U-Boot to a fixed address, so making +the builds position independent isn't strictly necessary. However, +position independent builds can be convenient because if U-Boot is +ever loaded to an address different from its link address, it will +still be able to boot. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/Kconfig | 1 + + configs/e2220-1170_defconfig | 2 +- + configs/p2371-0000_defconfig | 2 +- + configs/p2371-2180_defconfig | 2 +- + configs/p2571_defconfig | 2 +- + 5 files changed, 5 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig +index faa73559fd42..97e22ead5985 100644 +--- a/arch/arm/mach-tegra/Kconfig ++++ b/arch/arm/mach-tegra/Kconfig +@@ -87,6 +87,7 @@ config TEGRA_ARMV8_COMMON + bool "Tegra 64-bit common options" + select ARM64 + select LINUX_KERNEL_IMAGE_HEADER ++ select POSITION_INDEPENDENT + select TEGRA_COMMON + + if TEGRA_ARMV8_COMMON +diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig +index fbca72ace6ed..87668f8e517f 100644 +--- a/configs/e2220-1170_defconfig ++++ b/configs/e2220-1170_defconfig +@@ -1,6 +1,6 @@ + CONFIG_ARM=y + CONFIG_TEGRA=y +-CONFIG_SYS_TEXT_BASE=0x80110000 ++CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA210=y + CONFIG_NR_DRAM_BANKS=2 + CONFIG_OF_SYSTEM_SETUP=y +diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig +index c25872128e07..979cb8ec0a25 100644 +--- a/configs/p2371-0000_defconfig ++++ b/configs/p2371-0000_defconfig +@@ -1,6 +1,6 @@ + CONFIG_ARM=y + CONFIG_TEGRA=y +-CONFIG_SYS_TEXT_BASE=0x80110000 ++CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA210=y + CONFIG_TARGET_P2371_0000=y + CONFIG_NR_DRAM_BANKS=2 +diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig +index b662ef143141..2fac69917a92 100644 +--- a/configs/p2371-2180_defconfig ++++ b/configs/p2371-2180_defconfig +@@ -1,6 +1,6 @@ + CONFIG_ARM=y + CONFIG_TEGRA=y +-CONFIG_SYS_TEXT_BASE=0x80110000 ++CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA210=y + CONFIG_TARGET_P2371_2180=y + CONFIG_NR_DRAM_BANKS=2 +diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig +index 5f0f8c519b4c..ff4654cea9b4 100644 +--- a/configs/p2571_defconfig ++++ b/configs/p2571_defconfig +@@ -1,6 +1,6 @@ + CONFIG_ARM=y + CONFIG_TEGRA=y +-CONFIG_SYS_TEXT_BASE=0x80110000 ++CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA210=y + CONFIG_TARGET_P2571=y + CONFIG_NR_DRAM_BANKS=2 + +From patchwork Thu Mar 21 18:01:15 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,16/19] p2371-2180: Pass Ethernet MAC to the kernel +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060351 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-17-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:15 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Pass the ethernet MAC address to the kernel upon boot. This passes both +the local-mac-address property (as passed to U-Boot from cboot) and the +currently set MAC address via the mac-address property. The latter will +only be set if it is different from the address that was already passed +via the local-mac-address property. + +Signed-off-by: Thierry Reding +--- + board/nvidia/p2371-2180/p2371-2180.c | 50 ++++++++++++++++++++++++++++ + configs/p2371-2180_defconfig | 1 + + 2 files changed, 51 insertions(+) + +diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c +index 212037da5ac0..a444d692d7ea 100644 +--- a/board/nvidia/p2371-2180/p2371-2180.c ++++ b/board/nvidia/p2371-2180/p2371-2180.c +@@ -5,9 +5,12 @@ + */ + + #include ++#include + #include ++#include + #include + #include ++#include + #include "../p2571/max77620_init.h" + #include "pinmux-config-p2371-2180.h" + +@@ -94,3 +97,50 @@ int tegra_pcie_board_init(void) + return 0; + } + #endif /* PCI */ ++ ++static void ft_mac_address_setup(void *fdt) ++{ ++ const void *cboot_fdt = (const void *)cboot_boot_x0; ++ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; ++ const char *path; ++ int offset, err; ++ ++ err = cboot_get_ethaddr(cboot_fdt, local_mac); ++ if (err < 0) ++ memset(local_mac, 0, ETH_ALEN); ++ ++ path = fdt_get_alias(fdt, "ethernet"); ++ if (!path) ++ return; ++ ++ debug("ethernet alias found: %s\n", path); ++ ++ offset = fdt_path_offset(fdt, path); ++ if (offset < 0) { ++ printf("ethernet alias points to absent node %s\n", path); ++ return; ++ } ++ ++ if (is_valid_ethaddr(local_mac)) { ++ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, ++ ETH_ALEN); ++ if (!err) ++ debug("Local MAC address set: %pM\n", local_mac); ++ } ++ ++ if (eth_env_get_enetaddr("ethaddr", mac)) { ++ if (memcmp(local_mac, mac, ETH_ALEN) != 0) { ++ err = fdt_setprop(fdt, offset, "mac-address", mac, ++ ETH_ALEN); ++ if (!err) ++ debug("MAC address set: %pM\n", mac); ++ } ++ } ++} ++ ++int ft_board_setup(void *fdt, bd_t *bd) ++{ ++ ft_mac_address_setup(fdt); ++ ++ return 0; ++} +diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig +index 2fac69917a92..16afbba68ae7 100644 +--- a/configs/p2371-2180_defconfig ++++ b/configs/p2371-2180_defconfig +@@ -5,6 +5,7 @@ CONFIG_TEGRA210=y + CONFIG_TARGET_P2371_2180=y + CONFIG_NR_DRAM_BANKS=2 + CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_OF_BOARD_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y + CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # " + +From patchwork Thu Mar 21 18:01:16 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,17/19] p2771-0000: Pass Ethernet MAC to the kernel +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060356 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-18-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:16 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Pass the ethernet MAC address to the kernel upon boot. This passes both +the local-mac-address property (as passed to U-Boot from cboot) and the +currently set MAC address via the mac-address property. The latter will +only be set if it is different from the address that was already passed +via the local-mac-address property. + +Signed-off-by: Thierry Reding +--- + board/nvidia/p2771-0000/p2771-0000.c | 43 ++++++++++++++++++++++++++++ + configs/p2771-0000-000_defconfig | 1 + + configs/p2771-0000-500_defconfig | 1 + + 3 files changed, 45 insertions(+) + +diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c +index 6f88010c18c3..fe22067f6571 100644 +--- a/board/nvidia/p2771-0000/p2771-0000.c ++++ b/board/nvidia/p2771-0000/p2771-0000.c +@@ -4,7 +4,10 @@ + */ + + #include ++#include + #include ++#include ++#include + #include "../p2571/max77620_init.h" + + void pin_mux_mmc(void) +@@ -52,3 +55,43 @@ int tegra_pcie_board_init(void) + return 0; + } + #endif ++ ++int ft_board_setup(void *fdt, bd_t *bd) ++{ ++ const void *cboot_fdt = (const void *)cboot_boot_x0; ++ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; ++ const char *path; ++ int offset, err; ++ ++ err = cboot_get_ethaddr(cboot_fdt, local_mac); ++ if (err < 0) ++ memset(local_mac, 0, ETH_ALEN); ++ ++ path = fdt_get_alias(fdt, "ethernet"); ++ if (!path) ++ return 0; ++ ++ debug("ethernet alias found: %s\n", path); ++ ++ offset = fdt_path_offset(fdt, path); ++ if (offset < 0) ++ return 0; ++ ++ if (is_valid_ethaddr(local_mac)) { ++ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, ++ ETH_ALEN); ++ if (!err) ++ debug("Local MAC address set: %pM\n", local_mac); ++ } ++ ++ if (eth_env_get_enetaddr("ethaddr", mac)) { ++ if (memcmp(local_mac, mac, ETH_ALEN) != 0) { ++ err = fdt_setprop(fdt, offset, "mac-address", mac, ++ ETH_ALEN); ++ if (!err) ++ debug("MAC address set: %pM\n", mac); ++ } ++ } ++ ++ return 0; ++} +diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig +index ad0802067e73..91896e39a10f 100644 +--- a/configs/p2771-0000-000_defconfig ++++ b/configs/p2771-0000-000_defconfig +@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA186=y + CONFIG_NR_DRAM_BANKS=1026 + CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_OF_BOARD_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y + CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # " +diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig +index 459b67fd195f..20d4393838d6 100644 +--- a/configs/p2771-0000-500_defconfig ++++ b/configs/p2771-0000-500_defconfig +@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80080000 + CONFIG_TEGRA186=y + CONFIG_NR_DRAM_BANKS=1026 + CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_OF_BOARD_SETUP=y + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y + CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # " + +From patchwork Thu Mar 21 18:01:17 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,18/19] lib: Implement strndup() +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060343 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-19-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:17 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Signed-off-by: Thierry Reding +--- + include/linux/string.h | 1 + + lib/string.c | 23 +++++++++++++++++++++++ + 2 files changed, 24 insertions(+) + +diff --git a/include/linux/string.h b/include/linux/string.h +index 36066207392e..5d63be4ce5b0 100644 +--- a/include/linux/string.h ++++ b/include/linux/string.h +@@ -94,6 +94,7 @@ size_t strcspn(const char *s, const char *reject); + #ifndef __HAVE_ARCH_STRDUP + extern char * strdup(const char *); + #endif ++extern char * strndup(const char *, size_t); + #ifndef __HAVE_ARCH_STRSWAB + extern char * strswab(const char *); + #endif +diff --git a/lib/string.c b/lib/string.c +index af17c16f616d..9b779ddc3bbe 100644 +--- a/lib/string.c ++++ b/lib/string.c +@@ -326,6 +326,29 @@ char * strdup(const char *s) + } + #endif + ++char * strndup(const char *s, size_t n) ++{ ++ size_t len; ++ char *new; ++ ++ if (s == NULL) ++ return NULL; ++ ++ len = strlen(s); ++ ++ if (n < len) ++ len = n; ++ ++ new = malloc(len + 1); ++ if (new == NULL) ++ return NULL; ++ ++ strncpy(new, s, len); ++ new[len] = '\0'; ++ ++ return new; ++} ++ + #ifndef __HAVE_ARCH_STRSPN + /** + * strspn - Calculate the length of the initial substring of @s which only + +From patchwork Thu Mar 21 18:01:18 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3,19/19] ARM: tegra: Import cbootargs value from cboot DTB +X-Patchwork-Submitter: Thierry Reding +X-Patchwork-Id: 1060349 +X-Patchwork-Delegate: twarren@nvidia.com +Message-Id: <20190321180118.26475-20-thierry.reding@gmail.com> +To: Tom Warren +Cc: u-boot@lists.denx.de +Date: Thu, 21 Mar 2019 19:01:18 +0100 +From: Thierry Reding +List-Id: U-Boot discussion + +From: Thierry Reding + +Read the boot arguments passed by cboot via the /chosen/bootargs +property and store it in the cbootargs environment variable. + +Signed-off-by: Thierry Reding +--- + arch/arm/mach-tegra/cboot.c | 47 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c +index 9735380bda59..8bfcbcdc6e6d 100644 +--- a/arch/arm/mach-tegra/cboot.c ++++ b/arch/arm/mach-tegra/cboot.c +@@ -8,7 +8,9 @@ + #include + #include + #include ++#include + ++#include + #include + + #include +@@ -536,10 +538,49 @@ out: + return err; + } + ++static char *strip(const char *ptr) ++{ ++ const char *end; ++ ++ while (*ptr && isblank(*ptr)) ++ ptr++; ++ ++ /* empty string */ ++ if (*ptr == '\0') ++ return strdup(ptr); ++ ++ end = ptr; ++ ++ while (end[1]) ++ end++; ++ ++ while (isblank(*end)) ++ end--; ++ ++ return strndup(ptr, end - ptr + 1); ++} ++ ++static char *cboot_get_bootargs(const void *fdt) ++{ ++ const char *args; ++ int offset, len; ++ ++ offset = fdt_path_offset(fdt, "/chosen"); ++ if (offset < 0) ++ return NULL; ++ ++ args = fdt_getprop(fdt, offset, "bootargs", &len); ++ if (!args) ++ return NULL; ++ ++ return strip(args); ++} ++ + int cboot_late_init(void) + { + const void *fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN]; ++ char *bootargs; + int err; + + set_calculated_env_vars(); +@@ -554,5 +595,11 @@ int cboot_late_init(void) + if (!err) + eth_env_set_enetaddr("ethaddr", mac); + ++ bootargs = cboot_get_bootargs(fdt); ++ if (bootargs) { ++ env_set("cbootargs", bootargs); ++ free(bootargs); ++ } ++ + return 0; + } diff --git a/tegra-p2371-2180-Build-position-independent-binary.patch b/tegra-p2371-2180-Build-position-independent-binary.patch deleted file mode 100644 index eb9f5c5..0000000 --- a/tegra-p2371-2180-Build-position-independent-binary.patch +++ /dev/null @@ -1,37 +0,0 @@ -From patchwork Fri Mar 8 20:10:23 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot] p2371-2180: Build position independent binary -X-Patchwork-Submitter: Thierry Reding -X-Patchwork-Id: 1053674 -Message-Id: <20190308201023.2145-1-thierry.reding@gmail.com> -To: Tom Warren -Cc: u-boot@lists.denx.de, Stephen Warren -Date: Fri, 8 Mar 2019 21:10:23 +0100 -From: Thierry Reding -List-Id: U-Boot discussion - -From: Thierry Reding - -In order to support chainloading of U-Boot by an earlier bootloader, -make sure the binary is position independent, so that the earlier boot- -loader can relocate it if necessary. - -Signed-off-by: Thierry Reding ---- - configs/p2371-2180_defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig -index b66459e379ac..8d7cf3fb5346 100644 ---- a/configs/p2371-2180_defconfig -+++ b/configs/p2371-2180_defconfig -@@ -1,6 +1,7 @@ - CONFIG_ARM=y - CONFIG_TEGRA=y - CONFIG_SYS_TEXT_BASE=0x80110000 -+CONFIG_POSITION_INDEPENDENT=y - CONFIG_TEGRA210=y - CONFIG_TARGET_P2371_2180=y - CONFIG_NR_DRAM_BANKS=2 diff --git a/ti-am335x_evm-Enable-CONFIG_SPL_OF_CONTROL.patch b/ti-am335x_evm-Enable-CONFIG_SPL_OF_CONTROL.patch new file mode 100644 index 0000000..8415e8f --- /dev/null +++ b/ti-am335x_evm-Enable-CONFIG_SPL_OF_CONTROL.patch @@ -0,0 +1,183 @@ +From patchwork Tue Mar 19 11:19:21 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot] ti: am335x_evm: Enable CONFIG_SPL_OF_CONTROL +X-Patchwork-Submitter: Tom Rini +X-Patchwork-Id: 1058350 +X-Patchwork-Delegate: trini@ti.com +Message-Id: <1552994361-32058-1-git-send-email-trini@konsulko.com> +To: u-boot@lists.denx.de +Date: Tue, 19 Mar 2019 07:19:21 -0400 +From: Tom Rini +List-Id: U-Boot discussion + +Enable support for SPL_OF_CONTROL on this platform. That means doing a +few things: +- Add u-boot,dm-pre-reloc to a number of nodes +- Drop static platdata in the board file. +- A lot of tweaks to the defconfig. We remove some things such as + SPL_USE_ARCH_MEMCPY/SET for space. Increase our malloc len. +- Drop, for now at least, USB SPL support as it's causing a hang. + +Cc: Faiz Abbas +Cc: Lokesh Vutla +Signed-off-by: Tom Rini +--- + arch/arm/dts/am335x-evm-u-boot.dtsi | 45 +++++++++++++++++++++++++++++++++++-- + board/ti/am335x/board.c | 30 ------------------------- + configs/am335x_evm_defconfig | 14 ++++++++---- + 3 files changed, 53 insertions(+), 36 deletions(-) + +diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi +index b6b97ed16d91..16a9f855ad1f 100644 +--- a/arch/arm/dts/am335x-evm-u-boot.dtsi ++++ b/arch/arm/dts/am335x-evm-u-boot.dtsi +@@ -3,11 +3,52 @@ + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + ++#include "am33xx-u-boot.dtsi" + +-&mmc3 { +- status = "disabled"; ++&l4_wkup { ++ u-boot,dm-pre-reloc; ++}; ++ ++&scm { ++ u-boot,dm-pre-reloc; ++}; ++ ++&am33xx_pinmux { ++ u-boot,dm-pre-reloc; ++}; ++ ++&uart0_pins { ++ u-boot,dm-pre-reloc; ++}; ++ ++&uart0 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&gpio0 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&i2c0 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&i2c0_pins { ++ u-boot,dm-pre-reloc; + }; + + &usb0 { + dr_mode = "peripheral"; + }; ++ ++&mmc1 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&mmc1_pins { ++ u-boot,dm-pre-reloc; ++}; ++ ++&mmc3 { ++ status = "disabled"; ++}; +diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c +index d67f94ad47ba..bfad1a75a456 100644 +--- a/board/ti/am335x/board.c ++++ b/board/ti/am335x/board.c +@@ -1054,33 +1054,3 @@ void board_fit_image_post_process(void **p_image, size_t *p_size) + secure_boot_verify_image(p_image, p_size); + } + #endif +- +-#if !CONFIG_IS_ENABLED(OF_CONTROL) +-static const struct omap_hsmmc_plat am335x_mmc0_platdata = { +- .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, +- .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, +- .cfg.f_min = 400000, +- .cfg.f_max = 52000000, +- .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, +- .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +-}; +- +-U_BOOT_DEVICE(am335x_mmc0) = { +- .name = "omap_hsmmc", +- .platdata = &am335x_mmc0_platdata, +-}; +- +-static const struct omap_hsmmc_plat am335x_mmc1_platdata = { +- .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE, +- .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT, +- .cfg.f_min = 400000, +- .cfg.f_max = 52000000, +- .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, +- .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +-}; +- +-U_BOOT_DEVICE(am335x_mmc1) = { +- .name = "omap_hsmmc", +- .platdata = &am335x_mmc1_platdata, +-}; +-#endif +diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig +index 924116835251..dd690dcb495c 100644 +--- a/configs/am335x_evm_defconfig ++++ b/configs/am335x_evm_defconfig +@@ -1,23 +1,26 @@ + CONFIG_ARM=y ++# CONFIG_SPL_USE_ARCH_MEMCPY is not set ++# CONFIG_SPL_USE_ARCH_MEMSET is not set + CONFIG_ARCH_OMAP2PLUS=y + CONFIG_TI_COMMON_CMD_OPTIONS=y ++CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_AM33XX=y ++CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 + CONFIG_SPL=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 + CONFIG_SPL_LOAD_FIT=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" ++CONFIG_LOGLEVEL=3 + CONFIG_SYS_CONSOLE_INFO_QUIET=y + CONFIG_VERSION_VARIABLE=y + CONFIG_ARCH_MISC_INIT=y + # CONFIG_SPL_FS_EXT4 is not set + CONFIG_SPL_MTD_SUPPORT=y +-CONFIG_SPL_MUSB_NEW_SUPPORT=y + CONFIG_SPL_NET_SUPPORT=y + CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL" + CONFIG_SPL_OS_BOOT=y +-CONFIG_SPL_USB_GADGET=y +-CONFIG_SPL_USB_ETHER=y + CONFIG_CMD_SPL=y + CONFIG_CMD_SPL_NAND_OFS=0x00080000 + # CONFIG_CMD_FLASH is not set +@@ -28,10 +31,12 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0" + CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" + # CONFIG_SPL_EFI_PARTITION is not set + CONFIG_OF_CONTROL=y ++CONFIG_SPL_OF_CONTROL=y + CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" + CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" ++CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +-# CONFIG_BLK is not set ++CONFIG_SPL_OF_TRANSLATE=y + CONFIG_BOOTCOUNT_LIMIT=y + CONFIG_DFU_MMC=y + CONFIG_DFU_NAND=y +@@ -68,5 +73,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451 + CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 + CONFIG_USB_ETHER=y + CONFIG_DYNAMIC_CRC_TABLE=y ++CONFIG_SPL_TINY_MEMSET=y + CONFIG_RSA=y + CONFIG_LZO=y diff --git a/uboot-tools.spec b/uboot-tools.spec index e05f4bd..bdb9444 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2019.04 -Release: 0.6%{?candidate:.%{candidate}}%{?dist} +Release: 0.7%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -20,14 +20,15 @@ Patch1: uefi-use-Fedora-specific-path-name.patch # general fixes Patch2: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch Patch3: usb-kbd-fixes.patch +Patch4: uefi-rc5-fixes.patch # Board fixes and enablement Patch10: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch11: dragonboard-fixes.patch - -Patch12: ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch -Patch13: tegra-p2371-2180-Build-position-independent-binary.patch -Patch14: net-eth-uclass-Write-MAC-address-to-hardware-after-probe.patch +Patch12: ARM-tegra-Miscellaneous-improvements.patch +Patch13: ARM-tegra-Add-support-for-framebuffer-carveouts.patch +Patch14: ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch +Patch15: net-eth-uclass-Write-MAC-address-to-hardware-after-probe.patch BuildRequires: bc BuildRequires: dtc @@ -302,6 +303,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Sun Mar 24 2019 Peter Robinson 2019.04-0.7-rc4 +- Minor UEFI fixes, Tegra Jetson TX series rebase + * Wed Mar 20 2019 Peter Robinson 2019.04-0.6-rc4 - Tegra Jetson TX-series improvements diff --git a/uefi-rc5-fixes.patch b/uefi-rc5-fixes.patch new file mode 100644 index 0000000..fd36553 --- /dev/null +++ b/uefi-rc5-fixes.patch @@ -0,0 +1,245 @@ +From 306b16718edddd660b84bf3c6627ce5d41b53ce7 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Mon, 18 Mar 2019 20:01:59 +0100 +Subject: [PATCH 01/25] efi_loader: correct parameter size in efi_allocate_pool + +efi_allocate_pages() expects a (uint64_t *) pointer to pass the address of +the assigned memory. If we pass the address of a pointer here, an illegal +memory access occurs on 32bit systems. + +Fixes: 282a06cbcae8 ("efi_loader: Expose U-Boot addresses in memory map +for sandbox") +Signed-off-by: Heinrich Schuchardt +--- + lib/efi_loader/efi_memory.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c +index ebd2b36c03..55622d2fb4 100644 +--- a/lib/efi_loader/efi_memory.c ++++ b/lib/efi_loader/efi_memory.c +@@ -440,6 +440,7 @@ efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages) + efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer) + { + efi_status_t r; ++ u64 addr; + struct efi_pool_allocation *alloc; + u64 num_pages = efi_size_in_pages(size + + sizeof(struct efi_pool_allocation)); +@@ -453,9 +454,9 @@ efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer) + } + + r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, pool_type, num_pages, +- (uint64_t *)&alloc); +- ++ &addr); + if (r == EFI_SUCCESS) { ++ alloc = (struct efi_pool_allocation *)(uintptr_t)addr; + alloc->num_pages = num_pages; + *buffer = alloc->data; + } +-- +2.20.1 + +From bd3b7478d1e17b4d487d276f5cc0e4f4ef9fc4b7 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 19 Mar 2019 12:30:27 +0100 +Subject: [PATCH 02/25] efi_loader: endless loop in add_strings_package() + +Avoid an endless loop in add_strings_package(). + +Suggested-by: Takahiro Akashi +Reported-by: Coverity (CID 185833) +Signed-off-by: Heinrich Schuchardt +--- + lib/efi_loader/efi_hii.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c +index 3a966fa4df..61b71dec62 100644 +--- a/lib/efi_loader/efi_hii.c ++++ b/lib/efi_loader/efi_hii.c +@@ -227,9 +227,8 @@ out: + error: + if (stbl) { + free(stbl->language); +- if (idx > 0) +- while (--idx >= 0) +- free(stbl->strings[idx].string); ++ while (idx > 0) ++ free(stbl->strings[--idx].string); + free(stbl->strings); + } + free(stbl); +-- +2.20.1 + +From e7dae584b05feaf507c5b85a704a2c1d25abffc9 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 19 Mar 2019 18:36:21 +0100 +Subject: [PATCH 03/25] efi_loader: missing return in + efi_get_next_variable_name() + +Add a missing return statement in efi_get_next_variable_name(). + +Reported-by: Coverity (CID 185834) +Signed-off-by: Heinrich Schuchardt +--- + lib/efi_loader/efi_variable.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c +index e0d7f5736d..699f4184d9 100644 +--- a/lib/efi_loader/efi_variable.c ++++ b/lib/efi_loader/efi_variable.c +@@ -335,7 +335,7 @@ efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t *variable_name_size, + EFI_ENTRY("%p \"%ls\" %pUl", variable_name_size, variable_name, vendor); + + if (!variable_name_size || !variable_name || !vendor) +- EFI_EXIT(EFI_INVALID_PARAMETER); ++ return EFI_EXIT(EFI_INVALID_PARAMETER); + + if (variable_name[0]) { + /* check null-terminated string */ +-- +2.20.1 + +From 1fd7a4764103781e424ef687034da06de3cb60b7 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 19 Mar 2019 18:44:05 +0100 +Subject: [PATCH 04/25] efi_loader: memory leak in efi_dump_single_var() + +A misplaced return statement lead to a memory leak in +efi_dump_single_var(). + +Reported-by: Coverity (CID 185829) +Signed-off-by: Heinrich Schuchardt +--- + cmd/nvedit_efi.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c +index ca32566a61..e65b38dbf3 100644 +--- a/cmd/nvedit_efi.c ++++ b/cmd/nvedit_efi.c +@@ -80,7 +80,6 @@ static void efi_dump_single_var(u16 *name, efi_guid_t *guid) + printf(", DataSize = 0x%zx\n", size); + print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, data, size, true); + +- return; + out: + free(data); + } +-- +2.20.1 + +From d5974af7f7626777b5c41894f75c813ff35c1793 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 19 Mar 2019 18:58:58 +0100 +Subject: [PATCH 05/25] efi_loader: remove superfluous check in + efi_setup_loaded_image() + +It does not make any sense to check if a pointer is NULL if we have +dereferenced it before. + +Reported-by: Coverity (CID 185827) +Signed-off-by: Heinrich Schuchardt +--- + lib/efi_loader/efi_boottime.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c +index bd8b8a17ae..4fc550d9f3 100644 +--- a/lib/efi_loader/efi_boottime.c ++++ b/lib/efi_loader/efi_boottime.c +@@ -1581,10 +1581,8 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, + goto failure; + #endif + +- if (info_ptr) +- *info_ptr = info; +- if (handle_ptr) +- *handle_ptr = obj; ++ *info_ptr = info; ++ *handle_ptr = obj; + + return ret; + failure: +-- +2.20.1 + +From 1646e0928c8eb052bfa2283a6ab8d9f2a92a10e9 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 19 Mar 2019 19:16:23 +0100 +Subject: [PATCH 06/25] efi_loader: superfluous conversion in efi_file_open() + +printf("%ls", ..) expects u16 * as argument to print. There is not need for +a conversion to wchar_t *. + +Signed-off-by: Heinrich Schuchardt +--- + lib/efi_loader/efi_file.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c +index 3a7323765b..bc715218a1 100644 +--- a/lib/efi_loader/efi_file.c ++++ b/lib/efi_loader/efi_file.c +@@ -226,7 +226,7 @@ static efi_status_t EFIAPI efi_file_open(struct efi_file_handle *file, + efi_status_t ret; + + EFI_ENTRY("%p, %p, \"%ls\", %llx, %llu", file, new_handle, +- (wchar_t *)file_name, open_mode, attributes); ++ file_name, open_mode, attributes); + + /* Check parameters */ + if (!file || !new_handle || !file_name) { +-- +2.20.1 + +From d0bd87612f410a723d5ddb3001e805485e3efb4f Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 19 Mar 2019 20:08:46 +0100 +Subject: [PATCH 07/25] efi_selftest: fix test_hii_string_get_string() + +The check testing the string result of get_string() returned the wrong +result. The result was ignored. + +Use efi_st_strcmp_16_8() for the string comparison. + +Signed-off-by: Heinrich Schuchardt +--- + lib/efi_selftest/efi_selftest_hii.c | 17 ++++------------- + 1 file changed, 4 insertions(+), 13 deletions(-) + +diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c +index 8a0b3bc353..f4b70f7950 100644 +--- a/lib/efi_selftest/efi_selftest_hii.c ++++ b/lib/efi_selftest/efi_selftest_hii.c +@@ -783,19 +783,10 @@ static int test_hii_string_get_string(void) + goto out; + } + +-#if 1 +- u16 *c1, *c2; +- +- for (c1 = string, c2 = L"Japanese"; *c1 == *c2; c1++, c2++) +- ; +- if (!*c1 && !*c2) +- result = EFI_ST_SUCCESS; +- else +- result = EFI_ST_FAILURE; +-#else +- /* TODO: %ls */ +- efi_st_printf("got string is %s (can be wrong)\n", string); +-#endif ++ if (efi_st_strcmp_16_8(string, "Japanese")) { ++ efi_st_error("get_string returned incorrect string\n"); ++ goto out; ++ } + + result = EFI_ST_SUCCESS; + +-- +2.20.1 +