diff --git a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch new file mode 100644 index 0000000..3e76ea9 --- /dev/null +++ b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch @@ -0,0 +1,2526 @@ +From patchwork Tue May 12 18:47:08 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sylwester Nawrocki +X-Patchwork-Id: 1288721 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Authentication-Results: ozlabs.org; + dmarc=pass (p=none dis=none) header.from=samsung.com +Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; + unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 + header.s=mail20170921 header.b=d38K5udu; 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+ Tue, 12 May 2020 18:47:40 +0000 (GMT) +From: Sylwester Nawrocki +To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com +Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, + jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, + Sylwester Nawrocki +Subject: [PATCH v3 1/9] usb: xhci: Add missing cache flush in the scratchpad + array initialization +Date: Tue, 12 May 2020 20:47:08 +0200 +Message-Id: <20200512184716.2869-2-s.nawrocki@samsung.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> +X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsWy7djPc7q+73fFGWxeLm2xccZ6VoupPfEW + e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs + HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGXc + XfWasWAKZ8XHpQeYGhjPsncxcnJICJhIrF/3BMjm4hASWMEo8fr8L1YI5wujxJmdXcwQzmdG + idPv17PAtNxZtJQRIrGcUWLemw8scC33Vj8EG8wmYCjRe7SPEcQWEQiQuPZzGlgHs8BRRok1 + +/+AjRIWSJbY+GYJmM0ioCpxsucAmM0rYCXx7u4iVoh18hKrNxxgBrE5Bawlrm8+BnaThMAq + dokV/6ZAveEiMXnjaqgGYYlXx7dAxWUk/u+czwTR0Mwo0bP7NjuEM4FR4v7xBYwQVdYSd879 + Yuti5AC6T1Ni/S59EFNCwFHi83MtCJNP4sZbQZBiZiBz0rbpzBBhXomONiGIGSoSv1dNZ4Kw + pSS6n/yHhpaHxIFJu8DOFxLoY5SY9NFzAqP8LIRVCxgZVzGKp5YW56anFhvnpZbrFSfmFpfm + pesl5+duYgSmmtP/jn/dwbjvT9IhRgEORiUe3oj6XXFCrIllxZW5hxglOJiVRHhbMnfGCfGm + JFZWpRblxxeV5qQWH2KU5mBREuc1XvQyVkggPbEkNTs1tSC1CCbLxMEp1cAY8FeRl+/HltTN + X4Xs903RVHy5e6dgqpeg0jm+4OVBkrPvpUVJPnj+KVdkzo41t/PuMjReEPlxUCtyWmyHz103 + rgXPZq0ykbWOfJ3YefagS9XPQu/PB+O5tq6w9/7zm4Vf6+bV1z8qDodnyLT/WPJqT6T6+32H + jgl/27XgeAnrlllibgaZdotvKrEUZyQaajEXFScCAAKlHx8xAwAA +X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7o+73fFGUxZr2+xccZ6VoupPfEW + e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs + HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF + G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GXcXfWasWAKZ8XHpQeYGhjPsncx + cnJICJhI3Fm0lLGLkYtDSGApo8SCbWtZuhg5gBJSEvNblCBqhCX+XOtig6j5xCixZOleFpAE + m4ChRO/RPkYQW0QgROLF0StMIEXMAmcZJRZ1fmAFSQgLJErMbDgGZrMIqEqc7DkA1swrYCXx + 7u4iVogN8hKrNxxgBrE5Bawlrm8+BmYLAdXs+faObQIj3wJGhlWMIqmlxbnpucWGesWJucWl + eel6yfm5mxiBgb/t2M/NOxgvbQw+xCjAwajEw8tQuytOiDWxrLgy9xCjBAezkghvS+bOOCHe + lMTKqtSi/Pii0pzU4kOMpkBHTWSWEk3OB0ZlXkm8oamhuYWlobmxubGZhZI4b4fAwRghgfTE + ktTs1NSC1CKYPiYOTqkGRvHA5utdDK+71Gc8yncU/Jl1s8GwlfnWtf/fvVcf2j1n1dGNJtMn + +bzXEb/JdkYl/OLZA3Vvo7aKLFyzg7Gsd9N+h4PpR6bHn7zJ79VRWnHmnV1WVtDq6BmPbh3d + 8qTxqqDqXif96Ra5p80yGxK5+NgP7Gd22F52neeB/7I+A4//v1Y946i/MFmJpTgj0VCLuag4 + EQDJGyeQkgIAAA== +X-CMS-MailID: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9 +X-Msg-Generator: CA +X-RootMTR: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9 +X-EPHeader: CA +CMS-TYPE: 201P +X-CMS-RootMailID: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9 +References: <20200512184716.2869-1-s.nawrocki@samsung.com> + +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +In current code there is no cache flush after initializing the scratchpad +buffer array with the scratchpad buffer pointers. This leads to a failure +of the "slot enable" command on the rpi4 board (Broadcom STB PCIe +controller + VL805 USB hub) - the very first TRB transfer on the command +ring fails and there is a timeout while waiting for the command completion +event. After adding the missing cache flush everything seems to be working +as expected. + +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- +Changes since v1: + - none. +--- + drivers/usb/host/xhci-mem.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 93450ee..729bdc3 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) + scratchpad->sp_array[i] = cpu_to_le64(ptr); + } + ++ xhci_flush_cache((uintptr_t)scratchpad->sp_array, ++ sizeof(u64) * num_sp); ++ + return 0; + + fail_sp3: + +From patchwork Tue May 12 18:47:09 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sylwester Nawrocki +X-Patchwork-Id: 1288726 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; 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+ Tue, 12 May 2020 18:47:43 +0000 (GMT) +From: Sylwester Nawrocki +To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com +Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, + jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, + Sylwester Nawrocki , Sergey Temerkhanov + +Subject: [PATCH v3 2/9] usb: xhci: Use only 32-bit accesses in + xhci_writeq/xhci_readq +Date: Tue, 12 May 2020 20:47:09 +0200 +Message-Id: <20200512184716.2869-3-s.nawrocki@samsung.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> +X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRju2845O5qL05R8M8EYRRhecdQhLylJnh8ikpJSNFt5UPHappb1 + Q0NZzjuJGou8NGyhpKlrOW95NxLTJE1KUcMyRQu1RTPRnEfr3/M+l/d9+PhIvqgatyNjEpJZ + eYIsTkxYYvp+07Bz8I8WqVtrhxfd8KAep0vyIuj2pUKCnlhX4vSz3ikBvaS8i+jK4jmc1qu1 + BN2zdA+nq9UdAvqXTo/o5XaVwNeKUU8PEczDjHcYU65+jTEG9ZSAGZpsRkyBrgYx9boxjGka + vBNMXrL0imTjYlJZuavPVctoQ3EVnrRG3VrJ1hAZaFaYgyxIoCSge1mO5yBLUkQ9RfBdtUhw + w08Ekwuju8MaAlONUrAXaVQqESdoETR8LOH9i+hqX/DMLoJyh/y+AmTGNlQwjJtKdxJ8yojg + Te4IZhasqTBQjc4SZoxRx0G7odkJC6kz8HWwA+POOUDt806+GVtQnvChqZ9vXgRUnQDaCvMJ + zuQPBqMK57A1LA7odrvaw5ahgscFMhHktX4ScEMRgumBSsS5PGHy7fr2JnK7nyPUt7hytB9U + /NbzzDRQB2Bi+aCZ5m/D+/oyPkcLIVsp4tzH4E9NGY/DdpA7t7Xbn4G1vjoB90IFCDK7THgR + clD/P1aJUA2yZVMU8VGswiOBvemikMUrUhKiXK4nxjei7c8zuDlgbEYdG9e6EUUisZUwPL1F + KsJlqYq0+G4EJF9sI8yKMUhFwkhZ2m1WnhghT4ljFd3oCImJbYUejxeuiKgoWTIby7JJrHxP + 5ZEWdhno9GbOeQf7Vl+Jk8nnRLVIMhTnGHaoR+Kq6kppqzi7fMF7ZSKwp9d/3njKu0UyrZUG + Tc84TXaFfjOi1dHQi/OJY5rxG6VPqoZfHVWpIoICwvcHhkCAW2Rr+8RI+rBGmV13+Zzmi/Oj + GTj8WYhQFa/Or3a1d19tQ2xI5/ssqU2BGFNEy9xP8uUK2V8p3t8YOAMAAA== +X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42I5/e/4XV3/97viDHb26llsnLGe1WJqT7zF + 3jf9bBY3frWxWqw9cpfd4k1bI6PFgslPWC22zVrOZnH4TTurxdJZ+9gtvm3Zxmjxdm8nuwOP + x6z7Z9k8ZjdcZPGYN+sEi8fOWXfZPc7e2cHo0bdlFaPH+i1XWTw2n64O4IjSsynKLy1JVcjI + Ly6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQy9g5eSFrwWeBio8di9ka + GB/ydjFyckgImEhsamtj7GLk4hASWMoosWrtQiCHAyghJTG/RQmiRljiz7UuNoiaT4wSjVff + soAk2AQMJXqP9jGC2CICIRIvjl5hAiliFvjLKDGp9QkrSEJYIFTi7tP5YDaLgKrE8j+LmUBs + XgEriWen97FAbJCXWL3hADOIzSlgLXF98zEwWwioZs+3d2wTGPkWMDKsYhRJLS3OTc8tNtQr + TswtLs1L10vOz93ECIyBbcd+bt7BeGlj8CFGAQ5GJR5ehtpdcUKsiWXFlbmHGCU4mJVEeFsy + d8YJ8aYkVlalFuXHF5XmpBYfYjQFOmois5Rocj4wPvNK4g1NDc0tLA3Njc2NzSyUxHk7BA7G + CAmkJ5akZqemFqQWwfQxcXBKNTB6nbS75KLLcXaSEefxVQuf7fj8f9bj7/+W83UdTBPtbEo9 + LXT2+/znb9WWx/X7dl++fTu/uqBaPixV8t3/v6YG/SXmdQ/NeHqaT3MnmTe3rbNZkZFrr1IY + y//PRYDVYEtvSsrjr8UK0VdCpk42XPb0vaNeRErYDM4ZZm4ajV3LF4k56rzcN0uJpTgj0VCL + uag4EQCTL19flwIAAA== +X-CMS-MailID: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58 +X-Msg-Generator: CA +X-RootMTR: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58 +X-EPHeader: CA +CMS-TYPE: 201P +X-CMS-RootMailID: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58 +References: <20200512184716.2869-1-s.nawrocki@samsung.com> + +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +There might be hardware configurations where 64-bit data accesses +to XHCI registers are not supported properly. This patch removes +the readq/writeq so always two 32-bit accesses are used to read/write +64-bit XHCI registers, similarly as it is done in Linux kernel. + +This patch fixes operation of the XHCI controller on RPI4 Broadcom +BCM2711 SoC based board, where the VL805 USB XHCI controller is +connected to the PCIe Root Complex, which is attached to the system +through the SCB bridge. + +Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely +the 64-bit wide register accesses initiated by the CPU are not properly +translated to a sequence of 32-bit PCIe accesses. +xhci_readq(), for example, always returns same value in upper and lower +32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. + +Cc: Sergey Temerkhanov +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- +Changes since v1: + - none. +Changes since RFC: + - dropped Kconfig option, switched to not using readq/writeq + unconditionally. +--- + include/usb/xhci.h | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/include/usb/xhci.h b/include/usb/xhci.h +index 6017504..c16106a 100644 +--- a/include/usb/xhci.h ++++ b/include/usb/xhci.h +@@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) + */ + static inline u64 xhci_readq(__le64 volatile *regs) + { +-#if BITS_PER_LONG == 64 +- return readq(regs); +-#else + __u32 *ptr = (__u32 *)regs; + u64 val_lo = readl(ptr); + u64 val_hi = readl(ptr + 1); + return val_lo + (val_hi << 32); +-#endif + } + + static inline void xhci_writeq(__le64 volatile *regs, const u64 val) + { +-#if BITS_PER_LONG == 64 +- writeq(val, regs); +-#else + __u32 *ptr = (__u32 *)regs; + u32 val_lo = lower_32_bits(val); + /* FIXME */ + u32 val_hi = upper_32_bits(val); + writel(val_lo, ptr); + writel(val_hi, ptr + 1); +-#endif + } + + int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, + +From patchwork Tue May 12 18:47:10 2020 +Content-Type: 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0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +Some PCI Express register offsets are currently defined in multiple +drivers, move them to a common header to avoid re-definitions and +as a pre-requisite for adding new PCIe driver. +While at it replace some spaces with tabs. + +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- +Changes since v1: + - none. +Changes since RFC: + - whitespace clean up. +--- + drivers/pci/pci-rcar-gen3.c | 8 -------- + drivers/pci/pcie_intel_fpga.c | 3 --- + include/pci.h | 13 +++++++++++-- + 3 files changed, 11 insertions(+), 13 deletions(-) + +diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c +index 30eff67..393f1c9 100644 +--- a/drivers/pci/pci-rcar-gen3.c ++++ b/drivers/pci/pci-rcar-gen3.c +@@ -117,14 +117,6 @@ + #define RCAR_PCI_MAX_RESOURCES 4 + #define MAX_NR_INBOUND_MAPS 6 + +-#define PCI_EXP_FLAGS 2 /* Capabilities register */ +-#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +-#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +-#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +-#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +- + enum { + RCAR_PCI_ACCESS_READ, + RCAR_PCI_ACCESS_WRITE, +diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c +index 6a9f29c..69363a0 100644 +--- a/drivers/pci/pcie_intel_fpga.c ++++ b/drivers/pci/pcie_intel_fpga.c +@@ -65,9 +65,6 @@ + #define IS_ROOT_PORT(pcie, bdf) \ + ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) + +-#define PCI_EXP_LNKSTA 18 /* Link Status */ +-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +- + /** + * struct intel_fpga_pcie - Intel FPGA PCIe controller state + * @bus: Pointer to the PCI bus +diff --git a/include/pci.h b/include/pci.h +index aff56b2..dfdbb32 100644 +--- a/include/pci.h ++++ b/include/pci.h +@@ -471,10 +471,19 @@ + #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ + + /* PCI Express capabilities */ ++#define PCI_EXP_FLAGS 2 /* Capabilities register */ ++#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ ++#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ + #define PCI_EXP_DEVCAP 4 /* Device capabilities */ +-#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ ++#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ + #define PCI_EXP_DEVCTL 8 /* Device Control */ +-#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ ++#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ ++#define PCI_EXP_LNKSTA 18 /* Link Status */ ++#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ ++#define 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+List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +From: Marek Szyprowski + +Remove the overlap between DRAM and device's IO area. + +Signed-off-by: Marek Szyprowski +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Nicolas Saenz Julienne +--- +Changes since v1: + - none. +--- + arch/arm/mach-bcm283x/init.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 9966d6c..4295356 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +- .size = 0xfe000000UL, ++ .size = 0xfc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + +From patchwork Tue May 12 18:47:12 2020 +Content-Type: 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b.zolnierkie@samsung.com, + Sylwester Nawrocki +Subject: [PATCH v3 5/9] rpi4: add a mapping for the PCIe XHCI controller + MMIO registers (ARM 64bit) +Date: Tue, 12 May 2020 20:47:12 +0200 +Message-Id: <20200512184716.2869-6-s.nawrocki@samsung.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> +X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPKsWRmVeSWpSXmKPExsWy7djP87r173fFGXxfxWKxccZ6VoupPfEW + e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs + HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGV8 + WriNvWCTYMWOfbvYGxgX8HUxcnJICJhITDy4ka2LkYtDSGAFo0TT213MEM4XRokzu3YwQjif + GSXajuxjg2npnd7MBJFYzihx7fJ5FriWpYe+M4NUsQkYSvQe7WMEsUUEAiSu/ZwGNopZ4Cij + xJr9f1hAEsICqRKNrx6CjWURUJX4Nm82WJxXwEriSu8/qHXyEqs3HAAbyilgLXF98zFmiPgy + domli0UgbBeJ39tnM0HYwhKvjm9hh7BlJP7vnA92qoRAM6NEz+7b7BDOBEaJ+8cXMEJUWUvc + OfcLaBsH0HmaEut36UOEHSWWbO5iBQlLCPBJ3HgrCBJmBjInbZvODBHmlehoE4KoVpH4vWo6 + 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0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +From: Marek Szyprowski + +Create a non-cacheable mapping for the 0x600000000 physical memory region, +where MMIO registers for the PCIe XHCI controller are instantiated by the +PCIe bridge. + +Signed-off-by: Marek Szyprowski +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Nicolas Saenz Julienne +--- +Changes since v2: + - fixed typo MAX_MAP_MAX_ENTRIES -> MEM_MAP_MAX_ENTRIES +Changes since v1: + - none. +--- + arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 4295356..9f5bca3 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -11,10 +11,15 @@ + #include + #include + ++#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL ++#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL ++ + #ifdef CONFIG_ARM64 + #include + +-static struct mm_region bcm283x_mem_map[] = { ++#define MEM_MAP_MAX_ENTRIES (4) ++ ++static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { + } + }; + +-static struct mm_region bcm2711_mem_map[] = { ++static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { ++ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, ++ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, ++ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { + /* List terminator */ + 0, + } +@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) + { + int i; + +- for (i = 0; i < 2; i++) { ++ for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) { + mem_map[i].virt = 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+ +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +From: Nicolas Saenz Julienne + +Imports Al Viro's original Linux commit 00b0c9b82663a, which contains +an in depth explanation and two fixes from Johannes Berg: + e7d4a95da86e0 "bitfield: fix *_encode_bits()", + 37a3862e12382 "bitfield: add u8 helpers". + +Signed-off-by: Nicolas Saenz Julienne +[s.nawrocki: added empty lines between functions and macros] +Signed-off-by: Sylwester Nawrocki +--- +Changes since v1: + - added empty lines between functions and macros. + +Changes since RFC: + - new patch. +--- + include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index 8b9d6ff..7acba4c 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -103,4 +103,54 @@ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + ++extern void __compiletime_error("value doesn't fit into mask") ++__field_overflow(void); ++extern void __compiletime_error("bad bitfield mask") ++__bad_mask(void); ++static __always_inline u64 field_multiplier(u64 field) ++{ ++ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) ++ __bad_mask(); ++ return field & -field; ++} ++static __always_inline u64 field_mask(u64 field) ++{ ++ return field / field_multiplier(field); ++} ++ ++#define ____MAKE_OP(type,base,to,from) \ ++static __always_inline __##type type##_encode_bits(base v, base field) \ ++{ \ ++ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ ++ __field_overflow(); \ ++ return to((v & field_mask(field)) * field_multiplier(field)); \ ++} \ ++static __always_inline __##type type##_replace_bits(__##type old, \ ++ base val, base field) \ ++{ \ ++ return (old & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline void type##p_replace_bits(__##type *p, \ ++ base val, base field) \ ++{ \ ++ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline base type##_get_bits(__##type v, base field) \ ++{ \ ++ return (from(v) & field)/field_multiplier(field); \ ++} ++ ++#define __MAKE_OP(size) \ ++ ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ ++ ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ ++ ____MAKE_OP(u##size,u##size,,) ++ ++____MAKE_OP(u8,u8,,) ++__MAKE_OP(16) ++__MAKE_OP(32) ++__MAKE_OP(64) ++ ++#undef __MAKE_OP ++#undef ____MAKE_OP ++ + #endif + +From patchwork Tue May 12 18:47:14 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sylwester Nawrocki +X-Patchwork-Id: 1288733 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender 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+X-CMS-MailID: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985 +X-Msg-Generator: CA +X-RootMTR: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985 +X-EPHeader: CA +CMS-TYPE: 201P +X-CMS-RootMailID: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985 +References: <20200512184716.2869-1-s.nawrocki@samsung.com> + +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +Add PCI Express capability definitions required by the Broadcom +STB PCIe controller driver. + +Signed-off-by: Sylwester Nawrocki +Reviewed-by: Bin Meng +Reviewed-by: Nicolas Saenz Julienne +--- +Changes since v2: + - added Current Link Speed defines. +Changes since v1: + - none. +Changes since RFC: + - ensure the entries are added in order, sorted by ascending + address values. +--- + include/pci.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/include/pci.h b/include/pci.h +index dfdbb32..ff5f620 100644 +--- a/include/pci.h ++++ b/include/pci.h +@@ -479,11 +479,20 @@ + #define PCI_EXP_DEVCTL 8 /* Device Control */ + #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ + #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ ++#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ ++#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ + #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ + #define PCI_EXP_LNKSTA 18 /* Link Status */ ++#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ ++#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ ++#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ ++#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ ++#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ ++#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ + #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ + #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ + #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ ++#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ + + /* Include the ID list */ + + +From patchwork Tue May 12 18:47:15 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sylwester Nawrocki +X-Patchwork-Id: 1288734 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Authentication-Results: ozlabs.org; + dmarc=pass (p=none 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20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae +References: <20200512184716.2869-1-s.nawrocki@samsung.com> + +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +This patch adds basic driver PCI Express controller found on Broadcom +set-top-box SoCs, e.g. BCM2711. +The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI +handling removed. The inbound access memory region is not currently +parsed from dma-ranges DT property and a fixed 3GB region is used. + +The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 +USB Host Controller. + +Signed-off-by: Nicolas Saenz Julienne +Signed-off-by: Sylwester Nawrocki +--- +Changes since v2: + - removed MDO_RD_DONE, MDIO_WT_DONE macro definitions, + - updated the Kconfig entry help text, + - reordered #include entries to match the coding style, + - s/udev/dev, + - s/ENODEV/EINVAL in brcm_pcie_probe() and brcm_pcie_config_address() + functions, + - Simplified brcm_pcie_mdio_{read, write} functions (readl_poll_timeout), + - shortened register bit fields macro definitions, + - dropped brcm_pcie_perst_set() and brcm_pcie_bridge_sw_init_set() + function in favour of direct clrbits_le32/setbits_le32 calls, + - use setbits_le32/clrbits_le32/clrsetbits_le32 instead of + readl(), u32p_replace_bits(), writel() sequence + - simplified brcm_pcie_config_address(), brcm_pcie_set_gen() functions, + - changed reset pulse delay to 100 us, + - Replaced FIELD_GET() with open coded bitwise operations, + - brcm_cpie_cfg_index() function merged into brcm_pcie_config_address(), + - use standard PCI PCI_EXP_LNKSTA_CLS_* link speed defines + - added kernel-doc function comments. + +Changes since v1: + - fixed argument in brcm_pcie_set_ssc() function call, + - changed rc_bar2_size assignment to value 0xC0000000, as in upstream + devicetree. +Changes since RFC: + - reworked to align with current Linux mainline version and u-boot + driver by Nicolas Saenz Julienne. +--- + drivers/pci/Kconfig | 9 + + drivers/pci/Makefile | 1 + + drivers/pci/pcie_brcmstb.c | 623 +++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 633 insertions(+) + create mode 100644 drivers/pci/pcie_brcmstb.c + +diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig +index 437cd9a..543bd46 100644 +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -197,4 +197,13 @@ config PCIE_MEDIATEK + Say Y here if you want to enable Gen2 PCIe controller, + which could be found on MT7623 SoC family. + ++config PCI_BRCMSTB ++ bool "Broadcom STB PCIe controller" ++ depends on DM_PCI ++ depends on ARCH_BCM283X ++ help ++ Say Y here if you want to enable support for PCIe controller ++ on Broadcom set-top-box (STB) SoCs. ++ This driver currently supports only BCM2711 SoC and RC mode ++ of the controller. + endif +diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile +index c051ecc..3e53b1f 100644 +--- a/drivers/pci/Makefile ++++ b/drivers/pci/Makefile +@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o + obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o + obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o + obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o ++obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +new file mode 100644 +index 0000000..dade79e +--- /dev/null ++++ b/drivers/pci/pcie_brcmstb.c +@@ -0,0 +1,623 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB PCIe controller driver ++ * ++ * Copyright (C) 2020 Samsung Electronics Co., Ltd. ++ * ++ * Based on upstream Linux kernel driver: ++ * drivers/pci/controller/pcie-brcmstb.c ++ * Copyright (C) 2009 - 2017 Broadcom ++ * ++ * Based driver by Nicolas Saenz Julienne ++ * Copyright (C) 2020 Nicolas Saenz Julienne ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Offset of the mandatory PCIe capability config registers */ ++#define BRCM_PCIE_CAP_REGS 0x00ac ++ ++/* The PCIe controller register offsets */ ++#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188 ++#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc ++#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0 ++ ++#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c ++#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff ++ ++#define PCIE_RC_DL_MDIO_ADDR 0x1100 ++#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 ++#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 ++ ++#define PCIE_MISC_MISC_CTRL 0x4008 ++#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 ++#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 ++#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 ++#define MISC_CTRL_MAX_BURST_SIZE_128 0x0 ++#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c ++#define PCIE_MEM_WIN0_LO(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 ++#define PCIE_MEM_WIN0_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) ++ ++#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c ++#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f ++ ++#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 ++#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f ++#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 ++ ++#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c ++#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f ++ ++#define PCIE_MISC_PCIE_STATUS 0x4068 ++#define STATUS_PCIE_PORT_MASK 0x80 ++#define STATUS_PCIE_PORT_SHIFT 7 ++#define STATUS_PCIE_DL_ACTIVE_MASK 0x20 ++#define STATUS_PCIE_DL_ACTIVE_SHIFT 5 ++#define STATUS_PCIE_PHYLINKUP_MASK 0x10 ++#define STATUS_PCIE_PHYLINKUP_SHIFT 4 ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 ++#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 ++#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 ++#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 ++#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 ++#define MEM_WIN0_BASE_HI_BASE_MASK 0xff ++#define PCIE_MEM_WIN0_BASE_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 ++#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff ++#define PCIE_MEM_WIN0_LIMIT_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) ++ ++#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 ++#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 ++#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 ++ ++#define PCIE_MSI_INTR2_CLR 0x4508 ++#define PCIE_MSI_INTR2_MASK_SET 0x4510 ++ ++#define PCIE_EXT_CFG_DATA 0x8000 ++ ++#define PCIE_EXT_CFG_INDEX 0x9000 ++#define PCIE_EXT_BUSNUM_SHIFT 20 ++#define PCIE_EXT_SLOT_SHIFT 15 ++#define PCIE_EXT_FUNC_SHIFT 12 ++ ++#define PCIE_RGR1_SW_INIT_1 0x9210 ++#define RGR1_SW_INIT_1_PERST_MASK 0x1 ++#define RGR1_SW_INIT_1_INIT_MASK 0x2 ++ ++/* PCIe parameters */ ++#define BRCM_NUM_PCIE_OUT_WINS 4 ++ ++/* MDIO registers */ ++#define MDIO_PORT0 0x0 ++#define MDIO_DATA_MASK 0x7fffffff ++#define MDIO_DATA_SHIFT 0 ++#define MDIO_PORT_MASK 0xf0000 ++#define MDIO_PORT_SHIFT 16 ++#define MDIO_REGAD_MASK 0xffff ++#define MDIO_REGAD_SHIFT 0 ++#define MDIO_CMD_MASK 0xfff00000 ++#define MDIO_CMD_SHIFT 20 ++#define MDIO_CMD_READ 0x1 ++#define MDIO_CMD_WRITE 0x0 ++#define MDIO_DATA_DONE_MASK 0x80000000 ++#define SSC_REGS_ADDR 0x1100 ++#define SET_ADDR_OFFSET 0x1f ++#define SSC_CNTL_OFFSET 0x2 ++#define SSC_CNTL_OVRD_EN_MASK 0x8000 ++#define SSC_CNTL_OVRD_VAL_MASK 0x4000 ++#define SSC_STATUS_OFFSET 0x1 ++#define SSC_STATUS_SSC_MASK 0x400 ++#define SSC_STATUS_SSC_SHIFT 10 ++#define SSC_STATUS_PLL_LOCK_MASK 0x800 ++#define SSC_STATUS_PLL_LOCK_SHIFT 11 ++ ++/** ++ * struct brcm_pcie - the PCIe controller state ++ * @base: Base address of memory mapped IO registers of the controller ++ * @gen: Non-zero value indicates limitation of the PCIe controller operation ++ * to a specific generation (1, 2 or 3) ++ * @ssc: true indicates active Spread Spectrum Clocking operation ++ */ ++struct brcm_pcie { ++ void __iomem *base; ++ ++ int gen; ++ bool ssc; ++}; ++ ++/** ++ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size ++ * @size: The inbound region size ++ * ++ * This function converts size of the inbound "BAR" region to the non-linear ++ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field. ++ * ++ * Return: The encoded inbound region size ++ */ ++static int brcm_pcie_encode_ibar_size(u64 size) ++{ ++ int log2_in = ilog2(size); ++ ++ if (log2_in >= 12 && log2_in <= 15) ++ /* Covers 4KB to 32KB (inclusive) */ ++ return (log2_in - 12) + 0x1c; ++ else if (log2_in >= 16 && log2_in <= 37) ++ /* Covers 64KB to 32GB, (inclusive) */ ++ return log2_in - 15; ++ ++ /* Something is awry so disable */ ++ return 0; ++} ++ ++/** ++ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode ++ * @pcie: Pointer to the PCIe controller state ++ * ++ * The controller is capable of serving in both RC and EP roles. ++ * ++ * Return: true for RC mode, false for EP mode. ++ */ ++static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) ++{ ++ u32 val; ++ ++ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); ++ ++ return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; ++} ++ ++/** ++ * brcm_pcie_link_up() - Check whether the PCIe link is up ++ * @pcie: Pointer to the PCIe controller state ++ * ++ * Return: true if the link is up, false otherwise. ++ */ ++static bool brcm_pcie_link_up(struct brcm_pcie *pcie) ++{ ++ u32 val, dla, plu; ++ ++ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); ++ dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT; ++ plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT; ++ ++ return dla && plu; ++} ++ ++static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, ++ uint offset, void **paddress) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ unsigned int pci_bus = PCI_BUS(bdf); ++ unsigned int pci_dev = PCI_DEV(bdf); ++ unsigned int pci_func = PCI_FUNC(bdf); ++ int idx; ++ ++ /* ++ * Busses 0 (host PCIe bridge) and 1 (its immediate child) ++ * are limited to a single device each ++ */ ++ if (pci_bus < 2 && pci_dev > 0) ++ return -EINVAL; ++ ++ /* Accesses to the RC go right to the RC registers */ ++ if (pci_bus == 0) { ++ *paddress = pcie->base + offset; ++ return 0; ++ } ++ ++ /* For devices, write to the config space index register */ ++ idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT) ++ | (pci_dev << PCIE_EXT_SLOT_SHIFT) ++ | (pci_func << PCIE_EXT_FUNC_SHIFT); ++ ++ writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); ++ *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; ++ ++ return 0; ++} ++ ++static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong *valuep, ++ enum pci_size_t size) ++{ ++ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, ++ bdf, offset, valuep, size); ++} ++ ++static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong value, ++ enum pci_size_t size) ++{ ++ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, ++ bdf, offset, value, size); ++} ++ ++static const char *link_speed_to_str(unsigned int cls) ++{ ++ switch (cls) { ++ case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5"; ++ case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0"; ++ case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0"; ++ default: ++ break; ++ } ++ ++ return "??"; ++} ++ ++static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad, ++ unsigned int cmd) ++{ ++ u32 pkt; ++ ++ pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK; ++ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK; ++ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK; ++ ++ return pkt; ++} ++ ++/** ++ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus ++ * @base: Pointer to the PCIe controller IO registers ++ * @port: The MDIO port number ++ * @regad: The register address ++ * @val: A pointer at which to store the read value ++ * ++ * Return: 0 on success and register value in @val, negative error value ++ * on failure. ++ */ ++static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port, ++ unsigned int regad, u32 *val) ++{ ++ u32 data, addr; ++ int ret; ++ ++ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ); ++ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); ++ readl(base + PCIE_RC_DL_MDIO_ADDR); ++ ++ ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data, ++ (data & MDIO_DATA_DONE_MASK), 100); ++ ++ *val = data & MDIO_DATA_MASK; ++ ++ return ret; ++} ++ ++/** ++ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus ++ * @base: Pointer to the PCIe controller IO registers ++ * @port: The MDIO port number ++ * @regad: Address of the register ++ * @wrdata: The value to write ++ * ++ * Return: 0 on success, negative error value on failure. ++ */ ++static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port, ++ unsigned int regad, u16 wrdata) ++{ ++ u32 data, addr; ++ ++ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE); ++ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); ++ readl(base + PCIE_RC_DL_MDIO_ADDR); ++ writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); ++ ++ return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data, ++ !(data & MDIO_DATA_DONE_MASK), 100); ++} ++ ++/** ++ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking ++ * @base: pointer to the PCIe controller IO registers ++ * ++ * Return: 0 on success, negative error value on failure. ++ */ ++static int brcm_pcie_set_ssc(void __iomem *base) ++{ ++ int pll, ssc; ++ int ret; ++ u32 tmp; ++ ++ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, ++ SSC_REGS_ADDR); ++ if (ret < 0) ++ return ret; ++ ++ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK); ++ ++ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); ++ if (ret < 0) ++ return ret; ++ ++ udelay(1000); ++ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT; ++ pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT; ++ ++ return ssc && pll ? 0 : -EIO; ++} ++ ++/** ++ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3) ++ * @pcie: pointer to the PCIe controller state ++ * @gen: PCIe generation to limit the controller's operation to ++ */ ++static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen) ++{ ++ void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS; ++ ++ u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2); ++ u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP); ++ ++ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; ++ writel(lnkcap, cap_base + PCI_EXP_LNKCAP); ++ ++ lnkctl2 = (lnkctl2 & ~0xf) | gen; ++ writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2); ++} ++ ++static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, ++ unsigned int win, u64 phys_addr, ++ u64 pcie_addr, u64 size) ++{ ++ void __iomem *base = pcie->base; ++ u32 phys_addr_mb_high, limit_addr_mb_high; ++ phys_addr_t phys_addr_mb, limit_addr_mb; ++ int high_addr_shift; ++ u32 tmp; ++ ++ /* Set the base of the pcie_addr window */ ++ writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); ++ writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); ++ ++ /* Write the addr base & limit lower bits (in MBs) */ ++ phys_addr_mb = phys_addr / SZ_1M; ++ limit_addr_mb = (phys_addr + size - 1) / SZ_1M; ++ ++ tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); ++ u32p_replace_bits(&tmp, phys_addr_mb, ++ MEM_WIN0_BASE_LIMIT_BASE_MASK); ++ u32p_replace_bits(&tmp, limit_addr_mb, ++ MEM_WIN0_BASE_LIMIT_LIMIT_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); ++ ++ /* Write the cpu & limit addr upper bits */ ++ high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; ++ phys_addr_mb_high = phys_addr_mb >> high_addr_shift; ++ tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); ++ u32p_replace_bits(&tmp, phys_addr_mb_high, ++ MEM_WIN0_BASE_HI_BASE_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); ++ ++ limit_addr_mb_high = limit_addr_mb >> high_addr_shift; ++ tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); ++ u32p_replace_bits(&tmp, limit_addr_mb_high, ++ PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); ++} ++ ++static int brcm_pcie_probe(struct udevice *dev) ++{ ++ struct udevice *ctlr = pci_get_controller(dev); ++ struct pci_controller *hose = dev_get_uclass_priv(ctlr); ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ void __iomem *base = pcie->base; ++ bool ssc_good = false; ++ int num_out_wins = 0; ++ u64 rc_bar2_offset, rc_bar2_size; ++ unsigned int scb_size_val; ++ int i, ret; ++ u16 nlw, cls, lnksta; ++ u32 tmp; ++ ++ /* ++ * Reset the bridge, assert the fundamental reset. Note for some SoCs, ++ * e.g. BCM7278, the fundamental reset should not be asserted here. ++ * This will need to be changed when support for other SoCs is added. ++ */ ++ setbits_le32(base + PCIE_RGR1_SW_INIT_1, ++ RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK); ++ /* ++ * The delay is a safety precaution to preclude the reset signal ++ * from looking like a glitch. ++ */ ++ udelay(100); ++ ++ /* Take the bridge out of reset */ ++ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); ++ ++ clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); ++ ++ /* Wait for SerDes to be stable */ ++ udelay(100); ++ ++ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ ++ clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, ++ MISC_CTRL_MAX_BURST_SIZE_MASK, ++ MISC_CTRL_SCB_ACCESS_EN_MASK | ++ MISC_CTRL_CFG_READ_UR_MODE_MASK | ++ MISC_CTRL_MAX_BURST_SIZE_128); ++ /* ++ * TODO: When support for other SoCs than BCM2711 is added we may ++ * need to use the base address and size(s) provided in the dma-ranges ++ * property. ++ */ ++ rc_bar2_offset = 0; ++ rc_bar2_size = 0xc0000000; ++ ++ tmp = lower_32_bits(rc_bar2_offset); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); ++ writel(upper_32_bits(rc_bar2_offset), ++ base + PCIE_MISC_RC_BAR2_CONFIG_HI); ++ ++ scb_size_val = rc_bar2_size ? ++ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ ++ ++ tmp = readl(base + PCIE_MISC_MISC_CTRL); ++ u32p_replace_bits(&tmp, scb_size_val, ++ MISC_CTRL_SCB0_SIZE_MASK); ++ writel(tmp, base + PCIE_MISC_MISC_CTRL); ++ ++ /* Disable the PCIe->GISB memory window (RC_BAR1) */ ++ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, ++ RC_BAR1_CONFIG_LO_SIZE_MASK); ++ ++ /* Disable the PCIe->SCB memory window (RC_BAR3) */ ++ clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO, ++ RC_BAR3_CONFIG_LO_SIZE_MASK); ++ ++ /* Mask all interrupts since we are not handling any yet */ ++ writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); ++ ++ /* Clear any interrupts we find on boot */ ++ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); ++ ++ if (pcie->gen) ++ brcm_pcie_set_gen(pcie, pcie->gen); ++ ++ /* Unassert the fundamental reset */ ++ clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, ++ RGR1_SW_INIT_1_PERST_MASK); ++ ++ /* Give the RC/EP time to wake up, before trying to configure RC. ++ * Intermittently check status for link-up, up to a total of 100ms. ++ */ ++ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) ++ mdelay(5); ++ ++ if (!brcm_pcie_link_up(pcie)) { ++ printf("PCIe BRCM: link down\n"); ++ return -EINVAL; ++ } ++ ++ if (!brcm_pcie_rc_mode(pcie)) { ++ printf("PCIe misconfigured; is in EP mode\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < hose->region_count; i++) { ++ struct pci_region *reg = &hose->regions[i]; ++ ++ if (reg->flags != PCI_REGION_MEM) ++ continue; ++ ++ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) ++ return -EINVAL; ++ ++ brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, ++ reg->bus_start, reg->size); ++ ++ num_out_wins++; ++ } ++ ++ /* ++ * For config space accesses on the RC, show the right class for ++ * a PCIe-PCIe bridge (the default setting is to be EP mode). ++ */ ++ clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3, ++ CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400); ++ ++ if (pcie->ssc) { ++ ret = brcm_pcie_set_ssc(pcie->base); ++ if (!ret) ++ ssc_good = true; ++ else ++ printf("PCIe BRCM: failed attempt to enter SSC mode\n"); ++ } ++ ++ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); ++ cls = lnksta & PCI_EXP_LNKSTA_CLS; ++ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; ++ ++ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), ++ nlw, ssc_good ? "(SSC)" : "(!SSC)"); ++ ++ /* PCIe->SCB endian mode for BAR */ ++ clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1, ++ VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK, ++ VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN); ++ /* ++ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 ++ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. ++ */ ++ setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK); ++ ++ return 0; ++} ++ ++static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ ofnode dn = dev_ofnode(dev); ++ u32 max_link_speed; ++ int ret; ++ ++ /* Get the controller base address */ ++ pcie->base = dev_read_addr_ptr(dev); ++ if (!pcie->base) ++ return -EINVAL; ++ ++ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); ++ ++ ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); ++ if (ret < 0 || max_link_speed > 4) ++ pcie->gen = 0; ++ else ++ pcie->gen = max_link_speed; ++ ++ return 0; ++} ++ ++static const struct dm_pci_ops brcm_pcie_ops = { ++ .read_config = brcm_pcie_read_config, ++ .write_config = brcm_pcie_write_config, ++}; ++ ++static const struct udevice_id brcm_pcie_ids[] = { ++ { .compatible = "brcm,bcm2711-pcie" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(pcie_brcm_base) = { ++ .name = "pcie_brcm", ++ .id = UCLASS_PCI, ++ .ops = &brcm_pcie_ops, ++ .of_match = brcm_pcie_ids, ++ .probe = brcm_pcie_probe, ++ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, ++ .priv_auto_alloc_size = sizeof(struct brcm_pcie), ++}; + +From patchwork Tue May 12 18:47:16 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sylwester Nawrocki +X-Patchwork-Id: 1288735 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; 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To get it working one has to call the following commands: +"pci enum; usb start;", thus such commands have been added to the default +"preboot" environment variable. One has to update their environment if it +is already configured to get this feature working out of the box. + +Signed-off-by: Marek Szyprowski +Signed-off-by: Sylwester Nawrocki +--- +Changes since v2: + - rpi_4_32b_defconfig, rpi_4_defconfig changes moved to separate + patch +Changes since v1: + - removed unneeded CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY entry. + +Changes since RFC: + - none. +--- + configs/rpi_arm64_defconfig | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index fea86be..f12d1e3 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="usb start" ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y +@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_USB=y + CONFIG_DM_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_USB_DWC2=y + CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y diff --git a/USB-host-support-for-Raspberry-Pi-4-board.patch b/USB-host-support-for-Raspberry-Pi-4-board.patch deleted file mode 100644 index 7e025be..0000000 --- a/USB-host-support-for-Raspberry-Pi-4-board.patch +++ /dev/null @@ -1,2810 +0,0 @@ -From patchwork Tue Apr 21 16:50:51 2020 -Content-Type: text/plain; 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- Tue, 21 Apr 2020 16:51:13 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: agraf@suse.de, sjg@chrmium.org, jh80.chung@samsung.com, - m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki - -Subject: [RFC PATCH 1/9] usb: xhci: Add missing cache flush in the - scratchpad array initialization -Date: Tue, 21 Apr 2020 18:50:51 +0200 -Message-Id: <20200421165059.19394-2-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200421165059.19394-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm2zln5zhbHKfgi1nCMqJMTTM4qN1IbP4Toh8VaqsdVNymbV7z - j5dQ8555w8RZYa2ZaCbiBcXU5S2TQE3TKaZFefkzTacOze2s+vc8z/s8z8v38lGYqJRwoaKV - 8axKKZWL+QK89cP2mGeGuyb8bGndSWZwfA8xbysbCaYsP4KZ2skimIZ+A8msZqUjpvbJEsH0 - rWYTTM7EPmLWuh6RlwWS+eE0QlJTNYhL2qsMpGR0tg1JClt0SNLYMoFL3o2khpK3BIEyVh6d - yKq8L94RRM1V6/G4HCrZ1J9FpqFJfi6iKKD9YPuLay4SUCJai8D4owZxZAPBpmkO48g6grFp - Iy8X2VkTHeM6m+sVgmHNb/JfpGF7E7e4+LQPFOgLkQU70aEwuV1uTWC0BoHZWG4dONIy0OaX - kRaM0yfg5dMVzIKFdACsTG7xuXVuUN/UY9Xt6EAwbFXiliKgi0hI3yi2vSIIXmfIOb8jLA+0 - kBx2hf12DY/zZyLI75whOVKMYH6gFnGuAJj9tGMtwuhT0NjhzclX4KNpCOf6D8PUmoNFxg5g - SWsFxslCyMkScW532NVV2C7kAnlL+ziHJZBeUGc7YxGCrtJFohi5Vf1fVouQDjmzCWpFJKv2 - VbJJXmqpQp2gjPS6F6toRgd/ZWRvYKMNdZjv9iKaQuJDwqmxmnARIU1Upyh6EVCY2EnYtHAg - CWXSlAesKjZClSBn1b3oCIWLnYXnnv8KE9GR0ng2hmXjWNXfKY+yc0lD55dz3ienzrwJDn7s - UPJicdX3+efuozvfpvLOUKb7RRm3/et/ZhcOL+xEDdZc0l4I0HfaDxUbPHljHl4hZuOk4usz - o71upE3f85A8brgaM+8d1u0nModcr69sdg84tha+eyPyuwc/SJu5sTCtunlttNof9FVFtCyp - sLfOdb3Pw1OMq6OkPqcxlVr6Bzy9nkcnAwAA -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xu7pNKvPjDE7cEbA4ceUfo8XGGetZ - Lab2xFvc+NXGarH2yF12izdtjYwWCyY/YbU4/Kad1aLj6n9Gi7d7O9kduDzun2pg9Zg36wSL - x85Zd9k9zt7ZwejRt2UVo8f6LVdZPDafrg5gj9KzKcovLUlVyMgvLrFVija0MNIztLTQMzKx - 1DM0No+1MjJV0rezSUnNySxLLdK3S9DLuDfnKEtBB0fFjyNt7A2M19i6GDk5JARMJHZdWcXY - xcjFISSwlFFi0rUZQA4HUEJKYn6LEkSNsMSfa11g9UICnxglHj5wBLHZBAwleo/2MYLYIgIh - Ei+OXmECmcMMMudPwxtWkDnCAkkSu39yg9SwCKhKLJv9mhnE5hWwlnh97TvUDfISqzccAItz - CthI3P0+gwVil7VEw6UlLBMY+RYwMqxiFEktLc5Nzy021CtOzC0uzUvXS87P3cQIDPBtx35u - 3sF4aWPwIUYBDkYlHt4b5+fFCbEmlhVX5h5ilOBgVhLh3fAQKMSbklhZlVqUH19UmpNafIjR - FOioicxSosn5wOjLK4k3NDU0t7A0NDc2NzazUBLn7RA4GCMkkJ5YkpqdmlqQWgTTx8TBKdXA - 6LTra6plWsQmuwWK045dDM48yj+vtfXqqqSkoqBLwilHPikq2hWa3TbO25/wunvjY6ZD87SD - 2Sr/ON7d9NNMXpLHyiQiOfEn///MTYYno6+0nPnLOJdpR3t9L/8PU0Gh/YXHVzzNn2YzQ/37 - HO6/kmeSvty49tbYRC7kbMl5hcQNLmukTv+pU2Ipzkg01GIuKk4EAE74o8yGAgAA -X-CMS-MailID: 20200421165114eucas1p2baa595b46f7503331ab86163f69b7c0e -X-Msg-Generator: CA -X-RootMTR: 20200421165114eucas1p2baa595b46f7503331ab86163f69b7c0e -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200421165114eucas1p2baa595b46f7503331ab86163f69b7c0e -References: <20200421165059.19394-1-s.nawrocki@samsung.com> - -X-Mailman-Approved-At: Tue, 21 Apr 2020 19:40:20 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -In current code there is no cache flush after initializing the scratchpad -buffer array with the scratchpad buffer pointers. This leads to a failure -of the "slot enable" command on the rpi4 board (Broadcom STB PCIe -controller + VL805 USB hub) - the very first TRB transfer on the command -ring fails and there is a timeout while waiting for the command completion -event. After adding the missing cache flush everything seems to be working -as expected. - -Signed-off-by: Sylwester Nawrocki ---- - drivers/usb/host/xhci-mem.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c -index 93450ee..729bdc3 100644 ---- a/drivers/usb/host/xhci-mem.c -+++ b/drivers/usb/host/xhci-mem.c -@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) - scratchpad->sp_array[i] = cpu_to_le64(ptr); - } - -+ xhci_flush_cache((uintptr_t)scratchpad->sp_array, -+ sizeof(u64) * num_sp); -+ - return 0; - - fail_sp3: - -From patchwork Tue Apr 21 16:50:52 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1274444 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - 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-List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Some PCI Express register offsets are currently defined in multiple -drivers, move them to a common header to avoid re-definitions and -as a pre-requisite for adding new PCIe driver. - -Signed-off-by: Sylwester Nawrocki ---- - drivers/pci/pci-rcar-gen3.c | 8 -------- - drivers/pci/pcie_intel_fpga.c | 3 --- - include/pci.h | 13 +++++++++++++ - 3 files changed, 13 insertions(+), 11 deletions(-) - -diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c -index 30eff67..393f1c9 100644 ---- a/drivers/pci/pci-rcar-gen3.c -+++ b/drivers/pci/pci-rcar-gen3.c -@@ -117,14 +117,6 @@ - #define RCAR_PCI_MAX_RESOURCES 4 - #define MAX_NR_INBOUND_MAPS 6 - --#define PCI_EXP_FLAGS 2 /* Capabilities register */ --#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ --#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ --#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ --#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ --#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ --#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -- - enum { - RCAR_PCI_ACCESS_READ, - RCAR_PCI_ACCESS_WRITE, -diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c -index 6a9f29c..69363a0 100644 ---- a/drivers/pci/pcie_intel_fpga.c -+++ b/drivers/pci/pcie_intel_fpga.c -@@ -65,9 +65,6 @@ - #define IS_ROOT_PORT(pcie, bdf) \ - ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) - --#define PCI_EXP_LNKSTA 18 /* Link Status */ --#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -- - /** - * struct intel_fpga_pcie - Intel FPGA PCIe controller state - * @bus: Pointer to the PCI bus -diff --git a/include/pci.h b/include/pci.h -index 174ddd4..3d7646d 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -471,11 +471,24 @@ - #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ - - /* PCI Express capabilities */ -+#define PCI_EXP_FLAGS 2 /* Capabilities register */ -+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -+ - #define PCI_EXP_DEVCAP 4 /* Device capabilities */ - #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ - #define PCI_EXP_DEVCTL 8 /* Device Control */ - #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ - -+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -+ -+#define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -+ -+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -+ - /* Include the ID list */ - - #include - -From patchwork Tue Apr 21 16:50:53 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1274441 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - 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-List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Marek Szyprowski - -Remove the overlap between DRAM and device's IO area. - -Signed-off-by: Marek Szyprowski ---- - arch/arm/mach-bcm283x/init.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 9966d6c..4295356 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -- .size = 0xfe000000UL, -+ .size = 0xfc000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - -From patchwork Tue Apr 21 16:50:54 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1274442 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - 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-List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Marek Szyprowski - -Create a non-cacheable mapping for the 0x600000000 physical memory region, -where MMIO registers for the PCIe XHCI controller are instantiated by the -PCIe bridge. - -Signed-off-by: Marek Szyprowski ---- - arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- - 1 file changed, 15 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 4295356..6a748da 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -11,10 +11,15 @@ - #include - #include - -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL -+ - #ifdef CONFIG_ARM64 - #include - --static struct mm_region bcm283x_mem_map[] = { -+#define MAX_MAP_MAX_ENTRIES (4) -+ -+static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { - } - }; - --static struct mm_region bcm2711_mem_map[] = { -+static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { -+ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { - /* List terminator */ - 0, - } -@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) - { - int i; - -- for (i = 0; i < 2; i++) { -+ for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) { - mem_map[i].virt = pd[i].virt; - mem_map[i].phys = pd[i].phys; - mem_map[i].size = pd[i].size; - -From patchwork Tue Apr 21 16:50:55 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1274445 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - 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-List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Marek Szyprowski - -Create a non-cacheable mapping for the 0x600000000 physical memory region, -where MMIO registers for the PCIe XHCI controller are instantiated by the -PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM -32bit mode, this region is mapped at 0xff800000 CPU virtual address. - -Signed-off-by: Marek Szyprowski ---- - arch/arm/mach-bcm283x/Kconfig | 1 + - arch/arm/mach-bcm283x/include/mach/base.h | 7 +++++ - arch/arm/mach-bcm283x/init.c | 52 +++++++++++++++++++++++++++++++ - 3 files changed, 60 insertions(+) - -diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig -index 00419bf..bcb7f1d 100644 ---- a/arch/arm/mach-bcm283x/Kconfig -+++ b/arch/arm/mach-bcm283x/Kconfig -@@ -36,6 +36,7 @@ config BCM2711_32B - select BCM2711 - select ARMV7_LPAE - select CPU_V7A -+ select PHYS_64BIT - - config BCM2711_64B - bool "Broadcom BCM2711 SoC 64-bit support" -diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h -index c4ae398..1d10dc9 100644 ---- a/arch/arm/mach-bcm283x/include/mach/base.h -+++ b/arch/arm/mach-bcm283x/include/mach/base.h -@@ -6,6 +6,13 @@ - #ifndef _BCM283x_BASE_H_ - #define _BCM283x_BASE_H_ - -+#include -+ - extern unsigned long rpi_bcm283x_base; - -+#ifdef CONFIG_ARMV7_LPAE -+extern void *rpi4_phys_to_virt(phys_addr_t paddr); -+#define phys_to_virt(x) rpi4_phys_to_virt(x) -+#endif -+ - #endif -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 6a748da..5d0d160 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -145,6 +145,58 @@ int mach_cpu_init(void) - } - - #ifdef CONFIG_ARMV7_LPAE -+ -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL -+ -+void *rpi4_phys_to_virt(phys_addr_t paddr) -+{ -+ if (paddr >= BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS) -+ paddr = paddr - BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS + -+ BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT; -+ return (void *)(unsigned long)paddr; -+} -+ -+static void set_section_phys(unsigned int section, phys_addr_t phys, -+ enum dcache_option option) -+{ -+ u64 *page_table = (u64 *)gd->arch.tlb_addr; -+ /* Need to set the access flag to not fault */ -+ u64 value = TTB_SECT_AP | TTB_SECT_AF; -+ -+ /* Add the page offset */ -+ value |= (phys); -+ -+ /* Add caching bits */ -+ value |= option; -+ -+ /* Set PTE */ -+ page_table[section] = value; -+} -+ -+static void rpi4_create_pcie_xhci_mapping(void) -+{ -+ unsigned sect = BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT >> MMU_SECTION_SHIFT; -+ phys_addr_t phys_addr = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS; -+ unsigned int size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE; -+ -+ while (size) { -+ set_section_phys(sect, phys_addr, DCACHE_OFF); -+ sect++; -+ phys_addr += MMU_SECTION_SIZE; -+ size -= MMU_SECTION_SIZE; -+ } -+} -+ -+void arm_init_domains(void) -+{ -+ /* -+ * Hijack this function to prepare a mappings for the PCIe MMIO -+ * region for the XHCI controller on RPi4 board. -+ * This code is called before enabling the MMU in ARM 32bit mode. -+ */ -+ rpi4_create_pcie_xhci_mapping(); -+} -+ - void enable_caches(void) - { - dcache_enable(); - -From patchwork Tue Apr 21 16:50:56 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1274443 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; 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- Tue, 21 Apr 2020 16:51:23 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: agraf@suse.de, sjg@chrmium.org, jh80.chung@samsung.com, - m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki - -Subject: [RFC PATCH 6/9] usb: xhci: Allow accessing 64-bit registers with - DWORD accesses only -Date: Tue, 21 Apr 2020 18:50:56 +0200 -Message-Id: <20200421165059.19394-7-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200421165059.19394-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCKsWRmVeSWpSXmKPExsWy7djPc7o9KvPjDFY9ErA4ceUfo8XGGetZ - Lab2xFvc+NXGarH2yF12izdtjYwWCyY/YbU4/Kad1aLj6n9Gi7d7O9kduDzun2pg9Zg36wSL - x85Zd9k9zt7ZwejRt2UVo8f6LVdZPDafrg5gj+KySUnNySxLLdK3S+DKWHP3JXNBg1DFl0W7 - mBsY7/J1MXJySAiYSLy/coIVxBYSWMEo8e2sYxcjF5D9hVFi4beHjBDOZ0aJZQ0/GGE6Jn1d - wASRWM4osW7OOWa4lgfr5oFVsQkYSvQe7QOzRQQCJK79nAY2illgPqPEn0/TwBLCAvES958s - ZgOxWQRUJSZ2rGECsXkFrCWuLp/GDrFOXmL1hgPMIDangI3E3e8zWCDik9klFt2XhrBdJC5c - usoGYQtLvDq+BapXRuL/zvlgp0oINDNK9Oy+zQ7hTGCUuH98AdRD1hJ3zv0C6uYAOk9TYv0u - fYiwo0Tf1HesIGEJAT6JG28FQcLMQOakbdOZIcK8Eh1tQhDVKhK/V01ngrClJLqf/Ic600Pi - w8fFLJAA6meU6Nr7nnECo/wshGULGBlXMYqnlhbnpqcWG+allusVJ+YWl+al6yXn525iBKaV - 0/+Of9rB+PVS0iFGAQ5GJR7eG+fnxQmxJpYVV+YeYpTgYFYS4d3wECjEm5JYWZValB9fVJqT - WnyIUZqDRUmc13jRy1ghgfTEktTs1NSC1CKYLBMHp1QDo0NlrlZnZIZvA8+uwiqVNYzC/zbd - 8izctWfuNx4XYxXelzfU2SRYA08E32U8UlLxXiGjV3fxrc/35C7e3pyxj0dLTePrncrpBptb - FX6rXZLVnDGhff2fSQf+6HP95tKR3+wkzi0kXB99vkvDK6eoVW5d0uRYRxXTCfGnozzfc+wL - 6X+tWFehxFKckWioxVxUnAgAMSV15icDAAA= -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsVy+t/xu7rdKvPjDPr7bCxOXPnHaLFxxnpW - i6k98RY3frWxWqw9cpfd4k1bI6PFgslPWC0Ov2lntei4+p/R4u3eTnYHLo/7pxpYPebNOsHi - sXPWXXaPs3d2MHr0bVnF6LF+y1UWj82nqwPYo/RsivJLS1IVMvKLS2yVog0tjPQMLS30jEws - 9QyNzWOtjEyV9O1sUlJzMstSi/TtEvQy1tx9yVzQIFTxZdEu5gbGu3xdjJwcEgImEpO+LmDq - YuTiEBJYyihx8udKxi5GDqCElMT8FiWIGmGJP9e62CBqPjFKfOxoZgJJsAkYSvQe7WMEsUUE - QiReHL0CNogZZNCfhjesIAlhgViJGXMWsYPYLAKqEhM71oA18wpYS1xdPo0dYoO8xOoNB5hB - bE4BG4m732ewgNhCQDUNl5awTGDkW8DIsIpRJLW0ODc9t9hIrzgxt7g0L10vOT93EyMwyLcd - +7llB2PXu+BDjAIcjEo8vDfOz4sTYk0sK67MPcQowcGsJMK74SFQiDclsbIqtSg/vqg0J7X4 - EKMp0FETmaVEk/OBEZhXEm9oamhuYWlobmxubGahJM7bIXAwRkggPbEkNTs1tSC1CKaPiYNT - qoExbeNShg0BsVpXNX2+ynqZ6E7NXSE7VcnncfFtX/399bscXzZ29OomzhFKnuj8rz715Ruj - Dfa+8s+n7hDYcHyawgFVruDoGTumeS/WeHOltsT4QDWHrfWL65mbVjLm/99wxqyee9+3r8fY - 3h36XGPv8K1gQVD7jm/XPqUe2OMxsVg3m+mz4/cjSizFGYmGWsxFxYkAsqsjeYgCAAA= -X-CMS-MailID: 20200421165124eucas1p161d4049c0e136fc74ae2b00c2a1b3883 -X-Msg-Generator: CA -X-RootMTR: 20200421165124eucas1p161d4049c0e136fc74ae2b00c2a1b3883 -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200421165124eucas1p161d4049c0e136fc74ae2b00c2a1b3883 -References: <20200421165059.19394-1-s.nawrocki@samsung.com> - -X-Mailman-Approved-At: Tue, 21 Apr 2020 19:40:20 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -This patch adds a Kconfig option which allows accessing 64-bit xHCI -IO registers only with 2 double word accesses rather than using -a single quad word access. There might be HW configurations where -single quad word access doesn't work, even though the CPU is 64-bit. -That seems to be the case on rpi4 board with Broadcom BCM2711 SoC, -where the VL805 USB xHCI hub is connected to the PCIe controller -behind the SCB bridge. - -Signed-off-by: Sylwester Nawrocki ---- -So far I couldn't come up with anything better to make the xHCI host -controller working on the rpi4 board. For some reason dereferencing -a 64-bit pointer to access 64-bit registers doesn't work there, -might be a limitation of the PCIe bridge behind the SCB. In Linux -always 2 double word accesses are used. ---- - drivers/usb/host/Kconfig | 7 +++++++ - include/usb/xhci.h | 4 ++-- - 2 files changed, 9 insertions(+), 2 deletions(-) - -diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig -index 0987ff2..3990b8a 100644 ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -15,6 +15,13 @@ config USB_XHCI_HCD - - if USB_XHCI_HCD - -+config XHCI_64BIT_DWORD_ACCESS_ONLY -+ bool "Access xHCI 64-bit registers with double word accesses only" -+ help -+ Choose this option if your hardware does not support quad word accesses -+ for registers with 64-bit address pointers. -+ If unsure, say Y. -+ - config USB_XHCI_DWC3 - bool "DesignWare USB3 DRD Core Support" - help -diff --git a/include/usb/xhci.h b/include/usb/xhci.h -index 6017504..459e76b 100644 ---- a/include/usb/xhci.h -+++ b/include/usb/xhci.h -@@ -1111,7 +1111,7 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) - */ - static inline u64 xhci_readq(__le64 volatile *regs) - { --#if BITS_PER_LONG == 64 -+#if BITS_PER_LONG == 64 && !defined(CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY) - return readq(regs); - #else - __u32 *ptr = (__u32 *)regs; -@@ -1123,7 +1123,7 @@ static inline u64 xhci_readq(__le64 volatile *regs) - - static inline void xhci_writeq(__le64 volatile *regs, const u64 val) - { --#if BITS_PER_LONG == 64 -+#if BITS_PER_LONG == 64 && !defined(CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY) - writeq(val, regs); - #else - __u32 *ptr = (__u32 *)regs; - -From patchwork Tue Apr 21 16:50:57 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1274447 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - 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Tue, 21 Apr 2020 16:51:23 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: agraf@suse.de, sjg@chrmium.org, jh80.chung@samsung.com, - m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Sylwester Nawrocki - -Subject: [RFC PATCH 7/9] pci: Add some PCI Express capability register - offset definitions -Date: Tue, 21 Apr 2020 18:50:57 +0200 -Message-Id: <20200421165059.19394-8-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200421165059.19394-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKKsWRmVeSWpSXmKPExsWy7djPc7o9KvPjDOb3GFqcuPKP0WLjjPWs - FlN74i1u/GpjtVh75C67xZu2RkaLBZOfsFocftPOatFx9T+jxdu9newOXB73TzWwesybdYLF - Y+esu+weZ+/sYPTo27KK0WP9lqssHptPVwewR3HZpKTmZJalFunbJXBlLOnbw1Zwi7Ni8+9z - bA2Mv9m7GDk5JARMJA78WsXaxcjFISSwglHixo1PbBDOF0aJxyvOMUM4nxklNn7czwbT0j75 - CSNEYjmjxP62HQgtB7eeZQWpYhMwlOg92scIYosIBEhc+zkNrINZYD6jxJ9P08ASwgLREt3L - poI1sAioSkw9dxgszitgLXH2+hMWiHXyEqs3HGAGsTkFbCTufp/BAjJIQqCfXeL43lag1RxA - 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-Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Add PCI Express capability definitions required by the Broadcom STB PCIe -driver. - -Signed-off-by: Sylwester Nawrocki ---- - include/pci.h | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/include/pci.h b/include/pci.h -index 3d7646d..2b25a17 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -481,10 +481,17 @@ - #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ - - #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ -+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ - #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ - - #define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ -+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ -+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ -+ - #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ - - #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ - #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - -From patchwork Tue Apr 21 16:50:58 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1274450 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=V2q01bQ/; - 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-X-Mailman-Approved-At: Tue, 21 Apr 2020 19:40:20 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -This patch adds basic driver for the Broadcom STB PCIe host controller. -The code is based on Linux upstream driver (pcie-brcmtsb.c) with MSI -handling removed. The inbound access memory region is not currently -parsed from dma-ranges DT property and is fixed as a 1:1 mapping of -whole RAM. -The patch has been tested on rpi4 board, i.e. on BCM2711 SoC with VL805 -USB Host Controller. - -Signed-off-by: Sylwester Nawrocki ---- - drivers/pci/Kconfig | 5 + - drivers/pci/Makefile | 1 + - drivers/pci/pcie_brcmstb.c | 844 +++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 850 insertions(+) - create mode 100644 drivers/pci/pcie_brcmstb.c - -diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig -index 437cd9a..02dcc57 100644 ---- a/drivers/pci/Kconfig -+++ b/drivers/pci/Kconfig -@@ -197,4 +197,9 @@ config PCIE_MEDIATEK - Say Y here if you want to enable Gen2 PCIe controller, - which could be found on MT7623 SoC family. - -+config PCI_BRCMSTB -+ bool "Broadcom STB PCIe controller" -+ depends on DM_PCI -+ help -+ Say Y here if you want to enable PCI controller support on BCM2711 SoC. - endif -diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile -index c051ecc..3e53b1f 100644 ---- a/drivers/pci/Makefile -+++ b/drivers/pci/Makefile -@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o - obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o - obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o - obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o -+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -new file mode 100644 -index 0000000..e96e163 ---- /dev/null -+++ b/drivers/pci/pcie_brcmstb.c -@@ -0,0 +1,844 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Broadcom STB PCIe controller driver -+ * -+ * Copyright (C) 2020 Samsung Electronics Co., Ltd. -+ * Author: Sylwester Nawrocki -+ * -+ * Based on upstream Linux kernel driver: -+ * -+ * drivers/pci/controller/pcie-brcmstb.c -+ * Copyright (C) 2009 - 2017 Broadcom -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ -+#define BRCM_PCIE_CAP_REGS 0x00ac -+ -+/* -+ * Broadcom Settop Box PCIe Register Offsets. The names are from -+ * the chip's RDB and we use them here so that a script can correlate -+ * this code and the RDB to prevent discrepancies. -+ */ -+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 -+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c -+#define PCIE_RC_DL_MDIO_ADDR 0x1100 -+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 -+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 -+#define PCIE_MISC_MISC_CTRL 0x4008 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 -+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c -+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 -+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 -+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c -+#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 -+#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 -+#define PCIE_MISC_MSI_DATA_CONFIG 0x404c -+#define PCIE_MISC_EOI_CTRL 0x4060 -+#define PCIE_MISC_PCIE_CTRL 0x4064 -+#define PCIE_MISC_PCIE_STATUS 0x4068 -+#define PCIE_MISC_REVISION 0x406c -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 -+#define PCIE_INTR2_CPU_BASE 0x4300 -+#define PCIE_MSI_INTR2_BASE 0x4500 -+ -+/* -+ * Broadcom Settop Box PCIe Register Field shift and mask info. The -+ * names are from the chip's RDB and we use them here so that a script -+ * can correlate this code and the RDB to prevent discrepancies. -+ */ -+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc -+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2 -+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff -+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0 -+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 -+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc -+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 -+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd -+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 -+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14 -+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 -+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b -+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000 -+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16 -+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f -+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0 -+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f -+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0 -+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f -+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0 -+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f -+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0 -+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4 -+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2 -+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 -+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0 -+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 -+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7 -+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 -+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5 -+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 -+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4 -+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 -+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6 -+#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff -+#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0 -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1 -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b -+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 -+#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 -+ -+/* Offsets from PCIE_INTR2_CPU_BASE */ -+#define STATUS 0x0 -+#define SET 0x4 -+#define CLR 0x8 -+#define MASK_STATUS 0xc -+#define MASK_SET 0x10 -+#define MASK_CLR 0x14 -+ -+#define BRCM_NUM_PCIE_OUT_WINS 0x4 -+#define BRCM_MAX_SCB 0x4 -+ -+#define BURST_SIZE_128 0 -+ -+#define PCIE_BUSNUM_SHIFT 20 -+#define PCIE_SLOT_SHIFT 15 -+#define PCIE_FUNC_SHIFT 12 -+ -+#if defined(__BIG_ENDIAN) -+#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */ -+#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */ -+#else -+#define DATA_ENDIAN 0 -+#define MMIO_ENDIAN 0 -+#endif -+ -+#define MDIO_PORT0 0x0 -+#define MDIO_DATA_MASK 0x7fffffff -+#define MDIO_DATA_SHIFT 0x0 -+#define MDIO_PORT_MASK 0xf0000 -+#define MDIO_PORT_SHIFT 0x16 -+#define MDIO_REGAD_MASK 0xffff -+#define MDIO_REGAD_SHIFT 0x0 -+#define MDIO_CMD_MASK 0xfff00000 -+#define MDIO_CMD_SHIFT 0x14 -+#define MDIO_CMD_READ 0x1 -+#define MDIO_CMD_WRITE 0x0 -+#define MDIO_DATA_DONE_MASK 0x80000000 -+#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) -+#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) -+#define SSC_REGS_ADDR 0x1100 -+#define SET_ADDR_OFFSET 0x1f -+#define SSC_CNTL_OFFSET 0x2 -+#define SSC_CNTL_OVRD_EN_MASK 0x8000 -+#define SSC_CNTL_OVRD_EN_SHIFT 0xf -+#define SSC_CNTL_OVRD_VAL_MASK 0x4000 -+#define SSC_CNTL_OVRD_VAL_SHIFT 0xe -+#define SSC_STATUS_OFFSET 0x1 -+#define SSC_STATUS_SSC_MASK 0x400 -+#define SSC_STATUS_SSC_SHIFT 0xa -+#define SSC_STATUS_PLL_LOCK_MASK 0x800 -+#define SSC_STATUS_PLL_LOCK_SHIFT 0xb -+ -+#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) -+#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) -+#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) -+ -+enum { -+ RGR1_SW_INIT_1, -+ EXT_CFG_INDEX, -+ EXT_CFG_DATA, -+}; -+ -+enum { -+ RGR1_SW_INIT_1_INIT_MASK, -+ RGR1_SW_INIT_1_INIT_SHIFT, -+ RGR1_SW_INIT_1_PERST_MASK, -+ RGR1_SW_INIT_1_PERST_SHIFT, -+}; -+ -+enum pcie_type { -+ BCM7425, -+ BCM7435, -+ GENERIC, -+ BCM7278, -+ BCM2711, -+}; -+ -+struct brcm_window { -+ dma_addr_t pci_addr; -+ phys_addr_t phys_addr; -+ dma_addr_t size; -+}; -+ -+struct brcm_pcie { -+ struct resource mem; -+ bool ssc; -+ -+ struct device_node *dn; -+ void __iomem *base; -+ -+ int num_out_wins; -+ struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS]; -+ -+ int gen; -+ unsigned int rev; -+ -+ const int *reg_offsets; -+ const int *reg_field_info; -+ u32 max_burst_size; -+ enum pcie_type type; -+}; -+ -+struct pcie_cfg_data { -+ const int *reg_field_info; -+ const int *offsets; -+ const u32 max_burst_size; -+ const enum pcie_type type; -+}; -+ -+static struct brcm_window dma_ranges[1]; -+static int num_dma_ranges; -+ -+static const int pcie_reg_field_info[] = { -+ [RGR1_SW_INIT_1_INIT_MASK] = 0x2, -+ [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1, -+}; -+ -+static const int pcie_offsets[] = { -+ [RGR1_SW_INIT_1] = 0x9210, -+ [EXT_CFG_INDEX] = 0x9000, -+ [EXT_CFG_DATA] = 0x8000, -+}; -+ -+static const struct pcie_cfg_data generic_cfg = { -+ .reg_field_info = pcie_reg_field_info, -+ .offsets = pcie_offsets, -+ .max_burst_size = BURST_SIZE_128, -+ .type = GENERIC, -+}; -+ -+static const struct pcie_cfg_data bcm2711_cfg = { -+ .reg_field_info = pcie_reg_field_info, -+ .offsets = pcie_offsets, -+ .max_burst_size = BURST_SIZE_128, -+ .type = BCM2711, -+}; -+ -+/* These macros extract/insert fields to host controller's register set */ -+#define WR_FLD(base, reg, field, val) \ -+ wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val) -+#define WR_FLD_RB(base, reg, field, val) \ -+ wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val) -+#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \ -+ wr_fld(base + reg + off, reg##_##field##_MASK, \ -+ reg##_##field##_SHIFT, val) -+#define EXTRACT_FIELD(val, reg, field) \ -+ ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT) -+#define INSERT_FIELD(val, reg, field, field_val) \ -+ ((val & ~reg##_##field##_MASK) | \ -+ (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT))) -+ -+#define msleep(a) udelay((a) * 1000) -+ -+/* -+ * The roundup_pow_of_two() from log2.h invokes -+ * __roundup_pow_of_two(unsigned long), but we really need -+ * such a function to take a native u64 since unsigned long -+ * is 32 bits on some configurations. So we provide this helper -+ * function below. -+ */ -+static u64 roundup_pow_of_two_64(u64 n) -+{ -+ return 1ULL << fls64(n - 1); -+} -+ -+/* -+ * This is to convert the size of the inbound "BAR" region to the -+ * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE -+ */ -+int encode_ibar_size(u64 size) -+{ -+ int log2_in = ilog2(size); -+ -+ if (log2_in >= 12 && log2_in <= 15) -+ /* Covers 4KB to 32KB (inclusive) */ -+ return (log2_in - 12) + 0x1c; -+ else if (log2_in >= 16 && log2_in <= 37) -+ /* Covers 64KB to 32GB, (inclusive) */ -+ return log2_in - 15; -+ /* Something is awry so disable */ -+ return 0; -+} -+ -+/* Configuration space read/write support */ -+static int cfg_index(int busnr, int devfn, int reg) -+{ -+ return (PCI_DEV(devfn) << PCIE_SLOT_SHIFT) -+ | (PCI_FUNC(devfn) << PCIE_FUNC_SHIFT) -+ | (busnr << PCIE_BUSNUM_SHIFT) -+ | (reg & ~3); -+} -+ -+/* The controller is capable of serving in both RC and EP roles */ -+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) -+{ -+ void __iomem *base = pcie->base; -+ u32 val = readl(base + PCIE_MISC_PCIE_STATUS); -+ -+ return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT); -+} -+ -+static bool brcm_pcie_link_up(struct brcm_pcie *pcie) -+{ -+ void __iomem *base = pcie->base; -+ u32 val = readl(base + PCIE_MISC_PCIE_STATUS); -+ u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE); -+ u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP); -+ -+ return (dla && plu) ? true : false; -+} -+ -+static int brcm_pcie_config_address(const struct udevice *udev, pci_dev_t bdf, -+ uint offset, void **paddress) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(udev); -+ unsigned int bus = PCI_BUS(bdf); -+ unsigned int dev = PCI_DEV(bdf); -+ int idx; -+ -+ if (bus > 0 && !brcm_pcie_link_up(pcie)) -+ return -ENODEV; -+ -+ /* -+ * Busses 0 (host PCIe bridge) and 1 (its immediate child) -+ * are limited to a single device each -+ */ -+ if ((bus == (udev->seq + 1)) && dev > 0) -+ return -ENODEV; -+ -+ /* Accesses to the RC go right to the RC registers if PCI device == 0 */ -+ if (bus == udev->seq) { -+ if (PCI_DEV(bdf)) -+ return -ENODEV; -+ -+ *paddress = pcie->base + offset; -+ return 0; -+ } -+ -+ /* For devices, write to the config space index register */ -+ idx = cfg_index(bus, bdf, 0); -+ -+ writel(idx, pcie->base + IDX_ADDR(pcie)); -+ *paddress = pcie->base + DATA_ADDR(pcie) + offset; -+ -+ return 0; -+} -+ -+static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong *valuep, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, -+ bdf, offset, valuep, size); -+} -+ -+static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong value, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, -+ bdf, offset, value, size); -+} -+ -+static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val) -+{ -+ u32 reg = readl(p); -+ -+ reg = (reg & ~mask) | ((val << shift) & mask); -+ writel(reg, p); -+} -+ -+static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val) -+{ -+ wr_fld(p, mask, shift, val); -+ (void)readl(p); -+} -+ -+static const char *link_speed_to_str(int s) -+{ -+ switch (s) { -+ case 1: -+ return "2.5"; -+ case 2: -+ return "5.0"; -+ case 3: -+ return "8.0"; -+ default: -+ break; -+ } -+ return "???"; -+} -+ -+static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, -+ unsigned int val) -+{ -+ unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT]; -+ u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK]; -+ -+ wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val); -+} -+ -+static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, -+ unsigned int val) -+{ -+ if (pcie->type != BCM7278) -+ wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), -+ PCIE_RGR1_SW_INIT_1_PERST_MASK, -+ PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val); -+ else -+ /* Assert = 0, de-assert = 1 on 7278 */ -+ WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val); -+} -+ -+static u32 mdio_form_pkt(int port, int regad, int cmd) -+{ -+ u32 pkt = 0; -+ -+ pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK; -+ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK; -+ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK; -+ -+ return pkt; -+} -+ -+/* Negative return value indicates error */ -+static int mdio_read(void __iomem *base, u8 port, u8 regad) -+{ -+ int tries; -+ u32 data; -+ -+ writel(mdio_form_pkt(port, regad, MDIO_CMD_READ), -+ base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ -+ data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); -+ for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { -+ udelay(10); -+ data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); -+ } -+ -+ return MDIO_RD_DONE(data) -+ ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT -+ : -EIO; -+} -+ -+/* Negative return value indicates error */ -+static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata) -+{ -+ int tries; -+ u32 data; -+ -+ writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE), -+ base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ writel(MDIO_DATA_DONE_MASK | wrdata, -+ base + PCIE_RC_DL_MDIO_WR_DATA); -+ -+ data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); -+ for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { -+ udelay(10); -+ data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); -+ } -+ -+ return MDIO_WT_DONE(data) ? 0 : -EIO; -+} -+ -+/* -+ * Configures device for Spread Spectrum Clocking (SSC) mode; negative -+ * return value indicates error. -+ */ -+static int set_ssc(void __iomem *base) -+{ -+ int tmp; -+ u16 wrdata; -+ int pll, ssc; -+ -+ tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR); -+ if (tmp < 0) -+ return tmp; -+ -+ tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET); -+ if (tmp < 0) -+ return tmp; -+ -+ wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1); -+ wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1); -+ tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata); -+ if (tmp < 0) -+ return tmp; -+ -+ udelay(1500); -+ tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET); -+ if (tmp < 0) -+ return tmp; -+ -+ ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC); -+ pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK); -+ -+ return (ssc && pll) ? 0 : -EIO; -+} -+ -+/* Limits operation to a specific generation (1, 2, or 3) */ -+static void set_gen(void __iomem *base, int gen) -+{ -+ u32 lnkcap = readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); -+ u16 lnkctl2 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); -+ -+ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; -+ writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); -+ -+ lnkctl2 = (lnkctl2 & ~0xf) | gen; -+ writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); -+} -+ -+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, -+ unsigned int win, phys_addr_t phys_addr, -+ dma_addr_t pcie_addr, dma_addr_t size) -+{ -+ void __iomem *base = pcie->base; -+ phys_addr_t phys_addr_mb, limit_addr_mb; -+ u32 tmp; -+ -+ /* Set the base of the pcie_addr window */ -+ writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN, -+ base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8)); -+ writel(upper_32_bits(pcie_addr), -+ base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8)); -+ -+ phys_addr_mb = phys_addr >> 20; -+ limit_addr_mb = (phys_addr + size - 1) >> 20; -+ -+ /* Write the addr base low register */ -+ WR_FLD_WITH_OFFSET(base, (win * 4), -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT, -+ BASE, phys_addr_mb); -+ /* Write the addr limit low register */ -+ WR_FLD_WITH_OFFSET(base, (win * 4), -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT, -+ LIMIT, limit_addr_mb); -+ -+ if (pcie->type != BCM7435 && pcie->type != BCM7425) { -+ /* Write the cpu addr high register */ -+ tmp = (u32)(phys_addr_mb >> -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS); -+ WR_FLD_WITH_OFFSET(base, (win * 8), -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI, -+ BASE, tmp); -+ /* Write the cpu limit high register */ -+ tmp = (u32)(limit_addr_mb >> -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS); -+ WR_FLD_WITH_OFFSET(base, (win * 8), -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI, -+ LIMIT, tmp); -+ } -+} -+ -+static int brcm_pcie_setup(struct brcm_pcie *pcie) -+{ -+ phys_addr_t scb_size[BRCM_MAX_SCB] = {0}; -+ void __iomem *base = pcie->base; -+ unsigned int scb_size_val; -+ u64 rc_bar2_offset, rc_bar2_size; -+ u64 total_mem_size = 0; -+ int i, j, ret, limit, num_memc; -+ u16 nlw, cls, lnksta; -+ bool ssc_good = false; -+ u32 tmp; -+ -+ /* Reset the bridge */ -+ brcm_pcie_bridge_sw_init_set(pcie, 1); -+ -+ /* -+ * Ensure that the fundamental reset is asserted, except for 7278, -+ * which fails if we do this. -+ */ -+ if (pcie->type != BCM7278) -+ brcm_pcie_perst_set(pcie, 1); -+ -+ udelay(150); -+ -+ /* Take the bridge out of reset */ -+ brcm_pcie_bridge_sw_init_set(pcie, 0); -+ -+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0); -+ /* Wait for SerDes to be stable */ -+ udelay(150); -+ -+ /* Grab the PCIe hw revision number */ -+ tmp = readl(base + PCIE_MISC_REVISION); -+ pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN); -+ -+ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ -+ tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1); -+ tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1); -+ tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, -+ pcie->max_burst_size); -+ writel(tmp, base + PCIE_MISC_MISC_CTRL); -+ -+ /* -+ * Set up inbound memory view for the EP (called RC_BAR2, not to be -+ * confused with the BARs that are advertised by the EP). -+ * -+ * The PCIe host controller by design must set the inbound viewport -+ * to be a contiguous arrangement of all of the system's memory. -+ * In addition, its size must be a power of two. Further, the MSI -+ * target address must NOT be placed inside this region, as the -+ * decoding logic will consider its address to be inbound memory -+ * traffic. To further complicate matters, the viewport must start -+ * on a pcie-address that is aligned on a multiple of its size. -+ * If a portion of the viewport does not represent system memory -+ * -- e.g. 3GB of memory requires a 4GB viewport -- we can map -+ * the outbound memory in or after 3GB and even though the viewport -+ * will overlap the outbound memory the controller will know to send -+ * outbound memory downstream and everything else upstream. -+ */ -+ -+ if (num_dma_ranges) { -+ /* -+ * Use the base address and size(s) provided in the dma-ranges -+ * property. -+ */ -+ for (i = 0; i < num_dma_ranges; i++) -+ scb_size[i] = roundup_pow_of_two_64(dma_ranges[i].size); -+ -+ num_memc = num_dma_ranges; -+ rc_bar2_offset = dma_ranges[0].pci_addr; -+ } else { -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < num_memc; i++) -+ total_mem_size += scb_size[i]; -+ -+ rc_bar2_size = roundup_pow_of_two_64(total_mem_size); -+ -+ /* Verify the alignment is correct */ -+ if (rc_bar2_offset & (rc_bar2_size - 1)) { -+ printf("PCIe BRCM: inbound window is misaligned\n"); -+ return -EINVAL; -+ } -+ -+ tmp = lower_32_bits(rc_bar2_offset); -+ tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE, -+ encode_ibar_size(rc_bar2_size)); -+ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); -+ writel(upper_32_bits(rc_bar2_offset), -+ base + PCIE_MISC_RC_BAR2_CONFIG_HI); -+ -+ scb_size_val = scb_size[0] -+ ? ilog2(scb_size[0]) - 15 : 0xf; /* 0xf is 1GB */ -+ WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val); -+ -+ if (num_memc > 1) { -+ scb_size_val = scb_size[1] -+ ? ilog2(scb_size[1]) - 15 : 0xf; /* 0xf is 1GB */ -+ WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val); -+ } -+ -+ if (num_memc > 2) { -+ scb_size_val = scb_size[2] -+ ? ilog2(scb_size[2]) - 15 : 0xf; /* 0xf is 1GB */ -+ WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val); -+ } -+ -+ /* Disable the PCIe->GISB memory window (RC_BAR1) */ -+ WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0); -+ -+ /* Disable the PCIe->SCB memory window (RC_BAR3) */ -+ WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0); -+ -+ /* Clear any interrupts we find on boot */ -+ writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR); -+ (void)readl(base + PCIE_INTR2_CPU_BASE + CLR); -+ -+ /* Mask all interrupts since we are not handling any yet */ -+ writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET); -+ (void)readl(base + PCIE_INTR2_CPU_BASE + MASK_SET); -+ -+ if (pcie->gen) -+ set_gen(base, pcie->gen); -+ -+ /* Unassert the fundamental reset */ -+ brcm_pcie_perst_set(pcie, 0); -+ -+ /* Give the RC/EP time to wake up, before trying to configure RC. */ -+ limit = 100; -+ for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie); -+ j += i, i = i * 2) -+ msleep(i + j > limit ? limit - j : i); -+ -+ if (!brcm_pcie_link_up(pcie)) { -+ printf("PCIe BRCM: link down\n"); -+ return -ENODEV; -+ } -+ -+ if (!brcm_pcie_rc_mode(pcie)) { -+ printf("PCIe misconfigured; is in EP mode\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < pcie->num_out_wins; i++) -+ brcm_pcie_set_outbound_win(pcie, i, pcie->out_wins[i].phys_addr, -+ pcie->out_wins[i].pci_addr, -+ pcie->out_wins[i].size); -+ -+ /* -+ * For config space accesses on the RC, show the right class for -+ * a PCIe-PCIe bridge (the default setting is to be EP mode). -+ */ -+ WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400); -+ -+ if (pcie->ssc) { -+ ret = set_ssc(base); -+ if (ret == 0) -+ ssc_good = true; -+ else -+ printf("PCIe BRCM: failed attempt to enter ssc mode\n"); -+ } -+ -+ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); -+ cls = lnksta & PCI_EXP_LNKSTA_CLS; -+ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; -+ -+ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), -+ nlw, ssc_good ? "(SSC)" : "(!SSC)"); -+ -+ /* PCIe->SCB endian mode for BAR */ -+ /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */ -+ WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, -+ ENDIAN_MODE_BAR2, DATA_ENDIAN); -+ -+ /* -+ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 -+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. -+ */ -+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1); -+ -+ return 0; -+} -+ -+static const struct udevice_id brcm_pcie_ids[] = { -+ { .compatible = "brcm,bcm7445-pcie", .data = (ulong)&generic_cfg }, -+ { .compatible = "brcm,bcm2711-pcie", .data = (ulong)&bcm2711_cfg }, -+ { } -+}; -+ -+static int brcm_pcie_probe(struct udevice *dev) -+{ -+ struct udevice *ctlr = pci_get_controller(dev); -+ struct pci_controller *hose = dev_get_uclass_priv(ctlr); -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ struct pcie_cfg_data *data = (struct pcie_cfg_data *)dev_get_driver_data(dev); -+ ofnode dn = dev_ofnode(dev); -+ u32 max_link_speed; -+ int i; -+ -+ if (hose->region_count < 2) { -+ pr_err("PCIe BRCM: Missing PCI regions definition"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < hose->region_count; i++) { -+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY) -+ continue; -+ -+ pcie->out_wins[i].phys_addr = hose->regions[i].phys_start; -+ pcie->out_wins[i].pci_addr = hose->regions[i].bus_start; -+ pcie->out_wins[i].size = hose->regions[i].size; -+ pcie->num_out_wins++; -+ } -+ -+ /* TODO: Parse inbound access mapping from dma-ranges DT property */ -+ num_dma_ranges = 1; -+ for (i = 0; i < hose->region_count; i++) { -+ if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY) -+ continue; -+ -+ dma_ranges[0].pci_addr = hose->regions[i].bus_start; -+ dma_ranges[0].phys_addr = hose->regions[i].phys_start; -+ dma_ranges[0].size = hose->regions[i].size; -+ break; -+ } -+ -+ pcie->reg_offsets = data->offsets; -+ pcie->reg_field_info = data->reg_field_info; -+ pcie->max_burst_size = data->max_burst_size; -+ pcie->type = data->type; -+ -+ if (ofnode_read_u32(dn, "max-link-speed", &max_link_speed) || -+ max_link_speed > 4) -+ pcie->gen = 0; -+ else -+ pcie->gen = max_link_speed; -+ -+ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); -+ -+ return brcm_pcie_setup(pcie); -+} -+ -+static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ -+ /* Get the controller base address */ -+ pcie->base = dev_read_addr_ptr(dev); -+ if (!pcie->base) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static const struct dm_pci_ops brcm_pcie_ops = { -+ .read_config = brcm_pcie_read_config, -+ .write_config = brcm_pcie_write_config, -+}; -+ -+U_BOOT_DRIVER(pcie_brcm_base) = { -+ .name = "pcie_brcm", -+ .id = UCLASS_PCI, -+ .ops = &brcm_pcie_ops, -+ .of_match = brcm_pcie_ids, -+ .probe = brcm_pcie_probe, -+ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, -+ .priv_auto_alloc_size = sizeof(struct brcm_pcie), -+}; - -From patchwork Tue Apr 21 16:50:59 2020 -Content-Type: text/plain; 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- Tue, 21 Apr 2020 16:51:25 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: agraf@suse.de, sjg@chrmium.org, jh80.chung@samsung.com, - m.szyprowski@samsung.com, b.zolnierkie@samsung.com -Subject: [RFC PATCH 9/9] config: Enable support for the XHCI controller on - RPI4 board -Date: Tue, 21 Apr 2020 18:50:59 +0200 -Message-Id: <20200421165059.19394-10-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200421165059.19394-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA0WSbUhTcRTG+e++zppcp+AflYxhH9LUzIhbiVkG3Q998ENkRWpTb1PTKfc6 - zYQwheVbU7OcTFJLaWWEM81Xwlo1zdcvvoEbthzhLAObIFq63K7Vt995zvNwOIdDItIqzI9M - V+aynFKeKcM90G7TxmSoJqgp8fBYCUoPT20DuqO+HaMfVibRc5tqjH75wULQ39V3AN1ca8Po - 0mknoFfelBExYmZhpAhjGnXDKNOnsxDMuLkXMJquNsC0d02jTOdoYRxxxSMqlc1Mz2O58Ohr - HmnFzRt4TuX+m7XqQawIfPYvByQJqaPQ8DS2HHiQUuoZgMsPHCKhWAOwxdqJCIUDQJNmCZQD - sTvR8mlgt6EHsNioBf8iG48eYy4XTkXAex817oQPFQdnNurcjFA5sG7WhrvYm4qHFYb3bkap - A7DB8U7kYgkVBecNHbgwLRC+MLxFXCze0S3r9ahrGKQqCLhp78EE01lY12ncDXjD5aEuQuAA - 6OxrEgmBEgArB+YJoagGcGGoeXehk9A8sYm7zoFQB2F7f7ggn4Z6rRMTruQJ51a8hAU84f1u - LSLIEliqlgruIPirTSsS2A9W2JyowAy011h3r1UF4OvnZqIaBOr+D2sGoA34sio+S8HyR5Rs - fhgvz+JVSkVYSnbWK7DzJqPbQ2u9oP93shFQJJDtlcxNNiZKMXkeX5BlBJBEZD4Sg3VHkqTK - C26xXHYSp8pkeSPwJ1GZryTyiT1BSinkuewNls1hub9dESn2KwLJg1+3GcJnoqnQntS+dGor - g3FOHjdfGtBf3qOc0h3Sr0dor2/GpFrGwsdmW+P3rVGj+DHrlk2f34qDkC8hIzWmqbvG1YD+ - tBlrRoiXmps5Lynzjmsd+ZnClZ5zLJ4oi/3mQ6Y3jJ9R9Ny2R5pCfySsXo1WiS8uhnHBjYkd - F2QonyaPCEY4Xv4HlRBgdCIDAAA= -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRmVeSWpSXmKPExsVy+t/xu7q9KvPjDBrnaFmcuPKP0WLjjPWs - FlN74i1u/GpjtVh75C67xZu2RkaLBZOfsFp0XP3PaPF2bye7A6fH/VMNrB7zZp1g8dg56y67 - x9k7Oxg9+rasYvRYv+Uqi8fm09UB7FF6NkX5pSWpChn5xSW2StGGFkZ6hpYWekYmlnqGxuax - VkamSvp2NimpOZllqUX6dgl6GU0LfrIV9ChUTG7bz9rA+EC6i5GTQ0LARGLxyd3MXYxcHEIC - SxklPvy/yt7FyAGUkJKY36IEUSMs8edaFxtEzSdGibXPXzGDJNgEDCV6j/YxgtgiAiESL45e - YQKxmQXKJNa0vgaLCwuEStyd0gNmswioSsz+fBCshlfARuL2ho1sEAvkJVZvOAA2kxMofvf7 - DBYQW0jAWqLh0hKWCYx8CxgZVjGKpJYW56bnFhvpFSfmFpfmpesl5+duYgQG9rZjP7fsYOx6 - F3yIUYCDUYmH98b5eXFCrIllxZW5hxglOJiVRHg3PAQK8aYkVlalFuXHF5XmpBYfYjQFOmoi - s5Rocj4w6vJK4g1NDc0tLA3Njc2NzSyUxHk7BA7GCAmkJ5akZqemFqQWwfQxcXBKNTBWTnjA - 9rfi5OHFK1WDPefc1Lu4NHa3k0wcX1F135VL2qWb2AoizLZIZYrNyrjw0f+d94ZWruRVorea - j/wSO5bju/fInhW3XUo8DDUe22meFxPewrSBefPkV4tqufjmZfw2215cNE+8PDvoi1vXG/vu - HJazefOrPDX48nXr2GPVpXas8L377pESS3FGoqEWc1FxIgDja1QoggIAAA== -X-CMS-MailID: 20200421165125eucas1p12d7451082887a52073ba795aa0ee398a -X-Msg-Generator: CA -X-RootMTR: 20200421165125eucas1p12d7451082887a52073ba795aa0ee398a -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200421165125eucas1p12d7451082887a52073ba795aa0ee398a -References: <20200421165059.19394-1-s.nawrocki@samsung.com> - -X-Mailman-Approved-At: Tue, 21 Apr 2020 19:40:20 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Marek Szyprowski - -This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI -and USB commands. To get it working one has to call the following commands: -"pci enum; usb start;", thus such commands have been added to the default -"preboot" environment variable. One has to update his environment if it is -already configured to get this feature working out of the box. - -Signed-off-by: Marek Szyprowski ---- - configs/rpi_4_32b_defconfig | 9 +++++++++ - configs/rpi_4_defconfig | 10 ++++++++++ - configs/rpi_arm64_defconfig | 9 ++++++++- - 3 files changed, 27 insertions(+), 1 deletion(-) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index 72cda5d..0dd763f 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_DFU=y - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y - CONFIG_ENV_FAT_INTERFACE="mmc" -@@ -28,12 +32,17 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_DM_USB_GADGET=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_GADGET=y - CONFIG_USB_GADGET_MANUFACTURER="FSL" - CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index 6d148da..f80e5da 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_DFU=y - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y - CONFIG_ENV_FAT_INTERFACE="mmc" -@@ -28,12 +32,18 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_DM_USB_GADGET=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_GADGET=y - CONFIG_USB_GADGET_MANUFACTURER="FSL" - CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index fea86be..926dfc3 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_USE_PREBOOT=y --CONFIG_PREBOOT="usb start" -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y -@@ -26,11 +27,17 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_DWC2=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y -From 41e5d853779e91ea193ea0251bae9328083e2374 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 21 Apr 2020 20:18:31 +0100 -Subject: [PATCH] rpi4: add usb keyboard/storage - -Signed-off-by: Peter Robinson ---- - configs/rpi_4_32b_defconfig | 2 ++ - configs/rpi_4_defconfig | 2 ++ - 2 files changed, 4 insertions(+) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index 0dd763f06f..2e137414f7 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -49,6 +49,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 - CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 - CONFIG_USB_GADGET_DWC2_OTG=y - CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_STORAGE=y - CONFIG_DM_VIDEO=y - # CONFIG_VIDEO_BPP8 is not set - # CONFIG_VIDEO_BPP16 is not set -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index f80e5dac3e..bdefbd2a45 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -50,6 +50,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 - CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 - CONFIG_USB_GADGET_DWC2_OTG=y - CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_STORAGE=y - CONFIG_DM_VIDEO=y - # CONFIG_VIDEO_BPP8 is not set - # CONFIG_VIDEO_BPP16 is not set --- -2.26.1 - diff --git a/aarch64-boards b/aarch64-boards index 4782501..cc0d265 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -61,6 +61,7 @@ rockpro64-rk3399 roc-pc-rk3399 rpi_3 rpi_4 +rpi_arm64 sopine_baseboard teres_i turris_mox diff --git a/arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch b/arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch deleted file mode 100644 index 0dea1a8..0000000 --- a/arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch +++ /dev/null @@ -1,863 +0,0 @@ -From patchwork Tue Mar 31 09:39:57 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Lin Jinhan -X-Patchwork-Id: 1264692 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - 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2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Add rng node in rk3399-u-boot.dtsi and enable it in -rk3399-evb-u-boot.dtsi. - -Signed-off-by: Lin Jinhan ---- - arch/arm/dts/rk3399-evb-u-boot.dtsi | 5 +++++ - arch/arm/dts/rk3399-u-boot.dtsi | 6 ++++++ - 2 files changed, 11 insertions(+) - -diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi -index ccb33d34d1..5b50c5ba30 100644 ---- a/arch/arm/dts/rk3399-evb-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi -@@ -11,3 +11,8 @@ - u-boot,spl-boot-order = &sdhci, &sdmmc; - }; - }; -+ -+&rng { -+ status = "okay"; -+}; -+ -diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi -index 8b857ccfc7..757b8c10a2 100644 ---- a/arch/arm/dts/rk3399-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-u-boot.dtsi -@@ -25,6 +25,12 @@ - clock-names = "pclk_ddr_mon"; - }; - -+ rng: rng@ff8b8000 { -+ compatible = "rockchip,cryptov1-rng"; -+ reg = <0x0 0xff8b8000 0x0 0x1000>; -+ status = "disabled"; -+ }; -+ - dmc: dmc { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3399-dmc"; - -From patchwork Tue Mar 31 09:39:58 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Lin Jinhan -X-Patchwork-Id: 1264694 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) - header.from=rock-chips.com -Received: from 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-X-UNIQUE-TAG: <5d721e76916e55da5c0d6122d449dd8b> -X-RL-SENDER: troy.lin@rock-chips.com -X-SENDER: troy.lin@rock-chips.com -X-LOGIN-NAME: troy.lin@rock-chips.com -X-FST-TO: u-boot@lists.denx.de -X-SENDER-IP: 58.22.7.114 -X-ATTACHMENT-NUM: 0 -X-DNS-TYPE: 0 -X-System-Flag: 0 -From: Lin Jinhan -To: u-boot@lists.denx.de, - sughosh.ganu@linaro.org, - xypron.glpk@gmx.de -Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com, - Lin Jinhan -Subject: [PATCH 2/5] arm: dts: rockchip: px30: add and enable rng node -Date: Tue, 31 Mar 2020 17:39:58 +0800 -Message-Id: <20200331094001.13441-2-troy.lin@rock-chips.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200331094001.13441-1-troy.lin@rock-chips.com> -References: <20200331094001.13441-1-troy.lin@rock-chips.com> -X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Add enable rng node in px30-evb-u-boot.dtsi. - -Signed-off-by: Lin Jinhan ---- - arch/arm/dts/px30-evb-u-boot.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi -index a2a2c07dcc..a73c215c05 100644 ---- a/arch/arm/dts/px30-evb-u-boot.dtsi -+++ b/arch/arm/dts/px30-evb-u-boot.dtsi -@@ -12,6 +12,13 @@ - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -+ -+ rng: rng@ff0b0000 { -+ compatible = "rockchip,cryptov2-rng"; -+ reg = <0x0 0xff0b0000 0x0 0x4000>; -+ status = "okay"; -+ }; -+ - }; - - &dmc { - -From patchwork Tue Mar 31 09:39:59 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Lin Jinhan -X-Patchwork-Id: 1264693 -Return-Path: -X-Original-To: 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B1262A3EF8; - Tue, 31 Mar 2020 17:40:04 +0800 (CST) -X-MAIL-GRAY: 0 -X-MAIL-DELIVERY: 1 -X-ADDR-CHECKED: 0 -X-ANTISPAM-LEVEL: 2 -X-ABS-CHECKED: 0 -Received: from localhost.localdomain (unknown [58.22.7.114]) - by smtp.263.net (postfix) whith ESMTP id - P29487T139780956792576S1585647603180703_; - Tue, 31 Mar 2020 17:40:04 +0800 (CST) -X-IP-DOMAINF: 1 -X-UNIQUE-TAG: <78d4a197cac8da659f7b02fbce5e0ad8> -X-RL-SENDER: troy.lin@rock-chips.com -X-SENDER: troy.lin@rock-chips.com -X-LOGIN-NAME: troy.lin@rock-chips.com -X-FST-TO: u-boot@lists.denx.de -X-SENDER-IP: 58.22.7.114 -X-ATTACHMENT-NUM: 0 -X-DNS-TYPE: 0 -X-System-Flag: 0 -From: Lin Jinhan -To: u-boot@lists.denx.de, - sughosh.ganu@linaro.org, - xypron.glpk@gmx.de -Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com, - Lin Jinhan -Subject: [PATCH 3/5] rockchip: rng: Add a driver for random number - generator(rng) device -Date: Tue, 31 Mar 2020 17:39:59 +0800 -Message-Id: <20200331094001.13441-3-troy.lin@rock-chips.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200331094001.13441-1-troy.lin@rock-chips.com> -References: <20200331094001.13441-1-troy.lin@rock-chips.com> -X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Add a driver for the rng device found on rockchip platforms. -Support rng module of crypto v1 and crypto v2. - -Signed-off-by: Lin Jinhan ---- - drivers/rng/Kconfig | 8 ++ - drivers/rng/Makefile | 1 + - drivers/rng/rockchip_rng.c | 224 +++++++++++++++++++++++++++++++++++++ - 3 files changed, 233 insertions(+) - create mode 100644 drivers/rng/rockchip_rng.c - -diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig -index edb6152bb9..e4b22d79eb 100644 ---- a/drivers/rng/Kconfig -+++ b/drivers/rng/Kconfig -@@ -31,4 +31,12 @@ config RNG_STM32MP1 - help - Enable STM32MP1 rng driver. - -+config RNG_ROCKCHIP -+ bool "Enable random number generator for rockchip crypto rng" -+ depends on ARCH_ROCKCHIP && DM_RNG -+ default n -+ help -+ Enable random number generator for rockchip.This driver is -+ support rng module of crypto v1 and crypto v2. -+ - endif -diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile -index 6a8a66779b..44a0003917 100644 ---- a/drivers/rng/Makefile -+++ b/drivers/rng/Makefile -@@ -7,3 +7,4 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o - obj-$(CONFIG_RNG_MESON) += meson-rng.o - obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o - obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o -+obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o -diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c -new file mode 100644 -index 0000000000..47fb140077 ---- /dev/null -+++ b/drivers/rng/rockchip_rng.c -@@ -0,0 +1,224 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define RK_HW_RNG_MAX 32 -+ -+#define _SBF(s, v) ((v) << (s)) -+ -+/* start of CRYPTO V1 register define */ -+#define CRYPTO_V1_CTRL 0x0008 -+#define CRYPTO_V1_RNG_START BIT(8) -+#define CRYPTO_V1_RNG_FLUSH BIT(9) -+ -+#define CRYPTO_V1_TRNG_CTRL 0x0200 -+#define CRYPTO_V1_OSC_ENABLE BIT(16) -+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) -+ -+#define CRYPTO_V1_TRNG_DOUT_0 0x0204 -+/* end of CRYPTO V1 register define */ -+ -+/* start of CRYPTO V2 register define */ -+#define CRYPTO_V2_RNG_CTL 0x0400 -+#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) -+#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) -+#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) -+#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) -+#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) -+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) -+#define CRYPTO_V2_RNG_ENABLE BIT(1) -+#define CRYPTO_V2_RNG_START BIT(0) -+#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 -+#define CRYPTO_V2_RNG_DOUT_0 0x0410 -+/* end of CRYPTO V2 register define */ -+ -+#define RK_RNG_TIME_OUT 50000 /* max 50ms */ -+ -+struct rk_rng_soc_data { -+ int (*rk_rng_read)(struct udevice *dev, void *data, size_t len); -+}; -+ -+struct rk_rng_platdata { -+ fdt_addr_t base; -+ struct rk_rng_soc_data *soc_data; -+}; -+ -+static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size) -+{ -+ u32 count = RK_HW_RNG_MAX / sizeof(u32); -+ u32 reg, tmp_len; -+ -+ if (size > RK_HW_RNG_MAX) -+ return -EINVAL; -+ -+ while (size && count) { -+ reg = readl(addr); -+ tmp_len = min(size, sizeof(u32)); -+ memcpy(buf, ®, tmp_len); -+ addr += sizeof(u32); -+ buf += tmp_len; -+ size -= tmp_len; -+ count--; -+ } -+ -+ return 0; -+} -+ -+static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len) -+{ -+ struct rk_rng_platdata *pdata = dev_get_priv(dev); -+ u32 reg = 0; -+ int retval; -+ -+ if (len > RK_HW_RNG_MAX) -+ return -EINVAL; -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100), -+ pdata->base + CRYPTO_V1_TRNG_CTRL); -+ -+ rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START, -+ CRYPTO_V1_RNG_START); -+ -+ retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg, -+ !(reg & CRYPTO_V1_RNG_START), -+ RK_RNG_TIME_OUT); -+ if (retval) -+ goto exit; -+ -+ rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len); -+ -+exit: -+ /* close TRNG */ -+ rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START); -+ -+ return 0; -+} -+ -+static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len) -+{ -+ struct rk_rng_platdata *pdata = dev_get_priv(dev); -+ u32 reg = 0; -+ int retval; -+ -+ if (len > RK_HW_RNG_MAX) -+ return -EINVAL; -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT); -+ -+ reg |= CRYPTO_V2_RNG_256_BIT_LEN; -+ reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; -+ reg |= CRYPTO_V2_RNG_ENABLE; -+ reg |= CRYPTO_V2_RNG_START; -+ -+ rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg); -+ -+ retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg, -+ !(reg & CRYPTO_V2_RNG_START), -+ RK_RNG_TIME_OUT); -+ if (retval) -+ goto exit; -+ -+ rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len); -+ -+exit: -+ /* close TRNG */ -+ rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff); -+ -+ return retval; -+} -+ -+static int rockchip_rng_read(struct udevice *dev, void *data, size_t len) -+{ -+ unsigned char *buf = data; -+ unsigned int i; -+ int ret = -EIO; -+ -+ struct rk_rng_platdata *pdata = dev_get_priv(dev); -+ -+ if (!len) -+ return 0; -+ -+ if (!pdata->soc_data || !pdata->soc_data->rk_rng_read) -+ return -EINVAL; -+ -+ for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) { -+ ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX); -+ if (ret) -+ goto exit; -+ } -+ -+ if (len % RK_HW_RNG_MAX) -+ ret = pdata->soc_data->rk_rng_read(dev, buf, -+ len % RK_HW_RNG_MAX); -+ -+exit: -+ return ret; -+} -+ -+static int rockchip_rng_ofdata_to_platdata(struct udevice *dev) -+{ -+ struct rk_rng_platdata *pdata = dev_get_priv(dev); -+ -+ memset(pdata, 0x00, sizeof(*pdata)); -+ -+ pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev); -+ if (!pdata->base) -+ return -ENOMEM; -+ -+ return 0; -+} -+ -+static int rockchip_rng_probe(struct udevice *dev) -+{ -+ struct rk_rng_platdata *pdata = dev_get_priv(dev); -+ -+ pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev); -+ -+ return 0; -+} -+ -+static const struct rk_rng_soc_data rk_rng_v1_soc_data = { -+ .rk_rng_read = rk_v1_rng_read, -+}; -+ -+static const struct rk_rng_soc_data rk_rng_v2_soc_data = { -+ .rk_rng_read = rk_v2_rng_read, -+}; -+ -+static const struct dm_rng_ops rockchip_rng_ops = { -+ .read = rockchip_rng_read, -+}; -+ -+static const struct udevice_id rockchip_rng_match[] = { -+ { -+ .compatible = "rockchip,cryptov1-rng", -+ .data = (ulong)&rk_rng_v1_soc_data, -+ }, -+ { -+ .compatible = "rockchip,cryptov2-rng", -+ .data = (ulong)&rk_rng_v2_soc_data, -+ }, -+ {}, -+}; -+ -+U_BOOT_DRIVER(rockchip_rng) = { -+ .name = "rockchip-rng", -+ .id = UCLASS_RNG, -+ .of_match = rockchip_rng_match, -+ .ops = &rockchip_rng_ops, -+ .probe = rockchip_rng_probe, -+ .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata, -+ .priv_auto_alloc_size = sizeof(struct rk_rng_platdata), -+}; - -From patchwork Tue Mar 31 09:40:00 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Lin Jinhan -X-Patchwork-Id: 1264696 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org 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<20200331094001.13441-1-troy.lin@rock-chips.com> -X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled. - -Signed-off-by: Lin Jinhan ---- - configs/evb-rk3399_defconfig | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig -index 3f74be3b3c..7f14e18b1b 100644 ---- a/configs/evb-rk3399_defconfig -+++ b/configs/evb-rk3399_defconfig -@@ -39,6 +39,8 @@ CONFIG_PMIC_RK8XX=y - CONFIG_REGULATOR_PWM=y - CONFIG_REGULATOR_RK8XX=y - CONFIG_PWM_ROCKCHIP=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_BAUDRATE=1500000 - CONFIG_DEBUG_UART_SHIFT=2 - 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kever.yang@rock-chips.com, zhangzj@rock-chips.com, - Lin Jinhan -Subject: [PATCH 5/5] rockchip: px30: Enable CONFIG_RNG_ROCKCHIP -Date: Tue, 31 Mar 2020 17:40:01 +0800 -Message-Id: <20200331094001.13441-5-troy.lin@rock-chips.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200331094001.13441-1-troy.lin@rock-chips.com> -References: <20200331094001.13441-1-troy.lin@rock-chips.com> -X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled. - -Signed-off-by: Lin Jinhan ---- - configs/evb-px30_defconfig | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig -index b5ba75cc6e..d2cf13e54a 100644 ---- a/configs/evb-px30_defconfig -+++ b/configs/evb-px30_defconfig -@@ -85,6 +85,8 @@ CONFIG_SPL_RAM=y - CONFIG_TPL_RAM=y - CONFIG_ROCKCHIP_SDRAM_COMMON=y - CONFIG_DM_RESET=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - # CONFIG_SPECIFY_CONSOLE_INDEX is not set - CONFIG_DEBUG_UART_SHIFT=2 - CONFIG_DEBUG_UART_SKIP_INIT=y diff --git a/arm-tegra-define-fdtfile-option-for-distro-boot.patch b/arm-tegra-define-fdtfile-option-for-distro-boot.patch index 4f065ff..923ccb1 100644 --- a/arm-tegra-define-fdtfile-option-for-distro-boot.patch +++ b/arm-tegra-define-fdtfile-option-for-distro-boot.patch @@ -1,6 +1,6 @@ -From ce2493a9dec8af2dd57839e337b002d256d2a842 Mon Sep 17 00:00:00 2001 +From c3332b102d2ddae01710ae8f4393a2a18a3a1bb3 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 31 Mar 2020 10:38:41 +0100 +Date: Tue, 12 May 2020 08:19:48 +0100 Subject: [PATCH] arm: tegra: define fdtfile option for distro boot For booting via UEFI we need to define the fdtfile option so @@ -20,12 +20,12 @@ Signed-off-by: Peter Robinson 7 files changed, 12 insertions(+) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h -index f2cdd9c019..997b50394b 100644 +index 175c55c613..8026f4b32e 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h -@@ -55,6 +55,12 @@ - #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) - #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +@@ -52,6 +52,12 @@ + /* Boot Argument Buffer Size */ + #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#ifdef CONFIG_ARM64 +#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" @@ -109,5 +109,5 @@ index 54bc6756ab..6c5dc24b26 100644 "ramdisk_addr_r=0x83100000\0" -- -2.26.0 +2.26.2 diff --git a/initial-support-for-the-Pinebook-Pro-laptop-from.patch b/initial-support-for-the-Pinebook-Pro-laptop-from.patch index defa2f6..b8b6f34 100644 --- a/initial-support-for-the-Pinebook-Pro-laptop-from.patch +++ b/initial-support-for-the-Pinebook-Pro-laptop-from.patch @@ -49,11 +49,11 @@ Signed-off-by: Peter Robinson create mode 100644 arch/arm/dts/rk3399-pinebook-pro.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 820ee9733a..885bf0ef58 100644 +index 1325134bd4..c4d8ffb13c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-nanopi-m4.dtb \ +@@ -129,6 +129,7 @@ + rk3399-nanopi-m4-2gb.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ diff --git a/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch b/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch index 0efd838..0e30129 100644 --- a/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch +++ b/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch @@ -1,6 +1,6 @@ -From 7bf054b1b2e1e4105e94642e18fc74a63eccce97 Mon Sep 17 00:00:00 2001 +From 7389a936fbd5ccaae7c39d38d1440e0359f9d0e5 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 4 Dec 2018 15:26:59 +0000 +Date: Tue, 12 May 2020 08:14:26 +0100 Subject: [PATCH] rpi: Use firmware provided device tree Signed-off-by: Peter Robinson @@ -13,70 +13,70 @@ Signed-off-by: Peter Robinson 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig -index 66b0de31b60..9446465fdf7 100644 +index 5053a38822..3c6af2b367 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig -@@ -14,7 +14,7 @@ CONFIG_CMD_GPIO=y +@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig -index ba75e52dda0..d324e2bdd33 100644 +index 0000a759f1..f27c5ab1f6 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig -@@ -14,7 +14,7 @@ CONFIG_CMD_GPIO=y +@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig -index bbcdd91e909..46816cd1da7 100644 +index a714f9ec49..90ce6ea22e 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig -@@ -15,7 +15,7 @@ CONFIG_CMD_GPIO=y +@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig -index 54b6303c2d8..f05ddf8f61f 100644 +index 244d9b3a78..f72d6d35e2 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig -@@ -15,7 +15,7 @@ CONFIG_CMD_GPIO=y +@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig -index e7820cb147b..d248873174d 100644 +index 64bb184c2b..645dbbec33 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig -@@ -14,7 +14,7 @@ CONFIG_CMD_GPIO=y +@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- -2.19.2 +2.26.2 diff --git a/rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch b/rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch new file mode 100644 index 0000000..3b9726c --- /dev/null +++ b/rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch @@ -0,0 +1,62 @@ +From 50e353960a36f381f855b34b40117c64dc44ad33 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 12 May 2020 23:23:01 +0100 +Subject: [PATCH] config: Enable support for the XHCI controller on RPI4 board + +From: Marek Szyprowski + +This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI +and USB commands. To get it working one has to call the following commands: +"pci enum; usb start;", thus such commands have been added to the default +"preboot" environment variable. One has to update their environment if it +is already configured to get this feature working out of the box. + +Signed-off-by: Marek Szyprowski +Signed-off-by: Sylwester Nawrocki +--- + configs/rpi_4_defconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig +index f1c8f5ef7d..b3e7037bf5 100644 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_ARCH_FIXUP_FDT_MEMORY=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +@@ -27,12 +31,17 @@ CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_DM_USB_GADGET=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="FSL" + CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +-- +2.26.2 + diff --git a/rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch b/rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch new file mode 100644 index 0000000..a9c00c3 --- /dev/null +++ b/rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch @@ -0,0 +1,40 @@ +From c9a14b02aea84a37407df7d295e0f76eb529f472 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 12 May 2020 11:29:00 +0100 +Subject: [PATCH] rpi4: enable ARCH_FIXUP_FDT_MEMORY + +Signed-off-by: Peter Robinson +--- + configs/rpi_4_32b_defconfig | 2 +- + configs/rpi_4_defconfig | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig +index dd7da1cf06..9a0437d376 100644 +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -7,7 +7,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y +-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_ARCH_FIXUP_FDT_MEMORY=y + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig +index 6eeec4592e..b3e7037bf5 100644 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -7,7 +7,7 @@ + CONFIG_NR_DRAM_BANKS=2 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y +-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_ARCH_FIXUP_FDT_MEMORY=y + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +-- +2.26.2 + diff --git a/sources b/sources index 875b362..926a830 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2020.07-rc1.tar.bz2) = 345b451652ca8bf539f6629ce618113d66ff6690a1f9ccf5a5a4638e6f30c0302fe4af365b5751fa229b09dd354de1db1480c869f511384855d32f692a95acf7 +SHA512 (u-boot-2020.07-rc2.tar.bz2) = d4ee96a76cde9305a8733602ce8f9505412f9118e5625f3154249d302445e1c9f970bcf38abb63536129885f3443d1c9fdf9c4e8851e2c1655050d1ebcea7bd2 diff --git a/uboot-tools.spec b/uboot-tools.spec index 044a7c4..2c6e05f 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc1 +%global candidate rc2 Name: uboot-tools Version: 2020.07 -Release: 0.1%{?candidate:.%{candidate}}%{?dist} +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -22,21 +22,23 @@ Patch2: uefi-use-Fedora-specific-path-name.patch # Board fixes and enablement Patch4: usb-kbd-fixes.patch -Patch5: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch -Patch6: dragonboard-fixes.patch +Patch5: dragonboard-fixes.patch # Tegra improvements Patch10: arm-tegra-define-fdtfile-option-for-distro-boot.patch Patch11: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch # Rockchips improvements -Patch12: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch -Patch13: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch -Patch14: initial-support-for-the-Pinebook-Pro-laptop-from.patch -Patch15: rockpro64-limit-speed-on-mSD-slot.patch +Patch12: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch +Patch13: initial-support-for-the-Pinebook-Pro-laptop-from.patch +Patch14: rockpro64-limit-speed-on-mSD-slot.patch # AllWinner improvements -Patch16: AllWinner-Pine64-bits.patch +Patch15: AllWinner-Pine64-bits.patch # RPi4 -Patch17: USB-host-support-for-Raspberry-Pi-4-board.patch +Patch16: USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch +Patch17: usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch +Patch18: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch +Patch19: rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch +Patch20: rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch BuildRequires: bc BuildRequires: dtc @@ -250,6 +252,10 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Tue May 12 2020 Peter Robinson - 2020.07-0.2.rc2 +- 2020.07 RC2 +- Minor device updates + * Wed Apr 29 2020 Peter Robinson - 2020.07-0.1.rc1 - 2020.07 RC1 diff --git a/usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch b/usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch new file mode 100644 index 0000000..4b5f19c --- /dev/null +++ b/usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch @@ -0,0 +1,361 @@ +From patchwork Tue May 5 16:26:06 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Nicolas Saenz Julienne +X-Patchwork-Id: 1283753 +X-Patchwork-Delegate: marek.vasut@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Authentication-Results: ozlabs.org; + dmarc=none (p=none dis=none) header.from=suse.de +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 49GlV44bJCz9sT0 + for ; Wed, 6 May 2020 02:26:36 +1000 (AEST) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id C14658209E; + Tue, 5 May 2020 18:26:25 +0200 (CEST) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=suse.de +Authentication-Results: phobos.denx.de; + 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16:26:19 +0000 (UTC) +From: Nicolas Saenz Julienne +To: mbrugger@suse.com, u-boot@lists.denx.de, bmeng.cn@gmail.com, marex@denx.de, + linux-kernel@vger.kernel.org +Cc: sjg@chromium.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, + mark.kettenis@xs4all.nl, Nicolas Saenz Julienne +Subject: [PATCH v3 1/2] arm: rpi: Add function to trigger VL805's firmware load +Date: Tue, 5 May 2020 18:26:06 +0200 +Message-Id: <20200505162607.334-2-nsaenzjulienne@suse.de> +X-Mailer: git-send-email 2.26.2 +In-Reply-To: <20200505162607.334-1-nsaenzjulienne@suse.de> +References: <20200505162607.334-1-nsaenzjulienne@suse.de> +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware +may either be loaded directly from an EEPROM or, if not present, by the +SoC's VideCore (the SoC's co-processor). Introduce the function that +informs VideCore that VL805 may need its firmware loaded. + +Signed-off-by: Nicolas Saenz Julienne +--- +Changes since v2: + - Correct wrong function name in comment + - Add better comment on rpi_firmware_init_vl805() + +Changes since v1: + - Rename function so it's not mistaken with regular firmware loading + + arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++ + arch/arm/mach-bcm283x/include/mach/msg.h | 7 ++++ + arch/arm/mach-bcm283x/msg.c | 45 +++++++++++++++++++++++ + 3 files changed, 65 insertions(+) + +diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h +index 60e226ce1d..2ae2d3d97c 100644 +--- a/arch/arm/mach-bcm283x/include/mach/mbox.h ++++ b/arch/arm/mach-bcm283x/include/mach/mbox.h +@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette { + } body; + }; + ++#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 ++ ++struct bcm2835_mbox_tag_pci_dev_addr { ++ struct bcm2835_mbox_tag_hdr tag_hdr; ++ union { ++ struct { ++ u32 dev_addr; ++ } req; ++ struct { ++ } resp; ++ } body; ++}; ++ + /* + * Pass a raw u32 message to the VC, and receive a raw u32 back. + * +diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h +index 4afb08631b..f5213dd0e0 100644 +--- a/arch/arm/mach-bcm283x/include/mach/msg.h ++++ b/arch/arm/mach-bcm283x/include/mach/msg.h +@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, + int pixel_order, int alpha_mode, ulong *fb_basep, + ulong *fb_sizep, int *pitchp); + ++/** ++ * bcm2711_notify_vl805_reset() - get vl805's firmware loaded ++ * ++ * @return 0 if OK, -EIO on error ++ */ ++int bcm2711_notify_vl805_reset(void); ++ + #endif +diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c +index 94b75283f8..f8ef531652 100644 +--- a/arch/arm/mach-bcm283x/msg.c ++++ b/arch/arm/mach-bcm283x/msg.c +@@ -40,6 +40,12 @@ struct msg_setup { + u32 end_tag; + }; + ++struct msg_notify_vl805_reset { ++ struct bcm2835_mbox_hdr hdr; ++ struct bcm2835_mbox_tag_pci_dev_addr dev_addr; ++ u32 end_tag; ++}; ++ + int bcm2835_power_on_module(u32 module) + { + ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1); +@@ -151,3 +157,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, + + return 0; + } ++ ++/* ++ * The Raspberry Pi 4 gets its USB functionality from VL805, a PCIe chip that ++ * implements xHCI. After a PCI reset, VL805's firmware may either be loaded ++ * directly from an EEPROM or, if not present, by the SoC's co-processor, ++ * VideoCore. RPi4's VideoCore OS contains both the non public firmware load ++ * logic and the VL805 firmware blob. This function triggers the aforementioned ++ * process. ++ */ ++int bcm2711_notify_vl805_reset(void) ++{ ++ ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset, ++ msg_notify_vl805_reset, 1); ++ int ret; ++ ++ BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset); ++ BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr, ++ NOTIFY_XHCI_RESET); ++ ++ /* ++ * The pci device address is expected like this: ++ * ++ * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12 ++ * ++ * But since RPi4's PCIe setup is hardwired, we know the address in ++ * advance. ++ */ ++ msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000; ++ ++ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, ++ &msg_notify_vl805_reset->hdr); ++ if (ret) { ++ printf("bcm2711: Faild to load vl805's firmware, %d\n", ret); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ + +From patchwork Tue May 5 16:26:07 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Nicolas Saenz Julienne +X-Patchwork-Id: 1283757 +X-Patchwork-Delegate: marek.vasut@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Authentication-Results: ozlabs.org; + dmarc=none (p=none dis=none) header.from=suse.de +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 49GlVQ0MyZz9sT0 + for ; Wed, 6 May 2020 02:26:52 +1000 (AEST) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 40A20820AB; + Tue, 5 May 2020 18:26:27 +0200 (CEST) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=suse.de +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id A816381C4C; Tue, 5 May 2020 18:26:22 +0200 (CEST) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, + RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham + autolearn_force=no version=3.4.2 +Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) + (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) + (No client certificate requested) + by phobos.denx.de (Postfix) with ESMTPS id E5F898196A + for ; Tue, 5 May 2020 18:26:19 +0200 (CEST) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=suse.de +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=nsaenzjulienne@suse.de +Received: from relay2.suse.de (unknown [195.135.220.254]) + by mx2.suse.de (Postfix) with ESMTP id EB82AAF5D; + Tue, 5 May 2020 16:26:21 +0000 (UTC) +From: Nicolas Saenz Julienne +To: mbrugger@suse.com, u-boot@lists.denx.de, bmeng.cn@gmail.com, marex@denx.de, + linux-kernel@vger.kernel.org +Cc: sjg@chromium.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, + mark.kettenis@xs4all.nl, Nicolas Saenz Julienne +Subject: [PATCH v3 2/2] usb: xhci: Load Raspberry Pi 4 VL805's firmware +Date: Tue, 5 May 2020 18:26:07 +0200 +Message-Id: <20200505162607.334-3-nsaenzjulienne@suse.de> +X-Mailer: git-send-email 2.26.2 +In-Reply-To: <20200505162607.334-1-nsaenzjulienne@suse.de> +References: <20200505162607.334-1-nsaenzjulienne@suse.de> +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +When needed, RPi4's co-processor (called VideoCore) has to be instructed +to load VL805's firmware (the chip providing xHCI support). VideCore's +firmware expects the board's PCIe bus to be already configured in order +for it to load the xHCI chip firmware. So we have to make sure this +happens in between the PCIe configuration and xHCI startup. + +Introduce a callback in xhci_pci_probe() to run this platform specific +routine. + +Signed-off-by: Nicolas Saenz Julienne +--- + +Changes since v2: + - Get rid of #ifdef CONFIG_BCM2711 + - Get rid of redundant error message + +Changes since v1: + - Create callback + + board/raspberrypi/rpi/rpi.c | 6 ++++++ + drivers/usb/host/xhci-pci.c | 6 ++++++ + include/usb/xhci.h | 3 +++ + 3 files changed, 15 insertions(+) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index e367ba3092..dcaf45fbf2 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -494,3 +495,8 @@ int ft_board_setup(void *blob, bd_t *bd) + + return 0; + } ++ ++void xhci_pci_fixup(struct udevice *dev) ++{ ++ bcm2711_notify_vl805_reset(); ++} +diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c +index c1f60da541..1285dde1ef 100644 +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -11,6 +11,10 @@ + #include + #include + ++__weak void xhci_pci_fixup(struct udevice *dev) ++{ ++} ++ + static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor) + { +@@ -40,6 +44,8 @@ static int xhci_pci_probe(struct udevice *dev) + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + ++ xhci_pci_fixup(dev); ++ + xhci_pci_init(dev, &hccr, &hcor); + + return xhci_register(dev, hccr, hcor); +diff --git a/include/usb/xhci.h b/include/usb/xhci.h +index c16106a2fc..57feed7603 100644 +--- a/include/usb/xhci.h ++++ b/include/usb/xhci.h +@@ -16,6 +16,7 @@ + #ifndef HOST_XHCI_H_ + #define HOST_XHCI_H_ + ++#include + #include + #include + #include +@@ -1281,4 +1282,6 @@ extern struct dm_usb_ops xhci_usb_ops; + + struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); + ++extern void xhci_pci_fixup(struct udevice *dev); ++ + #endif /* HOST_XHCI_H_ */