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2020.07 RC2

This commit is contained in:
Peter Robinson 2020-05-12 23:33:51 +01:00
parent 3e0e8cf1f3
commit d5c5edbb72
12 changed files with 3035 additions and 3712 deletions
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2526
USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch Normal file
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File diff suppressed because it is too large Load Diff

2810
USB-host-support-for-Raspberry-Pi-4-board.patch
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File diff suppressed because it is too large Load Diff

1
aarch64-boards
View File

@ -61,6 +61,7 @@ rockpro64-rk3399
roc-pc-rk3399
rpi_3
rpi_4
rpi_arm64
sopine_baseboard
teres_i
turris_mox

863
arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch
View File

@ -1,863 +0,0 @@
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To: u-boot@lists.denx.de,
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xypron.glpk@gmx.de
Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com,
Lin Jinhan <troy.lin@rock-chips.com>
Subject: [PATCH 1/5] arm: dts: rockchip: rk3399: add and enable rng node
Date: Tue, 31 Mar 2020 17:39:57 +0800
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Add rng node in rk3399-u-boot.dtsi and enable it in
rk3399-evb-u-boot.dtsi.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 5 +++++
arch/arm/dts/rk3399-u-boot.dtsi | 6 ++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index ccb33d34d1..5b50c5ba30 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -11,3 +11,8 @@
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
};
+
+&rng {
+ status = "okay";
+};
+
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 8b857ccfc7..757b8c10a2 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -25,6 +25,12 @@
clock-names = "pclk_ddr_mon";
};
+ rng: rng@ff8b8000 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x0 0xff8b8000 0x0 0x1000>;
+ status = "disabled";
+ };
+
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-dmc";
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Subject: [PATCH 2/5] arm: dts: rockchip: px30: add and enable rng node
Date: Tue, 31 Mar 2020 17:39:58 +0800
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Add enable rng node in px30-evb-u-boot.dtsi.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
---
arch/arm/dts/px30-evb-u-boot.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi
index a2a2c07dcc..a73c215c05 100644
--- a/arch/arm/dts/px30-evb-u-boot.dtsi
+++ b/arch/arm/dts/px30-evb-u-boot.dtsi
@@ -12,6 +12,13 @@
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
+
+ rng: rng@ff0b0000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff0b0000 0x0 0x4000>;
+ status = "okay";
+ };
+
};
&dmc {
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Subject: [PATCH 3/5] rockchip: rng: Add a driver for random number
generator(rng) device
Date: Tue, 31 Mar 2020 17:39:59 +0800
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Add a driver for the rng device found on rockchip platforms.
Support rng module of crypto v1 and crypto v2.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
---
drivers/rng/Kconfig | 8 ++
drivers/rng/Makefile | 1 +
drivers/rng/rockchip_rng.c | 224 +++++++++++++++++++++++++++++++++++++
3 files changed, 233 insertions(+)
create mode 100644 drivers/rng/rockchip_rng.c
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index edb6152bb9..e4b22d79eb 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -31,4 +31,12 @@ config RNG_STM32MP1
help
Enable STM32MP1 rng driver.
+config RNG_ROCKCHIP
+ bool "Enable random number generator for rockchip crypto rng"
+ depends on ARCH_ROCKCHIP && DM_RNG
+ default n
+ help
+ Enable random number generator for rockchip.This driver is
+ support rng module of crypto v1 and crypto v2.
+
endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 6a8a66779b..44a0003917 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o
obj-$(CONFIG_RNG_MESON) += meson-rng.o
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
+obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
new file mode 100644
index 0000000000..47fb140077
--- /dev/null
+++ b/drivers/rng/rockchip_rng.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/iopoll.h>
+#include <linux/string.h>
+#include <rng.h>
+
+#define RK_HW_RNG_MAX 32
+
+#define _SBF(s, v) ((v) << (s))
+
+/* start of CRYPTO V1 register define */
+#define CRYPTO_V1_CTRL 0x0008
+#define CRYPTO_V1_RNG_START BIT(8)
+#define CRYPTO_V1_RNG_FLUSH BIT(9)
+
+#define CRYPTO_V1_TRNG_CTRL 0x0200
+#define CRYPTO_V1_OSC_ENABLE BIT(16)
+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
+
+#define CRYPTO_V1_TRNG_DOUT_0 0x0204
+/* end of CRYPTO V1 register define */
+
+/* start of CRYPTO V2 register define */
+#define CRYPTO_V2_RNG_CTL 0x0400
+#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
+#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
+#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
+#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
+#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
+#define CRYPTO_V2_RNG_ENABLE BIT(1)
+#define CRYPTO_V2_RNG_START BIT(0)
+#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
+#define CRYPTO_V2_RNG_DOUT_0 0x0410
+/* end of CRYPTO V2 register define */
+
+#define RK_RNG_TIME_OUT 50000 /* max 50ms */
+
+struct rk_rng_soc_data {
+ int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
+};
+
+struct rk_rng_platdata {
+ fdt_addr_t base;
+ struct rk_rng_soc_data *soc_data;
+};
+
+static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
+{
+ u32 count = RK_HW_RNG_MAX / sizeof(u32);
+ u32 reg, tmp_len;
+
+ if (size > RK_HW_RNG_MAX)
+ return -EINVAL;
+
+ while (size && count) {
+ reg = readl(addr);
+ tmp_len = min(size, sizeof(u32));
+ memcpy(buf, &reg, tmp_len);
+ addr += sizeof(u32);
+ buf += tmp_len;
+ size -= tmp_len;
+ count--;
+ }
+
+ return 0;
+}
+
+static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+ int retval;
+
+ if (len > RK_HW_RNG_MAX)
+ return -EINVAL;
+
+ /* enable osc_ring to get entropy, sample period is set as 100 */
+ writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100),
+ pdata->base + CRYPTO_V1_TRNG_CTRL);
+
+ rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
+ CRYPTO_V1_RNG_START);
+
+ retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
+ !(reg & CRYPTO_V1_RNG_START),
+ RK_RNG_TIME_OUT);
+ if (retval)
+ goto exit;
+
+ rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
+
+exit:
+ /* close TRNG */
+ rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
+
+ return 0;
+}
+
+static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+ int retval;
+
+ if (len > RK_HW_RNG_MAX)
+ return -EINVAL;
+
+ /* enable osc_ring to get entropy, sample period is set as 100 */
+ writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
+
+ reg |= CRYPTO_V2_RNG_256_BIT_LEN;
+ reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
+ reg |= CRYPTO_V2_RNG_ENABLE;
+ reg |= CRYPTO_V2_RNG_START;
+
+ rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg);
+
+ retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg,
+ !(reg & CRYPTO_V2_RNG_START),
+ RK_RNG_TIME_OUT);
+ if (retval)
+ goto exit;
+
+ rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len);
+
+exit:
+ /* close TRNG */
+ rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff);
+
+ return retval;
+}
+
+static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ unsigned char *buf = data;
+ unsigned int i;
+ int ret = -EIO;
+
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+
+ if (!len)
+ return 0;
+
+ if (!pdata->soc_data || !pdata->soc_data->rk_rng_read)
+ return -EINVAL;
+
+ for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) {
+ ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX);
+ if (ret)
+ goto exit;
+ }
+
+ if (len % RK_HW_RNG_MAX)
+ ret = pdata->soc_data->rk_rng_read(dev, buf,
+ len % RK_HW_RNG_MAX);
+
+exit:
+ return ret;
+}
+
+static int rockchip_rng_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+
+ memset(pdata, 0x00, sizeof(*pdata));
+
+ pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev);
+ if (!pdata->base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int rockchip_rng_probe(struct udevice *dev)
+{
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+
+ pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
+
+ return 0;
+}
+
+static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
+ .rk_rng_read = rk_v1_rng_read,
+};
+
+static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
+ .rk_rng_read = rk_v2_rng_read,
+};
+
+static const struct dm_rng_ops rockchip_rng_ops = {
+ .read = rockchip_rng_read,
+};
+
+static const struct udevice_id rockchip_rng_match[] = {
+ {
+ .compatible = "rockchip,cryptov1-rng",
+ .data = (ulong)&rk_rng_v1_soc_data,
+ },
+ {
+ .compatible = "rockchip,cryptov2-rng",
+ .data = (ulong)&rk_rng_v2_soc_data,
+ },
+ {},
+};
+
+U_BOOT_DRIVER(rockchip_rng) = {
+ .name = "rockchip-rng",
+ .id = UCLASS_RNG,
+ .of_match = rockchip_rng_match,
+ .ops = &rockchip_rng_ops,
+ .probe = rockchip_rng_probe,
+ .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct rk_rng_platdata),
+};
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Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com,
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Subject: [PATCH 4/5] rockchip: rk3399: Enable CONFIG_RNG_ROCKCHIP
Date: Tue, 31 Mar 2020 17:40:00 +0800
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CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
---
configs/evb-rk3399_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 3f74be3b3c..7f14e18b1b 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -39,6 +39,8 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
From patchwork Tue Mar 31 09:40:01 2020
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From: Lin Jinhan <troy.lin@rock-chips.com>
To: u-boot@lists.denx.de,
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Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com,
Lin Jinhan <troy.lin@rock-chips.com>
Subject: [PATCH 5/5] rockchip: px30: Enable CONFIG_RNG_ROCKCHIP
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CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
---
configs/evb-px30_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index b5ba75cc6e..d2cf13e54a 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -85,6 +85,8 @@ CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y

14
arm-tegra-define-fdtfile-option-for-distro-boot.patch
View File

@ -1,6 +1,6 @@
From ce2493a9dec8af2dd57839e337b002d256d2a842 Mon Sep 17 00:00:00 2001
From c3332b102d2ddae01710ae8f4393a2a18a3a1bb3 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Tue, 31 Mar 2020 10:38:41 +0100
Date: Tue, 12 May 2020 08:19:48 +0100
Subject: [PATCH] arm: tegra: define fdtfile option for distro boot
For booting via UEFI we need to define the fdtfile option so
@ -20,12 +20,12 @@ Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
7 files changed, 12 insertions(+)
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index f2cdd9c019..997b50394b 100644
index 175c55c613..8026f4b32e 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -55,6 +55,12 @@
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
@@ -52,6 +52,12 @@
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+#ifdef CONFIG_ARM64
+#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
@ -109,5 +109,5 @@ index 54bc6756ab..6c5dc24b26 100644
"ramdisk_addr_r=0x83100000\0"
--
2.26.0
2.26.2

6
initial-support-for-the-Pinebook-Pro-laptop-from.patch
View File

@ -49,11 +49,11 @@ Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
create mode 100644 arch/arm/dts/rk3399-pinebook-pro.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 820ee9733a..885bf0ef58 100644
index 1325134bd4..c4d8ffb13c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-nanopi-m4.dtb \
@@ -129,6 +129,7 @@
rk3399-nanopi-m4-2gb.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
+ rk3399-pinebook-pro.dtb \

36
rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
View File

@ -1,6 +1,6 @@
From 7bf054b1b2e1e4105e94642e18fc74a63eccce97 Mon Sep 17 00:00:00 2001
From 7389a936fbd5ccaae7c39d38d1440e0359f9d0e5 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Tue, 4 Dec 2018 15:26:59 +0000
Date: Tue, 12 May 2020 08:14:26 +0100
Subject: [PATCH] rpi: Use firmware provided device tree
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
@ -13,70 +13,70 @@ Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index 66b0de31b60..9446465fdf7 100644
index 5053a38822..3c6af2b367 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_GPIO=y
@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
+CONFIG_OF_BOARD=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w"
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index ba75e52dda0..d324e2bdd33 100644
index 0000a759f1..f27c5ab1f6 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_GPIO=y
@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
+CONFIG_OF_BOARD=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index bbcdd91e909..46816cd1da7 100644
index a714f9ec49..90ce6ea22e 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_GPIO=y
@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
+CONFIG_OF_BOARD=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 54b6303c2d8..f05ddf8f61f 100644
index 244d9b3a78..f72d6d35e2 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_GPIO=y
@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
+CONFIG_OF_BOARD=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index e7820cb147b..d248873174d 100644
index 64bb184c2b..645dbbec33 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_GPIO=y
@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
-CONFIG_OF_EMBED=y
+CONFIG_OF_BOARD=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
--
2.19.2
2.26.2

62
rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch Normal file
View File

@ -0,0 +1,62 @@
From 50e353960a36f381f855b34b40117c64dc44ad33 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Tue, 12 May 2020 23:23:01 +0100
Subject: [PATCH] config: Enable support for the XHCI controller on RPI4 board
From: Marek Szyprowski <m.szyprowski@samsung.com>
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
configs/rpi_4_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index f1c8f5ef7d..b3e7037bf5 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ARCH_FIXUP_FDT_MEMORY=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="pci enum; usb start;"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
CONFIG_CMD_FS_UUID=y
CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
@@ -27,12 +31,17 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
CONFIG_BCMGENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_BRCMSTB=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
--
2.26.2

40
rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch Normal file
View File

@ -0,0 +1,40 @@
From c9a14b02aea84a37407df7d295e0f76eb529f472 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Tue, 12 May 2020 11:29:00 +0100
Subject: [PATCH] rpi4: enable ARCH_FIXUP_FDT_MEMORY
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
configs/rpi_4_32b_defconfig | 2 +-
configs/rpi_4_defconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index dd7da1cf06..9a0437d376 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -7,7 +7,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_ARCH_FIXUP_FDT_MEMORY=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 6eeec4592e..b3e7037bf5 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -7,7 +7,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_ARCH_FIXUP_FDT_MEMORY=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
--
2.26.2

2
sources
View File

@ -1 +1 @@
SHA512 (u-boot-2020.07-rc1.tar.bz2) = 345b451652ca8bf539f6629ce618113d66ff6690a1f9ccf5a5a4638e6f30c0302fe4af365b5751fa229b09dd354de1db1480c869f511384855d32f692a95acf7
SHA512 (u-boot-2020.07-rc2.tar.bz2) = d4ee96a76cde9305a8733602ce8f9505412f9118e5625f3154249d302445e1c9f970bcf38abb63536129885f3443d1c9fdf9c4e8851e2c1655050d1ebcea7bd2

26
uboot-tools.spec
View File

@ -1,8 +1,8 @@
%global candidate rc1
%global candidate rc2
Name: uboot-tools
Version: 2020.07
Release: 0.1%{?candidate:.%{candidate}}%{?dist}
Release: 0.2%{?candidate:.%{candidate}}%{?dist}
Summary: U-Boot utilities
License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
URL: http://www.denx.de/wiki/U-Boot
@ -22,21 +22,23 @@ Patch2: uefi-use-Fedora-specific-path-name.patch
# Board fixes and enablement
Patch4: usb-kbd-fixes.patch
Patch5: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
Patch6: dragonboard-fixes.patch
Patch5: dragonboard-fixes.patch
# Tegra improvements
Patch10: arm-tegra-define-fdtfile-option-for-distro-boot.patch
Patch11: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch
# Rockchips improvements
Patch12: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch
Patch13: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch
Patch14: initial-support-for-the-Pinebook-Pro-laptop-from.patch
Patch15: rockpro64-limit-speed-on-mSD-slot.patch
Patch12: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch
Patch13: initial-support-for-the-Pinebook-Pro-laptop-from.patch
Patch14: rockpro64-limit-speed-on-mSD-slot.patch
# AllWinner improvements
Patch16: AllWinner-Pine64-bits.patch
Patch15: AllWinner-Pine64-bits.patch
# RPi4
Patch17: USB-host-support-for-Raspberry-Pi-4-board.patch
Patch16: USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch
Patch17: usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch
Patch18: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
Patch19: rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch
Patch20: rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch
BuildRequires: bc
BuildRequires: dtc
@ -250,6 +252,10 @@ cp -p board/warp7/README builds/docs/README.warp7
%endif
%changelog
* Tue May 12 2020 Peter Robinson <pbrobinson@fedoraproject.org> - 2020.07-0.2.rc2
- 2020.07 RC2
- Minor device updates
* Wed Apr 29 2020 Peter Robinson <pbrobinson@fedoraproject.org> - 2020.07-0.1.rc1
- 2020.07 RC1

361
usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch Normal file
View File

@ -0,0 +1,361 @@
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From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: mbrugger@suse.com, u-boot@lists.denx.de, bmeng.cn@gmail.com, marex@denx.de,
linux-kernel@vger.kernel.org
Cc: sjg@chromium.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com,
mark.kettenis@xs4all.nl, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Subject: [PATCH v3 1/2] arm: rpi: Add function to trigger VL805's firmware load
Date: Tue, 5 May 2020 18:26:06 +0200
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On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
may either be loaded directly from an EEPROM or, if not present, by the
SoC's VideCore (the SoC's co-processor). Introduce the function that
informs VideCore that VL805 may need its firmware loaded.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
Changes since v2:
- Correct wrong function name in comment
- Add better comment on rpi_firmware_init_vl805()
Changes since v1:
- Rename function so it's not mistaken with regular firmware loading
arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++
arch/arm/mach-bcm283x/include/mach/msg.h | 7 ++++
arch/arm/mach-bcm283x/msg.c | 45 +++++++++++++++++++++++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 60e226ce1d..2ae2d3d97c 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette {
} body;
};
+#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058
+
+struct bcm2835_mbox_tag_pci_dev_addr {
+ struct bcm2835_mbox_tag_hdr tag_hdr;
+ union {
+ struct {
+ u32 dev_addr;
+ } req;
+ struct {
+ } resp;
+ } body;
+};
+
/*
* Pass a raw u32 message to the VC, and receive a raw u32 back.
*
diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h
index 4afb08631b..f5213dd0e0 100644
--- a/arch/arm/mach-bcm283x/include/mach/msg.h
+++ b/arch/arm/mach-bcm283x/include/mach/msg.h
@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
int pixel_order, int alpha_mode, ulong *fb_basep,
ulong *fb_sizep, int *pitchp);
+/**
+ * bcm2711_notify_vl805_reset() - get vl805's firmware loaded
+ *
+ * @return 0 if OK, -EIO on error
+ */
+int bcm2711_notify_vl805_reset(void);
+
#endif
diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
index 94b75283f8..f8ef531652 100644
--- a/arch/arm/mach-bcm283x/msg.c
+++ b/arch/arm/mach-bcm283x/msg.c
@@ -40,6 +40,12 @@ struct msg_setup {
u32 end_tag;
};
+struct msg_notify_vl805_reset {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_pci_dev_addr dev_addr;
+ u32 end_tag;
+};
+
int bcm2835_power_on_module(u32 module)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
@@ -151,3 +157,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
return 0;
}
+
+/*
+ * The Raspberry Pi 4 gets its USB functionality from VL805, a PCIe chip that
+ * implements xHCI. After a PCI reset, VL805's firmware may either be loaded
+ * directly from an EEPROM or, if not present, by the SoC's co-processor,
+ * VideoCore. RPi4's VideoCore OS contains both the non public firmware load
+ * logic and the VL805 firmware blob. This function triggers the aforementioned
+ * process.
+ */
+int bcm2711_notify_vl805_reset(void)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
+ msg_notify_vl805_reset, 1);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
+ BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,
+ NOTIFY_XHCI_RESET);
+
+ /*
+ * The pci device address is expected like this:
+ *
+ * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12
+ *
+ * But since RPi4's PCIe setup is hardwired, we know the address in
+ * advance.
+ */
+ msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
+ &msg_notify_vl805_reset->hdr);
+ if (ret) {
+ printf("bcm2711: Faild to load vl805's firmware, %d\n", ret);
+ return -EIO;
+ }
+
+ return 0;
+}
+
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linux-kernel@vger.kernel.org
Cc: sjg@chromium.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com,
mark.kettenis@xs4all.nl, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Subject: [PATCH v3 2/2] usb: xhci: Load Raspberry Pi 4 VL805's firmware
Date: Tue, 5 May 2020 18:26:07 +0200
Message-Id: <20200505162607.334-3-nsaenzjulienne@suse.de>
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When needed, RPi4's co-processor (called VideoCore) has to be instructed
to load VL805's firmware (the chip providing xHCI support). VideCore's
firmware expects the board's PCIe bus to be already configured in order
for it to load the xHCI chip firmware. So we have to make sure this
happens in between the PCIe configuration and xHCI startup.
Introduce a callback in xhci_pci_probe() to run this platform specific
routine.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
Changes since v2:
- Get rid of #ifdef CONFIG_BCM2711
- Get rid of redundant error message
Changes since v1:
- Create callback
board/raspberrypi/rpi/rpi.c | 6 ++++++
drivers/usb/host/xhci-pci.c | 6 ++++++
include/usb/xhci.h | 3 +++
3 files changed, 15 insertions(+)
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index e367ba3092..dcaf45fbf2 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -14,6 +14,7 @@
#include <lcd.h>
#include <memalign.h>
#include <mmc.h>
+#include <usb/xhci.h>
#include <asm/gpio.h>
#include <asm/arch/mbox.h>
#include <asm/arch/msg.h>
@@ -494,3 +495,8 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
+
+void xhci_pci_fixup(struct udevice *dev)
+{
+ bcm2711_notify_vl805_reset();
+}
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index c1f60da541..1285dde1ef 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -11,6 +11,10 @@
#include <usb.h>
#include <usb/xhci.h>
+__weak void xhci_pci_fixup(struct udevice *dev)
+{
+}
+
static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
struct xhci_hcor **ret_hcor)
{
@@ -40,6 +44,8 @@ static int xhci_pci_probe(struct udevice *dev)
struct xhci_hccr *hccr;
struct xhci_hcor *hcor;
+ xhci_pci_fixup(dev);
+
xhci_pci_init(dev, &hccr, &hcor);
return xhci_register(dev, hccr, hcor);
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index c16106a2fc..57feed7603 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -16,6 +16,7 @@
#ifndef HOST_XHCI_H_
#define HOST_XHCI_H_
+#include <usb.h>
#include <asm/types.h>
#include <asm/cache.h>
#include <asm/io.h>
@@ -1281,4 +1282,6 @@ extern struct dm_usb_ops xhci_usb_ops;
struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev);
+extern void xhci_pci_fixup(struct udevice *dev);
+
#endif /* HOST_XHCI_H_ */