diff --git a/0001-Enable-sbi-command-and-SBI-sysreset.patch b/0001-Enable-sbi-command-and-SBI-sysreset.patch deleted file mode 100644 index d86f62d..0000000 --- a/0001-Enable-sbi-command-and-SBI-sysreset.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 04441858b575409271ea67d2e65b2f858f0b2522 Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Wed, 29 Jun 2022 14:30:30 +0300 -Subject: [PATCH] Enable "sbi" command and SBI sysreset - -Signed-off-by: David Abdurachmanov ---- - configs/qemu-riscv64_defconfig | 5 +++++ - configs/qemu-riscv64_smode_defconfig | 4 ++++ - configs/sifive_unleashed_defconfig | 5 +++++ - configs/sifive_unmatched_defconfig | 5 +++++ - 4 files changed, 19 insertions(+) - -diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig -index f7b9de10..bb4b8486 100644 ---- a/configs/qemu-riscv64_defconfig -+++ b/configs/qemu-riscv64_defconfig -@@ -16,3 +16,8 @@ CONFIG_CMD_NVEDIT_EFI=y - CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_DM_MTD=y - CONFIG_SYS_MAX_FLASH_BANKS=2 -+CONFIG_CMD_SBI=y -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_SBI=y -+CONFIG_CMD_POWEROFF=y -+CONFIG_SYSRESET_CMD_POWEROFF=y -diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig -index 4d83570c..f13f008d 100644 ---- a/configs/qemu-riscv64_smode_defconfig -+++ b/configs/qemu-riscv64_smode_defconfig -@@ -19,4 +19,8 @@ CONFIG_CMD_NVEDIT_EFI=y - CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_DM_MTD=y - CONFIG_SYS_MAX_FLASH_BANKS=2 -+CONFIG_SYSRESET=y - CONFIG_SYSRESET_SBI=y -+CONFIG_CMD_SBI=y -+CONFIG_CMD_POWEROFF=y -+CONFIG_SYSRESET_CMD_POWEROFF=y -diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig -index fe2227e5..082b23f1 100644 ---- a/configs/sifive_unleashed_defconfig -+++ b/configs/sifive_unleashed_defconfig -@@ -30,3 +30,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y - CONFIG_SPL_CLK=y - CONFIG_DM_MTD=y - CONFIG_DM_RESET=y -+CONFIG_CMD_SBI=y -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_SBI=y -+CONFIG_CMD_POWEROFF=y -+CONFIG_SYSRESET_CMD_POWEROFF=y -diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig -index 5d070843..0dd90856 100644 ---- a/configs/sifive_unmatched_defconfig -+++ b/configs/sifive_unmatched_defconfig -@@ -52,3 +52,8 @@ CONFIG_DM_SCSI=y - CONFIG_USB=y - CONFIG_USB_XHCI_HCD=y - CONFIG_USB_XHCI_PCI=y -+CONFIG_CMD_SBI=y -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_SBI=y -+CONFIG_CMD_POWEROFF=y -+CONFIG_SYSRESET_CMD_POWEROFF=y --- -2.35.1 - diff --git a/0004-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch b/0004-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch deleted file mode 100644 index d58b3c6..0000000 --- a/0004-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch +++ /dev/null @@ -1,35 +0,0 @@ -From d4546cee228b86b8ade6db23b4310880f7756ae0 Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Mon, 13 Sep 2021 03:22:32 -0700 -Subject: [PATCH 4/6] riscv: sifive: unmatched: disable FDT and initrd - relocation - -Same as on SiFive Unleashed we need to disable fdt and initrd relocation. Tom -Rini mentined 18 days ago that it's most likely due to RISC-V lacking -`arch_lmb_reserve` implementation. - -The patch seems to be submitted now: -[PATCH 09/12] lmb: riscv: Add arch_lmb_reserve() -https://lists.denx.de/pipermail/u-boot/2021-September/460333.html - -Signed-off-by: David Abdurachmanov ---- - include/configs/sifive-unmatched.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h -index fa734a66..e62ad6ac 100644 ---- a/include/configs/sifive-unmatched.h -+++ b/include/configs/sifive-unmatched.h -@@ -55,6 +55,8 @@ - "name=system,size=-,bootable,type=${type_guid_gpt_system};" - - #define CONFIG_EXTRA_ENV_SETTINGS \ -+ "fdt_high=0xffffffffffffffff\0" \ -+ "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x84000000\0" \ - "kernel_comp_addr_r=0x88000000\0" \ - "kernel_comp_size=0x4000000\0" \ --- -2.36.1 - diff --git a/0005-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch b/0005-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch deleted file mode 100644 index 3d0f899..0000000 --- a/0005-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch +++ /dev/null @@ -1,104 +0,0 @@ -From fbb43136d726289aba68f6222bf449b7e27ea70b Mon Sep 17 00:00:00 2001 -From: Vincent Chen -Date: Mon, 15 Nov 2021 03:31:04 -0800 -Subject: [PATCH 5/6] board: sifive: spl: Initialized the PWM setting in the - SPL stage - -LEDs and multiple fans can be controlled by SPL. This patch ensures -that all fans have been enabled in the SPL stage. In addition, the -LED's color will be set to yellow. ---- - board/sifive/unmatched/Makefile | 1 + - board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++ - board/sifive/unmatched/spl.c | 2 ++ - 3 files changed, 60 insertions(+) - create mode 100644 board/sifive/unmatched/pwm.c - -diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile -index 13453300..5df01982 100644 ---- a/board/sifive/unmatched/Makefile -+++ b/board/sifive/unmatched/Makefile -@@ -9,3 +9,4 @@ obj-y += spl.o - else - obj-y += unmatched.o - endif -+obj-y += pwm.o -diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c -new file mode 100644 -index 00000000..e1cc0231 ---- /dev/null -+++ b/board/sifive/unmatched/pwm.c -@@ -0,0 +1,57 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2021, SiFive Inc -+ * -+ * Authors: -+ * Vincent Chen -+ * David Abdurachmanov -+ */ -+ -+#include -+#include -+ -+struct pwm_sifive_regs { -+ unsigned int cfg; /* PWM configuration register */ -+ unsigned int pad0; /* Reserved */ -+ unsigned int cnt; /* PWM count register */ -+ unsigned int pad1; /* Reserved */ -+ unsigned int pwms; /* Scaled PWM count register */ -+ unsigned int pad2; /* Reserved */ -+ unsigned int pad3; /* Reserved */ -+ unsigned int pad4; /* Reserved */ -+ unsigned int cmp0; /* PWM 0 compare register */ -+ unsigned int cmp1; /* PWM 1 compare register */ -+ unsigned int cmp2; /* PWM 2 compare register */ -+ unsigned int cmp3; /* PWM 3 compare register */ -+}; -+ -+#define PWM0_BASE 0x10020000 -+#define PWM1_BASE 0x10021000 -+#define PWM_CFG_INIT 0x1000 -+#define PWM_CMP_ENABLE_VAL 0x0 -+#define PWM_CMP_DISABLE_VAL 0xffff -+ -+void pwm_device_init(void) -+{ -+ struct pwm_sifive_regs *pwm0, *pwm1; -+ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE; -+ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE; -+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0); -+ /* Set the 3-color PWM LEDs to yellow in SPL */ -+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1); -+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2); -+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3); -+ writel(PWM_CFG_INIT, (void *)&pwm0->cfg); -+ -+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3); -+ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */ -+ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0, -+ so here sets the initial value of PWM_COMP0 as DISABLE */ -+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3) -+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1); -+ else -+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1); -+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2); -+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3); -+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg); -+} -diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c -index 7c0beedc..f3a661a8 100644 ---- a/board/sifive/unmatched/spl.c -+++ b/board/sifive/unmatched/spl.c -@@ -90,6 +90,8 @@ int spl_board_init_f(void) - goto end; - } - -+ pwm_device_init(); -+ - ret = spl_gemgxl_init(); - if (ret) { - debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret); --- -2.36.1 - diff --git a/0006-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch b/0006-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch deleted file mode 100644 index 97ecfd5..0000000 --- a/0006-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch +++ /dev/null @@ -1,120 +0,0 @@ -From c920399ac5a2bd0d770b1f6833843b7abeb641e7 Mon Sep 17 00:00:00 2001 -From: Vincent Chen -Date: Mon, 24 Jan 2022 02:57:40 -0800 -Subject: [PATCH 6/6] board: sifive: spl: Set remote thermal of TMP451 to 85 - deg C for the unmatched board - -For TMP451 on the unmatched board, the default value of the remote -thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL. ---- - board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++ - drivers/misc/Kconfig | 10 ++++++++++ - include/configs/sifive-unmatched.h | 4 ++++ - scripts/config_whitelist.txt | 1 + - 4 files changed, 44 insertions(+) - -diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c -index f3a661a8..05ba5916 100644 ---- a/board/sifive/unmatched/spl.c -+++ b/board/sifive/unmatched/spl.c -@@ -10,6 +10,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -26,6 +28,27 @@ - #define MODE_SELECT_SD 0xb - #define MODE_SELECT_MASK GENMASK(3, 0) - -+#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19 -+#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55 -+ -+static inline int init_tmp451_remote_therm_limit(void) -+{ -+ struct udevice *dev; -+ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE; -+ int ret; -+ -+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM, -+ CONFIG_SYS_I2C_TMP451_ADDR, -+ CONFIG_SYS_I2C_TMP451_ADDR_LEN, -+ &dev); -+ -+ if (!ret) -+ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET, -+ &r_therm_limit, -+ sizeof(unsigned char)); -+ return ret; -+} -+ - static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width) - { - int ret; -@@ -92,6 +115,12 @@ int spl_board_init_f(void) - - pwm_device_init(); - -+ ret = init_tmp451_remote_therm_limit(); -+ if (ret) { -+ debug("TMP451 remote THERM limit init failed: %d\n", ret); -+ goto end; -+ } -+ - ret = spl_gemgxl_init(); - if (ret) { - debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret); -diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig -index 85ae7f62..38229cdf 100644 ---- a/drivers/misc/Kconfig -+++ b/drivers/misc/Kconfig -@@ -463,6 +463,16 @@ config SYS_I2C_EEPROM_ADDR - - if I2C_EEPROM - -+config SYS_I2C_TMP451_ADDR -+ hex "Chip address of the TMP451 device" -+ default 0 -+ -+config SYS_I2C_TMP451_ADDR_LEN -+ int "Length in bytes of the TMP451 memory array address" -+ default 1 -+ help -+ Note: This is NOT the chip address length! -+ - config SYS_I2C_EEPROM_ADDR_OVERFLOW - hex "EEPROM Address Overflow" - default 0x0 -diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h -index e62ad6ac..718108a3 100644 ---- a/include/configs/sifive-unmatched.h -+++ b/include/configs/sifive-unmatched.h -@@ -32,6 +32,10 @@ - - #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - -+#define CONFIG_SYS_TMP451_BUS_NUM 0 -+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c -+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1 -+ - /* Environment options */ - - #ifndef CONFIG_SPL_BUILD -diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt -index cecdda67..378faa09 100644 ---- a/scripts/config_whitelist.txt -+++ b/scripts/config_whitelist.txt -@@ -1671,6 +1671,7 @@ CONFIG_SYS_TIMER_BASE - CONFIG_SYS_TIMER_COUNTER - CONFIG_SYS_TIMER_COUNTS_DOWN - CONFIG_SYS_TIMER_RATE -+CONFIG_SYS_TMP451_BUS_NUM - CONFIG_SYS_TMPVIRT - CONFIG_SYS_TSEC1_OFFSET - CONFIG_SYS_TSEC2_OFFSET --- -2.36.1 - diff --git a/aarch64-boards b/aarch64-boards index a38107c..f8e2f3b 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -6,6 +6,7 @@ bananapi_m64 beelink_gs1 dragonboard410c dragonboard820c +dragonboard845c evb-rk3328 evb-rk3399 ficus-rk3399 @@ -58,9 +59,9 @@ pine64-lts pine64_plus pinebook pinebook-pro-rk3399 -pinephone-pro-rk3399 pine_h64 pinephone +pinephone-pro-rk3399 pinetab poplar puma-rk3399 @@ -77,8 +78,8 @@ roc-pc-rk3399 rpi_3 rpi_4 rpi_arm64 -starqltechn sopine_baseboard +starqltechn tanix_tx6 teres_i turris_mox diff --git a/riscv64-boards b/riscv64-boards deleted file mode 100644 index 12c1766..0000000 --- a/riscv64-boards +++ /dev/null @@ -1,5 +0,0 @@ -qemu-riscv64 -qemu-riscv64_smode -qemu-riscv64_spl -sifive_unleashed -sifive_unmatched diff --git a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch index 3dc7614..30012ad 100644 --- a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch +++ b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch @@ -1,34 +1,38 @@ -From: Martijn Braam -Subject: [PATCH] rockchip: Add initial support for the PinePhone Pro -Date: Thu, 21 Oct 2021 19:18:43 +0200 +From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 31 Dec 2022 09:20:34 +0000 +Subject: [PATCH v2 0/2] Initial support for Pinephone Pro -This is a new device by PINE64 that's very similar to the Pinebook Pro -that's already supported. +This adds initial support for the PINE64 Pinephone Pro. It's a rebase +to upstream core rk3399 DT pieces, and the addition of the upstream +PPP DT from 6.2-rc1 and the U-Boot pieces are based on my work on +the Pinebook Pro. -Specification: -- Rockchip RK3399 -- 4GB Dual-Channel LPDDR4 -- 128GB eMMC -- mSD card slot -- AP6255 for 802.11ac WiFi and Bluetooth -- 6 inch 720*1440 DSI display -- Quectel EG25g usb modem -- Type-C port with alt-mode display (DP 1.2) and PD charging. +Changes v2: +- Drop the rk3399.dtsi sync for time being, causing issues around + clock/dram +- Sync the Pinephone DT to 6.2-rc1 +- Update for the CONFIG_SYS_TEXT_BASE -> CONFIG_TEXT_BASE change +- usb: ohci: Use a flexible array member for portstatus +- Rename CONFIG_DM_VIDEO to CONFIG_VIDEO +- Enable DM_REGULATOR_FAN53555 +- Don't initialize i2c before relocation -Signed-off-by: Martijn Braam ---- +Peter Robinson (2): + arm64: dts: rk3399: Add upstream Pinephone Pro dts + rockchip: Add initial support for the PINE64 Pinephone Pro arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++ - arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++ + arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++ + arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinephone-pro-rk3399/Kconfig | 15 + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + board/pine64/pinephone-pro-rk3399/Makefile | 1 + - .../pinephone-pro-rk3399.c | 57 ++ - configs/pinephone-pro-rk3399_defconfig | 92 ++++ - include/configs/pinephone-pro-rk3399.h | 23 + - 10 files changed, 769 insertions(+) + .../pinephone-pro-rk3399.c | 76 +++ + configs/pinephone-pro-rk3399_defconfig | 104 ++++ + include/configs/pinephone-pro-rk3399.h | 19 + + 10 files changed, 737 insertions(+) create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig @@ -37,12 +41,30 @@ Signed-off-by: Martijn Braam create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c create mode 100644 configs/pinephone-pro-rk3399_defconfig create mode 100644 include/configs/pinephone-pro-rk3399.h - + +-- +2.39.0 + +From 9976caacb35316cbe047ded58855d2ca1a54243b Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 31 Dec 2022 09:18:44 +0000 +Subject: [PATCH v2 1/2] arm64: dts: rk3399: Add upstream Pinephone Pro dts + +Initial support for the PinePhone Pro has now landed upstream in +Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++++++++++ + 2 files changed, 475 insertions(+) + create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts + diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index ed3d360bb1..3206370226 100644 +index 43951a7731e..8c1eec1025f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ +@@ -153,6 +153,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-r4s.dtb \ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ @@ -50,106 +72,115 @@ index ed3d360bb1..3206370226 100644 rk3399-puma-haikou.dtb \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ -diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -new file mode 100644 -index 0000000000..9d44db5978 ---- /dev/null -+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Peter Robinson -+ * Copyright (C) 2021 Martijn Braam -+ */ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+ -+/ { -+ aliases { -+ spi0 = &spi1; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+ -+ config { -+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ -+ }; -+}; -+ -+&i2c0 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rk818 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rng { -+ status = "okay"; -+}; -+ -+&sdhci { -+ max-frequency = <25000000>; -+ u-boot,dm-pre-reloc; -+}; -+ -+&sdmmc { -+ max-frequency = <20000000>; -+ u-boot,dm-pre-reloc; -+}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts new file mode 100644 -index 0000000000..3fe1845ced +index 00000000000..04403a76238 --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro.dts -@@ -0,0 +1,520 @@ +@@ -0,0 +1,474 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* -+ * Copyright (c) 2021 Martijn Braam ++ * Copyright (c) 2020 Martijn Braam ++ * Copyright (c) 2021 Kamil Trzciński ++ */ ++ ++/* ++ * PinePhone Pro datasheet: ++ * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf + */ + +/dts-v1/; ++#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { -+ model = "Pine64 PinePhone Pro"; ++ model = "Pine64 PinePhonePro"; + compatible = "pine64,pinephone-pro", "rockchip,rk3399"; ++ chassis-type = "handset"; ++ ++ aliases { ++ mmc0 = &sdio0; ++ mmc1 = &sdmmc; ++ mmc2 = &sdhci; ++ }; + + chosen { -+ stdout-path = "serial2:1500000n8"; ++ stdout-path = "serial2:115200n8"; + }; + -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; ++ gpio-keys { ++ compatible = "gpio-keys"; + pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn_pin>; ++ ++ key-power { ++ debounce-interval = <20>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "Power"; ++ linux,code = ; ++ wakeup-source; ++ }; + }; + -+ /* Power tree */ -+ /* Root power source */ -+ vcc_sysin: vcc-sysin { ++ vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; -+ regulator-name = "vcc_sysin"; ++ regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + }; + -+ /* Main 3.3v supply */ -+ vcc3v3_sys: vcc3v3-sys { ++ vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sysin>; ++ vin-supply = <&vcc_sys>; ++ }; + -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; ++ vcca1v8_s3: vcc1v8-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca1v8_s3"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc1v8_codec: vcc1v8-codec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc1v8_codec_en>; ++ regulator-name = "vcc1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ wifi_pwrseq: sdio-wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk818 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h_pin>; ++ /* ++ * Wait between power-on and SDIO access for CYP43455 ++ * POR circuit. ++ */ ++ post-power-on-delay-ms = <110>; ++ /* ++ * Wait between consecutive toggles for CYP43455 CBUCK ++ * regulator discharge. ++ */ ++ power-off-delay-us = <10000>; ++ ++ /* WL_REG_ON on module */ ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + @@ -181,11 +212,6 @@ index 0000000000..3fe1845ced + status = "okay"; +}; + -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; @@ -204,22 +230,22 @@ index 0000000000..3fe1845ced + rockchip,system-power-controller; + wakeup-source; + -+ vcc1-supply = <&vcc_sysin>; -+ vcc2-supply = <&vcc_sysin>; -+ vcc3-supply = <&vcc_sysin>; -+ vcc4-supply = <&vcc_sysin>; -+ vcc6-supply = <&vcc_sysin>; ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc_sysin>; ++ vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_cpu_l: DCDC_REG1 { -+ regulator-name = "vdd_cpu_1"; ++ regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; @@ -231,7 +257,7 @@ index 0000000000..3fe1845ced + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1350000>; ++ regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; @@ -255,52 +281,35 @@ index 0000000000..3fe1845ced + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca3v0_codec: LDO_REG1 { + regulator-name = "vcca3v0_codec"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + + vcca1v8_codec: LDO_REG3 { + regulator-name = "vcca1v8_codec"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + -+ vcc_power_on: LDO_REG4 { -+ regulator-name = "vcc_power_on"; ++ rk818_pwr_on: LDO_REG4 { ++ regulator-name = "rk818_pwr_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; + }; + }; + @@ -312,7 +321,6 @@ index 0000000000..3fe1845ced + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; + }; + }; + @@ -324,19 +332,13 @@ index 0000000000..3fe1845ced + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_dvp: LDO_REG7 { + regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; + }; + + vcc3v3_s3: LDO_REG8 { @@ -350,14 +352,10 @@ index 0000000000..3fe1845ced + }; + }; + -+ vcc_sd: LDO_REG9 { -+ regulator-name = "vcc_sd"; ++ vccio_sd: LDO_REG9 { ++ regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; + }; + + vcc3v3_s0: SWITCH_REG { @@ -368,22 +366,6 @@ index 0000000000..3fe1845ced + regulator-on-in-suspend; + }; + }; -+ -+ boost_otg: DCDC_BOOST { -+ regulator-name = "boost_otg"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <5000000>; -+ }; -+ }; -+ -+ otg_switch: OTG_SWITCH { -+ regulator-name = "otg_switch"; -+ }; + }; + }; + @@ -394,8 +376,8 @@ index 0000000000..3fe1845ced + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; @@ -412,8 +394,8 @@ index 0000000000..3fe1845ced + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; @@ -424,95 +406,47 @@ index 0000000000..3fe1845ced + }; +}; + -+&i2c1 { -+ i2c-scl-rising-time-ns = <300>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; ++&cluster0_opp { ++ opp04 { ++ status = "disabled"; ++ }; ++ ++ opp05 { ++ status = "disabled"; ++ }; +}; + -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; ++&cluster1_opp { ++ opp06 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <1100000 1100000 1150000>; ++ }; + -+&i2c4 { -+ i2c-scl-rising-time-ns = <600>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+ -+ fusb0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int>; -+ status = "okay"; ++ opp07 { ++ status = "disabled"; + }; +}; + +&io_domains { -+ status = "okay"; -+ + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sd>; ++ sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; ++ status = "okay"; +}; + +&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; ++ pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ + buttons { -+ pwrbtn: pwrbtn { ++ pwrbtn_pin: pwrbtn-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + -+ fusb302x { -+ fusb0_int: fusb0-int { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ leds { -+ work_led_pin: work-led-pin { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ diy_led_pin: diy-led-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie_perst: pcie-perst { -+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_pwr_en: pcie-pwr-en { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -527,51 +461,40 @@ index 0000000000..3fe1845ced + }; + }; + -+ sdcard { -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ }; -+ + sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { ++ wifi_enable_h_pin: wifi-enable-h-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + -+ usb-typec { -+ vcc5v0_typec_en: vcc5v0_typec_en { -+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ sound { ++ vcc1v8_codec_en: vcc1v8-codec-en { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + -+ usb2 { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ wireless-bluetooth { ++ bt_wake_pin: bt-wake-pin { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_pin: bt-host-wake-pin { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_reset_pin: bt-reset-pin { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; ++ mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; @@ -582,13 +505,13 @@ index 0000000000..3fe1845ced +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; -+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v3_s3>; -+ vqmmc-supply = <&vcc_1v8>; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + @@ -600,51 +523,133 @@ index 0000000000..3fe1845ced +}; + +&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rk818 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ max-speed = <1500000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ }; ++}; ++ +&uart2 { + status = "okay"; +}; +-- +2.39.0 + +From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 28 Dec 2022 03:52:27 +0000 +Subject: [PATCH v2 2/2] rockchip: Add initial support for the PINE64 Pinephone + Pro + +The Pinephone Pro is another device by PINE64. It's closely related +to the Pinebook Pro of which this initial support is derived from. + +Specification: +- A variant of the Rockchip RK3399 +- A 6 inch 720*1440 DSI display +- Front and rear cameras +- Type-C interface with alt mode display (DP 1.2) and PD charging +- 4GB LPDDR4 RAM +- 128GB eMMC +- mSD card slot +- An AP6255 module for 802.11ac WiFi and Bluetooth 5 +- Quectel EG25-G 4G/LTE modem + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++++++ + arch/arm/mach-rockchip/rk3399/Kconfig | 8 ++ + board/pine64/pinephone-pro-rk3399/Kconfig | 15 +++ + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 ++ + board/pine64/pinephone-pro-rk3399/Makefile | 1 + + .../pinephone-pro-rk3399.c | 76 +++++++++++++ + configs/pinephone-pro-rk3399_defconfig | 104 ++++++++++++++++++ + include/configs/pinephone-pro-rk3399.h | 19 ++++ + 8 files changed, 262 insertions(+) + create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi + create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig + create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS + create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile + create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c + create mode 100644 configs/pinephone-pro-rk3399_defconfig + create mode 100644 include/configs/pinephone-pro-rk3399.h + +diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +new file mode 100644 +index 00000000000..1dad283ad05 +--- /dev/null ++++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2022 Peter Robinson ++ */ + -+&vopb { ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ }; ++ ++ config { ++ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ ++ }; ++}; ++ ++&rng { + status = "okay"; +}; + -+&vopb_mmu { -+ status = "okay"; ++&sdhci { ++ max-frequency = <25000000>; ++ u-boot,dm-pre-reloc; +}; + -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; ++&sdmmc { ++ max-frequency = <20000000>; ++ u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig -index 17628f9171..3ba603ca80 100644 +index b48feeb3466..d01063ac98b 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399 +@@ -39,6 +39,13 @@ config TARGET_PINEBOOK_PRO_RK3399 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, 1920*1080 screen and all the usual laptop features. +config TARGET_PINEPHONE_PRO_RK3399 + bool "PinePhone Pro" + help -+ PinePhone Pro is a phone based on the Rockchip rk3399 SoC -+ with 4Gb RAM, onboard eMMC, USB-C, a headphone jack, -+ 720x1440 screen and an external Quectel USB modem. ++ PinePhone Pro is a phone based on a variant of the Rockchip ++ rk3399 SoC with 4Gb RAM, onboard eMMC, USB-C, headphone jack, ++ 720x1440 screen and a Quectel 4G/LTE modem. + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help -@@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT +@@ -165,6 +172,7 @@ endif # BOOTCOUNT_LIMIT source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" @@ -654,7 +659,7 @@ index 17628f9171..3ba603ca80 100644 source "board/theobroma-systems/puma_rk3399/Kconfig" diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig new file mode 100644 -index 0000000000..13d6465ae6 +index 00000000000..13d6465ae6e --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Kconfig @@ -0,0 +1,15 @@ @@ -675,12 +680,12 @@ index 0000000000..13d6465ae6 +endif diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS new file mode 100644 -index 0000000000..9ca4fc4cbe +index 00000000000..c923ff1be32 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS @@ -0,0 +1,8 @@ +PINEPHONE_PRO -+M: Martijn Braam ++M: Peter Robinson +S: Maintained +F: board/pine64/rk3399-pinephone-pro/ +F: include/configs/rk3399-pinephone-pro.h @@ -689,21 +694,21 @@ index 0000000000..9ca4fc4cbe +F: configs/pinephone-pro-rk3399_defconfig diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile new file mode 100644 -index 0000000000..8d9203053e +index 00000000000..8d9203053e5 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Makefile @@ -0,0 +1 @@ +obj-y += pinephone-pro-rk3399.o diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c new file mode 100644 -index 0000000000..8efeb6ea3d +index 00000000000..eb639cd0d07 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -@@ -0,0 +1,57 @@ +@@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* -+ * (C) Copyright 2019 Vasily Khoruzhick -+ * (C) Copyright 2021 Martijn Braam ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ * (C) Copyright 2022 Peter Robinson + */ + +#include @@ -715,17 +720,39 @@ index 0000000000..8efeb6ea3d +#include +#include +#include ++#include + +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define PMUGRF_CON0_VSEL_SHIFT 8 + ++#ifndef CONFIG_SPL_BUILD ++int board_early_init_f(void) ++{ ++ struct udevice *regulator; ++ int ret; ++ ++ ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); ++ if (ret) { ++ pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); ++ goto out; ++ } ++ ++ ret = regulator_set_enable(regulator, true); ++ if (ret) ++ pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); ++ ++out: ++ return 0; ++} ++#endif ++ +#ifdef CONFIG_MISC_INIT_R +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); ++ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); @@ -751,42 +778,49 @@ index 0000000000..8efeb6ea3d + if (ret) + return ret; + -+ ret = rockchip_setup_macaddr(); -+ + return ret; +} -+ +#endif diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig new file mode 100644 -index 0000000000..2cf80f7d35 +index 00000000000..eb979f6c051 --- /dev/null +++ b/configs/pinephone-pro-rk3399_defconfig -@@ -0,0 +1,92 @@ +@@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_PINEPHONE_PRO_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" -+CONFIG_DEBUG_UART=y ++CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y ++CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x400000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y @@ -804,6 +838,7 @@ index 0000000000..2cf80f7d35 +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEYBOARD=y @@ -816,13 +851,14 @@ index 0000000000..2cf80f7d35 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_DM_ETH=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y ++CONFIG_DM_REGULATOR_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y @@ -849,23 +885,22 @@ index 0000000000..2cf80f7d35 +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y -+CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y ++CONFIG_VIDEO=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h new file mode 100644 -index 0000000000..fefa793fdd +index 00000000000..78017d6bcc3 --- /dev/null +++ b/include/configs/pinephone-pro-rk3399.h -@@ -0,0 +1,23 @@ +@@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd -+ * Copyright (C) 2020 Peter Robinson -+ * Copyright (C) 2021 Martijn Braam ++ * Copyright (C) 2022 Peter Robinson + */ + +#ifndef __PINEPHONE_PRO_RK3399_H @@ -880,7 +915,6 @@ index 0000000000..fefa793fdd + +#define SDRAM_BANK_SIZE (2UL << 30) + -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ +#endif +-- +2.39.0 diff --git a/rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch b/rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch new file mode 100644 index 0000000..7ef65bc --- /dev/null +++ b/rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch @@ -0,0 +1,296 @@ +From patchwork Wed Aug 10 12:39:26 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Antoine Mazeas +X-Patchwork-Id: 1665242 +X-Patchwork-Delegate: matthias.bgg@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: bilbo.ozlabs.org; + dkim=pass (1024-bit key; + unprotected) header.d=karthanis.net header.i=@karthanis.net + header.a=rsa-sha256 header.s=20191114 header.b=mcrC/rnn; + dkim-atps=neutral +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (2048 bits)) + (No client certificate requested) + by bilbo.ozlabs.org (Postfix) with ESMTPS id 4M2qkM6g8Vz9ryY + for ; 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Wed, 10 Aug 2022 14:40:43 +0200 (CEST) +Authentication-Results: phobos.denx.de; + dmarc=pass (p=none dis=none) header.from=karthanis.net +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=antoine@karthanis.net +Received: from smtp-3-0001.mail.infomaniak.ch (unknown [10.4.36.108]) + by smtp-2-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4M2qKl3S6GzMqbyx; + Wed, 10 Aug 2022 14:40:43 +0200 (CEST) +Received: from localhost.localdomain (unknown [88.168.170.86]) + by smtp-3-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4M2qKk6qXKzlnSD1; + Wed, 10 Aug 2022 14:40:42 +0200 (CEST) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=karthanis.net; + s=20191114; t=1660135243; + bh=YF4GTVv5pqqW0OMrNZFlf0WHnELr1KiKKA02ok/znf4=; + h=From:To:Cc:Subject:Date:In-Reply-To:References:From; + b=mcrC/rnnUv3FXlrllL2s9lLTjUEnTuLbiINuyrIQWr2HG3AmCcD11F7n0AypUdePp + 2XfG1PnZalJa2v3m6/DUWsz6B/cqmYo31h/6HpFeJ4g2i1pEZar7cC+9oScmbjJptV + w2oDsFHzyK2oWHUMGFJ4N6bboD8kq3z4WLaH2vrQ= +From: Antoine Mazeas +To: u-boot@lists.denx.de +Cc: Antoine Mazeas , + Sjoerd Simons +Subject: [PATCH 1/2] rpi: Copy properties from firmware dtb to the loaded dtb +Date: Wed, 10 Aug 2022 14:39:26 +0200 +Message-Id: <20220810123927.2567677-2-antoine@karthanis.net> +X-Mailer: git-send-email 2.37.1 +In-Reply-To: <20220810123927.2567677-1-antoine@karthanis.net> +References: <20220810123927.2567677-1-antoine@karthanis.net> +MIME-Version: 1.0 +X-Mailman-Approved-At: Wed, 10 Aug 2022 14:58:03 +0200 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de +X-Virus-Status: Clean + +The RPI firmware adjusts several property values in the dtb it passes +to u-boot depending on the board/SoC revision. Inherit some of these +when u-boot loads a dtb itself. Specificaly copy: + +* /model: The firmware provides a more specific string +* /memreserve: The firmware defines a reserved range, better keep it +* emmc2bus and pcie0 dma-ranges: The C0T revision of the bcm2711 Soc (as + present on rpi 400 and some rpi 4B boards) has different values for + these then the B0T revision. So these need to be adjusted to boot on + these boards +* blconfig: The firmware defines the memory area where the blconfig + stored. Copy those over so it can be enabled. +* /chosen/kaslr-seed: The firmware generates a kaslr seed, take advantage + of that. + +Signed-off-by: Sjoerd Simons +--- + board/raspberrypi/rpi/rpi.c | 48 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index 17b8108cc8..28b6f52506 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -504,10 +504,58 @@ void *board_fdt_blob_setup(int *err) + return (void *)fw_dtb_pointer; + } + ++int copy_property(void *dst, void *src, char *path, char *property) ++{ ++ int dst_offset, src_offset; ++ const fdt32_t *prop; ++ int len; ++ ++ src_offset = fdt_path_offset(src, path); ++ dst_offset = fdt_path_offset(dst, path); ++ ++ if (src_offset < 0 || dst_offset < 0) ++ return -1; ++ ++ prop = fdt_getprop(src, src_offset, property, &len); ++ if (!prop) ++ return -1; ++ ++ return fdt_setprop(dst, dst_offset, property, prop, len); ++} ++ ++/* Copy tweaks from the firmware dtb to the loaded dtb */ ++void update_fdt_from_fw(void *fdt, void *fw_fdt) ++{ ++ /* Using dtb from firmware directly; leave it alone */ ++ if (fdt == fw_fdt) ++ return; ++ ++ /* The firmware provides a more precie model; so copy that */ ++ copy_property(fdt, fw_fdt, "/", "model"); ++ ++ /* memory reserve as suggested by the firmware */ ++ copy_property(fdt, fw_fdt, "/", "memreserve"); ++ ++ /* Adjust dma-ranges for the SD card and PCI bus as they can depend on ++ * the SoC revision ++ */ ++ copy_property(fdt, fw_fdt, "emmc2bus", "dma-ranges"); ++ copy_property(fdt, fw_fdt, "pcie0", "dma-ranges"); ++ ++ /* Bootloader configuration template exposes as nvmem */ ++ if (copy_property(fdt, fw_fdt, "blconfig", "reg") == 0) ++ copy_property(fdt, fw_fdt, "blconfig", "status"); ++ ++ /* kernel address randomisation seed as provided by the firmware */ ++ copy_property(fdt, fw_fdt, "/chosen", "kaslr-seed"); ++} ++ + int ft_board_setup(void *blob, struct bd_info *bd) + { + int node; + ++ update_fdt_from_fw(blob, (void *)fw_dtb_pointer); ++ + node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer"); + if (node < 0) + fdt_simplefb_add_node(blob); + +From patchwork Wed Aug 10 12:39:27 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Antoine Mazeas +X-Patchwork-Id: 1665243 +X-Patchwork-Delegate: matthias.bgg@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: bilbo.ozlabs.org; + dkim=pass (1024-bit key; + unprotected) header.d=karthanis.net header.i=@karthanis.net + header.a=rsa-sha256 header.s=20191114 header.b=3Vltv92i; + dkim-atps=neutral +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (2048 bits)) + (No client certificate requested) + by bilbo.ozlabs.org (Postfix) with ESMTPS id 4M2qkb5v6sz9ryY + for ; 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The correct address is provided by the firmware, so we should carry it over into the loaded device tree so that ethernet works on such boards. + +Signed-off-by: Antoine Mazeas +--- + board/raspberrypi/rpi/rpi.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c +index 28b6f52506..793fd1aa30 100644 +--- a/board/raspberrypi/rpi/rpi.c ++++ b/board/raspberrypi/rpi/rpi.c +@@ -548,6 +548,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) + + /* kernel address randomisation seed as provided by the firmware */ + copy_property(fdt, fw_fdt, "/chosen", "kaslr-seed"); ++ ++ /* address of the PHY device as provided by the firmware */ ++ copy_property(fdt, fw_fdt, "ethernet0/mdio@e14/ethernet-phy@1", "reg"); + } + + int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/smbios-Simplify-reporting-of-unknown-values.patch b/smbios-Simplify-reporting-of-unknown-values.patch new file mode 100644 index 0000000..0aef8e7 --- /dev/null +++ b/smbios-Simplify-reporting-of-unknown-values.patch @@ -0,0 +1,544 @@ +From patchwork Tue Sep 6 13:44:25 2022 +Content-Type: text/plain; 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+ Tue, 06 Sep 2022 06:44:34 -0700 (PDT) +From: Ilias Apalodimas +To: u-boot@lists.denx.de +Cc: trini@konsulko.com, sjg@chromium.org, heinrich.schuchardt@canonical.com, + pbrobinson@gmail.com, Ilias Apalodimas +Subject: [PATCH 1/2] smbios: Simplify reporting of unknown values +Date: Tue, 6 Sep 2022 16:44:25 +0300 +Message-Id: <20220906134426.53748-1-ilias.apalodimas@linaro.org> +X-Mailer: git-send-email 2.37.2 +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de +X-Virus-Status: Clean + +If a value is not valid during the DT or SYSINFO parsing, we explicitly +set that to "Unknown Product" and "Unknown" for the product and +manufacturer respectively. It's cleaner if we move the checks insisde +smbios_add_string() and always report "Unknown" regardless of the missing +field. + +pre-patch dmidecode + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: Unknown + Product Name: Unknown Product + Version: Not Specified + Serial Number: Not Specified + UUID: Not Settable + Wake-up Type: Reserved + SKU Number: Not Specified + Family: Not Specified + +Handle 0x0002, DMI type 2, 14 bytes +Base Board Information + Manufacturer: Unknown + Product Name: Unknown Product + Version: Not Specified + Serial Number: Not Specified + Asset Tag: Not Specified + Features: + Board is a hosting board + Location In Chassis: Not Specified + Chassis Handle: 0x0000 + Type: Motherboard + + +post-patch dmidecode: + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: Unknown + Product Name: Unknown + Version: Unknown + Serial Number: Unknown + UUID: Not Settable + Wake-up Type: Reserved + SKU Number: Unknown + Family: Unknown + +Handle 0x0002, DMI type 2, 14 bytes +Base Board Information + Manufacturer: Unknown + Product Name: Unknown + Version: Unknown + Serial Number: Not Specified + Asset Tag: Unknown + Features: + Board is a hosting board + Location In Chassis: Not Specified + Chassis Handle: 0x0000 + Type: Motherboard + +Signed-off-by: Ilias Apalodimas +--- + lib/smbios.c | 17 +++-------------- + 1 file changed, 3 insertions(+), 14 deletions(-) + +diff --git a/lib/smbios.c b/lib/smbios.c +index d7f4999e8b2a..fcc8686993ef 100644 +--- a/lib/smbios.c ++++ b/lib/smbios.c +@@ -102,7 +102,7 @@ static int smbios_add_string(struct smbios_ctx *ctx, const char *str) + int i = 1; + char *p = ctx->eos; + +- if (!*str) ++ if (!str || !*str) + str = "Unknown"; + + for (;;) { +@@ -151,8 +151,7 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, + const char *str; + + str = ofnode_read_string(ctx->node, prop); +- if (str) +- return smbios_add_string(ctx, str); ++ return smbios_add_string(ctx, str); + } + + return 0; +@@ -231,7 +230,7 @@ static int smbios_write_type0(ulong *current, int handle, + t->vendor = smbios_add_string(ctx, "U-Boot"); + + t->bios_ver = smbios_add_prop(ctx, "version"); +- if (!t->bios_ver) ++ if (!strcmp(ctx->last_str, "Unknown")) + t->bios_ver = smbios_add_string(ctx, PLAIN_VERSION); + if (t->bios_ver) + gd->smbios_version = ctx->last_str; +@@ -281,11 +280,7 @@ static int smbios_write_type1(ulong *current, int handle, + fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); + smbios_set_eos(ctx, t->eos); + t->manufacturer = smbios_add_prop(ctx, "manufacturer"); +- if (!t->manufacturer) +- t->manufacturer = smbios_add_string(ctx, "Unknown"); + t->product_name = smbios_add_prop(ctx, "product"); +- if (!t->product_name) +- t->product_name = smbios_add_string(ctx, "Unknown Product"); + t->version = smbios_add_prop_si(ctx, "version", + SYSINFO_ID_SMBIOS_SYSTEM_VERSION); + if (serial_str) { +@@ -315,11 +310,7 @@ static int smbios_write_type2(ulong *current, int handle, + fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); + smbios_set_eos(ctx, t->eos); + t->manufacturer = smbios_add_prop(ctx, "manufacturer"); +- if (!t->manufacturer) +- t->manufacturer = smbios_add_string(ctx, "Unknown"); + t->product_name = smbios_add_prop(ctx, "product"); +- if (!t->product_name) +- t->product_name = smbios_add_string(ctx, "Unknown Product"); + t->version = smbios_add_prop_si(ctx, "version", + SYSINFO_ID_SMBIOS_BASEBOARD_VERSION); + t->asset_tag_number = smbios_add_prop(ctx, "asset-tag"); +@@ -344,8 +335,6 @@ static int smbios_write_type3(ulong *current, int handle, + fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); + smbios_set_eos(ctx, t->eos); + t->manufacturer = smbios_add_prop(ctx, "manufacturer"); +- if (!t->manufacturer) +- t->manufacturer = smbios_add_string(ctx, "Unknown"); + t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; + t->bootup_state = SMBIOS_STATE_SAFE; + t->power_supply_state = SMBIOS_STATE_SAFE; + +From patchwork Tue Sep 6 13:44:26 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Ilias Apalodimas +X-Patchwork-Id: 1674858 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Authentication-Results: legolas.ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 + header.s=google header.b=wBCOiKYw; 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+ Tue, 06 Sep 2022 06:44:48 -0700 (PDT) +From: Ilias Apalodimas +To: u-boot@lists.denx.de +Cc: trini@konsulko.com, sjg@chromium.org, heinrich.schuchardt@canonical.com, + pbrobinson@gmail.com, Ilias Apalodimas +Subject: [PATCH 2/2] smbios: Fallback to the default DT if sysinfo nodes are + missing +Date: Tue, 6 Sep 2022 16:44:26 +0300 +Message-Id: <20220906134426.53748-2-ilias.apalodimas@linaro.org> +X-Mailer: git-send-email 2.37.2 +In-Reply-To: <20220906134426.53748-1-ilias.apalodimas@linaro.org> +References: <20220906134426.53748-1-ilias.apalodimas@linaro.org> +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de +X-Virus-Status: Clean + +In order to fill in the SMBIOS tables U-Boot currently relies on a +"u-boot,sysinfo-smbios" compatible node. This is fine for the boards +that already include such nodes. However with some recent EFI changes, +the majority of boards can boot up distros, which usually rely on +things like dmidecode etc for their reporting. For boards that +lack this special node the SMBIOS output looks like: + +System Information + Manufacturer: Unknown + Product Name: Unknown + Version: Unknown + Serial Number: Unknown + UUID: Not Settable + Wake-up Type: Reserved + SKU Number: Unknown + Family: Unknown + +This looks problematic since most of the info are "Unknown". The DT spec +specifies standard properties containing relevant information like +'model' and 'compatible' for which the suggested format is +. So let's add a last resort to our current +smbios parsing. If none of the sysinfo properties are found, we can +scan the root node for 'model' and 'compatible'. + +pre-patch dmidecode: + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: Unknown + Product Name: Unknown + Version: Unknown + Serial Number: Unknown + UUID: Not Settable + Wake-up Type: Reserved + SKU Number: Unknown + Family: Unknown + +Handle 0x0002, DMI type 2, 14 bytes +Base Board Information + Manufacturer: Unknown + Product Name: Unknown + Version: Unknown + Serial Number: Not Specified + Asset Tag: Unknown + Features: + Board is a hosting board + Location In Chassis: Not Specified + Chassis Handle: 0x0000 + Type: Motherboard + +Handle 0x0003, DMI type 3, 21 bytes +Chassis Information + Manufacturer: Unknown + Type: Desktop + Lock: Not Present + Version: Not Specified + Serial Number: Not Specified + Asset Tag: Not Specified + Boot-up State: Safe + Power Supply State: Safe + Thermal State: Safe + Security Status: None + OEM Information: 0x00000000 + Height: Unspecified + Number Of Power Cords: Unspecified + Contained Elements: 0 + + +post-pastch dmidecode: + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: socionext,developer-box + Product Name: Socionext Developer Box + Version: Unknown + Serial Number: Unknown + UUID: Not Settable + Wake-up Type: Reserved + SKU Number: Unknown + Family: Unknown + +Handle 0x0002, DMI type 2, 14 bytes +Base Board Information + Manufacturer: socionext,developer-box + Product Name: Socionext Developer Box + Version: Unknown + Serial Number: Not Specified + Asset Tag: Unknown + Features: + Board is a hosting board + Location In Chassis: Not Specified + Chassis Handle: 0x0000 + Type: Motherboard + +Handle 0x0003, DMI type 3, 21 bytes +Chassis Information + Manufacturer: socionext,developer-box + Type: Desktop + Lock: Not Present + Version: Not Specified + Serial Number: Not Specified + Asset Tag: Not Specified + Boot-up State: Safe + Power Supply State: Safe + Thermal State: Safe + Security Status: None + OEM Information: 0x00000000 + Height: Unspecified + Number Of Power Cords: Unspecified + Contained Elements: 0 + + +Signed-off-by: Ilias Apalodimas +--- + lib/smbios.c | 41 +++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 39 insertions(+), 2 deletions(-) + +diff --git a/lib/smbios.c b/lib/smbios.c +index fcc8686993ef..f2eb961f514b 100644 +--- a/lib/smbios.c ++++ b/lib/smbios.c +@@ -43,6 +43,20 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++/** ++ * struct sysifno_to_dt - Mapping of sysinfo strings to DT ++ * ++ * @sysinfo_str: sysinfo string ++ * @dt_str: DT string ++ */ ++static const struct { ++ const char *sysinfo_str; ++ const char *dt_str; ++} sysifno_to_dt[] = { ++ { .sysinfo_str = "product", .dt_str = "model" }, ++ { .sysinfo_str = "manufacturer", .dt_str = "compatible" }, ++}; ++ + /** + * struct smbios_ctx - context for writing SMBIOS tables + * +@@ -87,6 +101,18 @@ struct smbios_write_method { + const char *subnode_name; + }; + ++static const char *convert_sysinfo_to_dt(const char *sysinfo_str) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(sysifno_to_dt); i++) { ++ if (!strcmp(sysinfo_str, sysifno_to_dt[i].sysinfo_str)) ++ return sysifno_to_dt[i].dt_str; ++ } ++ ++ return NULL; ++} ++ + /** + * smbios_add_string() - add a string to the string area + * +@@ -148,9 +174,20 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, + return smbios_add_string(ctx, val); + } + if (IS_ENABLED(CONFIG_OF_CONTROL)) { +- const char *str; ++ const char *str = NULL; + +- str = ofnode_read_string(ctx->node, prop); ++ /* ++ * If the node is not valid fallback and try the entire DT ++ * so we can at least fill in maufacturer and board type ++ */ ++ if (!ofnode_valid(ctx->node)) { ++ const char *nprop = convert_sysinfo_to_dt(prop); ++ ++ if (nprop) ++ str = ofnode_read_string(ofnode_root(), nprop); ++ } else { ++ str = ofnode_read_string(ctx->node, prop); ++ } + return smbios_add_string(ctx, str); + } + diff --git a/sources b/sources index 49e8e65..b8bf2c3 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.07-rc6.tar.bz2) = 9772c69b48e2d76f7c70e148d54cbb857c728c6cf131eb27e6baceeb9212d63220b7cfb7c43b6ef9620430bd754822691b3149b923ae57e2bf9805d36845b2b2 +SHA512 (u-boot-2023.01.tar.bz2) = 417a28267eb7875820d08fafc7316f164663609378637539e71648b0b9b7d28796b6c381717f31b0ab6472805fefd32628ef7d1b2e7b9f3c51c8ad122993f679 diff --git a/uboot-tools.spec b/uboot-tools.spec index e987a2e..b2f73a8 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,12 +1,13 @@ -%global candidate rc6 +#global candidate rc4 +%if 0%{?rhel} +%bcond_with toolsonly +%else %bcond_without toolsonly - -# Set it to "opensbi" (stable) or opensbi-unstable (unstable, git) -%global opensbi opensbi-unstable +%endif Name: uboot-tools -Version: 2022.07 -Release: 0.6%{?candidate:.%{candidate}}.0.riscv64%{?dist} +Version: 2023.01 +Release: 2%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -14,26 +15,21 @@ URL: http://www.denx.de/wiki/U-Boot ExcludeArch: s390x Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: aarch64-boards -Source2: riscv64-boards # Fedoraisms patches # Needed to find DT on boot partition that's not the first partition Patch1: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch +Patch2: smbios-Simplify-reporting-of-unknown-values.patch # Board fixes and enablement # RPi - uses RPI firmware device tree for HAT support Patch3: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch4: rpi-fallback-to-max-clock-for-mmc.patch Patch5: rpi-bcm2835_sdhost-firmware-managed-clock.patch +Patch6: rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch # Rockchips improvements Patch7: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch -# RISC-V (riscv64) patches -Patch43: 0004-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch -Patch44: 0005-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch -Patch45: 0006-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch -Patch46: 0001-Enable-sbi-command-and-SBI-sysreset.patch - BuildRequires: bc BuildRequires: bison BuildRequires: dtc @@ -48,13 +44,12 @@ BuildRequires: perl-interpreter BuildRequires: python3-devel BuildRequires: python3-setuptools BuildRequires: python3-libfdt -BuildRequires: SDL-devel +BuildRequires: SDL2-devel BuildRequires: swig +%if %{with toolsonly} %ifarch aarch64 BuildRequires: arm-trusted-firmware-armv8 %endif -%ifarch riscv64 -BuildRequires: %{opensbi} %endif Requires: dtc @@ -73,20 +68,10 @@ U-Boot firmware binaries for aarch64 boards %endif %endif -%ifarch riscv64 -%package -n uboot-images-riscv64 -Summary: u-boot bootloader images for riscv64 boards -Requires: uboot-tools -BuildArch: noarch - -%description -n uboot-images-riscv64 -u-boot bootloader binaries for riscv64 boards -%endif - %prep %autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} -cp %SOURCE1 %SOURCE2 . +cp %SOURCE1 . %build mkdir builds @@ -95,14 +80,7 @@ mkdir builds %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-all O=builds/ %if %{with toolsonly} -# U-Boot device firmwares don't currently support LTO -%define _lto_cflags %{nil} - -%ifarch riscv64 -export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin -%endif - -%ifarch aarch64 riscv64 +%ifarch aarch64 for board in $(cat %{_arch}-boards) do echo "Building board: $board" @@ -131,8 +109,8 @@ do fi # End ATF - make $(echo $board)_defconfig O=builds/$(echo $board)/ - %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" O=builds/$(echo $board)/ + BINMAN_ALLOW_MISSING=1 make $(echo $board)_defconfig O=builds/$(echo $board)/ + BINMAN_ALLOW_MISSING=1 %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" O=builds/$(echo $board)/ # build spi images for rockchip boards with SPI flash rkspi=(rock64-rk3328) @@ -167,6 +145,9 @@ do fi done done + +# For Apple M1 we also need the nodtb variant +install -p -m 0644 builds/apple_m1/u-boot-nodtb.bin %{buildroot}%{_datadir}/uboot/apple_m1/u-boot-nodtb.bin %endif # Bit of a hack to remove binaries we don't use as they're large @@ -198,20 +179,7 @@ done %endif %endif -%ifarch riscv64 -for board in $(cat %{_arch}-boards) -do -mkdir -p $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/ - for file in u-boot.bin u-boot.dtb u-boot.img u-boot-nodtb.bin u-boot-dtb.bin u-boot.itb u-boot-dtb.img u-boot.its spl/u-boot-spl.bin spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb spl/u-boot-spl-dtb.bin - do - if [ -f builds/$(echo $board)/$(echo $file) ]; then - install -p -m 0644 builds/$(echo $board)/$(echo $file) $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/ - fi - done -done -%endif - -for tool in bmp_logo dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc img2srec mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder ubsha1 xway-swap-bytes kwboot +for tool in bmp_logo dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc ifwitool img2srec kwboot mkeficapsule mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder ubsha1 xway-swap-bytes do install -p -m 0755 builds/tools/$tool %{buildroot}%{_bindir} done @@ -242,14 +210,54 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %endif %endif -%ifarch riscv64 -%files -n uboot-images-riscv64 -%{_datadir}/uboot/* -%endif - %changelog -* Mon Jul 04 2022 David Abdurachmanov - 2022.07-0.6.rc6.0.riscv64 -- Enable riscv64 +* Sat Jan 21 2023 Fedora Release Engineering - 2023.01-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_38_Mass_Rebuild + +* Wed Jan 18 2023 Peter Robinson - 2023.01-1 +- Update to 2023.01 GA + +* Sat Dec 31 2022 Peter Robinson - 2023.01-0.4.rc4 +- Update PinePhone Pro to latest rev + +* Tue Dec 20 2022 Peter Robinson - 2023.01-0.3.rc4 +- Update to 2023.01 RC4 + +* Mon Dec 05 2022 Peter Robinson - 2023.01-0.2.rc3 +- Update to 2023.01 RC3 + +* Thu Nov 24 2022 Peter Robinson - 2023.01-0.1.rc2 +- Update to U-Boot 2023.01 RC2 +- Update Pinephone Pro patches + +* Mon Oct 10 2022 Peter Robinson - 2022.10-1 +- Update to 2022.10 GA + +* Tue Sep 06 2022 Peter Robinson - 2022.10-0.6.rc4 +- Update SMBIOS patch + +* Tue Sep 06 2022 Peter Robinson - 2022.10-0.5.rc4 +- Update to 2022.10 RC4 +- Fix for booting Rockchip devices from NVME + +* Tue Aug 23 2022 Peter Robinson - 2022.10-0.4.rc3 +- Update to 2022.10 RC3 + +* Mon Aug 22 2022 Davide Cavalca - 2022.10-0.3.rc1 +- Install nodtb variant for Apple M1 (rhbz#2068958) + +* Tue Aug 16 2022 Peter Robinson - 2022.10-0.2.rc1 +- Fix for DT property propogation via firmware + +* Thu Jul 28 2022 Peter Robinson - 2022.10-0.1.rc1 +- Update to 2022.10 RC1 +- Enable LTO for firmware builds + +* Sat Jul 23 2022 Fedora Release Engineering - 2022.07-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_37_Mass_Rebuild + +* Sun Jul 17 2022 Peter Robinson - 2022.07-1 +- Update to 2022.07 GA * Mon Jul 04 2022 Peter Robinson - 2022.07-0.6.rc6 - Update to 2022.07 RC6 diff --git a/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch index c28fdb0..5954848 100644 --- a/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch +++ b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch @@ -1,6 +1,6 @@ -From fd3434c754b3b8dddb345352a2434b6b8445343a Mon Sep 17 00:00:00 2001 +From 4306c538d4a00dd1aa46c55c3c4005c2b0bf7cd5 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Sun, 18 Apr 2021 14:05:45 +0100 +Date: Thu, 24 Nov 2022 12:57:55 +0000 Subject: [PATCH] distro: load FDT from any partition on boot device In the EFI_LOADER boot path, we were only checking the FAT partition @@ -22,14 +22,14 @@ knows) and SoC/board specific ${fdtfile} (which grub does not know). Signed-off-by: Rob Clark Signed-off-by: Peter Robinson --- - include/config_distro_bootcmd.h | 35 ++++++++++++++++++++++----------- - 1 file changed, 23 insertions(+), 12 deletions(-) + include/config_distro_bootcmd.h | 37 +++++++++++++++++++++------------ + 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h -index 2627c2a6a5..eadd1080b3 100644 +index fcb319a20ae..e71004fad9c 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h -@@ -148,26 +148,37 @@ +@@ -155,28 +155,39 @@ "fi\0" \ \ "load_efi_dtb=" \ @@ -44,11 +44,13 @@ index 2627c2a6a5..eadd1080b3 100644 + "scan_dev_for_dtb=" \ "setenv efi_fdtfile ${fdtfile}; " \ BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + BOOTENV_RUN_EXTENSION_INIT \ - "for prefix in ${efi_dtb_prefixes}; do " \ - "if test -e ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${prefix}${efi_fdtfile}; then " \ - "run load_efi_dtb; " \ +- BOOTENV_RUN_EXTENSION_APPLY \ - "fi;" \ - "done;" \ - "run boot_efi_bootmgr;" \ @@ -65,6 +67,7 @@ index 2627c2a6a5..eadd1080b3 100644 + "${devnum}:${dtb_devp} " \ + "${prefix}${efi_fdtfile};"\ + "run load_efi_dtb; " \ ++ BOOTENV_RUN_EXTENSION_APPLY \ + "fi;" \ + "done; " \ + "done; " \ @@ -80,5 +83,5 @@ index 2627c2a6a5..eadd1080b3 100644 "fi; " \ "setenv efi_fdtfile\0" -- -2.31.1 +2.38.1