Misc. RISCV fixes
- Align boot image header format - Set preboot for QEMU to copy DTB in expected location - Set default bootargs for the boards Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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To: u-boot@lists.denx.de
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Date: Tue, 8 Oct 2019 18:14:02 -0700
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Cc: David Abdurachmanov <david.abdurachmanov@sifive.com>
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Subject: [U-Boot] [PATCH] RISC-V: Align boot image header with Linux.
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The release linux boot image header in v5.3 is different from the
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one present in U-boot. Align the header with the new version. The
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changes in Linux are backward compatible. Previous u-boot releases
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with older header will continue to work as well. As v5.3 kernel is
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the first one to support image header, there is no compatibility
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issue between new U-boot (with this patch) and older kernel.
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Signed-off-by: Atish Patra <atish.patra@wdc.com>
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---
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arch/riscv/lib/image.c | 11 ++++++-----
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1 file changed, 6 insertions(+), 5 deletions(-)
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diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
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index d063beb7dfbe..41fca5939020 100644
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--- a/arch/riscv/lib/image.c
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+++ b/arch/riscv/lib/image.c
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@@ -14,20 +14,21 @@
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DECLARE_GLOBAL_DATA_PTR;
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-/* ASCII version of "RISCV" defined in Linux kernel */
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-#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
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+/* ASCII version of "RSC\0x5" defined in Linux kernel */
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+#define LINUX_RISCV_IMAGE_MAGIC 0x05435352
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struct linux_image_h {
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uint32_t code0; /* Executable code */
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uint32_t code1; /* Executable code */
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uint64_t text_offset; /* Image load offset */
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uint64_t image_size; /* Effective Image size */
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- uint64_t res1; /* reserved */
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+ uint64_t flags; /* kernel flags(little endian) */
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+ uint32_t version; /* version of the header */
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+ uint32_t res1; /* reserved */
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uint64_t res2; /* reserved */
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uint64_t res3; /* reserved */
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- uint64_t magic; /* Magic number */
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+ uint32_t magic; /* Magic number */
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uint32_t res4; /* reserved */
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- uint32_t res5; /* reserved */
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};
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int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
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@ -0,0 +1,22 @@
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diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
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index 1c7a2d15..5548a649 100644
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--- a/configs/qemu-riscv64_smode_defconfig
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+++ b/configs/qemu-riscv64_smode_defconfig
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@@ -10,3 +10,7 @@ CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_CMD_BOOTEFI_SELFTEST=y
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# CONFIG_CMD_MII is not set
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CONFIG_OF_PRIOR_STAGE=y
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+CONFIG_USE_BOOTARGS=y
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+CONFIG_BOOTARGS="console=ttyS0 earlycon"
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+CONFIG_USE_PREBOOT=y
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+CONFIG_PREBOOT="cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x10000;"
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diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
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index 48865e5f..8a4bc0b7 100644
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--- a/configs/sifive_fu540_defconfig
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+++ b/configs/sifive_fu540_defconfig
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@@ -9,3 +9,5 @@ CONFIG_MISC_INIT_R=y
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_OF_PRIOR_STAGE=y
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+CONFIG_USE_BOOTARGS=y
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+CONFIG_BOOTARGS="console=ttySIF0 earlycon"
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@ -39,6 +39,17 @@ Patch11: Revert-ARM-tegra-reserve-unmapped-RAM-so-EFI-doesn-t-use-it.patch
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# the location where OpenSBI will place embedded DTB.
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Patch20: riscv64-set-fdt_addr.patch
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# Set bootargs (console and earlycon)
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# Fix fdt by use cp.l on QEMU (fixed in 5.4, corruption of DTB happens in
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# kernel)
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# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v5.4-rc2&id=922b0375fc93fb1a20c5617e37c389c26bbccb70
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# https://patchwork.kernel.org/patch/11165207/
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Patch21: riscv-bootargs-preboot.patch
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# https://patchwork.ozlabs.org/patch/1173557/
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# https://lists.denx.de/pipermail/u-boot/2019-October/385906.html
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Patch22: riscv-align-boot-image-header.patch
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BuildRequires: bc
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BuildRequires: dtc
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BuildRequires: make
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