From bed2a9c0b08f95007184a8091325c78f746f0744 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 14 May 2016 09:52:43 +0100 Subject: [PATCH] Enhanced PINE64 support, Add USB storage support to CHIP --- ...common.h-Fix-U-Boot-location-on-eMMC.patch | 33 + ...m_matches-Add-missing-memory-barrier.patch | 52 + ...map3-Use-raw-SPL-by-default-for-mmc1.patch | 35 + ...er-instructions-into-separate-header.patch | 130 ++ ...unxi-Reserve-ATF-memory-space-on-A64.patch | 43 + ...sunxi-reserve-space-for-boot0-header.patch | 42 + ...-sunxi-adjust-default-load-addresses.patch | 59 + ...ot-5-6-arm64-Pine64-update-FDT-files.patch | 1703 +++++++++++++++++ U-Boot-6-6-Pine64-rename-defconfig.patch | 80 + armv8-boards | 2 +- sunxi-Enable-USB-host-in-CHIP-defconfig.patch | 28 + uboot-tools.spec | 22 +- 12 files changed, 2225 insertions(+), 4 deletions(-) create mode 100644 0001-Revert-ti_armv7_common.h-Fix-U-Boot-location-on-eMMC.patch create mode 100644 0001-sunxi-mctl_mem_matches-Add-missing-memory-barrier.patch create mode 100644 0002-Revert-omap3-Use-raw-SPL-by-default-for-mmc1.patch create mode 100644 U-Boot-1-6-arm-arm64-Move-barrier-instructions-into-separate-header.patch create mode 100644 U-Boot-2-6-Revert-sunxi-Reserve-ATF-memory-space-on-A64.patch create mode 100644 U-Boot-3-6-arm64-sunxi-reserve-space-for-boot0-header.patch create mode 100644 U-Boot-4-6-arm64-sunxi-adjust-default-load-addresses.patch create mode 100644 U-Boot-5-6-arm64-Pine64-update-FDT-files.patch create mode 100644 U-Boot-6-6-Pine64-rename-defconfig.patch create mode 100644 sunxi-Enable-USB-host-in-CHIP-defconfig.patch diff --git a/0001-Revert-ti_armv7_common.h-Fix-U-Boot-location-on-eMMC.patch b/0001-Revert-ti_armv7_common.h-Fix-U-Boot-location-on-eMMC.patch new file mode 100644 index 0000000..100fb13 --- /dev/null +++ b/0001-Revert-ti_armv7_common.h-Fix-U-Boot-location-on-eMMC.patch @@ -0,0 +1,33 @@ +From f188357a155a5b7d6906f081c6e7265f6d6086ec Mon Sep 17 00:00:00 2001 +From: Tom Rini +Date: Mon, 2 May 2016 08:49:53 -0400 +Subject: [PATCH 01/53] Revert "ti_armv7_common.h: Fix U-Boot location on eMMC" + +We cannot change the long standing hard-coded offset for raw boot mode +for everyone to accommodate how Android expects things to be done here. + +This reverts commit ef5ebe951bec72631cdbc7cef9079e6c684e5d0b. + +Signed-off-by: Tom Rini +--- + include/configs/ti_armv7_common.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h +index 2c7d542..7db0881 100644 +--- a/include/configs/ti_armv7_common.h ++++ b/include/configs/ti_armv7_common.h +@@ -219,8 +219,8 @@ + #endif + + /* RAW SD card / eMMC locations. */ +-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* address 0x40000 */ +-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */ ++#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ ++#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + + /* FAT sd card locations. */ + #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +-- +2.7.4 + diff --git a/0001-sunxi-mctl_mem_matches-Add-missing-memory-barrier.patch b/0001-sunxi-mctl_mem_matches-Add-missing-memory-barrier.patch new file mode 100644 index 0000000..519d767 --- /dev/null +++ b/0001-sunxi-mctl_mem_matches-Add-missing-memory-barrier.patch @@ -0,0 +1,52 @@ +From bfb33f0bc45b9ee92ed2f85107cf20b9bfdf9f8a Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Thu, 14 Apr 2016 18:53:32 +0200 +Subject: [PATCH 01/61] sunxi: mctl_mem_matches: Add missing memory barrier + +We are running with the caches disabled when mctl_mem_matches gets called, +but the cpu's write buffer is still there and can still get in the way, +add a memory barrier to fix this. + +This avoids mctl_mem_matches always returning false in some cases, which +was resulting in: + +U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26) +DRAM: 1024 MiB + +U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology + +CPU: Allwinner A23 (SUN8I) +DRAM: 512 MiB + +Where 512 MiB is the right amount, but the DRAM controller would be +initialized for 1024 MiB. + +Signed-off-by: Hans de Goede +Acked-by: Ian Campbell +--- + arch/arm/mach-sunxi/dram_helpers.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c +index 50318d2..e0c823a 100644 +--- a/arch/arm/mach-sunxi/dram_helpers.c ++++ b/arch/arm/mach-sunxi/dram_helpers.c +@@ -7,6 +7,7 @@ + */ + + #include ++#include + #include + #include + +@@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset) + /* Try to write different values to RAM at two addresses */ + writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); ++ DSB; + /* Check if the same value is actually observed when reading back */ + return readl(CONFIG_SYS_SDRAM_BASE) == + readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); +-- +2.7.4 + diff --git a/0002-Revert-omap3-Use-raw-SPL-by-default-for-mmc1.patch b/0002-Revert-omap3-Use-raw-SPL-by-default-for-mmc1.patch new file mode 100644 index 0000000..bb5c267 --- /dev/null +++ b/0002-Revert-omap3-Use-raw-SPL-by-default-for-mmc1.patch @@ -0,0 +1,35 @@ +From 821c89d38cb6832f162b5b20ec86f07610407c25 Mon Sep 17 00:00:00 2001 +From: Tom Rini +Date: Mon, 2 May 2016 10:52:51 -0400 +Subject: [PATCH 02/53] Revert "omap3: Use raw SPL by default for mmc1" + +Unfortunately with this change we now are unable to do FS mode boots +from MMC1 as with the way the code works today we will always load and +assume that the hard-coded raw location contains U-Boot. Further, we +cannot fix this by just changing other logic to try FS-then-RAW as it +would also make us have to ignore what order the ROM is telling us to +try. + +This reverts commit 22d90d560a2b01c47f180e196e6c6485eb8e65db. + +Signed-off-by: Tom Rini +--- + arch/arm/cpu/armv7/omap-common/boot-common.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c +index ed9ba7b..0456263 100644 +--- a/arch/arm/cpu/armv7/omap-common/boot-common.c ++++ b/arch/arm/cpu/armv7/omap-common/boot-common.c +@@ -111,6 +111,8 @@ void save_omap_boot_params(void) + (boot_device <= MMC_BOOT_DEVICES_END)) { + switch (boot_device) { + case BOOT_DEVICE_MMC1: ++ boot_mode = MMCSD_MODE_FS; ++ break; + case BOOT_DEVICE_MMC2: + boot_mode = MMCSD_MODE_RAW; + break; +-- +2.7.4 + diff --git a/U-Boot-1-6-arm-arm64-Move-barrier-instructions-into-separate-header.patch b/U-Boot-1-6-arm-arm64-Move-barrier-instructions-into-separate-header.patch new file mode 100644 index 0000000..ed0b0d7 --- /dev/null +++ b/U-Boot-1-6-arm-arm64-Move-barrier-instructions-into-separate-header.patch @@ -0,0 +1,130 @@ +From patchwork Wed May 4 21:15:29 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, + 1/6] arm/arm64: Move barrier instructions into separate header +From: Andre Przywara +X-Patchwork-Id: 618677 +Message-Id: <1462396534-32390-2-git-send-email-andre.przywara@arm.com> +To: Hans de Goede , + Ian Campbell +Cc: u-boot@lists.denx.de, Andre Przywara , + Valentine Barshak , + Aneesh V +Date: Wed, 4 May 2016 22:15:29 +0100 + +Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory +barrier") broke compilation for the Pine64, as dram_helper.c now +includes , which does not compile on arm64. + +Fix this by moving all barrier instructions into a separate header +file, which can easily be shared between arm and arm64. +Also extend the inline assembly to take the "sy" argument, which is +optional for ARMv7, but mandatory for v8. + +This fixes compilation for 64-bit sunxi boards (Pine64). + +Signed-off-by: Andre Przywara +--- + arch/arm/include/asm/armv7.h | 21 +----------------- + arch/arm/include/asm/barriers.h | 44 ++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-sunxi/dram_helpers.c | 2 +- + 3 files changed, 46 insertions(+), 21 deletions(-) + create mode 100644 arch/arm/include/asm/barriers.h + +diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h +index 30e7939..423fc70 100644 +--- a/arch/arm/include/asm/armv7.h ++++ b/arch/arm/include/asm/armv7.h +@@ -59,26 +59,7 @@ + #ifndef __ASSEMBLY__ + #include + #include +- +-/* +- * CP15 Barrier instructions +- * Please note that we have separate barrier instructions in ARMv7 +- * However, we use the CP15 based instructtions because we use +- * -march=armv5 in U-Boot +- */ +-#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) +-#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) +-#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +- +-#ifdef __ARM_ARCH_7A__ +-#define ISB asm volatile ("isb" : : : "memory") +-#define DSB asm volatile ("dsb" : : : "memory") +-#define DMB asm volatile ("dmb" : : : "memory") +-#else +-#define ISB CP15ISB +-#define DSB CP15DSB +-#define DMB CP15DMB +-#endif ++#include + + /* + * Workaround for ARM errata # 798870 +diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h +new file mode 100644 +index 0000000..37870f9 +--- /dev/null ++++ b/arch/arm/include/asm/barriers.h +@@ -0,0 +1,44 @@ ++/* ++ * Copyright (C) 2016 ARM Ltd. ++ * ++ * ARM and ARM64 barrier instructions ++ * split from armv7.h to allow sharing between ARM and ARM64 ++ * ++ * Original copyright in armv7.h was: ++ * (C) Copyright 2010 Texas Instruments, Aneesh V ++ * ++ * Much of the original barrier code was contributed by: ++ * Valentine Barshak ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#ifndef __BARRIERS_H__ ++#define __BARRIERS_H__ ++ ++#ifndef __ASSEMBLY__ ++ ++#ifndef CONFIG_ARM64 ++/* ++ * CP15 Barrier instructions ++ * Please note that we have separate barrier instructions in ARMv7 ++ * However, we use the CP15 based instructtions because we use ++ * -march=armv5 in U-Boot ++ */ ++#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) ++#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) ++#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) ++ ++#endif /* !CONFIG_ARM64 */ ++ ++#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64) ++#define ISB asm volatile ("isb sy" : : : "memory") ++#define DSB asm volatile ("dsb sy" : : : "memory") ++#define DMB asm volatile ("dmb sy" : : : "memory") ++#else ++#define ISB CP15ISB ++#define DSB CP15DSB ++#define DMB CP15DMB ++#endif ++ ++#endif /* __ASSEMBLY__ */ ++#endif /* __BARRIERS_H__ */ +diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c +index e0c823a..20b430f 100644 +--- a/arch/arm/mach-sunxi/dram_helpers.c ++++ b/arch/arm/mach-sunxi/dram_helpers.c +@@ -7,7 +7,7 @@ + */ + + #include +-#include ++#include + #include + #include + diff --git a/U-Boot-2-6-Revert-sunxi-Reserve-ATF-memory-space-on-A64.patch b/U-Boot-2-6-Revert-sunxi-Reserve-ATF-memory-space-on-A64.patch new file mode 100644 index 0000000..e73e163 --- /dev/null +++ b/U-Boot-2-6-Revert-sunxi-Reserve-ATF-memory-space-on-A64.patch @@ -0,0 +1,43 @@ +From patchwork Wed May 4 21:15:30 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,2/6] Revert "sunxi: Reserve ATF memory space on A64" +From: Andre Przywara +X-Patchwork-Id: 618676 +Message-Id: <1462396534-32390-3-git-send-email-andre.przywara@arm.com> +To: Hans de Goede , + Ian Campbell +Cc: Andre Przywara , u-boot@lists.denx.de +Date: Wed, 4 May 2016 22:15:30 +0100 + +The ARM Trusted Firmware (ATF) code now lives in SRAM on the Pine64/A64, +so we can claim the whole of DRAM for OS use. + +This reverts commit 3ffe39ed2b66af71c7271d0cef2a248b5bf7dfdb. + +Signed-off-by: Andre Przywara +--- + board/sunxi/board.c | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 3cf3614..ccf4129 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -133,15 +133,6 @@ int dram_init(void) + return 0; + } + +-#ifdef CONFIG_MACH_SUN50I +-void dram_init_banksize(void) +-{ +- /* We need to reserve the first 16MB of RAM for ATF */ +- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); +- gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024); +-} +-#endif +- + #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) + static void nand_pinmux_setup(void) + { diff --git a/U-Boot-3-6-arm64-sunxi-reserve-space-for-boot0-header.patch b/U-Boot-3-6-arm64-sunxi-reserve-space-for-boot0-header.patch new file mode 100644 index 0000000..4142454 --- /dev/null +++ b/U-Boot-3-6-arm64-sunxi-reserve-space-for-boot0-header.patch @@ -0,0 +1,42 @@ +From patchwork Wed May 4 21:15:31 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,3/6] arm64: sunxi: reserve space for boot0 header +From: Andre Przywara +X-Patchwork-Id: 618678 +Message-Id: <1462396534-32390-4-git-send-email-andre.przywara@arm.com> +To: Hans de Goede , + Ian Campbell +Cc: Andre Przywara , u-boot@lists.denx.de +Date: Wed, 4 May 2016 22:15:31 +0100 + +The Allwinner provided boot0 boot loader requires a header before the +U-Boot binary to both check its validity and to find other blobs to +load. There is a tool called boot0img which fills the header +appropriately. +Reserve some space at the beginning of the binary to later hold the +header if needed. +Please note that the header is jumped over already by U-Boot anyway, +so filling the header is optional and can be skipped if for instance +boot0 is not used. + +Signed-off-by: Andre Przywara +--- + arch/arm/cpu/armv8/start.S | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S +index deb44a8..b4c4867 100644 +--- a/arch/arm/cpu/armv8/start.S ++++ b/arch/arm/cpu/armv8/start.S +@@ -21,6 +21,9 @@ + _start: + b reset + ++#ifdef CONFIG_ARCH_SUNXI ++ .space 0x5fc /* can be filled with a boot0 header if needed */ ++#endif + .align 3 + + .globl _TEXT_BASE diff --git a/U-Boot-4-6-arm64-sunxi-adjust-default-load-addresses.patch b/U-Boot-4-6-arm64-sunxi-adjust-default-load-addresses.patch new file mode 100644 index 0000000..82ff445 --- /dev/null +++ b/U-Boot-4-6-arm64-sunxi-adjust-default-load-addresses.patch @@ -0,0 +1,59 @@ +From patchwork Wed May 4 21:15:32 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,4/6] arm64: sunxi: adjust default load addresses +From: Andre Przywara +X-Patchwork-Id: 618679 +Message-Id: <1462396534-32390-5-git-send-email-andre.przywara@arm.com> +To: Hans de Goede , + Ian Campbell +Cc: Andre Przywara , u-boot@lists.denx.de +Date: Wed, 4 May 2016 22:15:32 +0100 + +As arm64 has slightly different expectations about load addresses, lets +use a different set of default addresses for things like the kernel. +As arm64 kernels don't come with a decompressor right now, reserve some +more space for really big uncompressed kernels. + +Signed-off-by: Andre Przywara +--- + include/configs/sunxi-common.h | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h +index 2406115..16f1a2c 100644 +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -390,6 +390,23 @@ extern int soft_i2c_gpio_scl; + #define CONFIG_PRE_CONSOLE_BUFFER + #define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */ + ++#ifdef CONFIG_ARM64 ++/* ++ * Boards seem to come with at least 512MB of DRAM. ++ * The kernel should go at 512K, which is the default text offset (that will ++ * be adjusted at runtime if needed). ++ * There is no compression for arm64 kernels (yet), so leave some space ++ * for really big kernels, say 256MB for now. ++ * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. ++ * Align the initrd to a 2MB page. ++ */ ++#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) ++#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) ++#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) ++#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) ++#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) ++ ++#else + /* + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. + * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, +@@ -401,6 +418,7 @@ extern int soft_i2c_gpio_scl; + #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) + #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) + #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) ++#endif + + #define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0xa000000\0" \ diff --git a/U-Boot-5-6-arm64-Pine64-update-FDT-files.patch b/U-Boot-5-6-arm64-Pine64-update-FDT-files.patch new file mode 100644 index 0000000..a30dfb5 --- /dev/null +++ b/U-Boot-5-6-arm64-Pine64-update-FDT-files.patch @@ -0,0 +1,1703 @@ +From patchwork Wed May 4 21:15:33 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,5/6] arm64: Pine64: update FDT files +From: Andre Przywara +X-Patchwork-Id: 618680 +Message-Id: <1462396534-32390-6-git-send-email-andre.przywara@arm.com> +To: Hans de Goede , + Ian Campbell +Cc: Andre Przywara , u-boot@lists.denx.de +Date: Wed, 4 May 2016 22:15:33 +0100 + +The originally committed .dts files for the Pine64 were from an early +proof-of-concept version and should have never been committed upstream. +Replace them with much more mature versions, which also use a different +naming scheme. +Please note that at this point there is at least one binding which has +not been agreed upon, so this is subject to change. + +Signed-off-by: Andre Przywara +--- + arch/arm/dts/Makefile | 3 +- + arch/arm/dts/a64.dtsi | 564 -------------------------- + arch/arm/dts/pine64.dts | 62 --- + arch/arm/dts/pine64_common.dtsi | 76 ---- + arch/arm/dts/pine64_plus.dts | 63 --- + arch/arm/dts/sun50i-a64-pine64-common.dtsi | 80 ++++ + arch/arm/dts/sun50i-a64-pine64-plus.dts | 59 +++ + arch/arm/dts/sun50i-a64-pine64.dts | 58 +++ + arch/arm/dts/sun50i-a64.dtsi | 624 +++++++++++++++++++++++++++++ + configs/pine64_plus_defconfig | 2 +- + 10 files changed, 824 insertions(+), 767 deletions(-) + delete mode 100644 arch/arm/dts/a64.dtsi + delete mode 100644 arch/arm/dts/pine64.dts + delete mode 100644 arch/arm/dts/pine64_common.dtsi + delete mode 100644 arch/arm/dts/pine64_plus.dts + create mode 100644 arch/arm/dts/sun50i-a64-pine64-common.dtsi + create mode 100644 arch/arm/dts/sun50i-a64-pine64-plus.dts + create mode 100644 arch/arm/dts/sun50i-a64-pine64.dts + create mode 100644 arch/arm/dts/sun50i-a64.dtsi + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index d1f8e22..bd68698 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -218,7 +218,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-plus.dtb + dtb-$(CONFIG_MACH_SUN50I) += \ +- pine64_plus.dtb ++ sun50i-a64-pine64-plus.dtb \ ++ sun50i-a64-pine64.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb +diff --git a/arch/arm/dts/a64.dtsi b/arch/arm/dts/a64.dtsi +deleted file mode 100644 +index f3ad000..0000000 +--- a/arch/arm/dts/a64.dtsi ++++ /dev/null +@@ -1,564 +0,0 @@ +-/* +- * Copyright (C) 2016 ARM Ltd. +- * based on the Allwinner H3 dtsi: +- * Copyright (C) 2015 Jens Kuske +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-/ { +- compatible = "allwinner,a64"; +- interrupt-parent = <&gic>; +- #address-cells = <1>; +- #size-cells = <1>; +- +- aliases { +- serial0 = &uart0; +- serial1 = &uart1; +- serial2 = &uart2; +- serial3 = &uart3; +- serial4 = &uart4; +- }; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- cpu@0 { +- compatible = "arm,cortex-a53", "arm,armv8"; +- device_type = "cpu"; +- reg = <0>; +- enable-method = "psci"; +- }; +- +- cpu@1 { +- compatible = "arm,cortex-a53", "arm,armv8"; +- device_type = "cpu"; +- reg = <1>; +- enable-method = "psci"; +- }; +- +- cpu@2 { +- compatible = "arm,cortex-a53", "arm,armv8"; +- device_type = "cpu"; +- reg = <2>; +- enable-method = "psci"; +- }; +- +- cpu@3 { +- compatible = "arm,cortex-a53", "arm,armv8"; +- device_type = "cpu"; +- reg = <3>; +- enable-method = "psci"; +- }; +- }; +- +- psci { +- compatible = "arm,psci-0.2", "arm,psci"; +- method = "smc"; +- cpu_suspend = <0xc4000001>; +- cpu_off = <0x84000002>; +- cpu_on = <0xc4000003>; +- }; +- +- memory { +- device_type = "memory"; +- reg = <0x40000000 0>; +- }; +- +- timer { +- compatible = "arm,armv8-timer"; +- interrupts = , +- , +- , +- ; +- }; +- +- clocks { +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- osc24M: osc24M_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <24000000>; +- clock-output-names = "osc24M"; +- }; +- +- osc32k: osc32k_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <32768>; +- clock-output-names = "osc32k"; +- }; +- +- pll1: clk@01c20000 { +- #clock-cells = <0>; +- compatible = "allwinner,sun8i-a23-pll1-clk"; +- reg = <0x01c20000 0x4>; +- clocks = <&osc24M>; +- clock-output-names = "pll1"; +- }; +- +- pll6: clk@01c20028 { +- #clock-cells = <1>; +- compatible = "allwinner,sun6i-a31-pll6-clk"; +- reg = <0x01c20028 0x4>; +- clocks = <&osc24M>; +- clock-output-names = "pll6", "pll6x2"; +- }; +- +- pll6d2: pll6d2_clk { +- #clock-cells = <0>; +- compatible = "fixed-factor-clock"; +- clock-div = <2>; +- clock-mult = <1>; +- clocks = <&pll6 0>; +- clock-output-names = "pll6d2"; +- }; +- +- /* dummy clock until pll6 can be reused */ +- pll8: pll8_clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <1>; +- clock-output-names = "pll8"; +- }; +- +- cpu: cpu_clk@01c20050 { +- #clock-cells = <0>; +- compatible = "allwinner,sun4i-a10-cpu-clk"; +- reg = <0x01c20050 0x4>; +- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; +- clock-output-names = "cpu"; +- }; +- +- axi: axi_clk@01c20050 { +- #clock-cells = <0>; +- compatible = "allwinner,sun4i-a10-axi-clk"; +- reg = <0x01c20050 0x4>; +- clocks = <&cpu>; +- clock-output-names = "axi"; +- }; +- +- ahb1: ahb1_clk@01c20054 { +- #clock-cells = <0>; +- compatible = "allwinner,sun6i-a31-ahb1-clk"; +- reg = <0x01c20054 0x4>; +- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; +- clock-output-names = "ahb1"; +- }; +- +- ahb2: ahb2_clk@01c2005c { +- #clock-cells = <0>; +- compatible = "allwinner,sun8i-h3-ahb2-clk"; +- reg = <0x01c2005c 0x4>; +- clocks = <&ahb1>, <&pll6d2>; +- clock-output-names = "ahb2"; +- }; +- +- apb1: apb1_clk@01c20054 { +- #clock-cells = <0>; +- compatible = "allwinner,sun4i-a10-apb0-clk"; +- reg = <0x01c20054 0x4>; +- clocks = <&ahb1>; +- clock-output-names = "apb1"; +- }; +- +- apb2: apb2_clk@01c20058 { +- #clock-cells = <0>; +- compatible = "allwinner,sun4i-a10-apb1-clk"; +- reg = <0x01c20058 0x4>; +- clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>; +- clock-output-names = "apb2"; +- }; +- +- bus_gates: clk@01c20060 { +- #clock-cells = <1>; +- compatible = "allwinner,a64-bus-gates-clk", +- "allwinner,sun8i-h3-bus-gates-clk"; +- reg = <0x01c20060 0x14>; +- clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; +- clock-names = "ahb1", "ahb2", "apb1", "apb2"; +- clock-indices = <1>, +- <5>, <6>, <8>, +- <9>, <10>, <13>, +- <14>, <17>, <18>, +- <19>, <20>, +- <21>, <23>, +- <24>, <25>, +- <28>, <29>, +- <32>, <35>, +- <36>, <37>, +- <40>, <43>, +- <44>, <52>, <53>, +- <54>, <64>, +- <65>, <69>, <72>, +- <76>, <77>, <78>, +- <96>, <97>, <98>, +- <101>, +- <112>, <113>, +- <114>, <115>, +- <116>, <135>; +- clock-output-names = "bus_mipidsi", +- "bus_ce", "bus_dma", "bus_mmc0", +- "bus_mmc1", "bus_mmc2", "bus_nand", +- "bus_sdram", "bus_gmac", "bus_ts", +- "bus_hstimer", "bus_spi0", +- "bus_spi1", "bus_otg", +- "bus_otg_ehci0", "bus_ehci0", +- "bus_otg_ohci0", "bus_ohci0", +- "bus_ve", "bus_lcd0", +- "bus_lcd1", "bus_deint", +- "bus_csi", "bus_hdmi", +- "bus_de", "bus_gpu", "bus_msgbox", +- "bus_spinlock", "bus_codec", +- "bus_spdif", "bus_pio", "bus_ths", +- "bus_i2s0", "bus_i2s1", "bus_i2s2", +- "bus_i2c0", "bus_i2c1", "bus_i2c2", +- "bus_scr", +- "bus_uart0", "bus_uart1", +- "bus_uart2", "bus_uart3", +- "bus_uart4", "bus_dbg"; +- }; +- +- mmc0_clk: clk@01c20088 { +- #clock-cells = <1>; +- compatible = "allwinner,sun4i-a10-mmc-clk"; +- reg = <0x01c20088 0x4>; +- clocks = <&osc24M>, <&pll6 0>, <&pll8>; +- clock-output-names = "mmc0", +- "mmc0_output", +- "mmc0_sample"; +- }; +- +- mmc1_clk: clk@01c2008c { +- #clock-cells = <1>; +- compatible = "allwinner,sun4i-a10-mmc-clk"; +- reg = <0x01c2008c 0x4>; +- clocks = <&osc24M>, <&pll6 0>, <&pll8>; +- clock-output-names = "mmc1", +- "mmc1_output", +- "mmc1_sample"; +- }; +- +- mmc2_clk: clk@01c20090 { +- #clock-cells = <1>; +- compatible = "allwinner,sun4i-a10-mmc-clk"; +- reg = <0x01c20090 0x4>; +- clocks = <&osc24M>, <&pll6 0>, <&pll8>; +- clock-output-names = "mmc2", +- "mmc2_output", +- "mmc2_sample"; +- }; +- }; +- +- regulators { +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; +- +- soc { +- compatible = "simple-bus"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges; +- +- mmc0: mmc@01c0f000 { +- compatible = "allwinner,sun5i-a13-mmc"; +- reg = <0x01c0f000 0x1000>; +- clocks = <&bus_gates 8>, +- <&mmc0_clk 0>, +- <&mmc0_clk 1>, +- <&mmc0_clk 2>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ahb_rst 8>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc1: mmc@01c10000 { +- compatible = "allwinner,sun5i-a13-mmc"; +- reg = <0x01c10000 0x1000>; +- clocks = <&bus_gates 9>, +- <&mmc1_clk 0>, +- <&mmc1_clk 1>, +- <&mmc1_clk 2>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ahb_rst 9>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- mmc2: mmc@01c11000 { +- compatible = "allwinner,sun5i-a13-mmc"; +- reg = <0x01c11000 0x1000>; +- clocks = <&bus_gates 10>, +- <&mmc2_clk 0>, +- <&mmc2_clk 1>, +- <&mmc2_clk 2>; +- clock-names = "ahb", +- "mmc", +- "output", +- "sample"; +- resets = <&ahb_rst 10>; +- reset-names = "ahb"; +- interrupts = ; +- status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- pio: pinctrl@01c20800 { +- compatible = "allwinner,a64-pinctrl"; +- reg = <0x01c20800 0x400>; +- interrupts = , +- , +- ; +- clocks = <&bus_gates 69>; +- gpio-controller; +- #gpio-cells = <3>; +- interrupt-controller; +- #interrupt-cells = <2>; +- +- uart0_pins_a: uart0@0 { +- allwinner,pins = "PB8", "PB9"; +- allwinner,function = "uart0"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- uart0_pins_b: uart0@1 { +- allwinner,pins = "PF2", "PF3"; +- allwinner,function = "uart0"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- uart1_pins: uart1@0 { +- allwinner,pins = "PG6", "PG7", "PG8", "PG9"; +- allwinner,function = "uart1"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- uart2_pins: uart2@0 { +- allwinner,pins = "PB0", "PB1", "PB2", "PB3"; +- allwinner,function = "uart2"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- uart3_pins_a: uart3@0 { +- allwinner,pins = "PD0", "PD1"; +- allwinner,function = "uart3"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- uart3_pins_b: uart3@1 { +- allwinner,pins = "PH4", "PH5", "PH6", "PH7"; +- allwinner,function = "uart3"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- uart4_pins: uart4@0 { +- allwinner,pins = "PD2", "PD3", "PD4", "PD5"; +- allwinner,function = "uart4"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- mmc0_pins: mmc0@0 { +- allwinner,pins = "PF0", "PF1", "PF2", "PF3", +- "PF4", "PF5"; +- allwinner,function = "mmc0"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- mmc0_default_cd_pin: mmc0_cd_pin@0 { +- allwinner,pins = "PF6"; +- allwinner,function = "gpio_in"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- mmc1_pins: mmc1@0 { +- allwinner,pins = "PG0", "PG1", "PG2", "PG3", +- "PG4", "PG5"; +- allwinner,function = "mmc1"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- +- mmc2_pins: mmc2@0 { +- allwinner,pins = "PC1", "PC5", "PC6", "PC8", +- "PC9", "PC10"; +- allwinner,function = "mmc2"; +- allwinner,drive = ; +- allwinner,pull = ; +- }; +- }; +- +- ahb_rst: reset@01c202c0 { +- #reset-cells = <1>; +- compatible = "allwinner,sun6i-a31-ahb1-reset"; +- reg = <0x01c202c0 0xc>; +- }; +- +- apb1_rst: reset@01c202d0 { +- #reset-cells = <1>; +- compatible = "allwinner,sun6i-a31-clock-reset"; +- reg = <0x01c202d0 0x4>; +- }; +- +- apb2_rst: reset@01c202d8 { +- #reset-cells = <1>; +- compatible = "allwinner,sun6i-a31-clock-reset"; +- reg = <0x01c202d8 0x4>; +- }; +- +- uart0: serial@01c28000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&bus_gates 112>; +- resets = <&apb2_rst 16>; +- reset-names = "apb2"; +- status = "disabled"; +- }; +- +- uart1: serial@01c28400 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28400 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&bus_gates 113>; +- resets = <&apb2_rst 17>; +- reset-names = "apb2"; +- status = "disabled"; +- }; +- +- uart2: serial@01c28800 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28800 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&bus_gates 114>; +- resets = <&apb2_rst 18>; +- reset-names = "apb2"; +- status = "disabled"; +- }; +- +- uart3: serial@01c28c00 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c28c00 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&bus_gates 115>; +- resets = <&apb2_rst 19>; +- reset-names = "apb2"; +- status = "disabled"; +- }; +- +- uart4: serial@01c29000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x01c29000 0x400>; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- clocks = <&bus_gates 116>; +- resets = <&apb2_rst 20>; +- reset-names = "apb2"; +- status = "disabled"; +- }; +- +- rtc: rtc@01f00000 { +- compatible = "allwinner,sun6i-a31-rtc"; +- reg = <0x01f00000 0x54>; +- interrupts = , +- ; +- }; +- }; +- +- gic: interrupt-controller@{ +- compatible = "arm,gic-400"; +- interrupt-controller; +- #interrupt-cells = <3>; +- #address-cells = <0>; +- +- reg = <0x01C81000 0x1000>, +- <0x01C82000 0x2000>, +- <0x01C84000 0x2000>, +- <0x01C86000 0x2000>; +- interrupts = ; +- }; +-}; +diff --git a/arch/arm/dts/pine64.dts b/arch/arm/dts/pine64.dts +deleted file mode 100644 +index dcc998f..0000000 +--- a/arch/arm/dts/pine64.dts ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright (c) 2016 ARM Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-/memreserve/ 0x45000000 0x00200000; +-/memreserve/ 0x41010000 0x00010800; +-/memreserve/ 0x40100000 0x00006000; +- +-#include "pine64_common.dtsi" +- +-/ { +- model = "Pine64"; +- compatible = "pine64,pine64", "allwinner,a64"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- reg = <0x40000000 0x20000000>; +- }; +-}; +diff --git a/arch/arm/dts/pine64_common.dtsi b/arch/arm/dts/pine64_common.dtsi +deleted file mode 100644 +index d968d76..0000000 +--- a/arch/arm/dts/pine64_common.dtsi ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* +- * Copyright (c) 2016 ARM Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "a64.dtsi" +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>; +- vmmc-supply = <®_vcc3v3>; +- cd-gpios = <&pio 5 6 0>; +- cd-inverted; +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_a>; +- status = "okay"; +-}; +- +-&uart2 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart2_pins>; +- status = "okay"; +-}; +- +-&uart3 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart3_pins_a>; +- status = "okay"; +-}; +- +-&uart4 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart4_pins>; +- status = "okay"; +-}; +diff --git a/arch/arm/dts/pine64_plus.dts b/arch/arm/dts/pine64_plus.dts +deleted file mode 100644 +index 5daff51..0000000 +--- a/arch/arm/dts/pine64_plus.dts ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * Copyright (c) 2016 ARM Ltd. +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This library is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This library is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-/dts-v1/; +- +-/memreserve/ 0x45000000 0x00200000; +-/memreserve/ 0x41010000 0x00010800; +-/memreserve/ 0x40100000 0x00006000; +- +-#include "pine64_common.dtsi" +- +-/ { +- model = "Pine64+"; +- compatible = "pine64,pine64_plus", "allwinner,a64"; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */ +- memory { +- reg = <0x40000000 0x40000000>; +- }; +-}; +diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi +new file mode 100644 +index 0000000..d5a7249 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi +@@ -0,0 +1,80 @@ ++/* ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "sun50i-a64.dtsi" ++ ++/ { ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ cd-gpios = <&pio 5 6 0>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts +new file mode 100644 +index 0000000..549dc15 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64-pine64-common.dtsi" ++ ++/ { ++ model = "Pine64+"; ++ compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ /* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++}; +diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts +new file mode 100644 +index 0000000..ebe029e +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pine64.dts +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64-pine64-common.dtsi" ++ ++/ { ++ model = "Pine64"; ++ compatible = "pine64,pine64", "allwinner,sun50i-a64"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x20000000>; ++ }; ++}; +diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi +new file mode 100644 +index 0000000..1bd436f +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64.dtsi +@@ -0,0 +1,624 @@ ++/* ++ * Copyright (C) 2016 ARM Ltd. ++ * based on the Allwinner H3 dtsi: ++ * Copyright (C) 2015 Jens Kuske ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include ++#include ++ ++/ { ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ device_type = "cpu"; ++ reg = <0>; ++ enable-method = "psci"; ++ }; ++ ++ cpu@1 { ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ device_type = "cpu"; ++ reg = <1>; ++ enable-method = "psci"; ++ }; ++ ++ cpu@2 { ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ device_type = "cpu"; ++ reg = <2>; ++ enable-method = "psci"; ++ }; ++ ++ cpu@3 { ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ device_type = "cpu"; ++ reg = <3>; ++ enable-method = "psci"; ++ }; ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x40000000 0>; ++ }; ++ ++ gic: interrupt-controller@1c81000 { ++ compatible = "arm,gic-400"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ ++ reg = <0x01c81000 0x1000>, ++ <0x01c82000 0x2000>, ++ <0x01c84000 0x2000>, ++ <0x01c86000 0x2000>; ++ interrupts = ; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ osc24M: osc24M_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "osc24M"; ++ }; ++ ++ osc32k: osc32k_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "osc32k"; ++ }; ++ ++ pll1: pll1_clk@1c20000 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun8i-a23-pll1-clk"; ++ reg = <0x01c20000 0x4>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll1"; ++ }; ++ ++ pll6: pll6_clk@1c20028 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun6i-a31-pll6-clk"; ++ reg = <0x01c20028 0x4>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll6", "pll6x2"; ++ }; ++ ++ pll6d2: pll6d2_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clock-div = <2>; ++ clock-mult = <1>; ++ clocks = <&pll6 0>; ++ clock-output-names = "pll6d2"; ++ }; ++ ++ pll7: pll7_clk@1c2002c { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun6i-a31-pll6-clk"; ++ reg = <0x01c2002c 0x4>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll7", "pll7x2"; ++ }; ++ ++ cpu: cpu_clk@1c20050 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-cpu-clk"; ++ reg = <0x01c20050 0x4>; ++ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; ++ clock-output-names = "cpu"; ++ critical-clocks = <0>; ++ }; ++ ++ axi: axi_clk@1c20050 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-axi-clk"; ++ reg = <0x01c20050 0x4>; ++ clocks = <&cpu>; ++ clock-output-names = "axi"; ++ }; ++ ++ ahb1: ahb1_clk@1c20054 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun6i-a31-ahb1-clk"; ++ reg = <0x01c20054 0x4>; ++ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; ++ clock-output-names = "ahb1"; ++ }; ++ ++ ahb2: ahb2_clk@1c2005c { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun8i-h3-ahb2-clk"; ++ reg = <0x01c2005c 0x4>; ++ clocks = <&ahb1>, <&pll6d2>; ++ clock-output-names = "ahb2"; ++ }; ++ ++ apb1: apb1_clk@1c20054 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-apb0-clk"; ++ reg = <0x01c20054 0x4>; ++ clocks = <&ahb1>; ++ clock-output-names = "apb1"; ++ }; ++ ++ apb2: apb2_clk@1c20058 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-apb1-clk"; ++ reg = <0x01c20058 0x4>; ++ clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>; ++ clock-output-names = "apb2"; ++ }; ++ ++ bus_gates: bus_gates_clk@1c20060 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun50i-a64-bus-gates-clk", ++ "allwinner,sunxi-multi-bus-gates-clk"; ++ reg = <0x01c20060 0x14>; ++ ahb1_parent { ++ clocks = <&ahb1>; ++ clock-indices = <1>, <5>, ++ <6>, <8>, ++ <9>, <10>, ++ <13>, <14>, ++ <18>, <19>, ++ <20>, <21>, ++ <23>, <24>, ++ <25>, <28>, ++ <32>, <35>, ++ <36>, <37>, ++ <40>, <43>, ++ <44>, <52>, ++ <53>, <54>, ++ <135>; ++ clock-output-names = "bus_mipidsi", "bus_ce", ++ "bus_dma", "bus_mmc0", ++ "bus_mmc1", "bus_mmc2", ++ "bus_nand", "bus_sdram", ++ "bus_ts", "bus_hstimer", ++ "bus_spi0", "bus_spi1", ++ "bus_otg", "bus_otg_ehci0", ++ "bus_ehci0", "bus_otg_ohci0", ++ "bus_ve", "bus_lcd0", ++ "bus_lcd1", "bus_deint", ++ "bus_csi", "bus_hdmi", ++ "bus_de", "bus_gpu", ++ "bus_msgbox", "bus_spinlock", ++ "bus_dbg"; ++ }; ++ ahb2_parent { ++ clocks = <&ahb2>; ++ clock-indices = <17>, <29>; ++ clock-output-names = "bus_gmac", "bus_ohci0"; ++ }; ++ apb1_parent { ++ clocks = <&apb1>; ++ clock-indices = <64>, <65>, ++ <69>, <72>, ++ <76>, <77>, ++ <78>; ++ clock-output-names = "bus_codec", "bus_spdif", ++ "bus_pio", "bus_ths", ++ "bus_i2s0", "bus_i2s1", ++ "bus_i2s2"; ++ }; ++ abp2_parent { ++ clocks = <&apb2>; ++ clock-indices = <96>, <97>, ++ <98>, <101>, ++ <112>, <113>, ++ <114>, <115>, ++ <116>; ++ clock-output-names = "bus_i2c0", "bus_i2c1", ++ "bus_i2c2", "bus_scr", ++ "bus_uart0", "bus_uart1", ++ "bus_uart2", "bus_uart3", ++ "bus_uart4"; ++ }; ++ }; ++ ++ mmc0_clk: mmc0_clk@1c20088 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c20088 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; ++ clock-output-names = "mmc0"; ++ }; ++ ++ mmc1_clk: mmc1_clk@1c2008c { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c2008c 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; ++ clock-output-names = "mmc1"; ++ }; ++ ++ mmc2_clk: mmc2_clk@1c20090 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c20090 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; ++ clock-output-names = "mmc2"; ++ }; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ mmc0: mmc@1c0f000 { ++ compatible = "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ reg = <0x01c0f000 0x1000>; ++ clocks = <&bus_gates 8>, <&mmc0_clk>, ++ <&mmc0_clk>, <&mmc0_clk>; ++ clock-names = "ahb", "mmc", ++ "output", "sample"; ++ resets = <&ahb_rst 8>; ++ reset-names = "ahb"; ++ interrupts = ; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mmc1: mmc@1c10000 { ++ compatible = "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ reg = <0x01c10000 0x1000>; ++ clocks = <&bus_gates 9>, <&mmc1_clk>, ++ <&mmc1_clk>, <&mmc1_clk>; ++ clock-names = "ahb", "mmc", ++ "output", "sample"; ++ resets = <&ahb_rst 9>; ++ reset-names = "ahb"; ++ interrupts = ; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mmc2: mmc@1c11000 { ++ compatible = "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ reg = <0x01c11000 0x1000>; ++ clocks = <&bus_gates 10>, <&mmc2_clk>, ++ <&mmc2_clk>, <&mmc2_clk>; ++ clock-names = "ahb", "mmc", ++ "output", "sample"; ++ resets = <&ahb_rst 10>; ++ reset-names = "ahb"; ++ interrupts = ; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ pio: pinctrl@1c20800 { ++ compatible = "allwinner,sun50i-a64-pinctrl"; ++ reg = <0x01c20800 0x400>; ++ interrupts = , ++ , ++ ; ++ clocks = <&bus_gates 69>; ++ gpio-controller; ++ #gpio-cells = <3>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ uart0_pins_a: uart0@0 { ++ allwinner,pins = "PB8", "PB9"; ++ allwinner,function = "uart0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart0_pins_b: uart0@1 { ++ allwinner,pins = "PF2", "PF3"; ++ allwinner,function = "uart0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart1_2pins: uart1_2@0 { ++ allwinner,pins = "PG6", "PG7"; ++ allwinner,function = "uart1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart1_4pins: uart1_4@0 { ++ allwinner,pins = "PG6", "PG7", "PG8", "PG9"; ++ allwinner,function = "uart1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart2_2pins: uart2_2@0 { ++ allwinner,pins = "PB0", "PB1"; ++ allwinner,function = "uart2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart2_4pins: uart2_4@0 { ++ allwinner,pins = "PB0", "PB1", "PB2", "PB3"; ++ allwinner,function = "uart2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart3_pins_a: uart3@0 { ++ allwinner,pins = "PD0", "PD1"; ++ allwinner,function = "uart3"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart3_2pins_b: uart3_2@1 { ++ allwinner,pins = "PH4", "PH5"; ++ allwinner,function = "uart3"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart3_4pins_b: uart3_4@1 { ++ allwinner,pins = "PH4", "PH5", "PH6", "PH7"; ++ allwinner,function = "uart3"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart4_2pins: uart4_2@0 { ++ allwinner,pins = "PD2", "PD3"; ++ allwinner,function = "uart4"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ uart4_4pins: uart4_4@0 { ++ allwinner,pins = "PD2", "PD3", "PD4", "PD5"; ++ allwinner,function = "uart4"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ mmc0_pins: mmc0@0 { ++ allwinner,pins = "PF0", "PF1", "PF2", "PF3", ++ "PF4", "PF5"; ++ allwinner,function = "mmc0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ mmc0_default_cd_pin: mmc0_cd_pin@0 { ++ allwinner,pins = "PF6"; ++ allwinner,function = "gpio_in"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ mmc1_pins: mmc1@0 { ++ allwinner,pins = "PG0", "PG1", "PG2", "PG3", ++ "PG4", "PG5"; ++ allwinner,function = "mmc1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ mmc2_pins: mmc2@0 { ++ allwinner,pins = "PC1", "PC5", "PC6", "PC8", ++ "PC9", "PC10"; ++ allwinner,function = "mmc2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c0_pins: i2c0_pins { ++ allwinner,pins = "PH0", "PH1"; ++ allwinner,function = "i2c0"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ allwinner,pins = "PH2", "PH3"; ++ allwinner,function = "i2c1"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ allwinner,pins = "PE14", "PE15"; ++ allwinner,function = "i2c2"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ }; ++ ++ ahb_rst: reset@1c202c0 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun6i-a31-clock-reset"; ++ reg = <0x01c202c0 0xc>; ++ }; ++ ++ apb1_rst: reset@1c202d0 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun6i-a31-clock-reset"; ++ reg = <0x01c202d0 0x4>; ++ }; ++ ++ apb2_rst: reset@1c202d8 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun6i-a31-clock-reset"; ++ reg = <0x01c202d8 0x4>; ++ }; ++ ++ uart0: serial@1c28000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x01c28000 0x400>; ++ interrupts = ; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&bus_gates 112>; ++ resets = <&apb2_rst 16>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@1c28400 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x01c28400 0x400>; ++ interrupts = ; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&bus_gates 113>; ++ resets = <&apb2_rst 17>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@1c28800 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x01c28800 0x400>; ++ interrupts = ; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&bus_gates 114>; ++ resets = <&apb2_rst 18>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@1c28c00 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x01c28c00 0x400>; ++ interrupts = ; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&bus_gates 115>; ++ resets = <&apb2_rst 19>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@1c29000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x01c29000 0x400>; ++ interrupts = ; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&bus_gates 116>; ++ resets = <&apb2_rst 20>; ++ status = "disabled"; ++ }; ++ ++ rtc: rtc@1f00000 { ++ compatible = "allwinner,sun6i-a31-rtc"; ++ reg = <0x01f00000 0x54>; ++ interrupts = , ++ ; ++ }; ++ ++ i2c0: i2c@1c2ac00 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2ac00 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 96>; ++ resets = <&apb2_rst 0>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c1: i2c@1c2b000 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2b000 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 97>; ++ resets = <&apb2_rst 1>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c2: i2c@1c2b400 { ++ compatible = "allwinner,sun6i-a31-i2c"; ++ reg = <0x01c2b400 0x400>; ++ interrupts = ; ++ clocks = <&bus_gates 98>; ++ resets = <&apb2_rst 2>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++}; +diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig +index 0494a9f..0977334 100644 +--- a/configs/pine64_plus_defconfig ++++ b/configs/pine64_plus_defconfig +@@ -4,7 +4,7 @@ CONFIG_MACH_SUN50I=y + CONFIG_DRAM_CLK=672 + CONFIG_DRAM_ZQ=3881915 + # CONFIG_VIDEO is not set +-CONFIG_DEFAULT_DEVICE_TREE="pine64_plus" ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_HUSH_PARSER=y + # CONFIG_CMD_IMLS is not set diff --git a/U-Boot-6-6-Pine64-rename-defconfig.patch b/U-Boot-6-6-Pine64-rename-defconfig.patch new file mode 100644 index 0000000..2db9446 --- /dev/null +++ b/U-Boot-6-6-Pine64-rename-defconfig.patch @@ -0,0 +1,80 @@ +From patchwork Wed May 4 21:15:34 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,6/6] Pine64: rename defconfig +From: Andre Przywara +X-Patchwork-Id: 618681 +Message-Id: <1462396534-32390-7-git-send-email-andre.przywara@arm.com> +To: Hans de Goede , + Ian Campbell +Cc: Andre Przywara , u-boot@lists.denx.de +Date: Wed, 4 May 2016 22:15:34 +0100 + +Rename the defconfig file for the Pine64 from pine64_plus_defconfig to +pine64_defconfig. +The differences between the two versions (more RAM and a different +Ethernet PHY) don't justify two board versions, so lets stick with the +generic name and try to differentiate between the versions at runtime +if this is needed later. + +Signed-off-by: Andre Przywara +--- + configs/pine64_defconfig | 20 ++++++++++++++++++++ + configs/pine64_plus_defconfig | 20 -------------------- + 2 files changed, 20 insertions(+), 20 deletions(-) + create mode 100644 configs/pine64_defconfig + delete mode 100644 configs/pine64_plus_defconfig + +diff --git a/configs/pine64_defconfig b/configs/pine64_defconfig +new file mode 100644 +index 0000000..0977334 +--- /dev/null ++++ b/configs/pine64_defconfig +@@ -0,0 +1,20 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN50I=y ++CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_ZQ=3881915 ++# CONFIG_VIDEO is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_HUSH_PARSER=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_MMC=y ++# CONFIG_CMD_FPGA is not set ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_EXT2=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y +diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig +deleted file mode 100644 +index 0977334..0000000 +--- a/configs/pine64_plus_defconfig ++++ /dev/null +@@ -1,20 +0,0 @@ +-CONFIG_ARM=y +-CONFIG_ARCH_SUNXI=y +-CONFIG_MACH_SUN50I=y +-CONFIG_DRAM_CLK=672 +-CONFIG_DRAM_ZQ=3881915 +-# CONFIG_VIDEO is not set +-CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" +-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +-CONFIG_HUSH_PARSER=y +-# CONFIG_CMD_IMLS is not set +-# CONFIG_CMD_FLASH is not set +-CONFIG_CMD_MMC=y +-# CONFIG_CMD_FPGA is not set +-CONFIG_CMD_DHCP=y +-CONFIG_CMD_MII=y +-CONFIG_CMD_PING=y +-CONFIG_CMD_EXT2=y +-CONFIG_CMD_EXT4=y +-CONFIG_CMD_FAT=y +-CONFIG_CMD_FS_GENERIC=y diff --git a/armv8-boards b/armv8-boards index 504996a..abc6404 100644 --- a/armv8-boards +++ b/armv8-boards @@ -1,7 +1,7 @@ dragonboard410c hikey p2371-2180 -pine64_plus +pine64 rpi_3 vexpress_aemv8a_dram vexpress_aemv8a_juno diff --git a/sunxi-Enable-USB-host-in-CHIP-defconfig.patch b/sunxi-Enable-USB-host-in-CHIP-defconfig.patch new file mode 100644 index 0000000..d347ce1 --- /dev/null +++ b/sunxi-Enable-USB-host-in-CHIP-defconfig.patch @@ -0,0 +1,28 @@ +From patchwork Thu May 12 17:29:37 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot] sunxi: Enable USB host in CHIP defconfig +From: Hans de Goede +X-Patchwork-Id: 621695 +Message-Id: <1463074177-3321-1-git-send-email-hdegoede@redhat.com> +To: Ian Campbell +Cc: Dennis Gilmore , u-boot@lists.denx.de +Date: Thu, 12 May 2016 19:29:37 +0200 + +Reported-and-tested-by: Dennis Gilmore +Signed-off-by: Hans de Goede +Acked-by: Ian Campbell +--- + configs/CHIP_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig +index 0eca229..cbbec47 100644 +--- a/configs/CHIP_defconfig ++++ b/configs/CHIP_defconfig +@@ -29,3 +29,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_G_DNL_MANUFACTURER="Allwinner Technology" + CONFIG_G_DNL_VENDOR_NUM=0x1f3a + CONFIG_G_DNL_PRODUCT_NUM=0x1010 ++CONFIG_USB_EHCI_HCD=y diff --git a/uboot-tools.spec b/uboot-tools.spec index 91d23fc..7ddf873 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2016.05 -Release: 0.4%{?candidate:.%{candidate}}%{?dist} +Release: 0.5%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities Group: Development/Tools @@ -17,6 +17,17 @@ Patch2: 0004-Add-BOOTENV_INIT_COMMAND-for-commands-that-may-be-ne.patch Patch3: 0005-port-utilite-to-distro-generic-boot-commands.patch Patch4: mvebu-enable-generic-distro-boot-config.patch Patch5: U-Boot-video-ipu_common-fix-build-error.patch +Patch6: sunxi-Enable-USB-host-in-CHIP-defconfig.patch +Patch7: 0001-Revert-ti_armv7_common.h-Fix-U-Boot-location-on-eMMC.patch +Patch8: 0002-Revert-omap3-Use-raw-SPL-by-default-for-mmc1.patch + +Patch10: 0001-sunxi-mctl_mem_matches-Add-missing-memory-barrier.patch +Patch11: U-Boot-1-6-arm-arm64-Move-barrier-instructions-into-separate-header.patch +Patch12: U-Boot-2-6-Revert-sunxi-Reserve-ATF-memory-space-on-A64.patch +Patch13: U-Boot-3-6-arm64-sunxi-reserve-space-for-boot0-header.patch +Patch14: U-Boot-4-6-arm64-sunxi-adjust-default-load-addresses.patch +Patch15: U-Boot-5-6-arm64-Pine64-update-FDT-files.patch +Patch16: U-Boot-6-6-Pine64-rename-defconfig.patch BuildRequires: bc BuildRequires: dtc @@ -174,8 +185,9 @@ install -p -m 0644 tools/env/fw_env.config $RPM_BUILD_ROOT%{_sysconfdir} %files -%doc README doc/README.imximage doc/README.kwbimage doc/uImage.FIT -%doc doc/README.odroid doc/README.efi doc/README.imximage doc/README.rockchip +%doc README doc/README.imximage doc/README.kwbimage doc/README.imximage +%doc doc/README.distro doc/README.gpt doc/README.efi doc/uImage.FIT +%doc doc/README.odroid doc/README.rockchip %{_bindir}/* %{_mandir}/man1/mkimage.1* %dir %{_datadir}/uboot/ @@ -192,6 +204,10 @@ install -p -m 0644 tools/env/fw_env.config $RPM_BUILD_ROOT%{_sysconfdir} %endif %changelog +* Thu May 12 2016 Peter Robinson 2016.05-0.5rc3 +- Add USB storage support to CHIP +- Enhanced PINE64 support + * Thu Apr 28 2016 Peter Robinson 2016.05-0.4rc3 - Upstream fix for i.MX6 breakage - Rebase mvebu distro boot patch