From b8137c1080d845aa5cb1354f18055e44dda4eafd Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 9 Apr 2016 14:13:05 +0100 Subject: [PATCH] Add upstream fix for ARMv7 cache issues preventing some devices from booting --- ...v7.c-with--O1-to-avoid-gcc6-breakage.patch | 37 --- ...DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch | 311 ++++++++++++++++++ ...ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch | 242 ++++++++++++++ uboot-tools.spec | 9 +- 4 files changed, 560 insertions(+), 39 deletions(-) delete mode 100644 ARMv7-Build-cache_v7.c-with--O1-to-avoid-gcc6-breakage.patch create mode 100644 U-Boot-v2-1-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch create mode 100644 U-Boot-v2-2-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch diff --git a/ARMv7-Build-cache_v7.c-with--O1-to-avoid-gcc6-breakage.patch b/ARMv7-Build-cache_v7.c-with--O1-to-avoid-gcc6-breakage.patch deleted file mode 100644 index 09e95b8..0000000 --- a/ARMv7-Build-cache_v7.c-with--O1-to-avoid-gcc6-breakage.patch +++ /dev/null @@ -1,37 +0,0 @@ -From patchwork Mon Mar 21 16:08:34 2016 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot] ARMv7: Build cache_v7.c with -O1 to avoid gcc6 breakage -From: Hans de Goede -X-Patchwork-Id: 600177 -Message-Id: <1458576514-9470-2-git-send-email-hdegoede@redhat.com> -To: u-boot@lists.denx.de -Date: Mon, 21 Mar 2016 17:08:34 +0100 - -It seems that building cache_v7.c with gcc6 with -O2 or -Os results in -an unreliable u-boot (only boots the kernel some of the time), at least -on sunxi boards. For details see: - -https://bugzilla.redhat.com/show_bug.cgi?id=1318788 - -This commit adds -O1 at the end of the CFLAGS when building -cache_v7.c working around this. - -Signed-off-by: Hans de Goede ---- - arch/arm/cpu/armv7/Makefile | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile -index 45f346c..45a49fe 100644 ---- a/arch/arm/cpu/armv7/Makefile -+++ b/arch/arm/cpu/armv7/Makefile -@@ -8,6 +8,7 @@ - extra-y := start.o - - obj-y += cache_v7.o -+CFLAGS_cache_v7.o := $(KBUILD_CFLAGS) -O1 - - obj-y += cpu.o cp15.o - obj-y += syslib.o diff --git a/U-Boot-v2-1-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch b/U-Boot-v2-1-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch new file mode 100644 index 0000000..1b6e178 --- /dev/null +++ b/U-Boot-v2-1-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch @@ -0,0 +1,311 @@ +From patchwork Sat Apr 9 11:53:48 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v2, + 1/2] arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) + with asm code +From: Hans de Goede +X-Patchwork-Id: 608366 +Message-Id: <1460202829-27276-1-git-send-email-hdegoede@redhat.com> +To: Albert ARIBAUD , Tom Rini , + Masahiro Yamada +Cc: Ian Campbell , u-boot@lists.denx.de +Date: Sat, 9 Apr 2016 13:53:48 +0200 + +v7_maint_dcache_all() does not work reliable when build with gcc6, +see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788 + +While debugging this I learned that v7_maint_dcache_all() is unreliable +when build with gcc5 too when it is marked as noinline. + +This commit fixes the reliability issues by replacing the C-code with +the ready to use asm implementation from the kernel. + +Given that this code when written as C-code clearly is quite fragile +(also see the existing comments about the C-code being the way it is + to get optimal assembly) and that we have a proven asm alternative, +I believe that this is the best solution. + +Note that we actually already had a copy of the kernel's +v7_flush_dcache_all() before this commit in +arch/arm/mach-uniphier/arm32/lowlevel_init.S. + +This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames +it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper +which saves / restores the clobbered registers for use from C-code. + +Signed-off-by: Hans de Goede +--- +Changes in v2: +-Remove "Copyright (C) 2012-2015 Masahiro Yamada" from the header +-Move the v7_flush_dcache_all asm code from + arch/arm/mach-uniphier/arm32/lowlevel_init.S to + arch/arm/cpu/armv7/cache_v7_asm.S instead of adding a second copy +--- + arch/arm/cpu/armv7/Makefile | 2 +- + arch/arm/cpu/armv7/cache_v7.c | 41 ++------------ + arch/arm/cpu/armv7/cache_v7_asm.S | 84 ++++++++++++++++++++++++++++ + arch/arm/mach-uniphier/arm32/lowlevel_init.S | 67 +--------------------- + 4 files changed, 92 insertions(+), 102 deletions(-) + create mode 100644 arch/arm/cpu/armv7/cache_v7_asm.S + +diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile +index 45f346c..328c4b1 100644 +--- a/arch/arm/cpu/armv7/Makefile ++++ b/arch/arm/cpu/armv7/Makefile +@@ -7,7 +7,7 @@ + + extra-y := start.o + +-obj-y += cache_v7.o ++obj-y += cache_v7.o cache_v7_asm.o + + obj-y += cpu.o cp15.o + obj-y += syslib.o +diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c +index 94ff488..dd07ba1 100644 +--- a/arch/arm/cpu/armv7/cache_v7.c ++++ b/arch/arm/cpu/armv7/cache_v7.c +@@ -16,6 +16,10 @@ + #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 + + #ifndef CONFIG_SYS_DCACHE_OFF ++ ++/* Asm functions from cache_v7_asm.S */ ++void v7_flush_dcache_all(void); ++ + static int check_cache_range(unsigned long start, unsigned long stop) + { + int ok = 1; +@@ -88,34 +92,6 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, + DSB; + } + +-static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, +- u32 num_ways, u32 way_shift, +- u32 log2_line_len) +-{ +- int way, set; +- u32 setway; +- +- /* +- * For optimal assembly code: +- * a. count down +- * b. have bigger loop inside +- */ +- for (way = num_ways - 1; way >= 0 ; way--) { +- for (set = num_sets - 1; set >= 0; set--) { +- setway = (level << 1) | (set << log2_line_len) | +- (way << way_shift); +- /* +- * Clean & Invalidate data/unified +- * cache line by set/way +- */ +- asm volatile (" mcr p15, 0, %0, c7, c14, 2" +- : : "r" (setway)); +- } +- } +- /* DSB to make sure the operation is complete */ +- DSB; +-} +- + static void v7_maint_dcache_level_setway(u32 level, u32 operation) + { + u32 ccsidr; +@@ -142,13 +118,8 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation) + log2_num_ways = log_2_n_round_up(num_ways); + + way_shift = (32 - log2_num_ways); +- if (operation == ARMV7_DCACHE_INVAL_ALL) { +- v7_inval_dcache_level_setway(level, num_sets, num_ways, ++ v7_inval_dcache_level_setway(level, num_sets, num_ways, + way_shift, log2_line_len); +- } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) { +- v7_clean_inval_dcache_level_setway(level, num_sets, num_ways, +- way_shift, log2_line_len); +- } + } + + static void v7_maint_dcache_all(u32 operation) +@@ -263,7 +234,7 @@ void invalidate_dcache_all(void) + */ + void flush_dcache_all(void) + { +- v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL); ++ v7_flush_dcache_all(); + + v7_outer_cache_flush_all(); + } +diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S +new file mode 100644 +index 0000000..2e4629f +--- /dev/null ++++ b/arch/arm/cpu/armv7/cache_v7_asm.S +@@ -0,0 +1,84 @@ ++/* ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_SYS_THUMB_BUILD ++#define ARM(x...) ++#define THUMB(x...) x ++#else ++#define ARM(x...) x ++#define THUMB(x...) ++#endif ++ ++/* ++ * v7_flush_dcache_all() ++ * ++ * Flush the whole D-cache. ++ * ++ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) ++ * ++ * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4 ++ */ ++ENTRY(__v7_flush_dcache_all) ++ dmb @ ensure ordering with previous memory accesses ++ mrc p15, 1, r0, c0, c0, 1 @ read clidr ++ mov r3, r0, lsr #23 @ move LoC into position ++ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr ++ beq finished @ if loc is 0, then no need to clean ++start_flush_levels: ++ mov r10, #0 @ start clean at cache level 0 ++flush_levels: ++ add r2, r10, r10, lsr #1 @ work out 3x current cache level ++ mov r1, r0, lsr r2 @ extract cache type bits from clidr ++ and r1, r1, #7 @ mask of the bits for current cache only ++ cmp r1, #2 @ see what cache we have at this level ++ blt skip @ skip if no cache, or just i-cache ++ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr ++ isb @ isb to sych the new cssr&csidr ++ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr ++ and r2, r1, #7 @ extract the length of the cache lines ++ add r2, r2, #4 @ add 4 (line length offset) ++ movw r4, #0x3ff ++ ands r4, r4, r1, lsr #3 @ find maximum number on the way size ++ clz r5, r4 @ find bit position of way size increment ++ movw r7, #0x7fff ++ ands r7, r7, r1, lsr #13 @ extract max number of the index size ++loop1: ++ mov r9, r7 @ create working copy of max index ++loop2: ++ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 ++ THUMB( lsl r6, r4, r5 ) ++ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 ++ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 ++ THUMB( lsl r6, r9, r2 ) ++ THUMB( orr r11, r11, r6 ) @ factor index number into r11 ++ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way ++ subs r9, r9, #1 @ decrement the index ++ bge loop2 ++ subs r4, r4, #1 @ decrement the way ++ bge loop1 ++skip: ++ add r10, r10, #2 @ increment cache number ++ cmp r3, r10 ++ bgt flush_levels ++finished: ++ mov r10, #0 @ swith back to cache level 0 ++ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr ++ dsb st ++ isb ++ bx lr ++ENDPROC(__v7_flush_dcache_all) ++ ++ENTRY(v7_flush_dcache_all) ++ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) ++ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) ++ bl __v7_flush_dcache_all ++ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) ++ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) ++ bx lr ++ENDPROC(v7_flush_dcache_all) +diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S +index dd03ad8..e2bb1fc 100644 +--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S ++++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S +@@ -38,7 +38,7 @@ ENTRY(lowlevel_init) + * to do next is to create a page table and switch over to it. + */ + bl create_page_table +- bl v7_flush_dcache_all ++ bl __v7_flush_dcache_all + + /* Disable MMU and Dcache before switching Page Table */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) +@@ -140,68 +140,3 @@ ENTRY(create_page_table) + str r0, [r12, #4] @ mark the second section as Normal + mov pc, lr + ENDPROC(create_page_table) +- +-/* We don't use Thumb instructions for now */ +-#define ARM(x...) x +-#define THUMB(x...) +- +-/* +- * v7_flush_dcache_all() +- * +- * Flush the whole D-cache. +- * +- * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) +- * +- * - mm - mm_struct describing address space +- * +- * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4 +- */ +-ENTRY(v7_flush_dcache_all) +- dmb @ ensure ordering with previous memory accesses +- mrc p15, 1, r0, c0, c0, 1 @ read clidr +- mov r3, r0, lsr #23 @ move LoC into position +- ands r3, r3, #7 << 1 @ extract LoC*2 from clidr +- beq finished @ if loc is 0, then no need to clean +-start_flush_levels: +- mov r10, #0 @ start clean at cache level 0 +-flush_levels: +- add r2, r10, r10, lsr #1 @ work out 3x current cache level +- mov r1, r0, lsr r2 @ extract cache type bits from clidr +- and r1, r1, #7 @ mask of the bits for current cache only +- cmp r1, #2 @ see what cache we have at this level +- blt skip @ skip if no cache, or just i-cache +- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr +- isb @ isb to sych the new cssr&csidr +- mrc p15, 1, r1, c0, c0, 0 @ read the new csidr +- and r2, r1, #7 @ extract the length of the cache lines +- add r2, r2, #4 @ add 4 (line length offset) +- movw r4, #0x3ff +- ands r4, r4, r1, lsr #3 @ find maximum number on the way size +- clz r5, r4 @ find bit position of way size increment +- movw r7, #0x7fff +- ands r7, r7, r1, lsr #13 @ extract max number of the index size +-loop1: +- mov r9, r7 @ create working copy of max index +-loop2: +- ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 +- THUMB( lsl r6, r4, r5 ) +- THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 +- ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 +- THUMB( lsl r6, r9, r2 ) +- THUMB( orr r11, r11, r6 ) @ factor index number into r11 +- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way +- subs r9, r9, #1 @ decrement the index +- bge loop2 +- subs r4, r4, #1 @ decrement the way +- bge loop1 +-skip: +- add r10, r10, #2 @ increment cache number +- cmp r3, r10 +- bgt flush_levels +-finished: +- mov r10, #0 @ swith back to cache level 0 +- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr +- dsb st +- isb +- mov pc, lr +-ENDPROC(v7_flush_dcache_all) diff --git a/U-Boot-v2-2-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch b/U-Boot-v2-2-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch new file mode 100644 index 0000000..1f531ac --- /dev/null +++ b/U-Boot-v2-2-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch @@ -0,0 +1,242 @@ +From patchwork Sat Apr 9 11:53:49 2016 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot, v2, + 2/2] arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with + asm code +From: Hans de Goede +X-Patchwork-Id: 608365 +Message-Id: <1460202829-27276-2-git-send-email-hdegoede@redhat.com> +To: Albert ARIBAUD , Tom Rini , + Masahiro Yamada +Cc: Ian Campbell , u-boot@lists.denx.de +Date: Sat, 9 Apr 2016 13:53:49 +0200 + +Lets be consistent and also replace v7_maint_dcache_all() +with asm code for the invalidate case. + +Signed-off-by: Hans de Goede +--- +Changes in v2: +-No changes +--- + arch/arm/cpu/armv7/cache_v7.c | 100 ++------------------------------------ + arch/arm/cpu/armv7/cache_v7_asm.S | 70 ++++++++++++++++++++++++++ + 2 files changed, 74 insertions(+), 96 deletions(-) + +diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c +index dd07ba1..dc309da 100644 +--- a/arch/arm/cpu/armv7/cache_v7.c ++++ b/arch/arm/cpu/armv7/cache_v7.c +@@ -10,15 +10,14 @@ + #include + #include + +-#define ARMV7_DCACHE_INVAL_ALL 1 +-#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2 +-#define ARMV7_DCACHE_INVAL_RANGE 3 +-#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 ++#define ARMV7_DCACHE_INVAL_RANGE 1 ++#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2 + + #ifndef CONFIG_SYS_DCACHE_OFF + + /* Asm functions from cache_v7_asm.S */ + void v7_flush_dcache_all(void); ++void v7_invalidate_dcache_all(void); + + static int check_cache_range(unsigned long start, unsigned long stop) + { +@@ -37,18 +36,6 @@ static int check_cache_range(unsigned long start, unsigned long stop) + return ok; + } + +-/* +- * Write the level and type you want to Cache Size Selection Register(CSSELR) +- * to get size details from Current Cache Size ID Register(CCSIDR) +- */ +-static void set_csselr(u32 level, u32 type) +-{ +- u32 csselr = level << 1 | type; +- +- /* Write to Cache Size Selection Register(CSSELR) */ +- asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); +-} +- + static u32 get_ccsidr(void) + { + u32 ccsidr; +@@ -58,85 +45,6 @@ static u32 get_ccsidr(void) + return ccsidr; + } + +-static u32 get_clidr(void) +-{ +- u32 clidr; +- +- /* Read current CP15 Cache Level ID Register */ +- asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr)); +- return clidr; +-} +- +-static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, +- u32 num_ways, u32 way_shift, +- u32 log2_line_len) +-{ +- int way, set; +- u32 setway; +- +- /* +- * For optimal assembly code: +- * a. count down +- * b. have bigger loop inside +- */ +- for (way = num_ways - 1; way >= 0 ; way--) { +- for (set = num_sets - 1; set >= 0; set--) { +- setway = (level << 1) | (set << log2_line_len) | +- (way << way_shift); +- /* Invalidate data/unified cache line by set/way */ +- asm volatile (" mcr p15, 0, %0, c7, c6, 2" +- : : "r" (setway)); +- } +- } +- /* DSB to make sure the operation is complete */ +- DSB; +-} +- +-static void v7_maint_dcache_level_setway(u32 level, u32 operation) +-{ +- u32 ccsidr; +- u32 num_sets, num_ways, log2_line_len, log2_num_ways; +- u32 way_shift; +- +- set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED); +- +- ccsidr = get_ccsidr(); +- +- log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> +- CCSIDR_LINE_SIZE_OFFSET) + 2; +- /* Converting from words to bytes */ +- log2_line_len += 2; +- +- num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >> +- CCSIDR_ASSOCIATIVITY_OFFSET) + 1; +- num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >> +- CCSIDR_NUM_SETS_OFFSET) + 1; +- /* +- * According to ARMv7 ARM number of sets and number of ways need +- * not be a power of 2 +- */ +- log2_num_ways = log_2_n_round_up(num_ways); +- +- way_shift = (32 - log2_num_ways); +- v7_inval_dcache_level_setway(level, num_sets, num_ways, +- way_shift, log2_line_len); +-} +- +-static void v7_maint_dcache_all(u32 operation) +-{ +- u32 level, cache_type, level_start_bit = 0; +- u32 clidr = get_clidr(); +- +- for (level = 0; level < 7; level++) { +- cache_type = (clidr >> level_start_bit) & 0x7; +- if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) || +- (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) || +- (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED)) +- v7_maint_dcache_level_setway(level, operation); +- level_start_bit += 3; +- } +-} +- + static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len) + { + u32 mva; +@@ -223,7 +131,7 @@ static void v7_inval_tlb(void) + + void invalidate_dcache_all(void) + { +- v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); ++ v7_invalidate_dcache_all(); + + v7_outer_cache_inval_all(); + } +diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S +index 2e4629f..a433628 100644 +--- a/arch/arm/cpu/armv7/cache_v7_asm.S ++++ b/arch/arm/cpu/armv7/cache_v7_asm.S +@@ -82,3 +82,73 @@ ENTRY(v7_flush_dcache_all) + THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) + bx lr + ENDPROC(v7_flush_dcache_all) ++ ++/* ++ * v7_invalidate_dcache_all() ++ * ++ * Invalidate the whole D-cache. ++ * ++ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) ++ * ++ * Note: copied from __v7_flush_dcache_all above with ++ * mcr p15, 0, r11, c7, c14, 2 ++ * Replaced with: ++ * mcr p15, 0, r11, c7, c6, 2 ++ */ ++ENTRY(__v7_invalidate_dcache_all) ++ dmb @ ensure ordering with previous memory accesses ++ mrc p15, 1, r0, c0, c0, 1 @ read clidr ++ mov r3, r0, lsr #23 @ move LoC into position ++ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr ++ beq inval_finished @ if loc is 0, then no need to clean ++ mov r10, #0 @ start clean at cache level 0 ++inval_levels: ++ add r2, r10, r10, lsr #1 @ work out 3x current cache level ++ mov r1, r0, lsr r2 @ extract cache type bits from clidr ++ and r1, r1, #7 @ mask of the bits for current cache only ++ cmp r1, #2 @ see what cache we have at this level ++ blt inval_skip @ skip if no cache, or just i-cache ++ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr ++ isb @ isb to sych the new cssr&csidr ++ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr ++ and r2, r1, #7 @ extract the length of the cache lines ++ add r2, r2, #4 @ add 4 (line length offset) ++ movw r4, #0x3ff ++ ands r4, r4, r1, lsr #3 @ find maximum number on the way size ++ clz r5, r4 @ find bit position of way size increment ++ movw r7, #0x7fff ++ ands r7, r7, r1, lsr #13 @ extract max number of the index size ++inval_loop1: ++ mov r9, r7 @ create working copy of max index ++inval_loop2: ++ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 ++ THUMB( lsl r6, r4, r5 ) ++ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 ++ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 ++ THUMB( lsl r6, r9, r2 ) ++ THUMB( orr r11, r11, r6 ) @ factor index number into r11 ++ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way ++ subs r9, r9, #1 @ decrement the index ++ bge inval_loop2 ++ subs r4, r4, #1 @ decrement the way ++ bge inval_loop1 ++inval_skip: ++ add r10, r10, #2 @ increment cache number ++ cmp r3, r10 ++ bgt inval_levels ++inval_finished: ++ mov r10, #0 @ swith back to cache level 0 ++ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr ++ dsb st ++ isb ++ bx lr ++ENDPROC(__v7_invalidate_dcache_all) ++ ++ENTRY(v7_invalidate_dcache_all) ++ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) ++ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) ++ bl __v7_invalidate_dcache_all ++ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) ++ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) ++ bx lr ++ENDPROC(v7_invalidate_dcache_all) diff --git a/uboot-tools.spec b/uboot-tools.spec index cfed053..90760b4 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2016.03 -Release: 4%{?candidate:.%{candidate}}%{?dist} +Release: 5%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities Group: Development/Tools @@ -11,7 +11,6 @@ URL: http://www.denx.de/wiki/U-Boot Source0: ftp://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: armv7-boards -Patch0: ARMv7-Build-cache_v7.c-with--O1-to-avoid-gcc6-breakage.patch Patch1: 0001-Copy-gcc5-over-to-compiler-gcc6.h-as-a-beginning-of-.patch Patch2: 0004-Add-BOOTENV_INIT_COMMAND-for-commands-that-may-be-ne.patch Patch3: 0005-port-utilite-to-distro-generic-boot-commands.patch @@ -26,6 +25,9 @@ Patch11: sunxi-Enable-support-for-the-eMMC-found-on-the-orangepi-plus.patch Patch12: sunxi-Add-support-for-USB-vbus-pin-for-USB3.patch Patch13: sunxi-Specify-USB-vbus-pins-for-orangepi-boards.patch Patch14: sunxi-Add-a-bunch-of-missing-compatible-strings-to-sunxi_gpio.c.patch +Patch15: U-Boot-v2-1-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch +Patch16: U-Boot-v2-2-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch + BuildRequires: bc BuildRequires: dtc @@ -175,6 +177,9 @@ install -p -m 0644 tools/env/fw_env.config $RPM_BUILD_ROOT%{_sysconfdir} %endif %changelog +* Sat Apr 9 2016 Peter Robinson 2016.03-5 +- Add upstream fix for ARMv7 cache issues preventing some devices from booting + * Tue Mar 22 2016 Peter Robinson 2016.03-4 - Add a better fix for network issue which caused follow on issues