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- 2016.05 RC1 

- Build aarch64 u-boot for HiKey, DragonBoard, PINE64
- Build new ARMv7 devices
- Temp disable some i.MX6 devices as build broken
This commit is contained in:
Peter Robinson 2016-04-21 09:29:59 +01:00
parent 9a632183ca
commit 980e20b473
16 changed files with 62 additions and 1715 deletions
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587
0001-WIP-RPi-3-32-bit-port.patch
View File

@ -1,587 +0,0 @@
From 202d830b11d88335652a7b25ccd023a860e4e66f Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Sat, 5 Mar 2016 13:15:04 -0700
Subject: [PATCH] WIP: RPi 3 (32-bit) port
FIXME:
- split up into n patches
- describe
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
---
arch/arm/mach-bcm283x/Kconfig | 6 ++
arch/arm/mach-bcm283x/include/mach/aux.h | 25 +++++
arch/arm/mach-bcm283x/include/mach/gpio.h | 2 +-
arch/arm/mach-bcm283x/include/mach/mbox.h | 2 +-
arch/arm/mach-bcm283x/include/mach/sdhci.h | 2 +-
arch/arm/mach-bcm283x/include/mach/timer.h | 2 +-
arch/arm/mach-bcm283x/include/mach/wdog.h | 2 +-
arch/arm/mach-bcm283x/phys2bus.c | 2 +-
board/raspberrypi/rpi/rpi.c | 51 +++++++++-
board/raspberrypi/rpi_3_32b/MAINTAINERS | 6 ++
board/raspberrypi/rpi_3_32b/Makefile | 7 ++
configs/rpi_3_32b_defconfig | 9 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_bcm283x_mu.c | 138 +++++++++++++++++++++++++++
include/configs/rpi-common.h | 12 ++-
include/configs/rpi.h | 1 +
include/configs/rpi_3_32b.h | 18 ++++
include/dm/platform_data/serial_bcm283x_mu.h | 22 +++++
18 files changed, 297 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/mach-bcm283x/include/mach/aux.h
create mode 100644 board/raspberrypi/rpi_3_32b/MAINTAINERS
create mode 100644 board/raspberrypi/rpi_3_32b/Makefile
create mode 100644 configs/rpi_3_32b_defconfig
create mode 100644 drivers/serial/serial_bcm283x_mu.c
create mode 100644 include/configs/rpi_3_32b.h
create mode 100644 include/dm/platform_data/serial_bcm283x_mu.h
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 2315a13..aa2cf28 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -13,11 +13,16 @@ config TARGET_RPI_2
bool "Raspberry Pi 2"
select CPU_V7
+config TARGET_RPI_3_32B
+ bool "Raspberry Pi 3 32-bit build"
+ select CPU_V7
+
endchoice
config SYS_BOARD
default "rpi" if TARGET_RPI
default "rpi_2" if TARGET_RPI_2
+ default "rpi_3_32b" if TARGET_RPI_3_32B
config SYS_VENDOR
default "raspberrypi"
@@ -28,5 +33,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "rpi" if TARGET_RPI
default "rpi_2" if TARGET_RPI_2
+ default "rpi_3_32b" if TARGET_RPI_3_32B
endmenu
diff --git a/arch/arm/mach-bcm283x/include/mach/aux.h b/arch/arm/mach-bcm283x/include/mach/aux.h
new file mode 100644
index 0000000..0f97e5c
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/aux.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BCM2835_AUX_H_
+#define _BCM2835_AUX_H_
+
+#ifndef CONFIG_BCM2835
+#define BCM2835_AUX_BASE 0x3f215000
+#else
+#define BCM2835_AUX_BASE 0x20215000
+#endif
+
+#define BCM2835_AUX_ENABLES_SPI2 BIT(0)
+#define BCM2835_AUX_ENABLES_SPI1 BIT(0)
+#define BCM2835_AUX_ENABLES_MINI_UART BIT(0)
+
+struct bcm2835_aux_regs {
+ u32 irq;
+ u32 enables;
+};
+
+#endif /* _BCM2835_AXU_H_ */
diff --git a/arch/arm/mach-bcm283x/include/mach/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h
index c8ef8f5..e6e5d16 100644
--- a/arch/arm/mach-bcm283x/include/mach/gpio.h
+++ b/arch/arm/mach-bcm283x/include/mach/gpio.h
@@ -9,7 +9,7 @@
#ifndef _BCM2835_GPIO_H_
#define _BCM2835_GPIO_H_
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_GPIO_BASE 0x3f200000
#else
#define BCM2835_GPIO_BASE 0x20200000
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 4a14391..627acb8 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -38,7 +38,7 @@
/* Raw mailbox HW */
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_MBOX_PHYSADDR 0x3f00b880
#else
#define BCM2835_MBOX_PHYSADDR 0x2000b880
diff --git a/arch/arm/mach-bcm283x/include/mach/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h
index 2a21ccb..64e582c 100644
--- a/arch/arm/mach-bcm283x/include/mach/sdhci.h
+++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h
@@ -7,7 +7,7 @@
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_SDHCI_BASE 0x3f300000
#else
#define BCM2835_SDHCI_BASE 0x20300000
diff --git a/arch/arm/mach-bcm283x/include/mach/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h
index 004c24b..2a85f23 100644
--- a/arch/arm/mach-bcm283x/include/mach/timer.h
+++ b/arch/arm/mach-bcm283x/include/mach/timer.h
@@ -7,7 +7,7 @@
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_TIMER_PHYSADDR 0x3f003000
#else
#define BCM2835_TIMER_PHYSADDR 0x20003000
diff --git a/arch/arm/mach-bcm283x/include/mach/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h
index cbc350e..7741d7b 100644
--- a/arch/arm/mach-bcm283x/include/mach/wdog.h
+++ b/arch/arm/mach-bcm283x/include/mach/wdog.h
@@ -7,7 +7,7 @@
#ifndef _BCM2835_WDOG_H
#define _BCM2835_WDOG_H
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define BCM2835_WDOG_PHYSADDR 0x3f100000
#else
#define BCM2835_WDOG_PHYSADDR 0x20100000
diff --git a/arch/arm/mach-bcm283x/phys2bus.c b/arch/arm/mach-bcm283x/phys2bus.c
index fc1c299..8e9f492 100644
--- a/arch/arm/mach-bcm283x/phys2bus.c
+++ b/arch/arm/mach-bcm283x/phys2bus.c
@@ -9,7 +9,7 @@
unsigned long phys_to_bus(unsigned long phys)
{
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
return 0xc0000000 | phys;
#else
return 0x40000000 | phys;
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 776a958..1abf0bd 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -13,11 +13,14 @@
#include <lcd.h>
#include <memalign.h>
#include <mmc.h>
+#include <asm/io.h>
#include <asm/gpio.h>
+#include <asm/arch/aux.h>
#include <asm/arch/mbox.h>
#include <asm/arch/sdhci.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_pl01x.h>
+#include <dm/platform_data/serial_bcm283x_mu.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -30,8 +33,9 @@ U_BOOT_DEVICE(bcm2835_gpios) = {
.platdata = &gpio_platdata,
};
+#if defined(CONFIG_BCM2835) || defined(CONFIG_BCM2836)
static const struct pl01x_serial_platdata serial_platdata = {
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
.base = 0x3f201000,
#else
.base = 0x20201000,
@@ -43,6 +47,16 @@ U_BOOT_DEVICE(bcm2835_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
};
+#else
+static const struct bcm283x_mu_serial_platdata serial_platdata = {
+ .base = 0x3f215040,
+};
+
+U_BOOT_DEVICE(bcm2837_serials) = {
+ .name = "serial_bcm283x_mu",
+ .platdata = &serial_platdata,
+};
+#endif
struct msg_get_arm_mem {
struct bcm2835_mbox_hdr hdr;
@@ -98,7 +112,9 @@ struct rpi_model {
static const struct rpi_model rpi_model_unknown = {
"Unknown model",
-#ifdef CONFIG_BCM2836
+#if defined(CONFIG_BCM2837)
+ "bcm2837-rpi-other.dtb",
+#elif defined(CONFIG_BCM2836)
"bcm2836-rpi-other.dtb",
#else
"bcm2835-rpi-other.dtb",
@@ -112,6 +128,11 @@ static const struct rpi_model rpi_models_new_scheme[] = {
"bcm2836-rpi-2-b.dtb",
true,
},
+ [0x8] = {
+ "3 Model B",
+ "bcm2837-rpi-3-b.dtb",
+ true,
+ },
[0x9] = {
"Zero",
"bcm2835-rpi-zero.dtb",
@@ -212,6 +233,32 @@ static uint32_t rev_scheme;
static uint32_t rev_type;
static const struct rpi_model *model;
+#ifdef CONFIG_BCM2837
+int board_early_init_f(void)
+{
+ struct bcm2835_gpio_regs *gpior =
+ (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+ struct bcm2835_aux_regs *auxr =
+ (struct bcm2835_aux_regs *)BCM2835_AUX_BASE;
+ u32 val;
+
+ /* Route mini UART to header UART pins */
+ val = readl(&gpior->gpfsel[BCM2835_GPIO_FSEL_BANK(14)]);
+ val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(14));
+ val |= (BCM2835_GPIO_ALT5 << BCM2835_GPIO_FSEL_SHIFT(14));
+ val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(15));
+ val |= (BCM2835_GPIO_ALT5 << BCM2835_GPIO_FSEL_SHIFT(15));
+ writel(val, &gpior->gpfsel[BCM2835_GPIO_FSEL_BANK(14)]);
+
+ /* Enable mini UART HW module */
+ val = readl(&auxr->enables);
+ val |= BCM2835_AUX_ENABLES_MINI_UART;
+ writel(val, &auxr->enables);
+
+ return 0;
+}
+#endif
+
int dram_init(void)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);
diff --git a/board/raspberrypi/rpi_3_32b/MAINTAINERS b/board/raspberrypi/rpi_3_32b/MAINTAINERS
new file mode 100644
index 0000000..bc9df87
--- /dev/null
+++ b/board/raspberrypi/rpi_3_32b/MAINTAINERS
@@ -0,0 +1,6 @@
+RPI_3_32B BOARD
+M: Stephen Warren <swarren@wwwdotorg.org>
+S: Maintained
+F: board/raspberrypi/rpi_3_32b/
+F: include/configs/rpi_3_32b.h
+F: configs/rpi_3_32b_defconfig
diff --git a/board/raspberrypi/rpi_3_32b/Makefile b/board/raspberrypi/rpi_3_32b/Makefile
new file mode 100644
index 0000000..e569431
--- /dev/null
+++ b/board/raspberrypi/rpi_3_32b/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2012,2015 Stephen Warren <swarren@wwwdotorg.org>
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := ../rpi/rpi.o
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
new file mode 100644
index 0000000..fcb8961
--- /dev/null
+++ b/configs/rpi_3_32b_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_3_32B=y
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_PHYS_TO_BUS=y
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 05bdf56..ee7147a 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
+obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c
new file mode 100644
index 0000000..97b57cc
--- /dev/null
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * Derived from pl01x code:
+ *
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Simple U-Boot driver for the BCM283x mini UART */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <dm/platform_data/serial_bcm283x_mu.h>
+#include <linux/compiler.h>
+#include <fdtdec.h>
+
+struct bcm283x_mu_regs {
+ u32 io;
+ u32 iir;
+ u32 ier;
+ u32 lcr;
+ u32 mcr;
+ u32 lsr;
+ u32 msr;
+ u32 scratch;
+ u32 cntl;
+ u32 stat;
+ u32 baud;
+};
+
+#define BCM283X_MU_LCR_DATA_SIZE_8 3
+
+#define BCM283X_MU_LSR_TX_IDLE BIT(6)
+/* This actually means not full, but is named not empty in the docs */
+#define BCM283X_MU_LSR_TX_EMPTY BIT(5)
+#define BCM283X_MU_LSR_RX_READY BIT(0)
+
+struct bcm283x_mu_priv {
+ struct bcm283x_mu_regs *regs;
+};
+
+static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+ /* FIXME: Get this from plat data later */
+ u32 clock_rate = 250000000;
+ u32 divider;
+
+ divider = clock_rate / (baudrate * 8);
+
+ writel(BCM283X_MU_LCR_DATA_SIZE_8, &regs->lcr);
+ writel(divider - 1, &regs->baud);
+
+ return 0;
+}
+
+static int bcm283x_mu_serial_probe(struct udevice *dev)
+{
+ struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct bcm283x_mu_regs *)plat->base;
+
+ return 0;
+}
+
+static int bcm283x_mu_serial_getc(struct udevice *dev)
+{
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+ u32 data;
+
+ /* Wait until there is data in the FIFO */
+ if (!(readl(&regs->lsr) & BCM283X_MU_LSR_RX_READY))
+ return -EAGAIN;
+
+ data = readl(&regs->io);
+
+ return (int)data;
+}
+
+static int bcm283x_mu_serial_putc(struct udevice *dev, const char data)
+{
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+
+ /* Wait until there is space in the FIFO */
+ if (!(readl(&regs->lsr) & BCM283X_MU_LSR_TX_EMPTY))
+ return -EAGAIN;
+
+ /* Send the character */
+ writel(data, &regs->io);
+
+ return 0;
+}
+
+static int bcm283x_mu_serial_pending(struct udevice *dev, bool input)
+{
+ struct bcm283x_mu_priv *priv = dev_get_priv(dev);
+ struct bcm283x_mu_regs *regs = priv->regs;
+ unsigned int lsr = readl(&regs->lsr);
+
+ if (input) {
+ WATCHDOG_RESET();
+ return lsr & BCM283X_MU_LSR_RX_READY;
+ } else {
+ return !(lsr & BCM283X_MU_LSR_TX_IDLE);
+ }
+}
+
+static const struct dm_serial_ops bcm283x_mu_serial_ops = {
+ .putc = bcm283x_mu_serial_putc,
+ .pending = bcm283x_mu_serial_pending,
+ .getc = bcm283x_mu_serial_getc,
+ .setbrg = bcm283x_mu_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_bcm283x_mu) = {
+ .name = "serial_bcm283x_mu",
+ .id = UCLASS_SERIAL,
+ .platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
+ .probe = bcm283x_mu_serial_probe,
+ .ops = &bcm283x_mu_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv),
+};
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 9ae6805..30cd319 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -11,7 +11,6 @@
#include <asm/arch/timer.h>
/* Architecture, CPU, etc.*/
-#define CONFIG_BCM2835
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_TIMER_RATE 1000000
@@ -25,8 +24,11 @@
* We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
* chose to use someone else's previously registered machine ID (3139, MX51_GGC)
* rather than obtaining a valid ID:-/
+ *
+ * For the bcm2837, hopefully a machine type is not needed, since everything
+ * is DT.
*/
-#ifndef CONFIG_BCM2836
+#ifdef CONFIG_BCM2835
#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
#endif
@@ -80,7 +82,7 @@
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
-#ifdef CONFIG_BCM2836
+#ifndef CONFIG_BCM2835
#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
#else
#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
@@ -95,7 +97,11 @@
#endif
/* Console UART */
+#ifdef CONFIG_BCM2837
+#define CONFIG_BCM283X_MU_SERIAL
+#else
#define CONFIG_PL01X_SERIAL
+#endif
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 86422e3..a788ce4 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -7,6 +7,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_BCM2835
#define CONFIG_SYS_CACHELINE_SIZE 32
#include "rpi-common.h"
diff --git a/include/configs/rpi_3_32b.h b/include/configs/rpi_3_32b.h
new file mode 100644
index 0000000..5343e33
--- /dev/null
+++ b/include/configs/rpi_3_32b.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2012,2015-2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BCM2837
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_DCACHE_OFF
+
+#include "rpi-common.h"
+
+#endif
diff --git a/include/dm/platform_data/serial_bcm283x_mu.h b/include/dm/platform_data/serial_bcm283x_mu.h
new file mode 100644
index 0000000..4415945
--- /dev/null
+++ b/include/dm/platform_data/serial_bcm283x_mu.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * Derived from pl01x code:
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __serial_bcm283x_mu_h
+#define __serial_bcm283x_mu_h
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ */
+struct bcm283x_mu_serial_platdata {
+ unsigned long base;
+};
+
+#endif
--
2.5.0

58
0001-sunxi-A23-Fix-some-revisions-needing-a-different-mag.patch
View File

@ -1,58 +0,0 @@
From 22f2f6dd2a0e835f329f87b5349130300fc46e42 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 4 Mar 2016 10:57:34 +0100
Subject: [PATCH 1/2] sunxi: A23: Fix some revisions needing a different magic
sram poke
I've had this one a23 tablet which would not boot and I've finally
figured out what the problem is by looking at the released boot0 code,
it seems the magic sram controller poke which we need to do in s_init()
depends on the revision of the a23.
Specifically this change is needed to get the A23 SoC I have with the
following serial to boot: "E6071AB 26Y7".
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/board.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index eb5f4b6..e80785b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -113,11 +113,27 @@ int spl_board_load_image(void)
void s_init(void)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
- /* Magic (undocmented) value taken from boot0, without this DRAM
- * access gets messed up (seems cache related) */
+ /*
+ * Undocumented magic taken from boot0, without this DRAM
+ * access gets messed up (seems cache related).
+ * The boot0 sources describe this as: "config ema for cache sram"
+ */
+#if defined CONFIG_MACH_SUN6I
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#elif defined CONFIG_MACH_SUN8I_A23
+ uint version;
+
+ /* Unlock sram version info reg, read it, relock */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+ version = readl(SUNXI_SRAMC_BASE + 0x24);
+ clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+
+ if ((version & 0xffff0000) == 0x16500000)
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+ else /* 0x1661 ? */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#endif
+
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN8I
--
2.7.3

140
0001-sunxi-Fix-gmac-not-working-due-to-cpu_eth_init-no-lo.patch
View File

@ -1,140 +0,0 @@
From 2df313a8a25136cf5d55bc744a9df0d2dc7965f9 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 17 Mar 2016 13:53:03 +0100
Subject: [PATCH v2 1/3] sunxi: Fix gmac not working due to cpu_eth_init no
longer being called
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.
This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().
The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.
Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
---
Changes in v2:
-Move enabling of phy power to board_init()
---
arch/arm/cpu/armv7/sunxi/board.c | 28 +---------------------------
arch/arm/include/asm/arch-sunxi/sys_proto.h | 6 +++++-
board/sunxi/board.c | 5 +++++
board/sunxi/gmac.c | 14 +-------------
4 files changed, 12 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index e80785b..7653148 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -152,6 +152,7 @@ void s_init(void)
timer_init();
gpio_init();
i2c_init_board();
+ eth_init_board();
}
#ifdef CONFIG_SPL_BUILD
@@ -259,30 +260,3 @@ void enable_caches(void)
dcache_enable();
}
#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- __maybe_unused int rc;
-
-#ifdef CONFIG_MACPWR
- gpio_request(CONFIG_MACPWR, "macpwr");
- gpio_direction_output(CONFIG_MACPWR, 1);
- mdelay(200);
-#endif
-
-#ifdef CONFIG_SUNXI_GMAC
- rc = sunxi_gmac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize gmac\n");
- return rc;
- }
-#endif
-
- return 0;
-}
-#endif
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
index 9df3744..a373319 100644
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -24,6 +24,10 @@ void sdelay(unsigned long);
void return_to_fel(uint32_t lr, uint32_t sp);
/* Board / SoC level designware gmac init */
-int sunxi_gmac_initialize(bd_t *bis);
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
+void eth_init_board(void);
+#else
+static inline void eth_init_board(void) {}
+#endif
#endif
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 80eae9c..e16718f 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -90,6 +90,11 @@ int board_init(void)
if (ret)
return ret;
+#ifdef CONFIG_MACPWR
+ gpio_request(CONFIG_MACPWR, "macpwr");
+ gpio_direction_output(CONFIG_MACPWR, 1);
+#endif
+
/* Uses dm gpio code so do this here and not in i2c_init_board() */
return soft_i2c_board_init();
}
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 4e222d8..69eb8ff 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -6,7 +6,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-int sunxi_gmac_initialize(bd_t *bis)
+void eth_init_board(void)
{
int pin;
struct sunxi_ccm_reg *const ccm =
@@ -79,16 +79,4 @@ int sunxi_gmac_initialize(bd_t *bis)
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif
-
-#ifdef CONFIG_DM_ETH
- return 0;
-#else
-# ifdef CONFIG_RGMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
-# elif defined CONFIG_GMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
-# else
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
-# endif
-#endif
}
--
2.7.3

311
U-Boot-v2-1-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch
View File

@ -1,311 +0,0 @@
From patchwork Sat Apr 9 11:53:48 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot, v2,
1/2] arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL)
with asm code
From: Hans de Goede <hdegoede@redhat.com>
X-Patchwork-Id: 608366
Message-Id: <1460202829-27276-1-git-send-email-hdegoede@redhat.com>
To: Albert ARIBAUD <albert.u.boot@aribaud.net>, Tom Rini <trini@konsulko.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Ian Campbell <ijc+uboot@hellion.org.uk>, u-boot@lists.denx.de
Date: Sat, 9 Apr 2016 13:53:48 +0200
v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788
While debugging this I learned that v7_maint_dcache_all() is unreliable
when build with gcc5 too when it is marked as noinline.
This commit fixes the reliability issues by replacing the C-code with
the ready to use asm implementation from the kernel.
Given that this code when written as C-code clearly is quite fragile
(also see the existing comments about the C-code being the way it is
to get optimal assembly) and that we have a proven asm alternative,
I believe that this is the best solution.
Note that we actually already had a copy of the kernel's
v7_flush_dcache_all() before this commit in
arch/arm/mach-uniphier/arm32/lowlevel_init.S.
This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames
it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper
which saves / restores the clobbered registers for use from C-code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-Remove "Copyright (C) 2012-2015 Masahiro Yamada" from the header
-Move the v7_flush_dcache_all asm code from
arch/arm/mach-uniphier/arm32/lowlevel_init.S to
arch/arm/cpu/armv7/cache_v7_asm.S instead of adding a second copy
---
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/cache_v7.c | 41 ++------------
arch/arm/cpu/armv7/cache_v7_asm.S | 84 ++++++++++++++++++++++++++++
arch/arm/mach-uniphier/arm32/lowlevel_init.S | 67 +---------------------
4 files changed, 92 insertions(+), 102 deletions(-)
create mode 100644 arch/arm/cpu/armv7/cache_v7_asm.S
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 45f346c..328c4b1 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -7,7 +7,7 @@
extra-y := start.o
-obj-y += cache_v7.o
+obj-y += cache_v7.o cache_v7_asm.o
obj-y += cpu.o cp15.o
obj-y += syslib.o
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 94ff488..dd07ba1 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -16,6 +16,10 @@
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
#ifndef CONFIG_SYS_DCACHE_OFF
+
+/* Asm functions from cache_v7_asm.S */
+void v7_flush_dcache_all(void);
+
static int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
@@ -88,34 +92,6 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
DSB;
}
-static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /*
- * Clean & Invalidate data/unified
- * cache line by set/way
- */
- asm volatile (" mcr p15, 0, %0, c7, c14, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- DSB;
-}
-
static void v7_maint_dcache_level_setway(u32 level, u32 operation)
{
u32 ccsidr;
@@ -142,13 +118,8 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation)
log2_num_ways = log_2_n_round_up(num_ways);
way_shift = (32 - log2_num_ways);
- if (operation == ARMV7_DCACHE_INVAL_ALL) {
- v7_inval_dcache_level_setway(level, num_sets, num_ways,
+ v7_inval_dcache_level_setway(level, num_sets, num_ways,
way_shift, log2_line_len);
- } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
- v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
- }
}
static void v7_maint_dcache_all(u32 operation)
@@ -263,7 +234,7 @@ void invalidate_dcache_all(void)
*/
void flush_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
+ v7_flush_dcache_all();
v7_outer_cache_flush_all();
}
diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S
new file mode 100644
index 0000000..2e4629f
--- /dev/null
+++ b/arch/arm/cpu/armv7/cache_v7_asm.S
@@ -0,0 +1,84 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <linux/sizes.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SYS_THUMB_BUILD
+#define ARM(x...)
+#define THUMB(x...) x
+#else
+#define ARM(x...) x
+#define THUMB(x...)
+#endif
+
+/*
+ * v7_flush_dcache_all()
+ *
+ * Flush the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
+ */
+ENTRY(__v7_flush_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq finished @ if loc is 0, then no need to clean
+start_flush_levels:
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop1:
+ mov r9, r7 @ create working copy of max index
+loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_flush_dcache_all)
+
+ENTRY(v7_flush_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_flush_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_flush_dcache_all)
diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
index dd03ad8..e2bb1fc 100644
--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
@@ -38,7 +38,7 @@ ENTRY(lowlevel_init)
* to do next is to create a page table and switch over to it.
*/
bl create_page_table
- bl v7_flush_dcache_all
+ bl __v7_flush_dcache_all
/* Disable MMU and Dcache before switching Page Table */
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
@@ -140,68 +140,3 @@ ENTRY(create_page_table)
str r0, [r12, #4] @ mark the second section as Normal
mov pc, lr
ENDPROC(create_page_table)
-
-/* We don't use Thumb instructions for now */
-#define ARM(x...) x
-#define THUMB(x...)
-
-/*
- * v7_flush_dcache_all()
- *
- * Flush the whole D-cache.
- *
- * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
- *
- * - mm - mm_struct describing address space
- *
- * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
- */
-ENTRY(v7_flush_dcache_all)
- dmb @ ensure ordering with previous memory accesses
- mrc p15, 1, r0, c0, c0, 1 @ read clidr
- mov r3, r0, lsr #23 @ move LoC into position
- ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
- beq finished @ if loc is 0, then no need to clean
-start_flush_levels:
- mov r10, #0 @ start clean at cache level 0
-flush_levels:
- add r2, r10, r10, lsr #1 @ work out 3x current cache level
- mov r1, r0, lsr r2 @ extract cache type bits from clidr
- and r1, r1, #7 @ mask of the bits for current cache only
- cmp r1, #2 @ see what cache we have at this level
- blt skip @ skip if no cache, or just i-cache
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- isb @ isb to sych the new cssr&csidr
- mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
- and r2, r1, #7 @ extract the length of the cache lines
- add r2, r2, #4 @ add 4 (line length offset)
- movw r4, #0x3ff
- ands r4, r4, r1, lsr #3 @ find maximum number on the way size
- clz r5, r4 @ find bit position of way size increment
- movw r7, #0x7fff
- ands r7, r7, r1, lsr #13 @ extract max number of the index size
-loop1:
- mov r9, r7 @ create working copy of max index
-loop2:
- ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
- THUMB( lsl r6, r4, r5 )
- THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
- ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
- THUMB( lsl r6, r9, r2 )
- THUMB( orr r11, r11, r6 ) @ factor index number into r11
- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
- subs r9, r9, #1 @ decrement the index
- bge loop2
- subs r4, r4, #1 @ decrement the way
- bge loop1
-skip:
- add r10, r10, #2 @ increment cache number
- cmp r3, r10
- bgt flush_levels
-finished:
- mov r10, #0 @ swith back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- dsb st
- isb
- mov pc, lr
-ENDPROC(v7_flush_dcache_all)

242
U-Boot-v2-2-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch
View File

@ -1,242 +0,0 @@
From patchwork Sat Apr 9 11:53:49 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot, v2,
2/2] arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with
asm code
From: Hans de Goede <hdegoede@redhat.com>
X-Patchwork-Id: 608365
Message-Id: <1460202829-27276-2-git-send-email-hdegoede@redhat.com>
To: Albert ARIBAUD <albert.u.boot@aribaud.net>, Tom Rini <trini@konsulko.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Ian Campbell <ijc+uboot@hellion.org.uk>, u-boot@lists.denx.de
Date: Sat, 9 Apr 2016 13:53:49 +0200
Lets be consistent and also replace v7_maint_dcache_all()
with asm code for the invalidate case.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-No changes
---
arch/arm/cpu/armv7/cache_v7.c | 100 ++------------------------------------
arch/arm/cpu/armv7/cache_v7_asm.S | 70 ++++++++++++++++++++++++++
2 files changed, 74 insertions(+), 96 deletions(-)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index dd07ba1..dc309da 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -10,15 +10,14 @@
#include <asm/armv7.h>
#include <asm/utils.h>
-#define ARMV7_DCACHE_INVAL_ALL 1
-#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
-#define ARMV7_DCACHE_INVAL_RANGE 3
-#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
+#define ARMV7_DCACHE_INVAL_RANGE 1
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
#ifndef CONFIG_SYS_DCACHE_OFF
/* Asm functions from cache_v7_asm.S */
void v7_flush_dcache_all(void);
+void v7_invalidate_dcache_all(void);
static int check_cache_range(unsigned long start, unsigned long stop)
{
@@ -37,18 +36,6 @@ static int check_cache_range(unsigned long start, unsigned long stop)
return ok;
}
-/*
- * Write the level and type you want to Cache Size Selection Register(CSSELR)
- * to get size details from Current Cache Size ID Register(CCSIDR)
- */
-static void set_csselr(u32 level, u32 type)
-{
- u32 csselr = level << 1 | type;
-
- /* Write to Cache Size Selection Register(CSSELR) */
- asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
-}
-
static u32 get_ccsidr(void)
{
u32 ccsidr;
@@ -58,85 +45,6 @@ static u32 get_ccsidr(void)
return ccsidr;
}
-static u32 get_clidr(void)
-{
- u32 clidr;
-
- /* Read current CP15 Cache Level ID Register */
- asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
- return clidr;
-}
-
-static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /* Invalidate data/unified cache line by set/way */
- asm volatile (" mcr p15, 0, %0, c7, c6, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- DSB;
-}
-
-static void v7_maint_dcache_level_setway(u32 level, u32 operation)
-{
- u32 ccsidr;
- u32 num_sets, num_ways, log2_line_len, log2_num_ways;
- u32 way_shift;
-
- set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
-
- ccsidr = get_ccsidr();
-
- log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
- CCSIDR_LINE_SIZE_OFFSET) + 2;
- /* Converting from words to bytes */
- log2_line_len += 2;
-
- num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
- CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
- num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
- CCSIDR_NUM_SETS_OFFSET) + 1;
- /*
- * According to ARMv7 ARM number of sets and number of ways need
- * not be a power of 2
- */
- log2_num_ways = log_2_n_round_up(num_ways);
-
- way_shift = (32 - log2_num_ways);
- v7_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
-}
-
-static void v7_maint_dcache_all(u32 operation)
-{
- u32 level, cache_type, level_start_bit = 0;
- u32 clidr = get_clidr();
-
- for (level = 0; level < 7; level++) {
- cache_type = (clidr >> level_start_bit) & 0x7;
- if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
- (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
- (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
- v7_maint_dcache_level_setway(level, operation);
- level_start_bit += 3;
- }
-}
-
static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
{
u32 mva;
@@ -223,7 +131,7 @@ static void v7_inval_tlb(void)
void invalidate_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
+ v7_invalidate_dcache_all();
v7_outer_cache_inval_all();
}
diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S
index 2e4629f..a433628 100644
--- a/arch/arm/cpu/armv7/cache_v7_asm.S
+++ b/arch/arm/cpu/armv7/cache_v7_asm.S
@@ -82,3 +82,73 @@ ENTRY(v7_flush_dcache_all)
THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
bx lr
ENDPROC(v7_flush_dcache_all)
+
+/*
+ * v7_invalidate_dcache_all()
+ *
+ * Invalidate the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from __v7_flush_dcache_all above with
+ * mcr p15, 0, r11, c7, c14, 2
+ * Replaced with:
+ * mcr p15, 0, r11, c7, c6, 2
+ */
+ENTRY(__v7_invalidate_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq inval_finished @ if loc is 0, then no need to clean
+ mov r10, #0 @ start clean at cache level 0
+inval_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt inval_skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+inval_loop1:
+ mov r9, r7 @ create working copy of max index
+inval_loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge inval_loop2
+ subs r4, r4, #1 @ decrement the way
+ bge inval_loop1
+inval_skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt inval_levels
+inval_finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_invalidate_dcache_all)
+
+ENTRY(v7_invalidate_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_invalidate_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_invalidate_dcache_all)

19
armv7-boards
View File

@ -18,26 +18,31 @@ Bananapro
CHIP
Chuwi_V7_CW0825
clearfog
cm_fx6
Colombus
colorfly_e708_q1
CSQ_CS908
Cubieboard
Cubieboard2
Cubietruck
Cubietruck_plus
db-mv784mp-gp
difrnce_dit4350
dserve_dsrv9703c
firefly-rk3288
highbank
Hummingbird_A31
Hyundai_A7HD
i12-tvbox
icnova-a20-swac
iNet_86VS
Itead_Ibox_A20
jesurun_q5
jetson-tk1
kc1
Lamobo_R1
Linksprite_pcDuino
Linksprite_pcDuino3
Linksprite_pcDuino3_Nano
marsboard
Marsboard_A10
Mele_A1000
Mele_A1000G_quad
@ -52,8 +57,6 @@ mk802ii
MK808C
MSI_Primo73
MSI_Primo81
mx6cuboxi
novena
nyan-big
odroid
odroid-xu3
@ -62,6 +65,7 @@ omap3_pandora
omap4_panda
omap5_uevm
Orangepi
orangepi_2
Orangepi_mini
orangepi_pc
orangepi_plus
@ -69,29 +73,28 @@ origen
paz00
peach-pi
peach-pit
polaroid_mid2809pxe04
pov_protab2_ips9
q8_a13_tablet
q8_a23_tablet_800x480
q8_a33_tablet_1024x600
q8_a33_tablet_800x480
r7-tv-dongle
riotboard
rock2
rpi_2
rpi_3_32b
Sinlinx_SinA31s
smdkv310
snow
spring
sunxi_Gemei_G9
trimslice
udoo
UTOO_P66
vexpress_ca15_tc2
vexpress_ca9x4
wandboard
warp
Wexler_TAB7200
Wits_Pro_A20_DKT
Yones_Toptech_BS1078_V2
zynq_microzed
zynq_zed
zynq_zybo

7
armv8-boards Normal file
View File

@ -0,0 +1,7 @@
dragonboard410c
hikey
pine64_plus
rpi_3
vexpress_aemv8a_dram
vexpress_aemv8a_juno
vexpress_aemv8a_semi

2
sources
View File

@ -1 +1 @@
973c1d896be751321cc3aafa564f64b2 u-boot-2016.03.tar.bz2
aa190afb64ae4f59d1a02d351e4ceedd u-boot-2016.05-rc1.tar.bz2

62
sunxi-Add-a-bunch-of-missing-compatible-strings-to-sunxi_gpio.c.patch
View File

@ -1,62 +0,0 @@
From patchwork Fri Mar 18 07:55:06 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot,
3/3] sunxi: Add a bunch of missing compatible strings to sunxi_gpio.c
From: Hans de Goede <hdegoede@redhat.com>
X-Patchwork-Id: 599343
Message-Id: <1458287706-6656-3-git-send-email-hdegoede@redhat.com>
To: Ian Campbell <ijc+uboot@hellion.org.uk>
Cc: u-boot@lists.denx.de
Date: Fri, 18 Mar 2016 08:55:06 +0100
The kernel has different compatible strings for the pio block
because the pin-muxing is different on all the different SoCs,
but sunxi_gpio.c only support the basic gpio functionality, which
is identical everywhere. Add the missing compatible strings for
various SoC models.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/gpio/sunxi_gpio.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 9d8f11e..a7cec18 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -277,9 +277,17 @@ static int gpio_sunxi_bind(struct udevice *parent)
start = 'L' - 'A';
no_banks = 2; /* L & M */
} else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
- "allwinner,sun8i-a23-r-pinctrl") == 0) {
+ "allwinner,sun8i-a23-r-pinctrl") == 0 ||
+ fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+ "allwinner,sun8i-a83t-r-pinctrl") == 0 ||
+ fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+ "allwinner,sun8i-h3-r-pinctrl") == 0) {
start = 'L' - 'A';
no_banks = 1; /* L only */
+ } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
+ "allwinner,sun9i-a80-r-pinctrl") == 0) {
+ start = 'L' - 'A';
+ no_banks = 3; /* L, M & N */
} else {
start = 0;
no_banks = SUNXI_GPIO_BANKS;
@@ -316,9 +324,14 @@ static const struct udevice_id sunxi_gpio_ids[] = {
{ .compatible = "allwinner,sun7i-a20-pinctrl" },
{ .compatible = "allwinner,sun8i-a23-pinctrl" },
{ .compatible = "allwinner,sun8i-a33-pinctrl" },
+ { .compatible = "allwinner,sun8i-a83t-pinctrl", },
+ { .compatible = "allwinner,sun8i-h3-pinctrl" },
{ .compatible = "allwinner,sun9i-a80-pinctrl" },
{ .compatible = "allwinner,sun6i-a31-r-pinctrl" },
{ .compatible = "allwinner,sun8i-a23-r-pinctrl" },
+ { .compatible = "allwinner,sun8i-a83t-r-pinctrl" },
+ { .compatible = "allwinner,sun8i-h3-r-pinctrl", },
+ { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
{ }
};

49
sunxi-Add-support-for-USB-vbus-pin-for-USB3.patch
View File

@ -1,49 +0,0 @@
From patchwork Fri Mar 18 07:55:04 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot,1/3] sunxi: Add support for USB vbus pin for USB3
From: Hans de Goede <hdegoede@redhat.com>
X-Patchwork-Id: 599342
Message-Id: <1458287706-6656-1-git-send-email-hdegoede@redhat.com>
To: Ian Campbell <ijc+uboot@hellion.org.uk>
Cc: u-boot@lists.denx.de
Date: Fri, 18 Mar 2016 08:55:04 +0100
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/cpu/armv7/sunxi/usb_phy.c | 1 +
board/sunxi/Kconfig | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c
index 6ac96cc..0749fbd 100644
--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
@@ -76,6 +76,7 @@ static int get_vbus_gpio(int index)
case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
}
return -EINVAL;
}
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5e9d3af..5e72fac 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -342,6 +342,12 @@ config USB2_VBUS_PIN
---help---
See USB1_VBUS_PIN help text.
+config USB3_VBUS_PIN
+ string "Vbus enable pin for usb3 (ehci2)"
+ default ""
+ ---help---
+ See USB1_VBUS_PIN help text.
+
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I

32
sunxi-Enable-support-for-the-eMMC-found-on-the-orangepi-plus.patch
View File

@ -1,32 +0,0 @@
From patchwork Sun Mar 20 13:21:13 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot] sunxi: Enable support for the eMMC found on the orangepi plus
From: Hans de Goede <hdegoede@redhat.com>
X-Patchwork-Id: 599840
Message-Id: <1458480073-22121-1-git-send-email-hdegoede@redhat.com>
To: Ian Campbell <ijc+uboot@hellion.org.uk>
Cc: u-boot@lists.denx.de
Date: Sun, 20 Mar 2016 14:21:13 +0100
This enables support for the eMMC found on the orangepi plus.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
configs/orangepi_plus_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index c4885f4..770bd98 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -4,6 +4,8 @@ CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_VIDEO is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

88
sunxi-Fix-2nd-usb-controller-on-sun4i-sun7i-no-longer-working.patch
View File

@ -1,88 +0,0 @@
From patchwork Mon Mar 21 13:50:16 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer
working
From: Hans de Goede <hdegoede@redhat.com>
X-Patchwork-Id: 600131
Message-Id: <1458568216-18179-1-git-send-email-hdegoede@redhat.com>
To: Ian Campbell <ijc+uboot@hellion.org.uk>
Cc: u-boot@lists.denx.de
Date: Mon, 21 Mar 2016 14:50:16 +0100
The 2nd usb controller on sun4i/sun7i has its base address 0x8000
bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
are interleaved with the ohci clk-gates introducing a hole between
the clks for usb1 and usb2.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
drivers/usb/host/ehci-sunxi.c | 13 +++++++++++--
drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++---
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index cf3dcc4..677a5d3 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -17,6 +17,14 @@
#include <dm.h>
#include "ehci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ehci_sunxi_priv {
struct ehci_ctrl ehci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice *dev)
#ifdef CONFIG_MACH_SUN8I_H3
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
#endif
- priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 1b1f651..d4fb95a 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -17,6 +17,14 @@
#include <usb.h>
#include "ohci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ohci_sunxi_priv {
ohci_t ohci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice *dev)
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
#endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
- priv->usb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->usb_gate_mask <<= priv->phy_index;
+ priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);

42
sunxi-Specify-USB-vbus-pins-for-orangepi-boards.patch
View File

@ -1,42 +0,0 @@
From patchwork Fri Mar 18 07:55:05 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot,2/3] sunxi: Specify USB vbus pins for orangepi boards
From: Hans de Goede <hdegoede@redhat.com>
X-Patchwork-Id: 599344
Message-Id: <1458287706-6656-2-git-send-email-hdegoede@redhat.com>
To: Ian Campbell <ijc+uboot@hellion.org.uk>
Cc: u-boot@lists.denx.de
Date: Fri, 18 Mar 2016 08:55:05 +0100
This fixes the USB ports not working on the orangepi_plus and stops us
from messing with gpio-s which we should not touch on the orangepi_pc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
configs/orangepi_pc_defconfig | 3 +++
configs/orangepi_plus_defconfig | 2 ++
2 files changed, 5 insertions(+)
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index aaf0f68..4e9051d 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -14,3 +14,6 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB3_VBUS_PIN=""
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index e52dcfc..c4885f4 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -14,3 +14,5 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PG13"
+CONFIG_USB3_VBUS_PIN="PG11"

35
sunxi-chip-enable-composite-video-out.patch
View File

@ -1,35 +0,0 @@
From patchwork Mon Mar 7 12:50:20 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot] sunxi: chip: enable composite video out
From: Maxime Ripard <maxime.ripard@free-electrons.com>
X-Patchwork-Id: 592941
Message-Id: <1457355020-13676-1-git-send-email-maxime.ripard@free-electrons.com>
To: Hans de Goede <hdegoede@redhat.com>
Cc: u-boot@lists.denx.de, Alex Kaplan <kaplan2539@gmail.com>
Date: Mon, 7 Mar 2016 13:50:20 +0100
From: Alex Kaplan <kaplan2539@gmail.com>
The CHIP has a composite video output in the mini-Jack connector, alongside
with the 2 audio channels. Enable this output in U-Boot.
Signed-off-by: Alex Kaplan <kaplan2539@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
configs/CHIP_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 3135d1c88e79..4f99d1efdf9e 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
# CONFIG_MMC is not set
CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"

37
sunxi-fix-DCDC2-output-in-CHIP_defconfig.patch
View File

@ -1,37 +0,0 @@
From patchwork Mon Mar 7 12:44:11 2016
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot] sunxi: fix DCDC2 output in CHIP_defconfig
From: Maxime Ripard <maxime.ripard@free-electrons.com>
X-Patchwork-Id: 592940
Message-Id: <1457354651-10083-1-git-send-email-maxime.ripard@free-electrons.com>
To: Hans de Goede <hdegoede@redhat.com>
Cc: u-boot@lists.denx.de
Date: Mon, 7 Mar 2016 13:44:11 +0100
From: Boris Brezillon <boris.brezillon@free-electrons.com>
Unlike the datasheet recommendation, the R8 SoC requires a 1.4V supply
for its CPU when operating at 1Ghz.
Rely on the default value specified in the Kconfig entry.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
configs/CHIP_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index 78b2c511bfa2..3135d1c88e79 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -9,7 +9,6 @@ CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPIO=y
-CONFIG_AXP_DCDC2_VOLT=1300
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_USB_MUSB_GADGET=y

66
uboot-tools.spec
View File

@ -1,8 +1,8 @@
#global candidate rc3
%global candidate rc1
Name: uboot-tools
Version: 2016.03
Release: 6%{?candidate:.%{candidate}}%{?dist}
Version: 2016.05
Release: 0.1%{?candidate:.%{candidate}}%{?dist}
Summary: U-Boot utilities
Group: Development/Tools
@ -10,24 +10,13 @@ License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
URL: http://www.denx.de/wiki/U-Boot
Source0: ftp://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2
Source1: armv7-boards
Source2: armv8-boards
Patch1: 0001-Copy-gcc5-over-to-compiler-gcc6.h-as-a-beginning-of-.patch
Patch2: 0004-Add-BOOTENV_INIT_COMMAND-for-commands-that-may-be-ne.patch
Patch3: 0005-port-utilite-to-distro-generic-boot-commands.patch
Patch4: mvebu-enable-generic-distro-boot-config.patch
Patch5: 0001-WIP-RPi-3-32-bit-port.patch
Patch6: sunxi-chip-enable-composite-video-out.patch
Patch7: sunxi-fix-DCDC2-output-in-CHIP_defconfig.patch
Patch8: 0001-sunxi-A23-Fix-some-revisions-needing-a-different-mag.patch
Patch9: 0001-sunxi-Fix-gmac-not-working-due-to-cpu_eth_init-no-lo.patch
Patch10: sunxi-Fix-2nd-usb-controller-on-sun4i-sun7i-no-longer-working.patch
Patch11: sunxi-Enable-support-for-the-eMMC-found-on-the-orangepi-plus.patch
Patch12: sunxi-Add-support-for-USB-vbus-pin-for-USB3.patch
Patch13: sunxi-Specify-USB-vbus-pins-for-orangepi-boards.patch
Patch14: sunxi-Add-a-bunch-of-missing-compatible-strings-to-sunxi_gpio.c.patch
Patch15: U-Boot-v2-1-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_CLEAN_INVAL_ALL-with-asm-code.patch
Patch16: U-Boot-v2-2-2-arm-Replace-v7_maint_dcache_all-ARMV7_DCACHE_INVAL_ALL-with-asm-code.patch
# Needs a rebase
#Patch4: mvebu-enable-generic-distro-boot-config.patch
BuildRequires: bc
BuildRequires: dtc
@ -50,6 +39,7 @@ BuildArch: noarch
%description -n uboot-images-armv8
u-boot bootloader binaries for the aarch64 vexpress_aemv8a
%endif
%ifarch %{arm}
@ -80,7 +70,7 @@ rm -rf .git
%build
mkdir builds
# convert fedora logo to bmp for use in u-boot
pngtopnm /usr/share/pixmaps/fedora-logo.png | ppmquant 256 | ppmtobmp -bpp 8 >fedora.bmp
# pngtopnm /usr/share/pixmaps/fedora-logo.png | ppmquant 256 | ppmtobmp -bpp 8 >fedora.bmp
#replace the logos with fedora's
#for bmp in tools/logos/*bmp
@ -89,8 +79,12 @@ pngtopnm /usr/share/pixmaps/fedora-logo.png | ppmquant 256 | ppmtobmp -bpp 8 >fe
#done
%ifarch aarch64
make vexpress_aemv8a_juno_config vexpress_aemv8a_semi_config O=builds/vexpress_aemv8a/
make HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" %{?_smp_mflags} V=1 O=builds/vexpress_aemv8a/
for board in $(cat %SOURCE2)
do
make $(echo $board)_defconfig O=builds/$(echo $board)/
make HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" %{?_smp_mflags} V=1 O=builds/$(echo $board)/
done
%endif
%ifarch %{arm}
@ -112,9 +106,16 @@ mkdir -p $RPM_BUILD_ROOT%{_mandir}/man1
mkdir -p $RPM_BUILD_ROOT%{_datadir}/uboot/
%ifarch aarch64
mkdir -p $RPM_BUILD_ROOT%{_datadir}/uboot/vexpress_aemv8a/
install -p -m 0644 builds/vexpress_aemv8a/u-boot.bin $RPM_BUILD_ROOT%{_datadir}/uboot/vexpress_aemv8a/
for board in $(cat %SOURCE2)
do
mkdir -p $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/
for file in MLO SPL spl/arndale-spl.bin spl/origen-spl.bin spl/smdkv310-spl.bin u-boot.bin u-boot.dtb u-boot-dtb-tegra.bin u-boot.img u-boot.imx u-boot-nodtb-tegra.bin u-boot-spl.kwb u-boot-sunxi-with-spl.bin
do
if [ -f builds/$(echo $board)/$(echo $file) ]; then
install -p -m 0644 builds/$(echo $board)/$(echo $file) $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/
fi
done
done
%endif
%ifarch %{arm}
@ -147,6 +148,19 @@ do
done
%endif
%ifarch aarch64
for board in $(cat %SOURCE2)
do
mkdir -p $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/
for file in MLO SPL spl/arndale-spl.bin spl/origen-spl.bin spl/smdkv310-spl.bin u-boot.bin u-boot.dtb u-boot-dtb-tegra.bin u-boot.img u-boot.imx u-boot-nodtb-tegra.bin u-boot-spl.kwb u-boot-sunxi-with-spl.bin
do
if [ -f builds/$(echo $board)/$(echo $file) ]; then
install -p -m 0644 builds/$(echo $board)/$(echo $file) $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/
fi
done
done
%endif
for tool in bmp_logo dumpimage easylogo/easylogo env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr img2srec mkenvimage mkimage ncb proftool ubsha1 xway-swap-bytes
do
install -p -m 0755 builds/tools/$tool $RPM_BUILD_ROOT%{_bindir}
@ -177,6 +191,12 @@ install -p -m 0644 tools/env/fw_env.config $RPM_BUILD_ROOT%{_sysconfdir}
%endif
%changelog
* Thu Apr 21 2016 Peter Robinson <pbrobinson@fedoraproject.org> 2016.05-0.1rc1
- 2016.05 RC1
- Build aarch64 u-boot for HiKey, DragonBoard, PINE64
- Build new ARMv7 devices
- Temp disable some i.MX6 devices as build broken
* Tue Apr 19 2016 Dennis Gilmore <dennis@ausil.us> - 2016.03-6
- drop using the fedora logos for now rhbz#1328505