From 70d667ee2990c5b7060620472fdeaaaaa436a8bf Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 1 Apr 2020 11:30:30 +0100 Subject: [PATCH] Support RNG for random seed for KASLR on some Rockchip devices --- ...kchip-rk3399-add-and-enable-rng-node.patch | 863 ++++++++++++++++++ ...nable-rng-on-rock960-and-firefly3399.patch | 108 +++ ...ader-enable-RNG-if-DM_RNG-is-enabled.patch | 31 + uboot-tools.spec | 7 + 4 files changed, 1009 insertions(+) create mode 100644 arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch create mode 100644 arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch create mode 100644 efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch diff --git a/arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch b/arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch new file mode 100644 index 0000000..0dea1a8 --- /dev/null +++ b/arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch @@ -0,0 +1,863 @@ +From patchwork Tue Mar 31 09:39:57 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Lin Jinhan +X-Patchwork-Id: 1264692 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; 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+ Tue, 31 Mar 2020 17:40:04 +0800 (CST) +X-IP-DOMAINF: 1 +X-UNIQUE-TAG: <29a98dd6429030be44046c52ecfec245> +X-RL-SENDER: troy.lin@rock-chips.com +X-SENDER: troy.lin@rock-chips.com +X-LOGIN-NAME: troy.lin@rock-chips.com +X-FST-TO: u-boot@lists.denx.de +X-SENDER-IP: 58.22.7.114 +X-ATTACHMENT-NUM: 0 +X-DNS-TYPE: 0 +X-System-Flag: 0 +From: Lin Jinhan +To: u-boot@lists.denx.de, + sughosh.ganu@linaro.org, + xypron.glpk@gmx.de +Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com, + Lin Jinhan +Subject: [PATCH 1/5] arm: dts: rockchip: rk3399: add and enable rng node +Date: Tue, 31 Mar 2020 17:39:57 +0800 +Message-Id: <20200331094001.13441-1-troy.lin@rock-chips.com> +X-Mailer: git-send-email 2.17.1 +X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +Add rng node in rk3399-u-boot.dtsi and enable it in +rk3399-evb-u-boot.dtsi. + +Signed-off-by: Lin Jinhan +--- + arch/arm/dts/rk3399-evb-u-boot.dtsi | 5 +++++ + arch/arm/dts/rk3399-u-boot.dtsi | 6 ++++++ + 2 files changed, 11 insertions(+) + +diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi +index ccb33d34d1..5b50c5ba30 100644 +--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi +@@ -11,3 +11,8 @@ + u-boot,spl-boot-order = &sdhci, &sdmmc; + }; + }; ++ ++&rng { ++ status = "okay"; ++}; ++ +diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi +index 8b857ccfc7..757b8c10a2 100644 +--- a/arch/arm/dts/rk3399-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-u-boot.dtsi +@@ -25,6 +25,12 @@ + clock-names = "pclk_ddr_mon"; + }; + ++ rng: rng@ff8b8000 { ++ compatible = "rockchip,cryptov1-rng"; ++ reg = <0x0 0xff8b8000 0x0 0x1000>; ++ status = "disabled"; ++ }; ++ + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-dmc"; + +From patchwork Tue Mar 31 09:39:58 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Lin Jinhan +X-Patchwork-Id: 1264694 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) + smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; + helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; 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Tue, 31 Mar 2020 11:40:10 +0200 (CEST) +Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) + header.from=rock-chips.com +Authentication-Results: phobos.denx.de; + spf=fail smtp.mailfrom=troy.lin@rock-chips.com +Received: from localhost (unknown [192.168.167.235]) + by lucky1.263xmail.com (Postfix) with ESMTP id 65A9594DC1; + Tue, 31 Mar 2020 17:40:04 +0800 (CST) +X-MAIL-GRAY: 0 +X-MAIL-DELIVERY: 1 +X-ADDR-CHECKED: 0 +X-ANTISPAM-LEVEL: 2 +X-ABS-CHECKED: 0 +Received: from localhost.localdomain (unknown [58.22.7.114]) + by smtp.263.net (postfix) whith ESMTP id + P29487T139780956792576S1585647603180703_; + Tue, 31 Mar 2020 17:40:04 +0800 (CST) +X-IP-DOMAINF: 1 +X-UNIQUE-TAG: <5d721e76916e55da5c0d6122d449dd8b> +X-RL-SENDER: troy.lin@rock-chips.com +X-SENDER: troy.lin@rock-chips.com +X-LOGIN-NAME: troy.lin@rock-chips.com +X-FST-TO: u-boot@lists.denx.de +X-SENDER-IP: 58.22.7.114 +X-ATTACHMENT-NUM: 0 +X-DNS-TYPE: 0 +X-System-Flag: 0 +From: Lin Jinhan +To: u-boot@lists.denx.de, + sughosh.ganu@linaro.org, + xypron.glpk@gmx.de +Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com, + Lin Jinhan +Subject: [PATCH 2/5] arm: dts: rockchip: px30: add and enable rng node +Date: Tue, 31 Mar 2020 17:39:58 +0800 +Message-Id: <20200331094001.13441-2-troy.lin@rock-chips.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200331094001.13441-1-troy.lin@rock-chips.com> +References: <20200331094001.13441-1-troy.lin@rock-chips.com> +X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +Add enable rng node in px30-evb-u-boot.dtsi. + +Signed-off-by: Lin Jinhan +--- + arch/arm/dts/px30-evb-u-boot.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi +index a2a2c07dcc..a73c215c05 100644 +--- a/arch/arm/dts/px30-evb-u-boot.dtsi ++++ b/arch/arm/dts/px30-evb-u-boot.dtsi +@@ -12,6 +12,13 @@ + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; ++ ++ rng: rng@ff0b0000 { ++ compatible = "rockchip,cryptov2-rng"; ++ reg = <0x0 0xff0b0000 0x0 0x4000>; ++ status = "okay"; ++ }; ++ + }; + + &dmc { + +From patchwork Tue Mar 31 09:39:59 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Lin Jinhan +X-Patchwork-Id: 1264693 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) + smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; + helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; + receiver=) +Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) + header.from=rock-chips.com +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 48s6j253gKz9sR4 + for ; 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dmarc=none (p=none dis=none) + header.from=rock-chips.com +Authentication-Results: phobos.denx.de; + spf=fail smtp.mailfrom=troy.lin@rock-chips.com +Received: from localhost (unknown [192.168.167.235]) + by lucky1.263xmail.com (Postfix) with ESMTP id B1262A3EF8; + Tue, 31 Mar 2020 17:40:04 +0800 (CST) +X-MAIL-GRAY: 0 +X-MAIL-DELIVERY: 1 +X-ADDR-CHECKED: 0 +X-ANTISPAM-LEVEL: 2 +X-ABS-CHECKED: 0 +Received: from localhost.localdomain (unknown [58.22.7.114]) + by smtp.263.net (postfix) whith ESMTP id + P29487T139780956792576S1585647603180703_; + Tue, 31 Mar 2020 17:40:04 +0800 (CST) +X-IP-DOMAINF: 1 +X-UNIQUE-TAG: <78d4a197cac8da659f7b02fbce5e0ad8> +X-RL-SENDER: troy.lin@rock-chips.com +X-SENDER: troy.lin@rock-chips.com +X-LOGIN-NAME: troy.lin@rock-chips.com +X-FST-TO: u-boot@lists.denx.de +X-SENDER-IP: 58.22.7.114 +X-ATTACHMENT-NUM: 0 +X-DNS-TYPE: 0 +X-System-Flag: 0 +From: Lin Jinhan +To: u-boot@lists.denx.de, + sughosh.ganu@linaro.org, + xypron.glpk@gmx.de +Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com, + Lin Jinhan +Subject: [PATCH 3/5] rockchip: rng: Add a driver for random number + generator(rng) device +Date: Tue, 31 Mar 2020 17:39:59 +0800 +Message-Id: <20200331094001.13441-3-troy.lin@rock-chips.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200331094001.13441-1-troy.lin@rock-chips.com> +References: <20200331094001.13441-1-troy.lin@rock-chips.com> +X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +Add a driver for the rng device found on rockchip platforms. +Support rng module of crypto v1 and crypto v2. + +Signed-off-by: Lin Jinhan +--- + drivers/rng/Kconfig | 8 ++ + drivers/rng/Makefile | 1 + + drivers/rng/rockchip_rng.c | 224 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 233 insertions(+) + create mode 100644 drivers/rng/rockchip_rng.c + +diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig +index edb6152bb9..e4b22d79eb 100644 +--- a/drivers/rng/Kconfig ++++ b/drivers/rng/Kconfig +@@ -31,4 +31,12 @@ config RNG_STM32MP1 + help + Enable STM32MP1 rng driver. + ++config RNG_ROCKCHIP ++ bool "Enable random number generator for rockchip crypto rng" ++ depends on ARCH_ROCKCHIP && DM_RNG ++ default n ++ help ++ Enable random number generator for rockchip.This driver is ++ support rng module of crypto v1 and crypto v2. ++ + endif +diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile +index 6a8a66779b..44a0003917 100644 +--- a/drivers/rng/Makefile ++++ b/drivers/rng/Makefile +@@ -7,3 +7,4 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o + obj-$(CONFIG_RNG_MESON) += meson-rng.o + obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o + obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o ++obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o +diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c +new file mode 100644 +index 0000000000..47fb140077 +--- /dev/null ++++ b/drivers/rng/rockchip_rng.c +@@ -0,0 +1,224 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RK_HW_RNG_MAX 32 ++ ++#define _SBF(s, v) ((v) << (s)) ++ ++/* start of CRYPTO V1 register define */ ++#define CRYPTO_V1_CTRL 0x0008 ++#define CRYPTO_V1_RNG_START BIT(8) ++#define CRYPTO_V1_RNG_FLUSH BIT(9) ++ ++#define CRYPTO_V1_TRNG_CTRL 0x0200 ++#define CRYPTO_V1_OSC_ENABLE BIT(16) ++#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) ++ ++#define CRYPTO_V1_TRNG_DOUT_0 0x0204 ++/* end of CRYPTO V1 register define */ ++ ++/* start of CRYPTO V2 register define */ ++#define CRYPTO_V2_RNG_CTL 0x0400 ++#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) ++#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) ++#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) ++#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) ++#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) ++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) ++#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) ++#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) ++#define CRYPTO_V2_RNG_ENABLE BIT(1) ++#define CRYPTO_V2_RNG_START BIT(0) ++#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 ++#define CRYPTO_V2_RNG_DOUT_0 0x0410 ++/* end of CRYPTO V2 register define */ ++ ++#define RK_RNG_TIME_OUT 50000 /* max 50ms */ ++ ++struct rk_rng_soc_data { ++ int (*rk_rng_read)(struct udevice *dev, void *data, size_t len); ++}; ++ ++struct rk_rng_platdata { ++ fdt_addr_t base; ++ struct rk_rng_soc_data *soc_data; ++}; ++ ++static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size) ++{ ++ u32 count = RK_HW_RNG_MAX / sizeof(u32); ++ u32 reg, tmp_len; ++ ++ if (size > RK_HW_RNG_MAX) ++ return -EINVAL; ++ ++ while (size && count) { ++ reg = readl(addr); ++ tmp_len = min(size, sizeof(u32)); ++ memcpy(buf, ®, tmp_len); ++ addr += sizeof(u32); ++ buf += tmp_len; ++ size -= tmp_len; ++ count--; ++ } ++ ++ return 0; ++} ++ ++static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len) ++{ ++ struct rk_rng_platdata *pdata = dev_get_priv(dev); ++ u32 reg = 0; ++ int retval; ++ ++ if (len > RK_HW_RNG_MAX) ++ return -EINVAL; ++ ++ /* enable osc_ring to get entropy, sample period is set as 100 */ ++ writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100), ++ pdata->base + CRYPTO_V1_TRNG_CTRL); ++ ++ rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START, ++ CRYPTO_V1_RNG_START); ++ ++ retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg, ++ !(reg & CRYPTO_V1_RNG_START), ++ RK_RNG_TIME_OUT); ++ if (retval) ++ goto exit; ++ ++ rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len); ++ ++exit: ++ /* close TRNG */ ++ rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START); ++ ++ return 0; ++} ++ ++static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len) ++{ ++ struct rk_rng_platdata *pdata = dev_get_priv(dev); ++ u32 reg = 0; ++ int retval; ++ ++ if (len > RK_HW_RNG_MAX) ++ return -EINVAL; ++ ++ /* enable osc_ring to get entropy, sample period is set as 100 */ ++ writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT); ++ ++ reg |= CRYPTO_V2_RNG_256_BIT_LEN; ++ reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; ++ reg |= CRYPTO_V2_RNG_ENABLE; ++ reg |= CRYPTO_V2_RNG_START; ++ ++ rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg); ++ ++ retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg, ++ !(reg & CRYPTO_V2_RNG_START), ++ RK_RNG_TIME_OUT); ++ if (retval) ++ goto exit; ++ ++ rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len); ++ ++exit: ++ /* close TRNG */ ++ rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff); ++ ++ return retval; ++} ++ ++static int rockchip_rng_read(struct udevice *dev, void *data, size_t len) ++{ ++ unsigned char *buf = data; ++ unsigned int i; ++ int ret = -EIO; ++ ++ struct rk_rng_platdata *pdata = dev_get_priv(dev); ++ ++ if (!len) ++ return 0; ++ ++ if (!pdata->soc_data || !pdata->soc_data->rk_rng_read) ++ return -EINVAL; ++ ++ for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) { ++ ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX); ++ if (ret) ++ goto exit; ++ } ++ ++ if (len % RK_HW_RNG_MAX) ++ ret = pdata->soc_data->rk_rng_read(dev, buf, ++ len % RK_HW_RNG_MAX); ++ ++exit: ++ return ret; ++} ++ ++static int rockchip_rng_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct rk_rng_platdata *pdata = dev_get_priv(dev); ++ ++ memset(pdata, 0x00, sizeof(*pdata)); ++ ++ pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev); ++ if (!pdata->base) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static int rockchip_rng_probe(struct udevice *dev) ++{ ++ struct rk_rng_platdata *pdata = dev_get_priv(dev); ++ ++ pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev); ++ ++ return 0; ++} ++ ++static const struct rk_rng_soc_data rk_rng_v1_soc_data = { ++ .rk_rng_read = rk_v1_rng_read, ++}; ++ ++static const struct rk_rng_soc_data rk_rng_v2_soc_data = { ++ .rk_rng_read = rk_v2_rng_read, ++}; ++ ++static const struct dm_rng_ops rockchip_rng_ops = { ++ .read = rockchip_rng_read, ++}; ++ ++static const struct udevice_id rockchip_rng_match[] = { ++ { ++ .compatible = "rockchip,cryptov1-rng", ++ .data = (ulong)&rk_rng_v1_soc_data, ++ }, ++ { ++ .compatible = "rockchip,cryptov2-rng", ++ .data = (ulong)&rk_rng_v2_soc_data, ++ }, ++ {}, ++}; ++ ++U_BOOT_DRIVER(rockchip_rng) = { ++ .name = "rockchip-rng", ++ .id = UCLASS_RNG, ++ .of_match = rockchip_rng_match, ++ .ops = &rockchip_rng_ops, ++ .probe = rockchip_rng_probe, ++ .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata, ++ .priv_auto_alloc_size = sizeof(struct rk_rng_platdata), ++}; + +From patchwork Tue Mar 31 09:40:00 2020 +Content-Type: text/plain; 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+ Tue, 31 Mar 2020 17:40:05 +0800 (CST) +X-MAIL-GRAY: 0 +X-MAIL-DELIVERY: 1 +X-ADDR-CHECKED: 0 +X-ANTISPAM-LEVEL: 2 +X-ABS-CHECKED: 0 +Received: from localhost.localdomain (unknown [58.22.7.114]) + by smtp.263.net (postfix) whith ESMTP id + P29487T139780956792576S1585647603180703_; + Tue, 31 Mar 2020 17:40:05 +0800 (CST) +X-IP-DOMAINF: 1 +X-UNIQUE-TAG: <7a2dd5c9974cf72e82c0752b3ad6f8eb> +X-RL-SENDER: troy.lin@rock-chips.com +X-SENDER: troy.lin@rock-chips.com +X-LOGIN-NAME: troy.lin@rock-chips.com +X-FST-TO: u-boot@lists.denx.de +X-SENDER-IP: 58.22.7.114 +X-ATTACHMENT-NUM: 0 +X-DNS-TYPE: 0 +X-System-Flag: 0 +From: Lin Jinhan +To: u-boot@lists.denx.de, + sughosh.ganu@linaro.org, + xypron.glpk@gmx.de +Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com, + Lin Jinhan +Subject: [PATCH 4/5] rockchip: rk3399: Enable CONFIG_RNG_ROCKCHIP +Date: Tue, 31 Mar 2020 17:40:00 +0800 +Message-Id: <20200331094001.13441-4-troy.lin@rock-chips.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200331094001.13441-1-troy.lin@rock-chips.com> +References: <20200331094001.13441-1-troy.lin@rock-chips.com> +X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled. + +Signed-off-by: Lin Jinhan +--- + configs/evb-rk3399_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig +index 3f74be3b3c..7f14e18b1b 100644 +--- a/configs/evb-rk3399_defconfig ++++ b/configs/evb-rk3399_defconfig +@@ -39,6 +39,8 @@ CONFIG_PMIC_RK8XX=y + CONFIG_REGULATOR_PWM=y + CONFIG_REGULATOR_RK8XX=y + CONFIG_PWM_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_BAUDRATE=1500000 + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_SYSRESET=y + +From patchwork Tue Mar 31 09:40:01 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Lin Jinhan +X-Patchwork-Id: 1264695 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) + smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; + helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; + receiver=) +Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) + header.from=rock-chips.com +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 48s6jR3jp0z9sR4 + for ; + Tue, 31 Mar 2020 22:36:27 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 632D581A0D; + Tue, 31 Mar 2020 13:35:45 +0200 (CEST) +Authentication-Results: phobos.denx.de; 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+ Tue, 31 Mar 2020 17:40:05 +0800 (CST) +X-MAIL-GRAY: 0 +X-MAIL-DELIVERY: 1 +X-ADDR-CHECKED: 0 +X-ANTISPAM-LEVEL: 2 +X-ABS-CHECKED: 0 +Received: from localhost.localdomain (unknown [58.22.7.114]) + by smtp.263.net (postfix) whith ESMTP id + P29487T139780956792576S1585647603180703_; + Tue, 31 Mar 2020 17:40:05 +0800 (CST) +X-IP-DOMAINF: 1 +X-UNIQUE-TAG: <81a0d8eceb16099cd760d4d11030d27a> +X-RL-SENDER: troy.lin@rock-chips.com +X-SENDER: troy.lin@rock-chips.com +X-LOGIN-NAME: troy.lin@rock-chips.com +X-FST-TO: u-boot@lists.denx.de +X-SENDER-IP: 58.22.7.114 +X-ATTACHMENT-NUM: 0 +X-DNS-TYPE: 0 +X-System-Flag: 0 +From: Lin Jinhan +To: u-boot@lists.denx.de, + sughosh.ganu@linaro.org, + xypron.glpk@gmx.de +Cc: kever.yang@rock-chips.com, zhangzj@rock-chips.com, + Lin Jinhan +Subject: [PATCH 5/5] rockchip: px30: Enable CONFIG_RNG_ROCKCHIP +Date: Tue, 31 Mar 2020 17:40:01 +0800 +Message-Id: <20200331094001.13441-5-troy.lin@rock-chips.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20200331094001.13441-1-troy.lin@rock-chips.com> +References: <20200331094001.13441-1-troy.lin@rock-chips.com> +X-Mailman-Approved-At: Tue, 31 Mar 2020 13:35:19 +0200 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +CONFIG_RNG_ROCKCHIP/CONFIG_DM_RNG is enabled. + +Signed-off-by: Lin Jinhan +--- + configs/evb-px30_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig +index b5ba75cc6e..d2cf13e54a 100644 +--- a/configs/evb-px30_defconfig ++++ b/configs/evb-px30_defconfig +@@ -85,6 +85,8 @@ CONFIG_SPL_RAM=y + CONFIG_TPL_RAM=y + CONFIG_ROCKCHIP_SDRAM_COMMON=y + CONFIG_DM_RESET=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + # CONFIG_SPECIFY_CONSOLE_INDEX is not set + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_DEBUG_UART_SKIP_INIT=y diff --git a/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch b/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch new file mode 100644 index 0000000..0987100 --- /dev/null +++ b/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch @@ -0,0 +1,108 @@ +From 32f17a93e08227c56a655f9b85977569e4e5daa2 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 1 Apr 2020 10:44:09 +0100 +Subject: [PATCH] arm: rk3399: enable rng on rock960 and firefly3399 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 4 ++++ + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 4 ++++ + configs/firefly-rk3399_defconfig | 2 ++ + configs/rock960-rk3399_defconfig | 2 ++ + 4 files changed, 12 insertions(+) + +diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi +index 38e0897db9..a6c7b913da 100644 +--- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi +@@ -11,3 +11,7 @@ + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; + }; ++ ++&rng { ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi +index 82f2c311af..401ad02c45 100644 +--- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi +@@ -24,3 +24,7 @@ + }; + + }; ++ ++&rng { ++ status = "okay"; ++}; +diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig +index 4c9f1e189b..27306b434f 100644 +--- a/configs/firefly-rk3399_defconfig ++++ b/configs/firefly-rk3399_defconfig +@@ -34,6 +34,8 @@ CONFIG_MMC_DW=y + CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_SF_DEFAULT_SPEED=20000000 + CONFIG_DM_ETH=y + CONFIG_ETH_DESIGNWARE=y +diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig +index ba4226e173..f823d0dabd 100644 +--- a/configs/rock960-rk3399_defconfig ++++ b/configs/rock960-rk3399_defconfig +@@ -35,6 +35,8 @@ CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_DM_ETH=y + CONFIG_PMIC_RK8XX=y + CONFIG_REGULATOR_PWM=y +-- +2.26.0 + +From 03a3e695cb24257e42a0a97abf7177ca788bedc4 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 1 Apr 2020 11:20:43 +0100 +Subject: [PATCH] arm: rk3399: enable rng on rockpro64 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ + configs/rockpro64-rk3399_defconfig | 2 ++ + 2 files changed, 6 insertions(+) + +diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +index deaa3efd39..2e99ef71f4 100644 +--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +@@ -15,6 +15,10 @@ + }; + }; + ++&rng { ++ status = "okay"; ++}; ++ + &vdd_center { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; +diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig +index 8074e4665a..285dccebe5 100644 +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -34,6 +34,8 @@ CONFIG_MMC_DW=y + CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_SPI_FLASH_GIGADEVICE=y + CONFIG_DM_ETH=y + CONFIG_ETH_DESIGNWARE=y +-- +2.26.0 + diff --git a/efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch b/efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch new file mode 100644 index 0000000..bd70605 --- /dev/null +++ b/efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch @@ -0,0 +1,31 @@ +From af59a07dad603740d0aaa103cd02b97e4a3267af Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 1 Apr 2020 11:11:12 +0100 +Subject: [PATCH] efi_loader: enable RNG if DM_RNG is enabled + +Enable EFI_RNG_PROTOCOL by default if DM_RNG is set. + +Signed-off-by: Peter Robinson +--- + +I think it makes sense to enable EFI_RNG_PROTOCOL by default if a config +has enabled both DM_RNG and UEFI. + + lib/efi_loader/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig +index 9890144d41..b9a770281e 100644 +--- a/lib/efi_loader/Kconfig ++++ b/lib/efi_loader/Kconfig +@@ -125,6 +125,7 @@ config EFI_GRUB_ARM32_WORKAROUND + + config EFI_RNG_PROTOCOL + bool "EFI_RNG_PROTOCOL support" ++ default y if DM_RNG + depends on DM_RNG + help + Provide a EFI_RNG_PROTOCOL implementation using the hardware random +-- +2.26.0 + diff --git a/uboot-tools.spec b/uboot-tools.spec index f63ea95..40ebdd3 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -24,7 +24,9 @@ Patch2: uefi-use-Fedora-specific-path-name.patch Patch4: usb-kbd-fixes.patch Patch5: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch6: dragonboard-fixes.patch +Patch7: efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch +# Tegra improvements Patch10: mtd-spi-Add-Macronix-MX25U3235F-device.patch Patch11: Misc-fixes-for-Tegra.patch Patch12: mmc-t210-fix-autocal-and-400KHz-clock.patch @@ -36,6 +38,10 @@ Patch16: ARM-tegra-Add-NVIDIA-Jetson-Nano.patch Patch17: arm-tegra-define-fdtfile-option-for-distro-boot.patch Patch18: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch +# Rockchips improvements +Patch20: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch +Patch21: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch + BuildRequires: bc BuildRequires: dtc BuildRequires: make @@ -259,6 +265,7 @@ cp -p board/warp7/README builds/docs/README.warp7 * Tue Mar 31 2020 Peter Robinson 2020.04-0.6-rc4 - 2020.04 RC4 - Updates for NVIDIA Jetson platforms +- Support RNG for random seed for KASLR on some Rockchip devices * Thu Mar 26 2020 Peter Robinson 2020.04-0.5-rc3 - Fix ext4 alignment issue seen on some NXP i.MX devices