From 65896be74ab0b6d7db58b4ca067631fcd2c8d969 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 31 Jan 2023 10:29:14 +0000 Subject: [PATCH] Update to 2023.04 rc1 --- ...nitial-support-for-the-PinePhone-Pro.patch | 1076 +++-------------- uboot-tools.spec | 12 +- 2 files changed, 204 insertions(+), 884 deletions(-) diff --git a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch index 30012ad..d127522 100644 --- a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch +++ b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch @@ -1,920 +1,236 @@ -From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001 +From a23687b77c1e0b5be7f0443e5fba9d9bb7514b6b Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Sat, 31 Dec 2022 09:20:34 +0000 -Subject: [PATCH v2 0/2] Initial support for Pinephone Pro +Date: Sun, 1 Jan 2023 02:11:29 +0000 +Subject: [PATCH] rockchip: pinephone pro: add initial display support -This adds initial support for the PINE64 Pinephone Pro. It's a rebase -to upstream core rk3399 DT pieces, and the addition of the upstream -PPP DT from 6.2-rc1 and the U-Boot pieces are based on my work on -the Pinebook Pro. +Add proposed upstream DT patches for display, disable edp, +enable mipi and backlight, add required clocks. -Changes v2: -- Drop the rk3399.dtsi sync for time being, causing issues around - clock/dram -- Sync the Pinephone DT to 6.2-rc1 -- Update for the CONFIG_SYS_TEXT_BASE -> CONFIG_TEXT_BASE change -- usb: ohci: Use a flexible array member for portstatus -- Rename CONFIG_DM_VIDEO to CONFIG_VIDEO -- Enable DM_REGULATOR_FAN53555 -- Don't initialize i2c before relocation - -Peter Robinson (2): - arm64: dts: rk3399: Add upstream Pinephone Pro dts - rockchip: Add initial support for the PINE64 Pinephone Pro - - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++ - arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++ - arch/arm/mach-rockchip/rk3399/Kconfig | 8 + - board/pine64/pinephone-pro-rk3399/Kconfig | 15 + - board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + - board/pine64/pinephone-pro-rk3399/Makefile | 1 + - .../pinephone-pro-rk3399.c | 76 +++ - configs/pinephone-pro-rk3399_defconfig | 104 ++++ - include/configs/pinephone-pro-rk3399.h | 19 + - 10 files changed, 737 insertions(+) - create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts - create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig - create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS - create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile - create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c - create mode 100644 configs/pinephone-pro-rk3399_defconfig - create mode 100644 include/configs/pinephone-pro-rk3399.h - --- -2.39.0 - -From 9976caacb35316cbe047ded58855d2ca1a54243b Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sat, 31 Dec 2022 09:18:44 +0000 -Subject: [PATCH v2 1/2] arm64: dts: rk3399: Add upstream Pinephone Pro dts - -Initial support for the PinePhone Pro has now landed upstream in -Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support. +Clocks may not be required based on upstream review. Still +need to add panel pieces, the rk3288-evb has an example for +panel DT for u-boot, or may need to do a mipi addition to +simple-panel, or something else. Signed-off-by: Peter Robinson --- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-pinephone-pro.dts | 474 ++++++++++++++++++++++++++ - 2 files changed, 475 insertions(+) - create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts + arch/arm/dts/rk3399-pinephone-pro.dts | 123 +++++++++++++++++++++++++ + configs/pinephone-pro-rk3399_defconfig | 3 +- + include/dt-bindings/clock/rk3399-cru.h | 2 + + 3 files changed, 127 insertions(+), 1 deletion(-) -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 43951a7731e..8c1eec1025f 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -153,6 +153,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-nanopi-r4s.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ -+ rk3399-pinephone-pro.dtb \ - rk3399-puma-haikou.dtb \ - rk3399-roc-pc.dtb \ - rk3399-roc-pc-mezzanine.dtb \ diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts -new file mode 100644 -index 00000000000..04403a76238 ---- /dev/null +index 04403a76238..d0609d1b534 100644 +--- a/arch/arm/dts/rk3399-pinephone-pro.dts +++ b/arch/arm/dts/rk3399-pinephone-pro.dts -@@ -0,0 +1,474 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Martijn Braam -+ * Copyright (c) 2021 Kamil Trzciński -+ */ -+ -+/* -+ * PinePhone Pro datasheet: -+ * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf -+ */ -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Pine64 PinePhonePro"; -+ compatible = "pine64,pinephone-pro", "rockchip,rk3399"; -+ chassis-type = "handset"; -+ -+ aliases { -+ mmc0 = &sdio0; -+ mmc1 = &sdmmc; -+ mmc2 = &sdhci; +@@ -29,6 +29,12 @@ + stdout-path = "serial2:115200n8"; + }; + ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm0 0 1000000 0>; ++ pwm-delay-us = <10000>; + }; + -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; +@@ -102,6 +108,32 @@ + /* WL_REG_ON on module */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwrbtn_pin>; -+ -+ key-power { -+ debounce-interval = <20>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ vcc_sys: vcc-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcca1v8_s3: vcc1v8-s3-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca1v8_s3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vcc1v8_codec: vcc1v8-codec-regulator { ++ /* MIPI DSI panel 1.8v supply */ ++ vcc1v8_lcd: vcc1v8-lcd-regulator { + compatible = "regulator-fixed"; + enable-active-high; -+ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc1v8_codec_en>; -+ regulator-name = "vcc1v8_codec"; ++ regulator-name = "vcc1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ wifi_pwrseq: sdio-wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk818 1>; -+ clock-names = "ext_clock"; ++ gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h_pin>; -+ /* -+ * Wait between power-on and SDIO access for CYP43455 -+ * POR circuit. -+ */ -+ post-power-on-delay-ms = <110>; -+ /* -+ * Wait between consecutive toggles for CYP43455 CBUCK -+ * regulator discharge. -+ */ -+ power-off-delay-us = <10000>; -+ -+ /* WL_REG_ON on module */ -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&display_pwren1>; + }; -+}; + -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk818: pmic@1c { -+ compatible = "rockchip,rk818"; -+ reg = <0x1c>; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; ++ /* MIPI DSI panel 2.8v supply */ ++ vcc2v8_lcd: vcc2v8-lcd-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ regulator-name = "vcc2v8_lcd"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <&vcc3v3_sys>; ++ gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ -+ regulators { -+ vdd_cpu_l: DCDC_REG1 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <875000>; -+ regulator-max-microvolt = <975000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_center: DCDC_REG2 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG1 { -+ regulator-name = "vcca3v0_codec"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ }; -+ -+ vcc3v0_touch: LDO_REG2 { -+ regulator-name = "vcc3v0_touch"; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ }; -+ -+ vcca1v8_codec: LDO_REG3 { -+ regulator-name = "vcca1v8_codec"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ rk818_pwr_on: LDO_REG4 { -+ regulator-name = "rk818_pwr_on"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG5 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG7 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ vcc3v3_s3: LDO_REG8 { -+ regulator-name = "vcc3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG9 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG { -+ regulator-name = "vcc3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ }; ++ pinctrl-0 = <&display_pwren>; + }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_pin>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <875000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_pin>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <875000>; -+ regulator-max-microvolt = <975000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&cluster0_opp { -+ opp04 { -+ status = "disabled"; -+ }; -+ -+ opp05 { -+ status = "disabled"; -+ }; -+}; -+ -+&cluster1_opp { -+ opp06 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <1100000 1100000 1150000>; -+ }; -+ -+ opp07 { -+ status = "disabled"; -+ }; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc1v8_dvp>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vccio_sd>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ buttons { -+ pwrbtn_pin: pwrbtn-pin { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_pin: vsel1-pin { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_pin: vsel2-pin { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h_pin: wifi-enable-h-pin { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sound { -+ vcc1v8_codec_en: vcc1v8-codec-en { -+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ wireless-bluetooth { -+ bt_wake_pin: bt-wake-pin { -+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_pin: bt-host-wake-pin { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reset_pin: bt-reset-pin { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ disable-wp; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ max-frequency = <150000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v3_sys>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rk818 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ max-speed = <1500000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_1v8>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; --- -2.39.0 - -From 004af623388022d258cbc29c0b71d8e22cd96c52 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 28 Dec 2022 03:52:27 +0000 -Subject: [PATCH v2 2/2] rockchip: Add initial support for the PINE64 Pinephone - Pro - -The Pinephone Pro is another device by PINE64. It's closely related -to the Pinebook Pro of which this initial support is derived from. - -Specification: -- A variant of the Rockchip RK3399 -- A 6 inch 720*1440 DSI display -- Front and rear cameras -- Type-C interface with alt mode display (DP 1.2) and PD charging -- 4GB LPDDR4 RAM -- 128GB eMMC -- mSD card slot -- An AP6255 module for 802.11ac WiFi and Bluetooth 5 -- Quectel EG25-G 4G/LTE modem - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 31 ++++++ - arch/arm/mach-rockchip/rk3399/Kconfig | 8 ++ - board/pine64/pinephone-pro-rk3399/Kconfig | 15 +++ - board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 ++ - board/pine64/pinephone-pro-rk3399/Makefile | 1 + - .../pinephone-pro-rk3399.c | 76 +++++++++++++ - configs/pinephone-pro-rk3399_defconfig | 104 ++++++++++++++++++ - include/configs/pinephone-pro-rk3399.h | 19 ++++ - 8 files changed, 262 insertions(+) - create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi - create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig - create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS - create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile - create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c - create mode 100644 configs/pinephone-pro-rk3399_defconfig - create mode 100644 include/configs/pinephone-pro-rk3399.h - -diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -new file mode 100644 -index 00000000000..1dad283ad05 ---- /dev/null -+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -@@ -0,0 +1,31 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2022 Peter Robinson -+ */ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+ -+/ { -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+ -+ config { -+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ -+ }; -+}; -+ -+&rng { -+ status = "okay"; -+}; -+ -+&sdhci { -+ max-frequency = <25000000>; -+ u-boot,dm-pre-reloc; -+}; -+ -+&sdmmc { -+ max-frequency = <20000000>; -+ u-boot,dm-pre-reloc; -+}; -diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig -index b48feeb3466..d01063ac98b 100644 ---- a/arch/arm/mach-rockchip/rk3399/Kconfig -+++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -39,6 +39,13 @@ config TARGET_PINEBOOK_PRO_RK3399 - with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, - 1920*1080 screen and all the usual laptop features. + }; -+config TARGET_PINEPHONE_PRO_RK3399 -+ bool "PinePhone Pro" -+ help -+ PinePhone Pro is a phone based on a variant of the Rockchip -+ rk3399 SoC with 4Gb RAM, onboard eMMC, USB-C, headphone jack, -+ 720x1440 screen and a Quectel 4G/LTE modem. + &cpu_l0 { +@@ -132,6 +164,11 @@ + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; + - config TARGET_PUMA_RK3399 - bool "Theobroma Systems RK3399-Q7 (Puma)" - help -@@ -165,6 +172,7 @@ endif # BOOTCOUNT_LIMIT - source "board/firefly/roc-pc-rk3399/Kconfig" - source "board/google/gru/Kconfig" - source "board/pine64/pinebook-pro-rk3399/Kconfig" -+source "board/pine64/pinephone-pro-rk3399/Kconfig" - source "board/pine64/rockpro64_rk3399/Kconfig" - source "board/rockchip/evb_rk3399/Kconfig" - source "board/theobroma-systems/puma_rk3399/Kconfig" -diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig -new file mode 100644 -index 00000000000..13d6465ae6e ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_PINEPHONE_PRO_RK3399 + &i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; +@@ -214,6 +251,9 @@ + regulator-name = "vcc3v0_touch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; + }; + + vcca1v8_codec: LDO_REG3 { +@@ -347,6 +387,25 @@ + }; + }; + ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; + -+config SYS_BOARD -+ default "pinephone-pro-rk3399" ++ touchscreen@14 { ++ compatible = "goodix,gt917s"; ++ reg = <0x14>; ++ interrupt-parent = <&gpio3>; ++ interrupts = ; ++ irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; ++ AVDD28-supply = <&vcc3v0_touch>; ++ VDDIO-supply = <&vcc3v0_touch>; ++ touchscreen-size-x = <720>; ++ touchscreen-size-y = <1440>; ++ }; ++}; + -+config SYS_VENDOR -+ default "pine64" + &io_domains { + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; +@@ -355,6 +414,40 @@ + status = "okay"; + }; + ++&mipi_dsi { ++ status = "okay"; ++ clock-master; + -+config SYS_CONFIG_NAME -+ default "pinephone-pro-rk3399" ++ ports { ++ mipi_out: port@1 { ++ #address-cells = <0>; ++ #size-cells = <0>; ++ reg = <1>; + -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y ++ mipi_out_panel: endpoint { ++ remote-endpoint = <&mipi_in_panel>; ++ }; ++ }; ++ }; + -+endif -diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS -new file mode 100644 -index 00000000000..c923ff1be32 ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS -@@ -0,0 +1,8 @@ -+PINEPHONE_PRO -+M: Peter Robinson -+S: Maintained -+F: board/pine64/rk3399-pinephone-pro/ -+F: include/configs/rk3399-pinephone-pro.h -+F: arch/arm/dts/rk3399-pinephone-pro.dts -+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi -+F: configs/pinephone-pro-rk3399_defconfig -diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile -new file mode 100644 -index 00000000000..8d9203053e5 ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/Makefile -@@ -0,0 +1 @@ -+obj-y += pinephone-pro-rk3399.o -diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -new file mode 100644 -index 00000000000..eb639cd0d07 ---- /dev/null -+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd -+ * (C) Copyright 2022 Peter Robinson -+ */ ++ panel@0 { ++ compatible = "hannstar,hsd060bhw4"; ++ reg = <0>; ++ backlight = <&backlight>; ++ reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; ++ vcc-supply = <&vcc2v8_lcd>; ++ iovcc-supply = <&vcc1v8_lcd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&display_rst_l>; + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++ port { ++ mipi_in_panel: endpoint { ++ remote-endpoint = <&mipi_out_panel>; ++ }; ++ }; ++ }; ++}; + -+#define GRF_IO_VSEL_BT565_SHIFT 0 -+#define PMUGRF_CON0_VSEL_SHIFT 8 + &pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +@@ -387,6 +480,20 @@ + }; + }; + ++ dsi { ++ display_rst_l: display-rst-l { ++ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; + -+#ifndef CONFIG_SPL_BUILD -+int board_early_init_f(void) -+{ -+ struct udevice *regulator; -+ int ret; ++ display_pwren: display-pwren { ++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; + -+ ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); -+ if (ret) { -+ pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); -+ goto out; -+ } ++ display_pwren1: display-pwren1 { ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; + -+ ret = regulator_set_enable(regulator, true); -+ if (ret) -+ pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); + sound { + vcc1v8_codec_en: vcc1v8-codec-en { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; +@@ -422,6 +529,10 @@ + status = "okay"; + }; + ++&pwm0 { ++ status = "okay"; ++}; + -+out: -+ return 0; -+} -+#endif + &sdmmc { + bus-width = <4>; + cap-sd-highspeed; +@@ -472,3 +583,15 @@ + &uart2 { + status = "okay"; + }; + -+#ifdef CONFIG_MISC_INIT_R -+static void setup_iodomain(void) -+{ -+ struct rk3399_grf_regs *grf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ struct rk3399_pmugrf_regs *pmugrf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); ++&vopb { ++ status = "okay"; ++ assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, ++ <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; ++ assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; ++ assigned-clock-parents = <&cru PLL_CPLL>, <&cru DCLK_VOP0_FRAC>; ++}; + -+ /* BT565 is in 1.8v domain */ -+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); -+ -+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ -+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); -+} -+ -+int misc_init_r(void) -+{ -+ const u32 cpuid_offset = 0x7; -+ const u32 cpuid_length = 0x10; -+ u8 cpuid[cpuid_length]; -+ int ret; -+ -+ setup_iodomain(); -+ -+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); -+ if (ret) -+ return ret; -+ -+ ret = rockchip_cpuid_set(cpuid, cpuid_length); -+ if (ret) -+ return ret; -+ -+ return ret; -+} -+#endif ++&vopb_mmu { ++ status = "okay"; ++}; diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig -new file mode 100644 -index 00000000000..eb979f6c051 ---- /dev/null +index eb979f6c051..25941abc93a 100644 +--- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig -@@ -0,0 +1,104 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x8000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_PINEPHONE_PRO_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI=y -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -+CONFIG_BOOTDELAY=3 -+CONFIG_USE_PREBOOT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x2e000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK=0x400000 -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_SPL_SPI_LOAD=y -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_SPI_FLASH=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SPL_DM_SEQ_ALIAS=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_DM_KEYBOARD=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_SF_DEFAULT_BUS=1 -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_TYPEC=y -+CONFIG_DM_PMIC_FAN53555=y -+CONFIG_DM_REGULATOR_FAN53555=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_DM_RESET=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_EDP=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y -diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h -new file mode 100644 -index 00000000000..78017d6bcc3 ---- /dev/null -+++ b/include/configs/pinephone-pro-rk3399.h -@@ -0,0 +1,19 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd -+ * Copyright (C) 2022 Peter Robinson -+ */ -+ -+#ifndef __PINEPHONE_PRO_RK3399_H -+#define __PINEPHONE_PRO_RK3399_H -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdin=serial,usbkbd\0" \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#include -+ -+#define SDRAM_BANK_SIZE (2UL << 30) -+ -+#endif +@@ -99,6 +99,7 @@ CONFIG_USB_ETHER_RTL8152=y + CONFIG_DISPLAY=y + CONFIG_VIDEO=y + CONFIG_VIDEO_ROCKCHIP=y +-CONFIG_DISPLAY_ROCKCHIP_EDP=y ++CONFIG_DISPLAY_ROCKCHIP_MIPI=y ++CONFIG_BACKLIGHT_PWM=y + CONFIG_SPL_TINY_MEMSET=y + CONFIG_ERRNO_STR=y +diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h +index 211faf8fa89..7866e5266d2 100644 +--- a/include/dt-bindings/clock/rk3399-cru.h ++++ b/include/dt-bindings/clock/rk3399-cru.h +@@ -131,6 +131,8 @@ + #define DCLK_VOP0_DIV 182 + #define DCLK_VOP1_DIV 183 + #define DCLK_M0_PERILP 184 ++#define DCLK_VOP0_FRAC 185 ++#define DCLK_VOP1_FRAC 186 + + #define FCLK_CM0S 190 + -- -2.39.0 +2.39.1 + diff --git a/uboot-tools.spec b/uboot-tools.spec index b2f73a8..60a8786 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,4 @@ -#global candidate rc4 +%global candidate rc1 %if 0%{?rhel} %bcond_with toolsonly %else @@ -6,8 +6,8 @@ %endif Name: uboot-tools -Version: 2023.01 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Version: 2023.04 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -179,7 +179,7 @@ done %endif %endif -for tool in bmp_logo dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc ifwitool img2srec kwboot mkeficapsule mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder ubsha1 xway-swap-bytes +for tool in dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc ifwitool img2srec kwboot mkeficapsule mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder ubsha1 xway-swap-bytes do install -p -m 0755 builds/tools/$tool %{buildroot}%{_bindir} done @@ -211,6 +211,10 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %endif %changelog +* Tue Jan 31 2023 Peter Robinson - 2023.04-0.1.rc1 +- Update to 2023.04 RC1 +- Drop bmp_logo tool + * Sat Jan 21 2023 Fedora Release Engineering - 2023.01-2 - Rebuilt for https://fedoraproject.org/wiki/Fedora_38_Mass_Rebuild