From 64787aacdcac3ee239f8e25d207d69fd05600a5b Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 6 Mar 2018 10:18:40 +0000 Subject: [PATCH] 2018.03 RC4, DragonBoard patch rebase# --- db-generic-fixes.patch | 50 - db410c-fixes.patch | 530 ---------- db820c-support.patch | 2149 --------------------------------------- dragonboard-fixes.patch | 130 ++- sources | 2 +- uboot-tools.spec | 15 +- 6 files changed, 94 insertions(+), 2782 deletions(-) delete mode 100644 db-generic-fixes.patch delete mode 100644 db410c-fixes.patch delete mode 100644 db820c-support.patch diff --git a/db-generic-fixes.patch b/db-generic-fixes.patch deleted file mode 100644 index b81ef13..0000000 --- a/db-generic-fixes.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 7921dacbe23c5430c8a6e12a7d3201eb55372297 Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Thu, 14 Dec 2017 12:09:07 +0100 -Subject: [PATCH 01/15] spmi: msm: display the PMIC Arb version (debug) - -Signed-off-by: Jorge Ramirez-Ortiz ---- - drivers/spmi/spmi-msm.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c -index c226913f9e..e9bfbb0203 100644 ---- a/drivers/spmi/spmi-msm.c -+++ b/drivers/spmi/spmi-msm.c -@@ -17,6 +17,11 @@ - - DECLARE_GLOBAL_DATA_PTR; - -+ -+/* PMIC Arbiter configuration registers */ -+#define PMIC_ARB_VERSION 0x0000 -+#define PMIC_ARB_VERSION_V2_MIN 0x20010000 -+ - #define ARB_CHANNEL_OFFSET(n) (0x4 * (n)) - #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000) - -@@ -148,6 +153,8 @@ static int msm_spmi_probe(struct udevice *dev) - struct udevice *parent = dev->parent; - struct msm_spmi_priv *priv = dev_get_priv(dev); - int node = dev_of_offset(dev); -+ u32 hw_ver; -+ bool is_v1; - int i; - - priv->arb_chnl = devfdt_get_addr(dev); -@@ -155,6 +162,12 @@ static int msm_spmi_probe(struct udevice *dev) - dev_of_offset(parent), node, "reg", 1, NULL, false); - priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, - dev_of_offset(parent), node, "reg", 2, NULL, false); -+ -+ hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800); -+ is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN); -+ -+ dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver); -+ - if (priv->arb_chnl == FDT_ADDR_T_NONE || - priv->spmi_core == FDT_ADDR_T_NONE || - priv->spmi_obs == FDT_ADDR_T_NONE) --- -2.14.3 diff --git a/db410c-fixes.patch b/db410c-fixes.patch deleted file mode 100644 index d76607f..0000000 --- a/db410c-fixes.patch +++ /dev/null @@ -1,530 +0,0 @@ -From 38527d254b1d2c439c9e3ebbe2c82ecd7c729023 Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Wed, 13 Dec 2017 21:55:10 +0100 -Subject: [PATCH 09/15] db410c: configs: increase gunzip buffer size for the - kernel - -the kernel fails to boot when it goes over the limit. - -Signed-off-by: Jorge Ramirez-Ortiz ---- - include/configs/dragonboard410c.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h -index d2447b27d8..3c5bb8a678 100644 ---- a/include/configs/dragonboard410c.h -+++ b/include/configs/dragonboard410c.h -@@ -23,7 +23,7 @@ - #define CONFIG_SYS_TEXT_BASE 0x80080000 - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) --#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */ -+#define CONFIG_SYS_BOOTM_LEN SZ_64M - - /* UART */ - --- -2.14.3 - -From ddc4e0d38d32d6a8a65780cf00a337c639628ca1 Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Thu, 14 Dec 2017 11:12:12 +0100 -Subject: [PATCH 10/15] db410c: update wlan and bt mac addresses from firmware - -The firmware that runs before u-boot modifies u-boot's device tree -adding the local-mac-address and local-bd-address properties for the -compatibles "qcom,wcnss-bt" and "qcom,wcnss-wlan". - -This commit reads that firmware, retrieves the properties and fixups -the device tree that is passed to the kernel before booting. - -Signed-off-by: Jorge Ramirez-Ortiz ---- - arch/arm/dts/dragonboard410c.dts | 10 +++++ - board/qualcomm/dragonboard410c/Makefile | 1 + - board/qualcomm/dragonboard410c/dragonboard410c.c | 49 +++++++++++++++++++++--- - board/qualcomm/dragonboard410c/lowlevel_init.S | 28 ++++++++++++++ - configs/dragonboard410c_defconfig | 3 ++ - 5 files changed, 85 insertions(+), 6 deletions(-) - create mode 100644 board/qualcomm/dragonboard410c/lowlevel_init.S - -diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts -index 7746622dda..25aeac46b1 100644 ---- a/arch/arm/dts/dragonboard410c.dts -+++ b/arch/arm/dts/dragonboard410c.dts -@@ -86,6 +86,16 @@ - clock-frequency = <200000000>; - }; - -+ wcnss { -+ bt { -+ compatible="qcom,wcnss-bt"; -+ }; -+ -+ wifi { -+ compatible="qcom,wcnss-wlan"; -+ }; -+ }; -+ - spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>; -diff --git a/board/qualcomm/dragonboard410c/Makefile b/board/qualcomm/dragonboard410c/Makefile -index cd678088fa..5082383be4 100644 ---- a/board/qualcomm/dragonboard410c/Makefile -+++ b/board/qualcomm/dragonboard410c/Makefile -@@ -5,4 +5,5 @@ - # - - obj-y := dragonboard410c.o -+obj-y += lowlevel_init.o - extra-y += head.o -diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c -index 848e27848b..9e5242170d 100644 ---- a/board/qualcomm/dragonboard410c/dragonboard410c.c -+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c -@@ -10,9 +10,16 @@ - #include - #include - #include -+#include - - DECLARE_GLOBAL_DATA_PTR; - -+/* pointer to the device tree ammended by the firmware */ -+extern const void *fw_dtb; -+ -+static char wlan_mac[ARP_HLEN]; -+static char bt_mac[ARP_HLEN]; -+ - int dram_init(void) - { - gd->ram_size = PHYS_SDRAM_1_SIZE; -@@ -27,7 +34,6 @@ int dram_init_banksize(void) - return 0; - } - -- - int board_prepare_usb(enum usb_init_type type) - { - static struct udevice *pmic_gpio; -@@ -96,11 +102,6 @@ int board_prepare_usb(enum usb_init_type type) - return 0; - } - --int board_init(void) --{ -- return 0; --} -- - /* Check for vol- button - if pressed - stop autoboot */ - int misc_init_r(void) - { -@@ -134,3 +135,39 @@ int misc_init_r(void) - - return 0; - } -+ -+int board_init(void) -+{ -+ int offset, len; -+ const char *mac; -+ -+ /* take a copy of the firmware information (the user could unknownly -+ overwrite that DDR via tftp or other means) */ -+ -+ offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-wlan"); -+ if (offset >= 0) { -+ mac = fdt_getprop(fw_dtb, offset, "local-mac-address", &len); -+ if (mac) -+ memcpy(wlan_mac, mac, ARP_HLEN); -+ } -+ -+ offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-bt"); -+ if (offset >= 0) { -+ mac = fdt_getprop(fw_dtb, offset, "local-bd-address", &len); -+ if (mac) -+ memcpy(bt_mac, mac, ARP_HLEN); -+ } -+ -+ return 0; -+} -+ -+int ft_board_setup(void *blob, bd_t *bd) -+{ -+ do_fixup_by_compat(blob, "qcom,wcnss-wlan", "local-mac-address", -+ wlan_mac, ARP_HLEN, 1); -+ -+ do_fixup_by_compat(blob, "qcom,wcnss-bt", "local-bd-address", -+ bt_mac, ARP_HLEN, 1); -+ -+ return 0; -+} -diff --git a/board/qualcomm/dragonboard410c/lowlevel_init.S b/board/qualcomm/dragonboard410c/lowlevel_init.S -new file mode 100644 -index 0000000000..15b2d0c7fd ---- /dev/null -+++ b/board/qualcomm/dragonboard410c/lowlevel_init.S -@@ -0,0 +1,28 @@ -+/* -+ * (C) Copyright 2016 -+ * Cédric Schieli -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+ -+.align 8 -+.global fw_dtb -+fw_dtb: -+ .dword 0x0 -+ -+/* -+ * Routine: save_boot_params (called after reset from start.S) -+ * Description: save ATAG/FDT address provided by the firmware at boot time -+ */ -+ -+.global save_boot_params -+save_boot_params: -+ -+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */ -+ adr x8, fw_dtb -+ str x0, [x8] -+ -+ /* Returns */ -+ b save_boot_params_ret -diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig -index b71bff7592..cfe9be97f3 100644 ---- a/configs/dragonboard410c_defconfig -+++ b/configs/dragonboard410c_defconfig -@@ -44,3 +44,6 @@ CONFIG_USB_ETHER_ASIX88179=y - CONFIG_USB_ETHER_MCS7830=y - CONFIG_USB_ETHER_SMSC95XX=y - CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_CONTROL=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_OF_BOARD_SETUP=y --- -2.14.3 - -From 5bdb47f83df86729d770601e294207dc42fb68be Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Thu, 21 Dec 2017 11:27:56 +0100 -Subject: [PATCH 11/15] db410c: replace reset driver with psci - -this should be the norm for armv8 platforms. - -Signed-off-by: Jorge Ramirez-Ortiz ---- - arch/arm/dts/dragonboard410c.dts | 5 --- - board/qualcomm/dragonboard410c/dragonboard410c.c | 5 +++ - configs/dragonboard410c_defconfig | 2 +- - drivers/sysreset/Makefile | 2 -- - drivers/sysreset/sysreset_snapdragon.c | 40 ------------------------ - 5 files changed, 6 insertions(+), 48 deletions(-) - delete mode 100644 drivers/sysreset/sysreset_snapdragon.c - -diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts -index 25aeac46b1..b67e58882a 100644 ---- a/arch/arm/dts/dragonboard410c.dts -+++ b/arch/arm/dts/dragonboard410c.dts -@@ -48,11 +48,6 @@ - clock = <&clkc 4>; - }; - -- restart@4ab000 { -- compatible = "qcom,pshold"; -- reg = <0x4ab000 0x4>; -- }; -- - soc_gpios: pinctrl@1000000 { - compatible = "qcom,apq8016-pinctrl"; - reg = <0x1000000 0x300000>; -diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c -index 9e5242170d..1c5ab7b175 100644 ---- a/board/qualcomm/dragonboard410c/dragonboard410c.c -+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c -@@ -171,3 +171,8 @@ int ft_board_setup(void *blob, bd_t *bd) - - return 0; - } -+ -+void reset_cpu(ulong addr) -+{ -+ psci_system_reset(); -+} -diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig -index cfe9be97f3..de923adbc3 100644 ---- a/configs/dragonboard410c_defconfig -+++ b/configs/dragonboard410c_defconfig -@@ -30,7 +30,6 @@ CONFIG_DM_PMIC=y - CONFIG_PMIC_PM8916=y - CONFIG_MSM_SERIAL=y - CONFIG_SPMI_MSM=y --CONFIG_SYSRESET=y - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_USB_EHCI_HCD=y -@@ -47,3 +46,4 @@ CONFIG_OF_LIBFDT_OVERLAY=y - CONFIG_OF_CONTROL=y - CONFIG_ENV_IS_IN_MMC=y - CONFIG_OF_BOARD_SETUP=y -+CONFIG_PSCI_RESET=y -diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile -index 2e9598e300..000c288eeb 100644 ---- a/drivers/sysreset/Makefile -+++ b/drivers/sysreset/Makefile -@@ -8,10 +8,8 @@ obj-$(CONFIG_SYSRESET) += sysreset-uclass.o - obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o - obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o - obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o -- - obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o - obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o --obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o - obj-$(CONFIG_ARCH_STI) += sysreset_sti.o - obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o - obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o -diff --git a/drivers/sysreset/sysreset_snapdragon.c b/drivers/sysreset/sysreset_snapdragon.c -deleted file mode 100644 -index 9869813978..0000000000 ---- a/drivers/sysreset/sysreset_snapdragon.c -+++ /dev/null -@@ -1,40 +0,0 @@ --/* -- * Qualcomm APQ8016 reset controller driver -- * -- * (C) Copyright 2015 Mateusz Kulikowski -- * -- * SPDX-License-Identifier: GPL-2.0+ -- */ -- --#include --#include --#include --#include --#include -- --DECLARE_GLOBAL_DATA_PTR; -- --static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type) --{ -- phys_addr_t addr = devfdt_get_addr(dev); -- if (!addr) -- return -EINVAL; -- writel(0, addr); -- return -EINPROGRESS; --} -- --static struct sysreset_ops msm_sysreset_ops = { -- .request = msm_sysreset_request, --}; -- --static const struct udevice_id msm_sysreset_ids[] = { -- { .compatible = "qcom,pshold" }, -- { } --}; -- --U_BOOT_DRIVER(msm_reset) = { -- .name = "msm_sysreset", -- .id = UCLASS_SYSRESET, -- .of_match = msm_sysreset_ids, -- .ops = &msm_sysreset_ops, --}; --- -2.14.3 - -From 0d607c98eaead3b14b15da821128b920b2bb7b13 Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Thu, 4 Jan 2018 19:27:56 +0100 -Subject: [PATCH 13/15] db410c: use the device tree parsed by the lk loader. - -We dont need to keep copies of the properties that we are going to -fixup since we will be using the dtb provided by the firmware. - -Signed-off-by: Jorge Ramirez-Ortiz ---- - board/qualcomm/dragonboard410c/dragonboard410c.c | 71 ++++++++++++++---------- - configs/dragonboard410c_defconfig | 1 + - 2 files changed, 44 insertions(+), 28 deletions(-) - -diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c -index 1c5ab7b175..236160afd4 100644 ---- a/board/qualcomm/dragonboard410c/dragonboard410c.c -+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c -@@ -15,14 +15,22 @@ - DECLARE_GLOBAL_DATA_PTR; - - /* pointer to the device tree ammended by the firmware */ --extern const void *fw_dtb; -+extern void *fw_dtb; - --static char wlan_mac[ARP_HLEN]; --static char bt_mac[ARP_HLEN]; -+void *board_fdt_blob_setup(void) -+{ -+ if (fdt_magic(fw_dtb) != FDT_MAGIC) { -+ printf("Firmware provided invalid dtb!\n"); -+ return NULL; -+ } -+ -+ return fw_dtb; -+} - - int dram_init(void) - { - gd->ram_size = PHYS_SDRAM_1_SIZE; -+ - return 0; - } - -@@ -138,36 +146,43 @@ int misc_init_r(void) - - int board_init(void) - { -- int offset, len; -- const char *mac; -- -- /* take a copy of the firmware information (the user could unknownly -- overwrite that DDR via tftp or other means) */ -- -- offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-wlan"); -- if (offset >= 0) { -- mac = fdt_getprop(fw_dtb, offset, "local-mac-address", &len); -- if (mac) -- memcpy(wlan_mac, mac, ARP_HLEN); -- } -- -- offset = fdt_node_offset_by_compatible(fw_dtb, -1, "qcom,wcnss-bt"); -- if (offset >= 0) { -- mac = fdt_getprop(fw_dtb, offset, "local-bd-address", &len); -- if (mac) -- memcpy(bt_mac, mac, ARP_HLEN); -- } -- - return 0; - } - - int ft_board_setup(void *blob, bd_t *bd) - { -- do_fixup_by_compat(blob, "qcom,wcnss-wlan", "local-mac-address", -- wlan_mac, ARP_HLEN, 1); -- -- do_fixup_by_compat(blob, "qcom,wcnss-bt", "local-bd-address", -- bt_mac, ARP_HLEN, 1); -+ int offset, len, i; -+ const char *mac; -+ struct { -+ const char *compatible; -+ const char *property; -+ } fix[] = { -+ [0] = { -+ /* update the kernel's dtb with wlan mac */ -+ .compatible = "qcom,wcnss-wlan", -+ .property = "local-mac-address", -+ }, -+ [1] = { -+ /* update the kernel's dtb with bt mac */ -+ .compatible = "qcom,wcnss-bt", -+ .property = "local-bd-address", -+ }, -+ }; -+ -+ for ( i = 0; i < sizeof(fix)/sizeof(fix[0]); i++) { -+ -+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, -+ fix[i].compatible); -+ if (offset < 0) -+ continue; -+ -+ mac = fdt_getprop(gd->fdt_blob, offset, fix[i].property, &len); -+ if (mac) -+ do_fixup_by_compat(blob, -+ fix[i].compatible, -+ fix[i].property, -+ mac, ARP_HLEN, 1); -+ } - - return 0; - } -diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig -index de923adbc3..4389f52b5c 100644 ---- a/configs/dragonboard410c_defconfig -+++ b/configs/dragonboard410c_defconfig -@@ -47,3 +47,4 @@ CONFIG_OF_CONTROL=y - CONFIG_ENV_IS_IN_MMC=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_PSCI_RESET=y -+CONFIG_OF_SEPARATE=y --- -2.14.3 - -From ff6b1225ccc02e5bb963bd72f68a5a36f96ca816 Mon Sep 17 00:00:00 2001 -From: Rob Clark -Date: Wed, 19 Jul 2017 11:40:15 -0400 -Subject: [PATCH 14/15] db410c: add reserved-memory node to dts - -If lk lights up display and populates simple-framebuffer node, it will -also setup a reserved-memory node (needed by simplefb on linux). But -it isn't clever enough to cope when the reserved-memory node is not -present. - -Signed-off-by: Rob Clark ---- - arch/arm/dts/dragonboard410c.dts | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts -index b67e58882a..5ccfe7f8c8 100644 ---- a/arch/arm/dts/dragonboard410c.dts -+++ b/arch/arm/dts/dragonboard410c.dts -@@ -23,11 +23,16 @@ - reg = <0 0x80000000 0 0x3da00000>; - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ - chosen { - stdout-path = "/soc/serial@78b0000"; - }; - -- - soc { - #address-cells = <0x1>; - #size-cells = <0x1>; --- -2.14.3 - -From ab8c14f869c2cdfe09a36619c965785fd60b9a3c Mon Sep 17 00:00:00 2001 -From: Rob Clark -Date: Mon, 26 Jun 2017 10:29:40 -0400 -Subject: [PATCH 15/15] db410c: on aarch64 the fdtfile is in per-vendor - subdirectory - -Signed-off-by: Rob Clark ---- - include/configs/dragonboard410c.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h -index 3c5bb8a678..530d667da8 100644 ---- a/include/configs/dragonboard410c.h -+++ b/include/configs/dragonboard410c.h -@@ -92,7 +92,7 @@ REFLASH(dragonboard/u-boot.img, 8)\ - "initrd_high=0xffffffffffffffff\0" \ - "linux_image=Image\0" \ - "kernel_addr_r=0x81000000\0"\ -- "fdtfile=apq8016-sbc.dtb\0" \ -+ "fdtfile=qcom/apq8016-sbc.dtb\0" \ - "fdt_addr_r=0x83000000\0"\ - "ramdisk_addr_r=0x84000000\0"\ - "scriptaddr=0x90000000\0"\ --- -2.14.3 - diff --git a/db820c-support.patch b/db820c-support.patch deleted file mode 100644 index 2c9f957..0000000 --- a/db820c-support.patch +++ /dev/null @@ -1,2149 +0,0 @@ -From defdef394618d728c47fcf8cd43d523c20ddc4eb Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Mon, 27 Nov 2017 11:59:13 +0100 -Subject: [PATCH 04/15] env: enable accessing the environment in an EXT4 - partition - -For example to store the environment in a file named "/uboot.env" in MMC -"0", where partition "1" contains the EXT4 filesystem, the following -configs should be added to the board's default config: - - CONFIG_ENV_IS_IN_EXT4=y - CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" - CONFIG_ENV_EXT4_FILE="/uboot.env" - CONFIG_ENV_EXT4_INTERFACE="mmc" - -Signed-off-by: Jorge Ramirez-Ortiz ---- - env/Kconfig | 39 +++++++++++++++++++++++++++++++++++++++ - env/env.c | 2 ++ - env/ext4.c | 20 ++++++++++---------- - 3 files changed, 51 insertions(+), 10 deletions(-) - -diff --git a/env/Kconfig b/env/Kconfig -index bef6e89bfc..692f8633b8 100644 ---- a/env/Kconfig -+++ b/env/Kconfig -@@ -81,6 +81,13 @@ config ENV_IS_IN_FAT - - CONFIG_FAT_WRITE: - This must be enabled. Otherwise it cannot save the environment file. - -+config ENV_IS_IN_EXT4 -+ bool "Environment is in a EXT4 filesystem" -+ depends on !CHAIN_OF_TRUST -+ select EXT4_WRITE -+ help -+ Define this if you want to use the EXT4 file system for the environment. -+ - config ENV_IS_IN_FLASH - bool "Environment in flash memory" - depends on !CHAIN_OF_TRUST -@@ -396,6 +403,38 @@ config ENV_FAT_FILE - It's a string of the FAT file name. This file use to store the - environment. - -+config ENV_EXT4_INTERFACE -+ string "Name of the block device for the environment" -+ depends on ENV_IS_IN_EXT4 -+ help -+ Define this to a string that is the name of the block device. -+ -+config ENV_EXT4_DEVICE_AND_PART -+ string "Device and partition for where to store the environemt in EXT4" -+ depends on ENV_IS_IN_EXT4 -+ help -+ Define this to a string to specify the partition of the device. It can -+ be as following: -+ -+ "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1) -+ - "D:P": device D partition P. Error occurs if device D has no -+ partition table. -+ - "D:0": device D. -+ - "D" or "D:": device D partition 1 if device D has partition -+ table, or the whole device D if has no partition -+ table. -+ - "D:auto": first partition in device D with bootable flag set. -+ If none, first valid partition in device D. If no -+ partition table then means device D. -+ -+config ENV_EXT4_FILE -+ string "Name of the EXT4 file to use for the environemnt" -+ depends on ENV_IS_IN_EXT4 -+ default "uboot.env" -+ help -+ It's a string of the EXT4 file name. This file use to store the -+ environment (explicit path to the file) -+ - if ARCH_SUNXI - - config ENV_OFFSET -diff --git a/env/env.c b/env/env.c -index 76a5608628..7455632fd3 100644 ---- a/env/env.c -+++ b/env/env.c -@@ -32,6 +32,8 @@ static enum env_location env_get_default_location(void) - return ENVL_EEPROM; - else if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) - return ENVL_FAT; -+ else if IS_ENABLED(CONFIG_ENV_IS_IN_EXT4) -+ return ENVL_EXT4; - else if IS_ENABLED(CONFIG_ENV_IS_IN_FLASH) - return ENVL_FLASH; - else if IS_ENABLED(CONFIG_ENV_IS_IN_MMC) -diff --git a/env/ext4.c b/env/ext4.c -index 65202213d3..07fd061e4b 100644 ---- a/env/ext4.c -+++ b/env/ext4.c -@@ -46,8 +46,8 @@ static int env_ext4_save(void) - if (err) - return err; - -- part = blk_get_device_part_str(EXT4_ENV_INTERFACE, -- EXT4_ENV_DEVICE_AND_PART, -+ part = blk_get_device_part_str(CONFIG_ENV_EXT4_INTERFACE, -+ CONFIG_ENV_EXT4_DEVICE_AND_PART, - &dev_desc, &info, 1); - if (part < 0) - return 1; -@@ -57,16 +57,16 @@ static int env_ext4_save(void) - - if (!ext4fs_mount(info.size)) { - printf("\n** Unable to use %s %s for saveenv **\n", -- EXT4_ENV_INTERFACE, EXT4_ENV_DEVICE_AND_PART); -+ CONFIG_ENV_EXT4_INTERFACE, CONFIG_ENV_EXT4_DEVICE_AND_PART); - return 1; - } - -- err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t)); -+ err = ext4fs_write(CONFIG_ENV_EXT4_FILE, (void *)&env_new, sizeof(env_t)); - ext4fs_close(); - - if (err == -1) { - printf("\n** Unable to write \"%s\" from %s%d:%d **\n", -- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part); -+ CONFIG_ENV_EXT4_FILE, CONFIG_ENV_EXT4_INTERFACE, dev, part); - return 1; - } - -@@ -84,8 +84,8 @@ static int env_ext4_load(void) - int err; - loff_t off; - -- part = blk_get_device_part_str(EXT4_ENV_INTERFACE, -- EXT4_ENV_DEVICE_AND_PART, -+ part = blk_get_device_part_str(CONFIG_ENV_EXT4_INTERFACE, -+ CONFIG_ENV_EXT4_DEVICE_AND_PART, - &dev_desc, &info, 1); - if (part < 0) - goto err_env_relocate; -@@ -95,16 +95,16 @@ static int env_ext4_load(void) - - if (!ext4fs_mount(info.size)) { - printf("\n** Unable to use %s %s for loading the env **\n", -- EXT4_ENV_INTERFACE, EXT4_ENV_DEVICE_AND_PART); -+ CONFIG_ENV_EXT4_INTERFACE, CONFIG_ENV_EXT4_DEVICE_AND_PART); - goto err_env_relocate; - } - -- err = ext4_read_file(EXT4_ENV_FILE, buf, 0, CONFIG_ENV_SIZE, &off); -+ err = ext4_read_file(CONFIG_ENV_EXT4_FILE, buf, 0, CONFIG_ENV_SIZE, &off); - ext4fs_close(); - - if (err == -1) { - printf("\n** Unable to read \"%s\" from %s%d:%d **\n", -- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part); -+ CONFIG_ENV_EXT4_FILE, CONFIG_ENV_EXT4_INTERFACE, dev, part); - goto err_env_relocate; - } - --- -2.14.3 - -From e346493063ddcd27402f2016a7797919d9237f59 Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Wed, 29 Nov 2017 16:19:30 +0100 -Subject: [PATCH 05/15] arm: mach-snapdragon: refactor clock driver - -In preparation to add support for the Dragonboard820c (APQ8096), -refactor the current Snapdragon clock driver. - -No new functionality has been added. - -Signed-off-by: Jorge Ramirez-Ortiz ---- - arch/arm/mach-snapdragon/Makefile | 5 +- - arch/arm/mach-snapdragon/clock-apq8016.c | 181 ++------------------- - arch/arm/mach-snapdragon/clock-snapdragon.c | 134 +++++++++++++++ - arch/arm/mach-snapdragon/clock-snapdragon.h | 40 +++++ - .../mach-snapdragon/include/mach/sysmap-apq8016.h | 29 +++- - 5 files changed, 216 insertions(+), 173 deletions(-) - create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.c - create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.h - -diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile -index d82a04dda6..d798b82f07 100644 ---- a/arch/arm/mach-snapdragon/Makefile -+++ b/arch/arm/mach-snapdragon/Makefile -@@ -4,5 +4,6 @@ - # SPDX-License-Identifier: GPL-2.0+ - # - --obj-y += clock-apq8016.o --obj-y += sysmap-apq8016.o -+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o -+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -+obj-y += clock-snapdragon.o -diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c -index da05015c32..a2424178c6 100644 ---- a/arch/arm/mach-snapdragon/clock-apq8016.c -+++ b/arch/arm/mach-snapdragon/clock-apq8016.c -@@ -14,146 +14,12 @@ - #include - #include - #include -+#include "clock-snapdragon.h" - - /* GPLL0 clock control registers */ --#define GPLL0_STATUS 0x2101C - #define GPLL0_STATUS_ACTIVE BIT(17) -- --#define APCS_GPLL_ENA_VOTE 0x45000 - #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) - --/* vote reg for blsp1 clock */ --#define APCS_CLOCK_BRANCH_ENA_VOTE 0x45004 --#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10) -- --/* SDC(n) clock control registers; n=1,2 */ -- --/* block control register */ --#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) --/* cmd */ --#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) --/* cfg */ --#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) --/* m */ --#define SDCC_M(n) ((n * 0x1000) + 0x4100C) --/* n */ --#define SDCC_N(n) ((n * 0x1000) + 0x41010) --/* d */ --#define SDCC_D(n) ((n * 0x1000) + 0x41014) --/* branch control */ --#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) --#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) -- --/* BLSP1 AHB clock (root clock for BLSP) */ --#define BLSP1_AHB_CBCR 0x1008 -- --/* Uart clock control registers */ --#define BLSP1_UART2_BCR 0x3028 --#define BLSP1_UART2_APPS_CBCR 0x302C --#define BLSP1_UART2_APPS_CMD_RCGR 0x3034 --#define BLSP1_UART2_APPS_CFG_RCGR 0x3038 --#define BLSP1_UART2_APPS_M 0x303C --#define BLSP1_UART2_APPS_N 0x3040 --#define BLSP1_UART2_APPS_D 0x3044 -- --/* CBCR register fields */ --#define CBCR_BRANCH_ENABLE_BIT BIT(0) --#define CBCR_BRANCH_OFF_BIT BIT(31) -- --struct msm_clk_priv { -- phys_addr_t base; --}; -- --/* Enable clock controlled by CBC soft macro */ --static void clk_enable_cbc(phys_addr_t cbcr) --{ -- setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT); -- -- while (readl(cbcr) & CBCR_BRANCH_OFF_BIT) -- ; --} -- --/* clock has 800MHz */ --static void clk_enable_gpll0(phys_addr_t base) --{ -- if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) -- return; /* clock already enabled */ -- -- setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0); -- -- while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0) -- ; --} -- --#define APPS_CMD_RGCR_UPDATE BIT(0) -- --/* Update clock command via CMD_RGCR */ --static void clk_bcr_update(phys_addr_t apps_cmd_rgcr) --{ -- setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE); -- -- /* Wait for frequency to be updated. */ -- while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE) -- ; --} -- --struct bcr_regs { -- uintptr_t cfg_rcgr; -- uintptr_t cmd_rcgr; -- uintptr_t M; -- uintptr_t N; -- uintptr_t D; --}; -- --/* RCGR_CFG register fields */ --#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */ -- --/* sources */ --#define CFG_CLK_SRC_CXO (0 << 8) --#define CFG_CLK_SRC_GPLL0 (1 << 8) --#define CFG_CLK_SRC_MASK (7 << 8) -- --/* Mask for supported fields */ --#define CFG_MASK 0x3FFF -- --#define CFG_DIVIDER_MASK 0x1F -- --/* root set rate for clocks with half integer and MND divider */ --static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, -- int div, int m, int n, int source) --{ -- uint32_t cfg; -- /* M value for MND divider. */ -- uint32_t m_val = m; -- /* NOT(N-M) value for MND divider. */ -- uint32_t n_val = ~((n)-(m)) * !!(n); -- /* NOT 2D value for MND divider. */ -- uint32_t d_val = ~(n); -- -- /* Program MND values */ -- writel(m_val, base + regs->M); -- writel(n_val, base + regs->N); -- writel(d_val, base + regs->D); -- -- /* setup src select and divider */ -- cfg = readl(base + regs->cfg_rcgr); -- cfg &= ~CFG_MASK; -- cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ -- -- /* Set the divider; HW permits fraction dividers (+0.5), but -- for simplicity, we will support integers only */ -- if (div) -- cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; -- -- if (n_val) -- cfg |= CFG_MODE_DUAL_EDGE; -- -- writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ -- -- /* Inform h/w to start using the new config. */ -- clk_bcr_update(base + regs->cmd_rcgr); --} -- - static const struct bcr_regs sdc_regs[] = { - { - .cfg_rcgr = SDCC_CFG_RCGR(1), -@@ -171,7 +37,14 @@ static const struct bcr_regs sdc_regs[] = { - } - }; - --/* Init clock for SDHCI controller */ -+static struct gpll0_ctrl gpll0_ctrl = { -+ .status = GPLL0_STATUS, -+ .status_bit = GPLL0_STATUS_ACTIVE, -+ .ena_vote = APCS_GPLL_ENA_VOTE, -+ .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, -+}; -+ -+/* SDHCI */ - static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) - { - int div = 8; /* 100MHz default */ -@@ -183,7 +56,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) - /* 800Mhz/div, gpll0 */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, - CFG_CLK_SRC_GPLL0); -- clk_enable_gpll0(priv->base); -+ clk_enable_gpll0(priv->base, &gpll0_ctrl); - clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); - - return rate; -@@ -197,7 +70,7 @@ static const struct bcr_regs uart2_regs = { - .D = BLSP1_UART2_APPS_D, - }; - --/* Init UART clock, 115200 */ -+/* UART: 115200 */ - static int clk_init_uart(struct msm_clk_priv *priv) - { - /* Enable iface clk */ -@@ -205,7 +78,7 @@ static int clk_init_uart(struct msm_clk_priv *priv) - /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, - CFG_CLK_SRC_GPLL0); -- clk_enable_gpll0(priv->base); -+ clk_enable_gpll0(priv->base, &gpll0_ctrl); - /* Enable core clk */ - clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); - -@@ -230,33 +103,3 @@ ulong msm_set_rate(struct clk *clk, ulong rate) - return 0; - } - } -- --static int msm_clk_probe(struct udevice *dev) --{ -- struct msm_clk_priv *priv = dev_get_priv(dev); -- -- priv->base = devfdt_get_addr(dev); -- if (priv->base == FDT_ADDR_T_NONE) -- return -EINVAL; -- -- return 0; --} -- --static struct clk_ops msm_clk_ops = { -- .set_rate = msm_set_rate, --}; -- --static const struct udevice_id msm_clk_ids[] = { -- { .compatible = "qcom,gcc-msm8916" }, -- { .compatible = "qcom,gcc-apq8016" }, -- { } --}; -- --U_BOOT_DRIVER(clk_msm) = { -- .name = "clk_msm", -- .id = UCLASS_CLK, -- .of_match = msm_clk_ids, -- .ops = &msm_clk_ops, -- .priv_auto_alloc_size = sizeof(struct msm_clk_priv), -- .probe = msm_clk_probe, --}; -diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c -new file mode 100644 -index 0000000000..da44544245 ---- /dev/null -+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c -@@ -0,0 +1,134 @@ -+/* -+ * Clock drivers for Qualcomm APQ8016, APQ8096 -+ * -+ * (C) Copyright 2015 Mateusz Kulikowski -+ * -+ * Based on Little Kernel driver, simplified -+ * -+ * SPDX-License-Identifier: BSD-3-Clause -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "clock-snapdragon.h" -+ -+/* CBCR register fields */ -+#define CBCR_BRANCH_ENABLE_BIT BIT(0) -+#define CBCR_BRANCH_OFF_BIT BIT(31) -+ -+extern ulong msm_set_rate(struct clk *clk, ulong rate); -+ -+/* Enable clock controlled by CBC soft macro */ -+void clk_enable_cbc(phys_addr_t cbcr) -+{ -+ setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT); -+ -+ while (readl(cbcr) & CBCR_BRANCH_OFF_BIT) -+ ; -+} -+ -+void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) -+{ -+ if (readl(base + gpll0->status) & gpll0->status_bit) -+ return; /* clock already enabled */ -+ -+ setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); -+ -+ while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) -+ ; -+} -+ -+#define APPS_CMD_RGCR_UPDATE BIT(0) -+ -+/* Update clock command via CMD_RGCR */ -+void clk_bcr_update(phys_addr_t apps_cmd_rgcr) -+{ -+ setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE); -+ -+ /* Wait for frequency to be updated. */ -+ while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE) -+ ; -+} -+ -+#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */ -+ -+#define CFG_MASK 0x3FFF -+ -+#define CFG_DIVIDER_MASK 0x1F -+ -+/* root set rate for clocks with half integer and MND divider */ -+void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, -+ int div, int m, int n, int source) -+{ -+ uint32_t cfg; -+ /* M value for MND divider. */ -+ uint32_t m_val = m; -+ /* NOT(N-M) value for MND divider. */ -+ uint32_t n_val = ~((n)-(m)) * !!(n); -+ /* NOT 2D value for MND divider. */ -+ uint32_t d_val = ~(n); -+ -+ /* Program MND values */ -+ writel(m_val, base + regs->M); -+ writel(n_val, base + regs->N); -+ writel(d_val, base + regs->D); -+ -+ /* setup src select and divider */ -+ cfg = readl(base + regs->cfg_rcgr); -+ cfg &= ~CFG_MASK; -+ cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ -+ -+ /* Set the divider; HW permits fraction dividers (+0.5), but -+ for simplicity, we will support integers only */ -+ if (div) -+ cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; -+ -+ if (n_val) -+ cfg |= CFG_MODE_DUAL_EDGE; -+ -+ writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ -+ -+ /* Inform h/w to start using the new config. */ -+ clk_bcr_update(base + regs->cmd_rcgr); -+} -+ -+static int msm_clk_probe(struct udevice *dev) -+{ -+ struct msm_clk_priv *priv = dev_get_priv(dev); -+ -+ priv->base = devfdt_get_addr(dev); -+ if (priv->base == FDT_ADDR_T_NONE) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static ulong msm_clk_set_rate(struct clk *clk, ulong rate) -+{ -+ return msm_set_rate(clk, rate); -+} -+ -+static struct clk_ops msm_clk_ops = { -+ .set_rate = msm_clk_set_rate, -+}; -+ -+static const struct udevice_id msm_clk_ids[] = { -+ { .compatible = "qcom,gcc-msm8916" }, -+ { .compatible = "qcom,gcc-apq8016" }, -+ { .compatible = "qcom,gcc-msm8996" }, -+ { .compatible = "qcom,gcc-apq8096" }, -+ { } -+}; -+ -+U_BOOT_DRIVER(clk_msm) = { -+ .name = "clk_msm", -+ .id = UCLASS_CLK, -+ .of_match = msm_clk_ids, -+ .ops = &msm_clk_ops, -+ .priv_auto_alloc_size = sizeof(struct msm_clk_priv), -+ .probe = msm_clk_probe, -+}; -diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h -new file mode 100644 -index 0000000000..c087eb9c81 ---- /dev/null -+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h -@@ -0,0 +1,40 @@ -+/* -+ * Qualcomm APQ8016, APQ8096 -+ * -+ * (C) Copyright 2017 Jorge Ramirez-Ortiz -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+#ifndef _CLOCK_SNAPDRAGON_H -+#define _CLOCK_SNAPDRAGON_H -+ -+#define CFG_CLK_SRC_CXO (0 << 8) -+#define CFG_CLK_SRC_GPLL0 (1 << 8) -+#define CFG_CLK_SRC_MASK (7 << 8) -+ -+struct gpll0_ctrl { -+ uintptr_t status; -+ int status_bit; -+ uintptr_t ena_vote; -+ int vote_bit; -+}; -+ -+struct bcr_regs { -+ uintptr_t cfg_rcgr; -+ uintptr_t cmd_rcgr; -+ uintptr_t M; -+ uintptr_t N; -+ uintptr_t D; -+}; -+ -+struct msm_clk_priv { -+ phys_addr_t base; -+}; -+ -+void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0); -+void clk_bcr_update(phys_addr_t apps_cmd_rgcr); -+void clk_enable_cbc(phys_addr_t cbcr); -+void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, -+ int div, int m, int n, int source); -+ -+#endif -diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h -index cdbfad0def..1094b14a80 100644 ---- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h -+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h -@@ -8,7 +8,32 @@ - #ifndef _MACH_SYSMAP_APQ8016_H - #define _MACH_SYSMAP_APQ8016_H - --#define GICD_BASE 0x0b000000 --#define GICC_BASE 0x0a20c000 -+#define GICD_BASE (0x0b000000) -+#define GICC_BASE (0x0a20c000) -+ -+/* Clocks: (from CLK_CTL_BASE) */ -+#define GPLL0_STATUS (0x2101C) -+#define APCS_GPLL_ENA_VOTE (0x45000) -+ -+#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -+#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) -+#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) -+#define SDCC_M(n) ((n * 0x1000) + 0x4100C) -+#define SDCC_N(n) ((n * 0x1000) + 0x41010) -+#define SDCC_D(n) ((n * 0x1000) + 0x41014) -+#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) -+#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) -+ -+/* BLSP1 AHB clock (root clock for BLSP) */ -+#define BLSP1_AHB_CBCR 0x1008 -+ -+/* Uart clock control registers */ -+#define BLSP1_UART2_BCR (0x3028) -+#define BLSP1_UART2_APPS_CBCR (0x302C) -+#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -+#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -+#define BLSP1_UART2_APPS_M (0x303C) -+#define BLSP1_UART2_APPS_N (0x3040) -+#define BLSP1_UART2_APPS_D (0x3044) - - #endif --- -2.14.3 - -From 847d9a003f89d34c6aacc8098e3c1b1ab3bee09b Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Wed, 29 Nov 2017 16:22:35 +0100 -Subject: [PATCH 06/15] db820c: add qualcomm dragonboard 820C support - -This commit adds support for 96Boards Dragonboard820C. - -The board is based on APQ8086 Qualcomm Soc, complying with the -96Boards specification. - -Features - - 4x Kyro CPU (64 bit) up to 2.15GHz - - USB2.0 - - USB3.0 - - ISP - - Qualcomm Hexagon DSP - - SD 3.0 (UHS-I) - - UFS 2.0 - - Qualcomm Adreno 530 GPU - - GPS - - BT 4.2 - - Wi-Fi 2.4GHz, 5GHz (802.11ac) - - PCIe 2.0 - - MIPI-CSI, MIPI-DSI - - I2S - -U-Boot boots chained from LK (LK implements the fastboot protocol) in -64-bit mode. - -For detailed build instructions see readme.txt in the board directory. - -Signed-off-by: Jorge Ramirez-Ortiz ---- - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/dragonboard820c.dts | 65 +++ - arch/arm/mach-snapdragon/Kconfig | 10 + - arch/arm/mach-snapdragon/Makefile | 2 + - arch/arm/mach-snapdragon/clock-apq8096.c | 62 +++ - .../mach-snapdragon/include/mach/sysmap-apq8096.h | 29 ++ - arch/arm/mach-snapdragon/sysmap-apq8096.c | 32 ++ - board/qualcomm/dragonboard820c/Kconfig | 15 + - board/qualcomm/dragonboard820c/MAINTAINERS | 6 + - board/qualcomm/dragonboard820c/Makefile | 8 + - board/qualcomm/dragonboard820c/dragonboard820c.c | 128 ++++++ - board/qualcomm/dragonboard820c/head.S | 34 ++ - board/qualcomm/dragonboard820c/readme.txt | 459 +++++++++++++++++++++ - board/qualcomm/dragonboard820c/u-boot.lds | 106 +++++ - configs/dragonboard820c_defconfig | 36 ++ - include/configs/dragonboard820c.h | 72 ++++ - 16 files changed, 1066 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/dts/dragonboard820c.dts - create mode 100644 arch/arm/mach-snapdragon/clock-apq8096.c - create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h - create mode 100644 arch/arm/mach-snapdragon/sysmap-apq8096.c - create mode 100644 board/qualcomm/dragonboard820c/Kconfig - create mode 100644 board/qualcomm/dragonboard820c/MAINTAINERS - create mode 100644 board/qualcomm/dragonboard820c/Makefile - create mode 100644 board/qualcomm/dragonboard820c/dragonboard820c.c - create mode 100644 board/qualcomm/dragonboard820c/head.S - create mode 100644 board/qualcomm/dragonboard820c/readme.txt - create mode 100644 board/qualcomm/dragonboard820c/u-boot.lds - create mode 100644 configs/dragonboard820c_defconfig - create mode 100644 include/configs/dragonboard820c.h - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index a895c70284..6d0587eda0 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -211,7 +211,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ - fsl-ls1012a-rdb.dtb \ - fsl-ls1012a-frdm.dtb - --dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb -+dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb -+dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb - - dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ - stm32f769-disco.dtb -diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts -new file mode 100644 -index 0000000000..2d49830e77 ---- /dev/null -+++ b/arch/arm/dts/dragonboard820c.dts -@@ -0,0 +1,65 @@ -+/* -+ * Qualcomm APQ8096 based Dragonboard 820C board device tree source -+ * -+ * (C) Copyright 2017 Jorge Ramirez-Ortiz -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+/dts-v1/; -+ -+#include "skeleton64.dtsi" -+ -+/ { -+ model = "Qualcomm Technologies, Inc. DB820c"; -+ compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial0 = &blsp2_uart1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0 0x80000000 0 0xc0000000>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ soc: soc { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0 0 0xffffffff>; -+ compatible = "simple-bus"; -+ -+ gcc: clock-controller@300000 { -+ compatible = "qcom,gcc-msm8996"; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ #power-domain-cells = <1>; -+ reg = <0x300000 0x90000>; -+ }; -+ -+ blsp2_uart1: serial@75b0000 { -+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; -+ reg = <0x75b0000 0x1000>; -+ }; -+ -+ sdhc2: sdhci@74a4900 { -+ compatible = "qcom,sdhci-msm-v4"; -+ reg = <0x74a4900 0x314>, <0x74a4000 0x800>; -+ index = <0x0>; -+ bus-width = <4>; -+ clock = <&gcc 0>; -+ clock-frequency = <200000000>; -+ }; -+ }; -+}; -diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig -index dc7ba21c18..d55dc1aaa1 100644 ---- a/arch/arm/mach-snapdragon/Kconfig -+++ b/arch/arm/mach-snapdragon/Kconfig -@@ -19,8 +19,18 @@ config TARGET_DRAGONBOARD410C - - HDMI - - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons - -+config TARGET_DRAGONBOARD820C -+ bool "96Boards Dragonboard 820C" -+ help -+ Support for 96Boards Dragonboard 820C. This board complies with -+ 96Board Open Platform Specifications. Features: -+ - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU) -+ - 3GiB RAM -+ - 32GiB UFS drive -+ - endchoice - - source "board/qualcomm/dragonboard410c/Kconfig" -+source "board/qualcomm/dragonboard820c/Kconfig" - - endif -diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile -index d798b82f07..090c355b6b 100644 ---- a/arch/arm/mach-snapdragon/Makefile -+++ b/arch/arm/mach-snapdragon/Makefile -@@ -4,6 +4,8 @@ - # SPDX-License-Identifier: GPL-2.0+ - # - -+obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o -+obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o - obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o - obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o - obj-y += clock-snapdragon.o -diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c -new file mode 100644 -index 0000000000..32248121d6 ---- /dev/null -+++ b/arch/arm/mach-snapdragon/clock-apq8096.c -@@ -0,0 +1,62 @@ -+/* -+ * Clock drivers for Qualcomm APQ8096 -+ * -+ * (C) Copyright 2017 Jorge Ramirez Ortiz -+ * -+ * Based on Little Kernel driver, simplified -+ * -+ * SPDX-License-Identifier: BSD-3-Clause -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "clock-snapdragon.h" -+ -+/* GPLL0 clock control registers */ -+#define GPLL0_STATUS_ACTIVE BIT(30) -+#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) -+ -+static const struct bcr_regs sdc_regs = { -+ .cfg_rcgr = SDCC2_CFG_RCGR, -+ .cmd_rcgr = SDCC2_CMD_RCGR, -+ .M = SDCC2_M, -+ .N = SDCC2_N, -+ .D = SDCC2_D, -+}; -+ -+static const struct gpll0_ctrl gpll0_ctrl = { -+ .status = GPLL0_STATUS, -+ .status_bit = GPLL0_STATUS_ACTIVE, -+ .ena_vote = APCS_GPLL_ENA_VOTE, -+ .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, -+}; -+ -+static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) -+{ -+ int div = 3; -+ -+ clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); -+ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, -+ CFG_CLK_SRC_GPLL0); -+ clk_enable_gpll0(priv->base, &gpll0_ctrl); -+ clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); -+ -+ return rate; -+} -+ -+ulong msm_set_rate(struct clk *clk, ulong rate) -+{ -+ struct msm_clk_priv *priv = dev_get_priv(clk->dev); -+ -+ switch (clk->id) { -+ case 0: /* SDC1 */ -+ return clk_init_sdc(priv, rate); -+ break; -+ default: -+ return 0; -+ } -+} -diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h -new file mode 100644 -index 0000000000..fb89de258d ---- /dev/null -+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h -@@ -0,0 +1,29 @@ -+/* -+ * Qualcomm APQ8096 sysmap -+ * -+ * (C) Copyright 2017 Jorge Ramirez-Ortiz -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+#ifndef _MACH_SYSMAP_APQ8096_H -+#define _MACH_SYSMAP_APQ8096_H -+ -+#define TLMM_BASE_ADDR (0x1010000) -+ -+/* Strength (sdc1) */ -+#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) -+ -+/* Clocks: (from CLK_CTL_BASE) */ -+#define GPLL0_STATUS (0x0000) -+#define APCS_GPLL_ENA_VOTE (0x52000) -+ -+#define SDCC2_BCR (0x14000) /* block reset */ -+#define SDCC2_APPS_CBCR (0x14004) /* branch control */ -+#define SDCC2_AHB_CBCR (0x14008) -+#define SDCC2_CMD_RCGR (0x14010) -+#define SDCC2_CFG_RCGR (0x14014) -+#define SDCC2_M (0x14018) -+#define SDCC2_N (0x1401C) -+#define SDCC2_D (0x14020) -+ -+#endif -diff --git a/arch/arm/mach-snapdragon/sysmap-apq8096.c b/arch/arm/mach-snapdragon/sysmap-apq8096.c -new file mode 100644 -index 0000000000..cb6d1e475b ---- /dev/null -+++ b/arch/arm/mach-snapdragon/sysmap-apq8096.c -@@ -0,0 +1,32 @@ -+/* -+ * Qualcomm APQ8096 memory map -+ * -+ * (C) Copyright 2017 Jorge Ramirez Ortiz -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+ -+static struct mm_region apq8096_mem_map[] = { -+ { -+ .virt = 0x0UL, /* Peripheral block */ -+ .phys = 0x0UL, /* Peripheral block */ -+ .size = 0x10000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ .virt = 0x80000000UL, /* DDR */ -+ .phys = 0x80000000UL, /* DDR */ -+ .size = 0xC0000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | -+ PTE_BLOCK_INNER_SHARE -+ }, { -+ /* List terminator */ -+ 0, -+ } -+}; -+ -+struct mm_region *mem_map = apq8096_mem_map; -diff --git a/board/qualcomm/dragonboard820c/Kconfig b/board/qualcomm/dragonboard820c/Kconfig -new file mode 100644 -index 0000000000..aff9af5271 ---- /dev/null -+++ b/board/qualcomm/dragonboard820c/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_DRAGONBOARD820C -+ -+config SYS_BOARD -+ default "dragonboard820c" -+ -+config SYS_VENDOR -+ default "qualcomm" -+ -+config SYS_SOC -+ default "apq8096" -+ -+config SYS_CONFIG_NAME -+ default "dragonboard820c" -+ -+endif -diff --git a/board/qualcomm/dragonboard820c/MAINTAINERS b/board/qualcomm/dragonboard820c/MAINTAINERS -new file mode 100644 -index 0000000000..a157033bf0 ---- /dev/null -+++ b/board/qualcomm/dragonboard820c/MAINTAINERS -@@ -0,0 +1,6 @@ -+DRAGONBOARD820C BOARD -+M: Jorge Ramirez-Ortiz -+S: Maintained -+F: board/qualcomm/dragonboard820c/ -+F: include/configs/dragonboard820c.h -+F: configs/dragonboard820c_defconfig -diff --git a/board/qualcomm/dragonboard820c/Makefile b/board/qualcomm/dragonboard820c/Makefile -new file mode 100644 -index 0000000000..a1ce4b210f ---- /dev/null -+++ b/board/qualcomm/dragonboard820c/Makefile -@@ -0,0 +1,8 @@ -+# -+# (C) Copyright 2017 Jorge Ramirez-Ortiz -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y := dragonboard820c.o -+extra-y += head.o -diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c -new file mode 100644 -index 0000000000..f5dd62e18e ---- /dev/null -+++ b/board/qualcomm/dragonboard820c/dragonboard820c.c -@@ -0,0 +1,128 @@ -+/* -+ * Board init file for Dragonboard 820C -+ * -+ * (C) Copyright 2017 Jorge Ramirez-Ortiz -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+int dram_init(void) -+{ -+ gd->ram_size = PHYS_SDRAM_SIZE; -+ -+ return 0; -+} -+ -+int dram_init_banksize(void) -+{ -+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; -+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -+ -+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; -+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -+ -+ return 0; -+} -+ -+static void sdhci_power_init(void) -+{ -+ const uint32_t TLMM_PULL_MASK = 0x3; -+ const uint32_t TLMM_HDRV_MASK = 0x7; -+ -+ struct tlmm_cfg { -+ uint32_t bit; /* bit in the register */ -+ uint8_t mask; /* mask clk/dat/cmd control */ -+ uint8_t val; -+ }; -+ -+ /* bit offsets in the sdc tlmm register */ -+ enum { SDC1_DATA_HDRV = 0, -+ SDC1_CMD_HDRV = 3, -+ SDC1_CLK_HDRV = 6, -+ SDC1_DATA_PULL = 9, -+ SDC1_CMD_PULL = 11, -+ SDC1_CLK_PULL = 13, -+ SDC1_RCLK_PULL = 15, -+ }; -+ -+ enum { TLMM_PULL_DOWN = 0x1, -+ TLMM_PULL_UP = 0x3, -+ TLMM_NO_PULL = 0x0, -+ }; -+ -+ enum { TLMM_CUR_VAL_10MA = 0x04, -+ TLMM_CUR_VAL_16MA = 0x07, -+ }; -+ int i; -+ -+ /* drive strength configs for sdhc pins */ -+ const struct tlmm_cfg hdrv[] = -+ { -+ { SDC1_CLK_HDRV, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, }, -+ { SDC1_CMD_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, }, -+ { SDC1_DATA_HDRV, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, }, -+ }; -+ -+ /* pull configs for sdhc pins */ -+ const struct tlmm_cfg pull[] = -+ { -+ { SDC1_CLK_PULL, TLMM_NO_PULL, TLMM_PULL_MASK, }, -+ { SDC1_CMD_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, }, -+ { SDC1_DATA_PULL, TLMM_PULL_UP, TLMM_PULL_MASK, }, -+ }; -+ -+ const struct tlmm_cfg rclk[] = -+ { -+ { SDC1_RCLK_PULL, TLMM_PULL_DOWN, TLMM_PULL_MASK,}, -+ }; -+ -+ for (i = 0; i < ARRAY_SIZE(hdrv); i++) -+ clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG, -+ hdrv[i].mask << hdrv[i].bit, -+ hdrv[i].val << hdrv[i].bit); -+ -+ for (i = 0; i < ARRAY_SIZE(pull); i++) -+ clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG, -+ pull[i].mask << pull[i].bit, -+ pull[i].val << pull[i].bit); -+ -+ for (i = 0; i < ARRAY_SIZE(rclk); i++) -+ clrsetbits_le32(SDC1_HDRV_PULL_CTL_REG, -+ rclk[i].mask << rclk[i].bit, -+ rclk[i].val << rclk[i].bit); -+} -+ -+static void show_psci_version(void) -+{ -+ struct arm_smccc_res res; -+ -+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); -+ -+ printf("PSCI: v%ld.%ld\n", -+ PSCI_VERSION_MAJOR(res.a0), -+ PSCI_VERSION_MINOR(res.a0)); -+} -+ -+int board_init(void) -+{ -+ sdhci_power_init(); -+ show_psci_version(); -+ -+ return 0; -+} -+ -+void reset_cpu(ulong addr) -+{ -+ psci_system_reset(); -+} -diff --git a/board/qualcomm/dragonboard820c/head.S b/board/qualcomm/dragonboard820c/head.S -new file mode 100644 -index 0000000000..06d82d5831 ---- /dev/null -+++ b/board/qualcomm/dragonboard820c/head.S -@@ -0,0 +1,34 @@ -+/* -+ * ARM64 header for proper chain-loading with Little Kernel. -+ * -+ * Little Kernel shipped with Dragonboard820C boots standard Linux images for -+ * ARM64. This file adds header that is required to boot U-Boot properly. -+ * -+ * For details see: -+ * https://www.kernel.org/doc/Documentation/arm64/booting.txt -+ * -+ * (C) Copyright 2015 Mateusz Kulikowski -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+ -+/* -+ * per document in linux/Doc/arm64/booting.text -+ */ -+.global _arm64_header -+_arm64_header: -+ b _start -+ .word 0 -+ .quad CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */ -+ .quad 0 /* Effective size of kernel image, little-endian */ -+ .quad 0 /* kernel flags, little-endian */ -+ .quad 0 /* reserved */ -+ .quad 0 /* reserved */ -+ .quad 0 /* reserved */ -+ .byte 0x41 /* Magic number, "ARM\x64" */ -+ .byte 0x52 -+ .byte 0x4d -+ .byte 0x64 -+ .word 0 /* reserved (used for PE COFF offset) */ -diff --git a/board/qualcomm/dragonboard820c/readme.txt b/board/qualcomm/dragonboard820c/readme.txt -new file mode 100644 -index 0000000000..1f310b31c7 ---- /dev/null -+++ b/board/qualcomm/dragonboard820c/readme.txt -@@ -0,0 +1,459 @@ -+# -+# (C) Copyright 2017 Jorge Ramirez-Ortiz -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+================================================================================ -+ What is working (enough to boot a distro from SD card) -+================================================================================ -+ - UART -+ - SD card -+ - PSCI reset -+ - Environment in EXT4 partition 1 in SD card (check defconfig for details) -+ dont forget to insert the card in the SD slot before booting if you -+ are going to make mods to the environment -+ -+================================================================================ -+ Build & Run instructions -+================================================================================ -+ -+1) Install mkbootimg and dtbTool from Codeaurora: -+ -+ git://codeaurora.org/quic/kernel/skales -+ commit 8492547e404e969262d9070dee9bdd15668bb70f worked for me. -+ -+2) Setup CROSS_COMPILE to aarch64 compiler or if you use ccache just do -+ CROSS_COMPILE="ccache aarch64-linux-gnu-" -+ -+3) cd to the u-boot tree -+ -+ $ make dragonboard820c_config -+ $ make -j `nproc` -+ -+4) generate fake, empty ramdisk (can have 0 bytes) -+ -+ $ touch rd -+ -+5) Generate qualcomm device tree table with dtbTool -+ -+ $ dtbTool -o dt.img arch/arm/dts -+ -+6) Generate Android boot image with mkbootimg: -+ -+ $ mkbootimg --kernel=u-boot-dtb.bin \ -+ --output=u-boot.img \ -+ --dt=dt.img \ -+ --pagesize 4096 \ -+ --base 0x80000000 \ -+ --ramdisk=rd \ -+ --cmdline="" -+ -+7) Reboot the board into fastboot mode -+ - plug the board micro-usb to your laptop usb host. -+ - reboot the board with vol- button pressed -+ -+8) Boot the uboot image using fastboot -+ -+ $ fastboot boot u-boot.img -+ -+ or flash it to the UFS drive boot partition: -+ -+ $ fastboot flash boot u-boot.img -+ $ fastboot reboot -+ -+ -+================================================================================ -+ To boot a linux kernel from SDHCI with the ROOTFS on an NFS share: -+================================================================================ -+ -+1) create an EXT4 partition on the SD card (must be partition #1) -+ -+2) build the kernel image and dtb (documented extensively somewhere else) -+ -+3) copy the drivers to the NFS partition (ie: 192.168.1.2 /exports/db820c-rootfs) -+ -+4) add the u-boot headers to the image: -+ -+ $ mkimage -A arm64 \ -+ -O linux \ -+ -C none \ -+ -T kernel \ -+ -a 0x80080000 \ -+ -e 0x80080000 \ -+ -n Dragonboard820c \ -+ -d $kernel/arch/arm64/boot/Image \ -+ uImage -+ -+5) copy the generated uImage and the device tree binary to the SD card EXT4 -+ partition -+ -+ $ cp uImage /mnt/boot/ -+ $ cp apq8096-db820c.dtb /mnt/boot/ -+ -+6) on the SD card create /extlinux/extlinux.conf as follows: -+ -+ default nfs -+ prompt 1 -+ timeout 10 -+ -+ LABEL nfs -+ MENU NFS entry -+ LINUX /uImage -+ FDT /apq8096-db820c.dtb -+ APPEND root=/dev/nfs rw \ -+ nfsroot=192.168.1.2:/exports/db829c-rootfs,v3,tcp \ -+ rootwait \ -+ ip=dhcp consoleblank=0 \ -+ console=tty0 \ -+ console=ttyMSM0,115200n8 \ -+ earlyprintk earlycon=msm_serial_dm,0x75b0000 \ -+ androidboot.bootdevice=624000.ufshc \ -+ androidboot.verifiedbootstate=orange \ -+ androidboot.ver0 -+ -+7) remove the SD card from the laptop and insert it back to the db820 board. -+ the SD card EXT4 partition#1 should contain: -+ /uImage -+ /apq8096-db820c.dtb -+ /extlinux/extlinux.conf -+ -+8) reboot the db820 board -+ -+================================================================================ -+ Successful boot sequence -+================================================================================ -+ -+Format: Log Type - Time(microsec) - Message - Optional Info -+Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic -+S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00301 -+S - IMAGE_VARIANT_STRING=M8996LAB -+S - OEM_IMAGE_VERSION_STRING=crm-ubuntu68 -+S - Boot Interface: UFS -+S - Secure Boot: Off -+S - Boot Config @ 0x00076044 = 0x000001c9 -+S - JTAG ID @ 0x000760f4 = 0x4003e0e1 -+S - OEM ID @ 0x000760f8 = 0x00000000 -+S - Serial Number @ 0x00074138 = 0x2e8844ce -+S - OEM Config Row 0 @ 0x00074188 = 0x0000000000000000 -+S - OEM Config Row 1 @ 0x00074190 = 0x0000000000000000 -+S - Feature Config Row 0 @ 0x000741a0 = 0x0050000010000100 -+S - Feature Config Row 1 @ 0x000741a8 = 0x00fff00001ffffff -+S - Core 0 Frequency, 1228 MHz -+B - 0 - PBL, Start -+B - 10412 - bootable_media_detect_entry, Start -+B - 47480 - bootable_media_detect_success, Start -+B - 47481 - elf_loader_entry, Start -+B - 49027 - auth_hash_seg_entry, Start -+B - 49129 - auth_hash_seg_exit, Start -+B - 82403 - elf_segs_hash_verify_entry, Start -+B - 84905 - PBL, End -+B - 86955 - SBL1, Start -+B - 182969 - usb: hs_phy_nondrive_start -+B - 183305 - usb: PLL lock success - 0x3 -+B - 186294 - usb: hs_phy_nondrive_finish -+B - 190442 - boot_flash_init, Start -+D - 30 - boot_flash_init, Delta -+B - 197548 - sbl1_ddr_set_default_params, Start -+D - 30 - sbl1_ddr_set_default_params, Delta -+B - 205509 - boot_config_data_table_init, Start -+D - 200659 - boot_config_data_table_init, Delta - (60 Bytes) -+B - 410713 - CDT Version:3,Platform ID:24,Major ID:1,Minor ID:0,Subtype:0 -+B - 415410 - Image Load, Start -+D - 22570 - PMIC Image Loaded, Delta - (37272 Bytes) -+B - 437980 - pm_device_init, Start -+B - 443744 - PON REASON:PM0:0x200000061 PM1:0x200000021 -+B - 480161 - PM_SET_VAL:Skip -+D - 40016 - pm_device_init, Delta -+B - 482083 - pm_driver_init, Start -+D - 2928 - pm_driver_init, Delta -+B - 488671 - pm_sbl_chg_init, Start -+D - 91 - pm_sbl_chg_init, Delta -+B - 495442 - vsense_init, Start -+D - 0 - vsense_init, Delta -+B - 505171 - Pre_DDR_clock_init, Start -+D - 396 - Pre_DDR_clock_init, Delta -+B - 509045 - ddr_initialize_device, Start -+B - 512766 - 8996 v3.x detected, Max frequency = 1.8 GHz -+B - 522373 - ddr_initialize_device, Delta -+B - 522404 - DDR ID, Rank 0, Rank 1, 0x6, 0x300, 0x300 -+B - 526247 - Basic DDR tests done -+B - 594994 - clock_init, Start -+D - 274 - clock_init, Delta -+B - 598349 - Image Load, Start -+D - 4331 - QSEE Dev Config Image Loaded, Delta - (46008 Bytes) -+B - 603808 - Image Load, Start -+D - 5338 - APDP Image Loaded, Delta - (0 Bytes) -+B - 612409 - usb: UFS Serial - 2f490ecf -+B - 616801 - usb: fedl, vbus_low -+B - 620431 - Image Load, Start -+D - 55418 - QSEE Image Loaded, Delta - (1640572 Bytes) -+B - 675849 - Image Load, Start -+D - 2013 - SEC Image Loaded, Delta - (4096 Bytes) -+B - 683413 - sbl1_efs_handle_cookies, Start -+D - 457 - sbl1_efs_handle_cookies, Delta -+B - 691892 - Image Load, Start -+D - 14396 - QHEE Image Loaded, Delta - (254184 Bytes) -+B - 706319 - Image Load, Start -+D - 14061 - RPM Image Loaded, Delta - (223900 Bytes) -+B - 721111 - Image Load, Start -+D - 3233 - STI Image Loaded, Delta - (0 Bytes) -+B - 727913 - Image Load, Start -+D - 34709 - APPSBL Image Loaded, Delta - (748716 Bytes) -+B - 762713 - SBL1, End -+D - 680028 - SBL1, Delta -+S - Flash Throughput, 94000 KB/s (2959024 Bytes, 31250 us) -+S - DDR Frequency, 1017 MHz -+Android Bootloader - UART_DM Initialized!!! -+ -+[0] BUILD_VERSION= -+[0] BUILD_DATE=16:07:51 - Nov 17 2017 -+[0] welcome to lk -+[10] platform_init() -+[10] target_init() -+[10] RPM GLink Init -+[10] Opening RPM Glink Port success -+[10] Opening SSR Glink Port success -+[20] Glink Connection between APPS and RPM established -+[20] Glink Connection between APPS and RPM established -+[40] UFS init success -+[80] Qseecom Init Done in Appsbl -+[80] secure app region addr=0x86600000 size=0x2200000[90] TZ App region notif returned with status:0 addr:86600000 size:35651584 -+[100] TZ App log region register returned with status:0 addr:916d4000 size:4096 -+[100] Qseecom TZ Init Done in Appsbl -+[120] Loading cmnlib done -+[120] qseecom_start_app: Loading app keymaster for the first time -+[150] <8>keymaster: "\"KEYMASTER Init \"" -+[160] Selected panel: none -+Skip panel configuration -+[160] pm8x41_get_is_cold_boot: cold boot -+[170] boot_verifier: Device is in ORANGE boot state. -+[180] Device is unlocked! Skipping verification... -+[180] Loading (boot) image (348160): start -+[190] Loading (boot) image (348160): done -+[190] use_signed_kernel=1, is_unlocked=1, is_tampered=0. -+[200] Your device has been unlocked and cant be trusted. -+Wait for 5 seconds before proceeding -+ -+[5200] mdtp: mdtp_img loaded -+[5210] mdtp: is_test_mode: test mode is set to 1 -+[5210] mdtp: read_metadata: SUCCESS -+[5230] LK SEC APP Handle: 0x1 -+[5230] Return value from recv_data: 14 -+[5240] Return value from recv_data: 14 -+[5250] Return value from recv_data: 14 -+[5260] DTB Total entry: 1, DTB version: 3 -+[5260] Using DTB entry 0x00000123/00000000/0x00000018/0 for device 0x00000123/00030001/0x00010018/0 -+[5270] cmdline: androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.veritymode=enforcing androidboot.serialno=2f490ecf androidboot.baseband=apq mdss_mdp.panel=0 -+[5290] Updating device tree: start -+[5290] Updating device tree: done -+[5290] Return value from recv_data: 14 -+[5300] RPM GLINK UnInit -+[5300] Qseecom De-Init Done in Appsbl -+[5300] booting linux @ 0x80080000, ramdisk @ 0x82200000 (0), tags/device tree @ 0x82000000 -+[5310] Jumping to kernel via monitor -+ -+U-Boot 2017.11-00145-ge895117 (Nov 29 2017 - 10:04:06 +0100) -+Qualcomm-DragonBoard 820C -+ -+DRAM: 3 GiB -+PSCI: v1.0 -+MMC: sdhci@74a4900: 0 -+In: serial@75b0000 -+Out: serial@75b0000 -+Err: serial@75b0000 -+Net: Net Initialization Skipped -+No ethernet found. -+Hit any key to stop autoboot: 0 -+switch to partitions #0, OK -+mmc0 is current device -+Scanning mmc 0:1... -+Found /extlinux/extlinux.conf -+Retrieving file: /extlinux/extlinux.conf -+433 bytes read in 71 ms (5.9 KiB/s) -+1: nfs root -+ -+Retrieving file: /uImage -+19397184 bytes read in 2024 ms (9.1 MiB/s) -+append: root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.ver0 -+ -+Retrieving file: /apq8096-db820c.dtb -+38134 bytes read in 37 ms (1005.9 KiB/s) -+ -+## Booting kernel from Legacy Image at 95000000 ... -+ Image Name: Dragonboard820c -+ Image Type: AArch64 Linux Kernel Image (uncompressed) -+ Data Size: 19397120 Bytes = 18.5 MiB -+ Load Address: 80080000 -+ Entry Point: 80080000 -+ Verifying Checksum ... OK -+## Flattened Device Tree blob at 93000000 -+ Booting using the fdt blob at 0x93000000 -+ Loading Kernel Image ... OK -+ Using Device Tree in place at 0000000093000000, end 000000009300c4f5 -+ -+Starting kernel ... -+ -+[ 0.000000] Booting Linux on physical CPU 0x0 -+[ 0.000000] Linux version 4.11.3-30039-g5a922a1 (jramirez@igloo) (gcc version 6.3.1 20170404 (Linaro GCC 6.3-2017.05) ) #1 SMP PREEMPT Wed Oct 18 10:21:11 CEST 2017 -+[ 0.000000] Boot CPU: AArch64 Processor [511f2112] -+[ 0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000075b0000 (options '') -+[ 0.000000] bootconsole [msm_serial_dm0] enabled -+[ 0.000000] efi: Getting EFI parameters from FDT: -+[ 0.000000] efi: UEFI not found. -+[ 0.000000] OF: reserved mem: OVERLAP DETECTED! -+[ 0.000000] adsp@8ea00000 (0x000000008ea00000--0x0000000090400000) overlaps with gpu@8f200000 (0x000000008f200000--0x000000008f300000) -+[ 0.000000] Reserved memory: created DMA memory pool at 0x000000008f200000, size 1 MiB -+[ 0.000000] OF: reserved mem: initialized node gpu@8f200000, compatible id shared-dma-pool -+[ 0.000000] Reserved memory: created DMA memory pool at 0x0000000090400000, size 8 MiB -+[ 0.000000] OF: reserved mem: initialized node venus@90400000, compatible id shared-dma-pool -+[ 0.000000] cma: Reserved 128 MiB at 0x00000000b8000000 -+[ 0.000000] NUMA: No NUMA configuration found -+[ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000bfffffff] -+[ 0.000000] NUMA: Adding memblock [0x80000000 - 0x857fffff] on node 0 -+[ 0.000000] NUMA: Adding memblock [0x91800000 - 0xbfffffff] on node 0 -+[ 0.000000] NUMA: Initmem setup node 0 [mem 0x80000000-0xbfffffff] -+[ 0.000000] NUMA: NODE_DATA [mem 0xb7fb6680-0xb7fb817f] -+[ 0.000000] Zone ranges: -+[ 0.000000] DMA [mem 0x0000000080000000-0x00000000bfffffff] -+[ 0.000000] Normal empty -+[ 0.000000] Movable zone start for each node -+[ 0.000000] Early memory node ranges -+[ 0.000000] node 0: [mem 0x0000000080000000-0x00000000857fffff] -+[ 0.000000] node 0: [mem 0x0000000091800000-0x00000000bfffffff] -+[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000bfffffff] -+[ 0.000000] psci: probing for conduit method from DT. -+[ 0.000000] psci: PSCIv1.0 detected in firmware. -+[ 0.000000] psci: Using standard PSCI v0.2 function IDs -+[ 0.000000] psci: MIGRATE_INFO_TYPE not supported. -+[ 0.000000] percpu: Embedded 23 pages/cpu @ffff8000de9a3000 s57240 r8192 d28776 u94208 -+[ 0.000000] pcpu-alloc: s57240 r8192 d28776 u94208 alloc=23*4096 -+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 -+[ 0.000000] Detected PIPT I-cache on CPU0 -+[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 720293 -+[ 0.000000] Policy zone: Normal -+[ 0.000000] Kernel command line: root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 -+console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange a -+ndroidboot.ver0 -+[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) -+[ 0.000000] software IO TLB [mem 0xd3fff000-0xd7fff000] (64MB) mapped at [ffff800053fff000-ffff800057ffefff] -+[ 0.000000] Memory: 2644172K/2926908K available (11196K kernel code, 1470K rwdata, 5132K rodata, 1088K init, 449K bss, 151664K reserved, 131072K cma-reser -+ved) -+[ 0.000000] Virtual kernel memory layout: -+[ 0.000000] modules : 0xffff000000000000 - 0xffff000008000000 ( 128 MB) -+[ 0.000000] vmalloc : 0xffff000008000000 - 0xffff7dffbfff0000 (129022 GB) -+[ 0.000000] .text : 0xffff000008080000 - 0xffff000008b70000 ( 11200 KB) -+[ 0.000000] .rodata : 0xffff000008b70000 - 0xffff000009080000 ( 5184 KB) -+[ 0.000000] .init : 0xffff000009080000 - 0xffff000009190000 ( 1088 KB) -+[ 0.000000] .data : 0xffff000009190000 - 0xffff0000092ffa00 ( 1471 KB) -+[ 0.000000] .bss : 0xffff0000092ffa00 - 0xffff00000937014c ( 450 KB) -+[ 0.000000] fixed : 0xffff7dfffe7fd000 - 0xffff7dfffec00000 ( 4108 KB) -+[ 0.000000] PCI I/O : 0xffff7dfffee00000 - 0xffff7dffffe00000 ( 16 MB) -+[ 0.000000] vmemmap : 0xffff7e0000000000 - 0xffff800000000000 ( 2048 GB maximum) -+[ 0.000000] 0xffff7e0000000000 - 0xffff7e00037a93c0 ( 55 MB actual) -+[ 0.000000] memory : 0xffff800000000000 - 0xffff8000dea4f000 ( 3562 MB) -+[ 0.000000] SLUB: HWalign=128, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 -+[ 0.000000] Preemptible hierarchical RCU implementation. -+[ 0.000000] Build-time adjustment of leaf fanout to 64. -+[ 0.000000] RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4. -+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4 -+[ 0.000000] NR_IRQS:64 nr_irqs:64 0 -+[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000009c00000 -+[ 0.000000] GICv2m: range[mem 0x09bd0000-0x09bd0fff], SPI[544:639] -+[ 0.000000] arm_arch_timer: Architected cp15 and mmio timer(s) running at 19.20MHz (virt/virt). -+[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns -+[ 0.000002] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 4398046511078ns -+ -+[....] -+ -+ -+Some kernel information: -+ -+root@linaro-developer:~# cat /proc/cpuinfo -+processor : 0 -+BogoMIPS : 38.40 -+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -+CPU implementer : 0x51 -+CPU architecture: 8 -+CPU variant : 0x1 -+CPU part : 0x211 -+CPU revision : 2 -+ -+processor : 1 -+BogoMIPS : 38.40 -+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -+CPU implementer : 0x51 -+CPU architecture: 8 -+CPU variant : 0x1 -+CPU part : 0x211 -+CPU revision : 2 -+ -+processor : 2 -+BogoMIPS : 38.40 -+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -+CPU implementer : 0x51 -+CPU architecture: 8 -+CPU variant : 0x1 -+CPU part : 0x205 -+CPU revision : 2 -+ -+processor : 3 -+BogoMIPS : 38.40 -+Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -+CPU implementer : 0x51 -+CPU architecture: 8 -+CPU variant : 0x1 -+CPU part : 0x205 -+CPU revision : 2 -+ -+root@linaro-developer:~# uname -a -+Linux linaro-developer 4.11.3-30039-g5a922a1 #1 SMP PREEMPT Wed Oct 18 10:21:11 CEST 2017 aarch64 GNU/Linux -+ -+root@linaro-developer:~# cat /proc/cmdline -+root=/dev/nfs rw nfsroot=192.168.1.2:/db820c/rootfs,v3,tcp rootwait ip=dhcp consoleblank=0 console=tty0 console=ttyMSM0,115200n8 earlyprintk earlycon=msm_serial_dm,0x75b0000 androidboot.bootdevice=624000.ufshc androidboot.verifiedbootstate=orange androidboot.ver0 -+ -+root@linaro-developer:~# cat /proc/meminfo -+MemTotal: 2776332 kB -+MemFree: 2593696 kB -+MemAvailable: 2561432 kB -+Buffers: 0 kB -+Cached: 94744 kB -+SwapCached: 0 kB -+Active: 43888 kB -+Inactive: 72972 kB -+Active(anon): 22968 kB -+Inactive(anon): 24616 kB -+Active(file): 20920 kB -+Inactive(file): 48356 kB -+Unevictable: 0 kB -+Mlocked: 0 kB -+SwapTotal: 0 kB -+SwapFree: 0 kB -+Dirty: 0 kB -+Writeback: 0 kB -+AnonPages: 22120 kB -+Mapped: 29284 kB -+Shmem: 25468 kB -+Slab: 32876 kB -+SReclaimable: 12924 kB -+SUnreclaim: 19952 kB -+KernelStack: 2144 kB -+PageTables: 928 kB -+NFS_Unstable: 0 kB -+Bounce: 0 kB -+WritebackTmp: 0 kB -+CommitLimit: 1388164 kB -+Committed_AS: 204192 kB -+VmallocTotal: 135290290112 kB -+VmallocUsed: 0 kB -+VmallocChunk: 0 kB -+AnonHugePages: 2048 kB -+ShmemHugePages: 0 kB -+ShmemPmdMapped: 0 kB -+CmaTotal: 131072 kB -+CmaFree: 130356 kB -+HugePages_Total: 0 -+HugePages_Free: 0 -+HugePages_Rsvd: 0 -+HugePages_Surp: 0 -+Hugepagesize: 2048 kB -diff --git a/board/qualcomm/dragonboard820c/u-boot.lds b/board/qualcomm/dragonboard820c/u-boot.lds -new file mode 100644 -index 0000000000..b84b4ac8b3 ---- /dev/null -+++ b/board/qualcomm/dragonboard820c/u-boot.lds -@@ -0,0 +1,106 @@ -+/* -+ * Override linker script for fastboot-readable images -+ * -+ * (C) Copyright 2015 Mateusz Kulikowski -+ * -+ * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header) -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") -+OUTPUT_ARCH(aarch64) -+ENTRY(_arm64_header) -+SECTIONS -+{ -+ . = 0x00000000; -+ -+ . = ALIGN(8); -+ .text : -+ { -+ *(.__image_copy_start) -+ board/qualcomm/dragonboard820c/head.o (.text*) -+ CPUDIR/start.o (.text*) -+ *(.text*) -+ } -+ -+ . = ALIGN(8); -+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } -+ -+ . = ALIGN(8); -+ .data : { -+ *(.data*) -+ } -+ -+ . = ALIGN(8); -+ -+ . = .; -+ -+ . = ALIGN(8); -+ .u_boot_list : { -+ KEEP(*(SORT(.u_boot_list*))); -+ } -+ -+ . = ALIGN(8); -+ -+ .efi_runtime : { -+ __efi_runtime_start = .; -+ *(efi_runtime_text) -+ *(efi_runtime_data) -+ __efi_runtime_stop = .; -+ } -+ -+ .efi_runtime_rel : { -+ __efi_runtime_rel_start = .; -+ *(.relaefi_runtime_text) -+ *(.relaefi_runtime_data) -+ __efi_runtime_rel_stop = .; -+ } -+ -+ . = ALIGN(8); -+ -+ .image_copy_end : -+ { -+ *(.__image_copy_end) -+ } -+ -+ . = ALIGN(8); -+ -+ .rel_dyn_start : -+ { -+ *(.__rel_dyn_start) -+ } -+ -+ .rela.dyn : { -+ *(.rela*) -+ } -+ -+ .rel_dyn_end : -+ { -+ *(.__rel_dyn_end) -+ } -+ -+ _end = .; -+ -+ . = ALIGN(8); -+ -+ .bss_start : { -+ KEEP(*(.__bss_start)); -+ } -+ -+ .bss : { -+ *(.bss*) -+ . = ALIGN(8); -+ } -+ -+ .bss_end : { -+ KEEP(*(.__bss_end)); -+ } -+ -+ /DISCARD/ : { *(.dynsym) } -+ /DISCARD/ : { *(.dynstr*) } -+ /DISCARD/ : { *(.dynamic*) } -+ /DISCARD/ : { *(.plt*) } -+ /DISCARD/ : { *(.interp*) } -+ /DISCARD/ : { *(.gnu*) } -+} -diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig -new file mode 100644 -index 0000000000..53f095d4e5 ---- /dev/null -+++ b/configs/dragonboard820c_defconfig -@@ -0,0 +1,36 @@ -+CONFIG_ARM=y -+CONFIG_ARM_SMCCC=y -+CONFIG_ARCH_SNAPDRAGON=y -+CONFIG_TARGET_DRAGONBOARD820C=y -+CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" -+CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c" -+CONFIG_USE_BOOTARGS=y -+# CONFIG_DISPLAY_CPUINFO is not set -+# CONFIG_DISPLAY_BOARDINFO is not set -+CONFIG_BOOTARGS="console=ttyMSM0,115200n8" -+CONFIG_SYS_PROMPT="dragonboard820c => " -+CONFIG_HUSH_PARSER=y -+CONFIG_CMD_BOOTEFI=y -+CONFIG_EFI_LOADER=y -+CONFIG_CMD_BOOTEFI_HELLO=y -+CONFIG_CMD_PXE=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_MEMINFO=y -+CONFIG_CMD_MD5SUM=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_TIMER=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_OF_CONTROL=y -+CONFIG_MSM_SERIAL=y -+CONFIG_MMC_SDHCI_MSM=y -+CONFIG_MMC_SDHCI=y -+CONFIG_DM_MMC=y -+CONFIG_CLK=y -+CONFIG_PSCI_RESET=y -+CONFIG_ENV_IS_IN_EXT4=y -+CONFIG_ENV_EXT4_INTERFACE="mmc" -+CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" -+CONFIG_ENV_EXT4_FILE="/uboot.env" -diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h -new file mode 100644 -index 0000000000..76bcaf89e5 ---- /dev/null -+++ b/include/configs/dragonboard820c.h -@@ -0,0 +1,72 @@ -+/* -+ * Board configuration file for Dragonboard 410C -+ * -+ * (C) Copyright 2017 Jorge Ramirez-Ortiz -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIGS_DRAGONBOARD820C_H -+#define __CONFIGS_DRAGONBOARD820C_H -+ -+#include -+#include -+ -+/* Physical Memory Map */ -+#define CONFIG_NR_DRAM_BANKS 2 -+ -+#define PHYS_SDRAM_SIZE 0xC0000000 -+#define PHYS_SDRAM_1 0x80000000 -+#define PHYS_SDRAM_1_SIZE 0x60000000 -+#define PHYS_SDRAM_2 0x100000000 -+#define PHYS_SDRAM_2_SIZE 0x5ea4ffff -+ -+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -+#define CONFIG_SYS_TEXT_BASE 0x80080000 -+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) -+#define CONFIG_SYS_BOOTM_LEN SZ_64M -+#define CONFIG_SYS_LDSCRIPT "board/qualcomm/dragonboard820c/u-boot.lds" -+ -+/* Generic Timer Definitions */ -+#define COUNTER_FREQUENCY 19000000 -+ -+/* Partition table support */ -+#define HAVE_BLOCK_DEVICE -+ -+/* BOOTP options */ -+#define CONFIG_BOOTP_BOOTFILESIZE -+ -+#ifndef CONFIG_SPL_BUILD -+#include -+#include -+#endif -+ -+#define BOOT_TARGET_DEVICES(func) \ -+ func(MMC, mmc, 0) -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ "loadaddr=0x95000000\0" \ -+ "fdt_high=0xffffffffffffffff\0" \ -+ "initrd_high=0xffffffffffffffff\0" \ -+ "linux_image=uImage\0" \ -+ "kernel_addr_r=0x95000000\0"\ -+ "fdtfile=qcom/apq8096-db820c.dtb\0" \ -+ "fdt_addr_r=0x93000000\0"\ -+ "ramdisk_addr_r=0x91000000\0"\ -+ "scriptaddr=0x90000000\0"\ -+ "pxefile_addr_r=0x90100000\0"\ -+ BOOTENV -+ -+#define CONFIG_EXT4_WRITE -+#define CONFIG_ENV_SIZE 0x4000 -+#define CONFIG_ENV_VARS_UBOOT_CONFIG -+ -+/* Size of malloc() pool */ -+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) -+ -+/* Monitor Command Prompt */ -+#define CONFIG_SYS_CBSIZE 512 -+#define CONFIG_SYS_MAXARGS 64 -+ -+#endif --- -2.14.3 - -From d026c7e9deecef72bfe1a1ea980ad3d3182c4762 Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Mon, 4 Dec 2017 12:14:01 +0100 -Subject: [PATCH 07/15] db820c: enable pmic gpios for pm8994 - -Signed-off-by: Jorge Ramirez-Ortiz ---- - arch/arm/dts/dragonboard820c.dts | 43 +++++++++++++++++++++++++++++++++++++++ - configs/dragonboard820c_defconfig | 7 +++++++ - drivers/gpio/pm8916_gpio.c | 7 +++++-- - 3 files changed, 55 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts -index 2d49830e77..64249449af 100644 ---- a/arch/arm/dts/dragonboard820c.dts -+++ b/arch/arm/dts/dragonboard820c.dts -@@ -61,5 +61,48 @@ - clock = <&gcc 0>; - clock-frequency = <200000000>; - }; -+ -+ spmi@400f000 { -+ compatible = "qcom,spmi-pmic-arb"; -+ reg = <0x400f800 0x200>, -+ <0x4400000 0x400000>, -+ <0x4c00000 0x400000>; -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ -+ pmic0: pm8994@0 { -+ compatible = "qcom,spmi-pmic"; -+ reg = <0x0 0x1>; -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ -+ pm8994_pon: pm8994_pon@800 { -+ compatible = "qcom,pm8994-pwrkey"; -+ reg = <0x800 0x96>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ gpio-bank-name="pm8994_key."; -+ }; -+ -+ pm8994_gpios: pm8994_gpios@c000 { -+ compatible = "qcom,pm8994-gpio"; -+ reg = <0xc000 0x400>; -+ gpio-controller; -+ gpio-count = <24>; -+ #gpio-cells = <2>; -+ gpio-bank-name="pm8994."; -+ }; -+ }; -+ -+ pmic1: pm8994@1 { -+ compatible = "qcom,spmi-pmic"; -+ reg = <0x1 0x1>; -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ }; -+ }; - }; -+ - }; -+ -+#include "dragonboard820c-uboot.dtsi" -diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig -index 53f095d4e5..8af54aa3c4 100644 ---- a/configs/dragonboard820c_defconfig -+++ b/configs/dragonboard820c_defconfig -@@ -23,11 +23,18 @@ CONFIG_CMD_TIMER=y - CONFIG_CMD_EXT4=y - CONFIG_CMD_GPT=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_PMIC=y - CONFIG_OF_CONTROL=y - CONFIG_MSM_SERIAL=y -+CONFIG_SPMI_MSM=y - CONFIG_MMC_SDHCI_MSM=y - CONFIG_MMC_SDHCI=y - CONFIG_DM_MMC=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_PM8916=y -+CONFIG_PM8916_GPIO=y - CONFIG_CLK=y - CONFIG_PSCI_RESET=y - CONFIG_ENV_IS_IN_EXT4=y -diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c -index 9ec2a24b3e..056b982163 100644 ---- a/drivers/gpio/pm8916_gpio.c -+++ b/drivers/gpio/pm8916_gpio.c -@@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; - #define REG_STATUS_VAL_MASK 0x1 - - /* MODE_CTL */ --#define REG_CTL 0x40 -+#define REG_CTL 0x40 - #define REG_CTL_MODE_MASK 0x70 - #define REG_CTL_MODE_INPUT 0x00 - #define REG_CTL_MODE_INOUT 0x20 -@@ -183,7 +183,7 @@ static int pm8916_gpio_probe(struct udevice *dev) - return -ENODEV; - - reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE); -- if (reg != 0x5) -+ if (reg != 0x5 && reg != 0x1) - return -ENODEV; - - return 0; -@@ -203,6 +203,7 @@ static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev) - - static const struct udevice_id pm8916_gpio_ids[] = { - { .compatible = "qcom,pm8916-gpio" }, -+ { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ - { } - }; - -@@ -278,6 +279,7 @@ static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev) - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - - uc_priv->gpio_count = 2; -+ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); - if (uc_priv->bank_name == NULL) - uc_priv->bank_name = "pm8916_key"; - -@@ -286,6 +288,7 @@ static int pm8941_pwrkey_ofdata_to_platdata(struct udevice *dev) - - static const struct udevice_id pm8941_pwrkey_ids[] = { - { .compatible = "qcom,pm8916-pwrkey" }, -+ { .compatible = "qcom,pm8994-pwrkey" }, - { } - }; - --- -2.14.3 - -From c9205ed29e3476620d7b2e1bbab4ce8a56db601b Mon Sep 17 00:00:00 2001 -From: Jorge Ramirez-Ortiz -Date: Sun, 3 Dec 2017 16:30:08 +0100 -Subject: [PATCH 08/15] db820c: stop autoboot when vol- pressed - -Signed-off-by: Jorge Ramirez-Ortiz ---- - arch/arm/dts/dragonboard820c-uboot.dtsi | 19 ++++++++++++ - board/qualcomm/dragonboard820c/dragonboard820c.c | 37 +++++++++++++++++++++++- - include/configs/dragonboard820c.h | 2 ++ - 3 files changed, 57 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/dts/dragonboard820c-uboot.dtsi - -diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi -new file mode 100644 -index 0000000000..167e72c0ae ---- /dev/null -+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi -@@ -0,0 +1,19 @@ -+/* -+ * U-Boot addition to handle Dragonboard 820c pins -+ * -+ * (C) Copyright 2017 Jorge Ramirez-Ortiz -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+&pm8994_pon { -+ key_vol_down { -+ gpios = <&pm8994_pon 1 0>; -+ label = "key_vol_down"; -+ }; -+ -+ key_power { -+ gpios = <&pm8994_pon 0 0>; -+ label = "key_power"; -+ }; -+}; -diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c -index f5dd62e18e..d4a20d22d9 100644 ---- a/board/qualcomm/dragonboard820c/dragonboard820c.c -+++ b/board/qualcomm/dragonboard820c/dragonboard820c.c -@@ -1,7 +1,7 @@ - /* - * Board init file for Dragonboard 820C - * -- * (C) Copyright 2017 Jorge Ramirez-Ortiz -+ * (C) Copyright 2017 Jorge Ramirez-Ortiz - * - * SPDX-License-Identifier: GPL-2.0+ - */ -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - - DECLARE_GLOBAL_DATA_PTR; - -@@ -126,3 +127,37 @@ void reset_cpu(ulong addr) - { - psci_system_reset(); - } -+ -+/* Check for vol- button - if pressed - stop autoboot */ -+int misc_init_r(void) -+{ -+ struct udevice *pon; -+ struct gpio_desc resin; -+ int node, ret; -+ -+ ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8994_pon@800", &pon); -+ if (ret < 0) { -+ printf("Failed to find PMIC pon node. Check device tree\n"); -+ return 0; -+ } -+ -+ node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), -+ "key_vol_down"); -+ if (node < 0) { -+ printf("Failed to find key_vol_down node. Check device tree\n"); -+ return 0; -+ } -+ -+ if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, -+ &resin, 0)) { -+ printf("Failed to request key_vol_down button.\n"); -+ return 0; -+ } -+ -+ if (dm_gpio_get_value(&resin)) { -+ env_set("bootdelay", "-1"); -+ printf("Power button pressed - dropping to console.\n"); -+ } -+ -+ return 0; -+} -diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h -index 76bcaf89e5..e0c3c0c670 100644 ---- a/include/configs/dragonboard820c.h -+++ b/include/configs/dragonboard820c.h -@@ -12,6 +12,8 @@ - #include - #include - -+#define CONFIG_MISC_INIT_R /* To stop autoboot */ -+ - /* Physical Memory Map */ - #define CONFIG_NR_DRAM_BANKS 2 - --- -2.14.3 - diff --git a/dragonboard-fixes.patch b/dragonboard-fixes.patch index 1360c1e..1e6ec7b 100644 --- a/dragonboard-fixes.patch +++ b/dragonboard-fixes.patch @@ -1,17 +1,17 @@ -From a2782063c8daf9000d131e85200bc631a16450b4 Mon Sep 17 00:00:00 2001 +From fbd0bffb20ca5edd21bbeb7cc20e24d091ab4280 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 21 Jun 2017 14:21:15 -0400 -Subject: [PATCH 01/23] WIP: fix usb +Subject: [PATCH 1/4] WIP: fix usb --- common/usb_storage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_storage.c b/common/usb_storage.c -index df0b057308..b2a3ab49ec 100644 +index a91b1c0d2f..caea87a09f 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c -@@ -996,7 +996,7 @@ static int usb_request_sense(struct scsi_cmd *srb, struct us_data *ss) +@@ -1018,7 +1018,7 @@ static int usb_request_sense(struct scsi_cmd *srb, struct us_data *ss) static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) { @@ -20,7 +20,7 @@ index df0b057308..b2a3ab49ec 100644 do { memset(&srb->cmd[0], 0, 12); -@@ -1019,7 +1019,7 @@ static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) +@@ -1041,7 +1041,7 @@ static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) if ((srb->sense_buf[2] == 0x02) && (srb->sense_buf[12] == 0x3a)) return -1; @@ -30,12 +30,12 @@ index df0b057308..b2a3ab49ec 100644 return -1; -- -2.13.3 +2.14.3 -From 40b06f8d422efc1d9674f081ef22445904c01f4f Mon Sep 17 00:00:00 2001 +From d1b25b8d6461c5278228d657de9c24e0979e4b9d Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 3 Jul 2017 08:34:37 -0400 -Subject: [PATCH 02/23] HACK: disable emmc +Subject: [PATCH 2/4] HACK: disable emmc Hitting some timeout which makes boot take much longer. And uefi/boot/rootfs partitions will be on sd-card or usb disk, etc, @@ -45,7 +45,7 @@ so we can just ignore emmc. 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts -index 7746622dda..0d3b7a35f4 100644 +index 5ccfe7f8c8..9e2d3f5d9b 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -67,6 +67,7 @@ @@ -65,11 +65,12 @@ index 7746622dda..0d3b7a35f4 100644 sdhci@07864000 { compatible = "qcom,sdhci-msm-v4"; -- -2.13.3 -From 7f9d2f7d2ba72cbf62bdabaa98c489b514dc136c Mon Sep 17 00:00:00 2001 +2.14.3 + +From a43912730613da9f17a185e55a980d9acd0e437e Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 16 Jan 2018 03:16:35 +0000 -Subject: [PATCH 1/2] db410c: config updates +Date: Tue, 6 Mar 2018 10:08:32 +0000 +Subject: [PATCH 3/4] db410c: config updates Enable USB keyboards and video output, VFAT writes (useful for EFI boot) and a common USB eth adapter @@ -80,58 +81,64 @@ Signed-off-by: Peter Robinson 1 file changed, 10 insertions(+) diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig -index 4389f52b5c..9dcadb938c 100644 +index e6114db2ce..30e5cb3f5d 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig -@@ -41,10 +41,20 @@ CONFIG_USB_HOST_ETHER=y +@@ -20,6 +20,8 @@ CONFIG_CMD_USB=y + CONFIG_CMD_CACHE=y + CONFIG_CMD_TIMER=y + CONFIG_ENV_IS_IN_MMC=y ++CONFIG_FAT_WRITE=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y + CONFIG_CLK=y + CONFIG_MSM_GPIO=y + CONFIG_PM8916_GPIO=y +@@ -32,10 +34,17 @@ CONFIG_DM_PMIC=y + CONFIG_PMIC_PM8916=y + CONFIG_MSM_SERIAL=y + CONFIG_SPMI_MSM=y ++CONFIG_DM_ETH=y ++CONFIG_DM_KEYBOARD=y ++CONFIG_DM_VIDEO=y ++# CONFG_VIDEO_BPP8 is not set ++CONFIG_NO_FB_CLEAR=y ++CONFIG_VIDEO_SIMPLE=y + CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_MSM=y ++CONFIG_USB_KEYBOARD=y + CONFIG_USB_ULPI_VIEWPORT=y + CONFIG_USB_ULPI=y + CONFIG_USB_STORAGE=y +@@ -43,5 +52,6 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_ETH=y CONFIG_OF_LIBFDT_OVERLAY=y - CONFIG_OF_CONTROL=y - CONFIG_ENV_IS_IN_MMC=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_PSCI_RESET=y - CONFIG_OF_SEPARATE=y -+CONFIG_DM_KEYBOARD=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -+CONFIG_DM_VIDEO=y -+# CONFG_VIDEO_BPP8 is not set -+CONFIG_NO_FB_CLEAR=y -+CONFIG_VIDEO_SIMPLE=y -+CONFIG_FAT_WRITE=y -- 2.14.3 -From 5d4690815f188a46a2eebad023403819fe4d053a Mon Sep 17 00:00:00 2001 +From 363da4f7cb3668077fc0bb83e36605080bba5aa7 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 16 Jan 2018 03:23:07 +0000 -Subject: [PATCH 2/2] db820c: config updates +Date: Tue, 6 Mar 2018 10:13:32 +0000 +Subject: [PATCH 4/4] db820c: config updates -Enable LEDs, FAT write, and various DT functionality +Enable LEDs, FAT write (useful for EFI boot), various DT functionality, wnable USB keyboards and +video output, and some common USB eth adapters Signed-off-by: Peter Robinson --- - configs/dragonboard820c_defconfig | 6 ++++++ - 1 file changed, 6 insertions(+) + configs/dragonboard820c_defconfig | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig -index 8af54aa3c4..dcec65d212 100644 +index ec4a5b952e..11150a25a6 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig -@@ -35,9 +35,15 @@ CONFIG_DM_GPIO=y - CONFIG_DM_PMIC=y - CONFIG_PMIC_PM8916=y - CONFIG_PM8916_GPIO=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y - CONFIG_CLK=y - CONFIG_PSCI_RESET=y - CONFIG_ENV_IS_IN_EXT4=y +@@ -25,8 +25,14 @@ CONFIG_ENV_IS_IN_EXT4=y CONFIG_ENV_EXT4_INTERFACE="mmc" CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" CONFIG_ENV_EXT4_FILE="/uboot.env" @@ -139,6 +146,39 @@ index 8af54aa3c4..dcec65d212 100644 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y + CONFIG_CLK=y + CONFIG_PM8916_GPIO=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y + CONFIG_DM_MMC=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_MSM=y +@@ -34,3 +40,25 @@ CONFIG_DM_PMIC=y + CONFIG_PMIC_PM8916=y + CONFIG_MSM_SERIAL=y + CONFIG_SPMI_MSM=y ++CONFIG_DM_ETH=y ++CONFIG_DM_KEYBOARD=y ++CONFIG_DM_VIDEO=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_DM_VIDEO=y ++# CONFG_VIDEO_BPP8 is not set ++CONFIG_NO_FB_CLEAR=y ++CONFIG_VIDEO_SIMPLE=y ++CONFIG_USB=y ++CONFIG_DM_USB=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_MSM=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_ULPI_VIEWPORT=y ++CONFIG_USB_ULPI=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y -- 2.14.3 diff --git a/sources b/sources index 8746452..f5ac3bc 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2018.03-rc3.tar.bz2) = aa2de0a0c55cea73b454a972648369b2f2be50dd37ac3b837448f49622e19007178d97cac2d9852556feb3e4dcdd808aa5900dafa1b9fd9d16254c73e5facf15 +SHA512 (u-boot-2018.03-rc4.tar.bz2) = 65116776c02650a98d55b42b81264675bc9e850c63a145a7686c3c3bea128055fe96f96d07013211f1313acaeb2c6be84683ecd552004cff5f689a350850947d diff --git a/uboot-tools.spec b/uboot-tools.spec index a078a70..d393b54 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc3 +%global candidate rc4 Name: uboot-tools Version: 2018.03 -Release: 0.8%{?candidate:.%{candidate}}%{?dist} +Release: 0.9%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -27,11 +27,8 @@ Patch7: rk33xx-enable-make-itb.patch Patch8: mx6cuboxi-add-support-for-detecting-Revision-1.5-SoM.patch # Board fixes and enablement -#Patch10: db-generic-fixes.patch -#Patch11: db410c-fixes.patch -#Patch12: db820c-support.patch -#Patch13: dragonboard-fixes.patch -# Patch14: mvebu-enable-generic-distro-boot-config.patch +Patch10: dragonboard-fixes.patch +# Patch11: mvebu-enable-generic-distro-boot-config.patch BuildRequires: bc BuildRequires: dtc @@ -290,6 +287,10 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Tue Mar 6 2018 Peter Robinson 2018.03-0.9.rc4 +- 2018.03 RC4 +- DragonBoard patch rebase + * Sun Mar 4 2018 Peter Robinson 2018.03-0.8.rc3 - Add support for SoM rev 1.5 to mx6cuboxi - Rebuild for new ATF 1.5 rc0 release