From 633a253ebb0eefd279d8174d7507972f72c442f6 Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Thu, 17 Nov 2022 13:24:51 +0200 Subject: [PATCH] Add support for riscv64 Signed-off-by: David Abdurachmanov --- ...-Initialized-the-PWM-setting-in-the-.patch | 104 +++++++++++++++ ...-Set-remote-thermal-of-TMP451-to-85-.patch | 120 ++++++++++++++++++ ...-Enable-sbi-command-and-SBI-sysreset.patch | 68 ++++++++++ riscv64-boards | 5 + uboot-tools.spec | 41 +++++- 5 files changed, 336 insertions(+), 2 deletions(-) create mode 100644 0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch create mode 100644 0002-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch create mode 100644 0003-Enable-sbi-command-and-SBI-sysreset.patch create mode 100644 riscv64-boards diff --git a/0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch b/0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch new file mode 100644 index 0000000..97669f7 --- /dev/null +++ b/0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch @@ -0,0 +1,104 @@ +From f6c0dda1c82c6abb108e3511497e37c54ccb8e59 Mon Sep 17 00:00:00 2001 +From: Vincent Chen +Date: Mon, 15 Nov 2021 03:31:04 -0800 +Subject: [PATCH 1/3] board: sifive: spl: Initialized the PWM setting in the + SPL stage + +LEDs and multiple fans can be controlled by SPL. This patch ensures +that all fans have been enabled in the SPL stage. In addition, the +LED's color will be set to yellow. +--- + board/sifive/unmatched/Makefile | 1 + + board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++ + board/sifive/unmatched/spl.c | 2 ++ + 3 files changed, 60 insertions(+) + create mode 100644 board/sifive/unmatched/pwm.c + +diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile +index 13453300..5df01982 100644 +--- a/board/sifive/unmatched/Makefile ++++ b/board/sifive/unmatched/Makefile +@@ -9,3 +9,4 @@ obj-y += spl.o + else + obj-y += unmatched.o + endif ++obj-y += pwm.o +diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c +new file mode 100644 +index 00000000..e1cc0231 +--- /dev/null ++++ b/board/sifive/unmatched/pwm.c +@@ -0,0 +1,57 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2021, SiFive Inc ++ * ++ * Authors: ++ * Vincent Chen ++ * David Abdurachmanov ++ */ ++ ++#include ++#include ++ ++struct pwm_sifive_regs { ++ unsigned int cfg; /* PWM configuration register */ ++ unsigned int pad0; /* Reserved */ ++ unsigned int cnt; /* PWM count register */ ++ unsigned int pad1; /* Reserved */ ++ unsigned int pwms; /* Scaled PWM count register */ ++ unsigned int pad2; /* Reserved */ ++ unsigned int pad3; /* Reserved */ ++ unsigned int pad4; /* Reserved */ ++ unsigned int cmp0; /* PWM 0 compare register */ ++ unsigned int cmp1; /* PWM 1 compare register */ ++ unsigned int cmp2; /* PWM 2 compare register */ ++ unsigned int cmp3; /* PWM 3 compare register */ ++}; ++ ++#define PWM0_BASE 0x10020000 ++#define PWM1_BASE 0x10021000 ++#define PWM_CFG_INIT 0x1000 ++#define PWM_CMP_ENABLE_VAL 0x0 ++#define PWM_CMP_DISABLE_VAL 0xffff ++ ++void pwm_device_init(void) ++{ ++ struct pwm_sifive_regs *pwm0, *pwm1; ++ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE; ++ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE; ++ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0); ++ /* Set the 3-color PWM LEDs to yellow in SPL */ ++ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1); ++ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2); ++ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3); ++ writel(PWM_CFG_INIT, (void *)&pwm0->cfg); ++ ++ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3); ++ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */ ++ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0, ++ so here sets the initial value of PWM_COMP0 as DISABLE */ ++ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3) ++ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1); ++ else ++ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1); ++ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2); ++ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3); ++ writel(PWM_CFG_INIT, (void *)&pwm1->cfg); ++} +diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c +index 7c0beedc..f3a661a8 100644 +--- a/board/sifive/unmatched/spl.c ++++ b/board/sifive/unmatched/spl.c +@@ -90,6 +90,8 @@ int spl_board_init_f(void) + goto end; + } + ++ pwm_device_init(); ++ + ret = spl_gemgxl_init(); + if (ret) { + debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret); +-- +2.37.3 + diff --git a/0002-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch b/0002-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch new file mode 100644 index 0000000..b3477a6 --- /dev/null +++ b/0002-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch @@ -0,0 +1,120 @@ +From 918c6f91b146aabb74d7d721da8747827a873f8a Mon Sep 17 00:00:00 2001 +From: Vincent Chen +Date: Thu, 17 Nov 2022 13:13:03 +0200 +Subject: [PATCH 2/3] board: sifive: spl: Set remote thermal of TMP451 to 85 + deg C for the unmatched board + +For TMP451 on the unmatched board, the default value of the remote +thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL. +--- + board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++ + drivers/misc/Kconfig | 10 ++++++++++ + include/configs/sifive-unmatched.h | 4 ++++ + scripts/config_whitelist.txt | 1 + + 4 files changed, 44 insertions(+) + +diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c +index f3a661a8..05ba5916 100644 +--- a/board/sifive/unmatched/spl.c ++++ b/board/sifive/unmatched/spl.c +@@ -10,6 +10,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -26,6 +28,27 @@ + #define MODE_SELECT_SD 0xb + #define MODE_SELECT_MASK GENMASK(3, 0) + ++#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19 ++#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55 ++ ++static inline int init_tmp451_remote_therm_limit(void) ++{ ++ struct udevice *dev; ++ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE; ++ int ret; ++ ++ ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM, ++ CONFIG_SYS_I2C_TMP451_ADDR, ++ CONFIG_SYS_I2C_TMP451_ADDR_LEN, ++ &dev); ++ ++ if (!ret) ++ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET, ++ &r_therm_limit, ++ sizeof(unsigned char)); ++ return ret; ++} ++ + static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width) + { + int ret; +@@ -92,6 +115,12 @@ int spl_board_init_f(void) + + pwm_device_init(); + ++ ret = init_tmp451_remote_therm_limit(); ++ if (ret) { ++ debug("TMP451 remote THERM limit init failed: %d\n", ret); ++ goto end; ++ } ++ + ret = spl_gemgxl_init(); + if (ret) { + debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret); +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index a6da6e21..f166de4c 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -538,6 +538,16 @@ config SYS_I2C_EEPROM_ADDR + + if I2C_EEPROM + ++config SYS_I2C_TMP451_ADDR ++ hex "Chip address of the TMP451 device" ++ default 0 ++ ++config SYS_I2C_TMP451_ADDR_LEN ++ int "Length in bytes of the TMP451 memory array address" ++ default 1 ++ help ++ Note: This is NOT the chip address length! ++ + config SYS_I2C_EEPROM_ADDR_OVERFLOW + hex "EEPROM Address Overflow" + default 0x0 +diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h +index 9923f3d9..96c6e8df 100644 +--- a/include/configs/sifive-unmatched.h ++++ b/include/configs/sifive-unmatched.h +@@ -15,6 +15,10 @@ + + #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + ++#define CONFIG_SYS_TMP451_BUS_NUM 0 ++#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c ++#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1 ++ + /* Environment options */ + + #define BOOT_TARGET_DEVICES(func) \ +diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt +index f505722f..032126d8 100644 +--- a/scripts/config_whitelist.txt ++++ b/scripts/config_whitelist.txt +@@ -1268,6 +1268,7 @@ CONFIG_SYS_TIMER_BASE + CONFIG_SYS_TIMER_COUNTER + CONFIG_SYS_TIMER_COUNTS_DOWN + CONFIG_SYS_TIMER_RATE ++CONFIG_SYS_TMP451_BUS_NUM + CONFIG_SYS_TMPVIRT + CONFIG_SYS_TSEC1_OFFSET + CONFIG_SYS_TX_ETH_BUFFER +-- +2.37.3 + diff --git a/0003-Enable-sbi-command-and-SBI-sysreset.patch b/0003-Enable-sbi-command-and-SBI-sysreset.patch new file mode 100644 index 0000000..6e33c8d --- /dev/null +++ b/0003-Enable-sbi-command-and-SBI-sysreset.patch @@ -0,0 +1,68 @@ +From 9fba4e75ae1b09bd9d58bf09b3dab02d25f85b30 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Thu, 17 Nov 2022 13:16:58 +0200 +Subject: [PATCH 3/3] Enable "sbi" command and SBI sysreset + +Signed-off-by: David Abdurachmanov +--- + configs/qemu-riscv64_defconfig | 5 +++++ + configs/qemu-riscv64_smode_defconfig | 5 +++++ + configs/sifive_unleashed_defconfig | 5 +++++ + configs/sifive_unmatched_defconfig | 5 +++++ + 4 files changed, 20 insertions(+) + +diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig +index d5eae95c..611d5eb3 100644 +--- a/configs/qemu-riscv64_defconfig ++++ b/configs/qemu-riscv64_defconfig +@@ -21,3 +21,8 @@ CONFIG_CMD_NVEDIT_EFI=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM_MTD=y + CONFIG_SYS_MAX_FLASH_BANKS=2 ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y +diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig +index 1cb06b4b..26f9f632 100644 +--- a/configs/qemu-riscv64_smode_defconfig ++++ b/configs/qemu-riscv64_smode_defconfig +@@ -24,3 +24,8 @@ CONFIG_CMD_NVEDIT_EFI=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_DM_MTD=y + CONFIG_SYS_MAX_FLASH_BANKS=2 ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y +diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig +index 99faabaa..e85877bc 100644 +--- a/configs/sifive_unleashed_defconfig ++++ b/configs/sifive_unleashed_defconfig +@@ -40,3 +40,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y + CONFIG_SPL_CLK=y + CONFIG_DM_MTD=y + CONFIG_DM_RESET=y ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y +diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig +index c390af26..4dd545fa 100644 +--- a/configs/sifive_unmatched_defconfig ++++ b/configs/sifive_unmatched_defconfig +@@ -62,3 +62,8 @@ CONFIG_DM_SCSI=y + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_PCI=y ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y +-- +2.37.3 + diff --git a/riscv64-boards b/riscv64-boards new file mode 100644 index 0000000..12c1766 --- /dev/null +++ b/riscv64-boards @@ -0,0 +1,5 @@ +qemu-riscv64 +qemu-riscv64_smode +qemu-riscv64_spl +sifive_unleashed +sifive_unmatched diff --git a/uboot-tools.spec b/uboot-tools.spec index 1cf1c00..b9459ff 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -5,9 +5,12 @@ %bcond_with toolsonly %endif +# Set it to "opensbi" (stable) or opensbi-unstable (unstable, git) +%global opensbi opensbi-unstable + Name: uboot-tools Version: 2022.10 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 1%{?candidate:.%{candidate}}.0.riscv64%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -15,6 +18,7 @@ URL: http://www.denx.de/wiki/U-Boot ExcludeArch: s390x Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: aarch64-boards +Source2: riscv64-boards # Fedoraisms patches # Needed to find DT on boot partition that's not the first partition @@ -31,6 +35,11 @@ Patch6: rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch Patch7: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch Patch8: 0001-Revert-power-pmic-rk8xx-Support-sysreset-shutdown-me.patch +# RISC-V (riscv64) patches +Patch20: 0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch +Patch21: 0002-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch +Patch22: 0003-Enable-sbi-command-and-SBI-sysreset.patch + BuildRequires: bc BuildRequires: bison BuildRequires: dtc @@ -51,6 +60,9 @@ BuildRequires: swig BuildRequires: arm-trusted-firmware-armv8 %endif Requires: dtc +%ifarch riscv64 +BuildRequires: %{opensbi} +%endif %description This package contains a few U-Boot utilities - mkimage for creating boot images @@ -79,7 +91,11 @@ mkdir builds %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-all O=builds/ %if %{with toolsonly} -%ifarch aarch64 +%ifarch riscv64 +export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin +%endif + +%ifarch aarch64 riscv64 for board in $(cat %{_arch}-boards) do echo "Building board: $board" @@ -149,6 +165,19 @@ done install -p -m 0644 builds/apple_m1/u-boot-nodtb.bin %{buildroot}%{_datadir}/uboot/apple_m1/u-boot-nodtb.bin %endif +%ifarch riscv64 +for board in $(ls builds) +do +mkdir -p %{buildroot}%{_datadir}/uboot/$(echo $board)/ + for file in u-boot.bin u-boot.dtb u-boot.img u-boot-nodtb.bin u-boot-dtb.bin u-boot.itb u-boot-dtb.img u-boot.its spl/u-boot-spl.bin spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb spl/u-boot-spl-dtb.bin + do + if [ -f builds/$(echo $board)/$(echo $file) ]; then + install -p -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/ + fi + done +done +%endif + # Bit of a hack to remove binaries we don't use as they're large %ifarch aarch64 for board in $(ls builds) @@ -207,9 +236,17 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %files -n uboot-images-armv8 %{_datadir}/uboot/* %endif + +%ifarch riscv64 +%files -n uboot-images-riscv64 +%{_datadir}/uboot/* +%endif %endif %changelog +* Thu Nov 17 2022 David Abdurachmanov - 2022.10-1.0.riscv64 +- Add support for riscv64 + * Mon Oct 10 2022 Peter Robinson - 2022.10-1 - Update to 2022.10 GA