Add support for riscv64
Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
This commit is contained in:
parent
716e4d578e
commit
633a253ebb
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@ -0,0 +1,104 @@
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From f6c0dda1c82c6abb108e3511497e37c54ccb8e59 Mon Sep 17 00:00:00 2001
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From: Vincent Chen <vincent.chen@sifive.com>
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Date: Mon, 15 Nov 2021 03:31:04 -0800
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Subject: [PATCH 1/3] board: sifive: spl: Initialized the PWM setting in the
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SPL stage
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LEDs and multiple fans can be controlled by SPL. This patch ensures
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that all fans have been enabled in the SPL stage. In addition, the
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LED's color will be set to yellow.
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---
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board/sifive/unmatched/Makefile | 1 +
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board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++
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board/sifive/unmatched/spl.c | 2 ++
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3 files changed, 60 insertions(+)
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create mode 100644 board/sifive/unmatched/pwm.c
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diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
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index 13453300..5df01982 100644
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--- a/board/sifive/unmatched/Makefile
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+++ b/board/sifive/unmatched/Makefile
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@@ -9,3 +9,4 @@ obj-y += spl.o
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else
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obj-y += unmatched.o
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endif
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+obj-y += pwm.o
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diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
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new file mode 100644
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index 00000000..e1cc0231
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--- /dev/null
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+++ b/board/sifive/unmatched/pwm.c
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@@ -0,0 +1,57 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (c) 2021, SiFive Inc
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+ *
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+ * Authors:
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+ * Vincent Chen <vincent.chen@sifive.com>
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+ * David Abdurachmanov <david.abdurachmanov@sifive.com>
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+ */
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+
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+#include <linux/io.h>
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+#include <asm/arch/eeprom.h>
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+
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+struct pwm_sifive_regs {
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+ unsigned int cfg; /* PWM configuration register */
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+ unsigned int pad0; /* Reserved */
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+ unsigned int cnt; /* PWM count register */
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+ unsigned int pad1; /* Reserved */
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+ unsigned int pwms; /* Scaled PWM count register */
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+ unsigned int pad2; /* Reserved */
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+ unsigned int pad3; /* Reserved */
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+ unsigned int pad4; /* Reserved */
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+ unsigned int cmp0; /* PWM 0 compare register */
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+ unsigned int cmp1; /* PWM 1 compare register */
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+ unsigned int cmp2; /* PWM 2 compare register */
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+ unsigned int cmp3; /* PWM 3 compare register */
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+};
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+
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+#define PWM0_BASE 0x10020000
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+#define PWM1_BASE 0x10021000
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+#define PWM_CFG_INIT 0x1000
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+#define PWM_CMP_ENABLE_VAL 0x0
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+#define PWM_CMP_DISABLE_VAL 0xffff
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+
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+void pwm_device_init(void)
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+{
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+ struct pwm_sifive_regs *pwm0, *pwm1;
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+ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
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+ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
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+ /* Set the 3-color PWM LEDs to yellow in SPL */
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
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+ writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
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+
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
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+ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
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+ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
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+ so here sets the initial value of PWM_COMP0 as DISABLE */
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+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
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+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
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+ else
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
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+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
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+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
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+}
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diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
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index 7c0beedc..f3a661a8 100644
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--- a/board/sifive/unmatched/spl.c
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+++ b/board/sifive/unmatched/spl.c
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@@ -90,6 +90,8 @@ int spl_board_init_f(void)
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goto end;
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}
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+ pwm_device_init();
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+
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ret = spl_gemgxl_init();
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if (ret) {
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debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
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--
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2.37.3
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@ -0,0 +1,120 @@
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From 918c6f91b146aabb74d7d721da8747827a873f8a Mon Sep 17 00:00:00 2001
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From: Vincent Chen <vincent.chen@sifive.com>
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Date: Thu, 17 Nov 2022 13:13:03 +0200
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Subject: [PATCH 2/3] board: sifive: spl: Set remote thermal of TMP451 to 85
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deg C for the unmatched board
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For TMP451 on the unmatched board, the default value of the remote
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thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL.
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---
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board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++
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drivers/misc/Kconfig | 10 ++++++++++
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include/configs/sifive-unmatched.h | 4 ++++
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scripts/config_whitelist.txt | 1 +
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4 files changed, 44 insertions(+)
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diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
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index f3a661a8..05ba5916 100644
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--- a/board/sifive/unmatched/spl.c
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+++ b/board/sifive/unmatched/spl.c
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@@ -10,6 +10,8 @@
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#include <spl.h>
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#include <misc.h>
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#include <log.h>
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+#include <config.h>
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+#include <i2c.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <asm/gpio.h>
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@@ -26,6 +28,27 @@
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#define MODE_SELECT_SD 0xb
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#define MODE_SELECT_MASK GENMASK(3, 0)
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+#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19
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+#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55
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+
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+static inline int init_tmp451_remote_therm_limit(void)
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+{
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+ struct udevice *dev;
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+ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE;
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+ int ret;
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+
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+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM,
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+ CONFIG_SYS_I2C_TMP451_ADDR,
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+ CONFIG_SYS_I2C_TMP451_ADDR_LEN,
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+ &dev);
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+
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+ if (!ret)
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+ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET,
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+ &r_therm_limit,
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+ sizeof(unsigned char));
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+ return ret;
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+}
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+
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static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
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{
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int ret;
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@@ -92,6 +115,12 @@ int spl_board_init_f(void)
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pwm_device_init();
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+ ret = init_tmp451_remote_therm_limit();
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+ if (ret) {
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+ debug("TMP451 remote THERM limit init failed: %d\n", ret);
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+ goto end;
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+ }
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+
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ret = spl_gemgxl_init();
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if (ret) {
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debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
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diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
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index a6da6e21..f166de4c 100644
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--- a/drivers/misc/Kconfig
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+++ b/drivers/misc/Kconfig
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@@ -538,6 +538,16 @@ config SYS_I2C_EEPROM_ADDR
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if I2C_EEPROM
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+config SYS_I2C_TMP451_ADDR
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+ hex "Chip address of the TMP451 device"
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+ default 0
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+
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+config SYS_I2C_TMP451_ADDR_LEN
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+ int "Length in bytes of the TMP451 memory array address"
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+ default 1
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+ help
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+ Note: This is NOT the chip address length!
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+
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config SYS_I2C_EEPROM_ADDR_OVERFLOW
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hex "EEPROM Address Overflow"
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default 0x0
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diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
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index 9923f3d9..96c6e8df 100644
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--- a/include/configs/sifive-unmatched.h
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+++ b/include/configs/sifive-unmatched.h
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@@ -15,6 +15,10 @@
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
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+#define CONFIG_SYS_TMP451_BUS_NUM 0
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+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c
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+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1
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+
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/* Environment options */
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#define BOOT_TARGET_DEVICES(func) \
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diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
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index f505722f..032126d8 100644
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--- a/scripts/config_whitelist.txt
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+++ b/scripts/config_whitelist.txt
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@@ -1268,6 +1268,7 @@ CONFIG_SYS_TIMER_BASE
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CONFIG_SYS_TIMER_COUNTER
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CONFIG_SYS_TIMER_COUNTS_DOWN
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CONFIG_SYS_TIMER_RATE
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+CONFIG_SYS_TMP451_BUS_NUM
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CONFIG_SYS_TMPVIRT
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CONFIG_SYS_TSEC1_OFFSET
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CONFIG_SYS_TX_ETH_BUFFER
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--
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2.37.3
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@ -0,0 +1,68 @@
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From 9fba4e75ae1b09bd9d58bf09b3dab02d25f85b30 Mon Sep 17 00:00:00 2001
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From: David Abdurachmanov <davidlt@rivosinc.com>
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Date: Thu, 17 Nov 2022 13:16:58 +0200
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Subject: [PATCH 3/3] Enable "sbi" command and SBI sysreset
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Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
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---
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configs/qemu-riscv64_defconfig | 5 +++++
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configs/qemu-riscv64_smode_defconfig | 5 +++++
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configs/sifive_unleashed_defconfig | 5 +++++
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configs/sifive_unmatched_defconfig | 5 +++++
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4 files changed, 20 insertions(+)
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diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
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index d5eae95c..611d5eb3 100644
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--- a/configs/qemu-riscv64_defconfig
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+++ b/configs/qemu-riscv64_defconfig
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@@ -21,3 +21,8 @@ CONFIG_CMD_NVEDIT_EFI=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_DM_MTD=y
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CONFIG_SYS_MAX_FLASH_BANKS=2
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+CONFIG_CMD_SBI=y
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+CONFIG_SYSRESET=y
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+CONFIG_SYSRESET_SBI=y
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+CONFIG_CMD_POWEROFF=y
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+CONFIG_SYSRESET_CMD_POWEROFF=y
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diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
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index 1cb06b4b..26f9f632 100644
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--- a/configs/qemu-riscv64_smode_defconfig
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+++ b/configs/qemu-riscv64_smode_defconfig
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@@ -24,3 +24,8 @@ CONFIG_CMD_NVEDIT_EFI=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_DM_MTD=y
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CONFIG_SYS_MAX_FLASH_BANKS=2
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+CONFIG_CMD_SBI=y
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+CONFIG_SYSRESET=y
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+CONFIG_SYSRESET_SBI=y
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+CONFIG_CMD_POWEROFF=y
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+CONFIG_SYSRESET_CMD_POWEROFF=y
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diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
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index 99faabaa..e85877bc 100644
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--- a/configs/sifive_unleashed_defconfig
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+++ b/configs/sifive_unleashed_defconfig
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@@ -40,3 +40,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_CLK=y
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CONFIG_DM_MTD=y
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CONFIG_DM_RESET=y
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+CONFIG_CMD_SBI=y
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+CONFIG_SYSRESET=y
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+CONFIG_SYSRESET_SBI=y
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+CONFIG_CMD_POWEROFF=y
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+CONFIG_SYSRESET_CMD_POWEROFF=y
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diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
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index c390af26..4dd545fa 100644
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--- a/configs/sifive_unmatched_defconfig
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+++ b/configs/sifive_unmatched_defconfig
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@@ -62,3 +62,8 @@ CONFIG_DM_SCSI=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PCI=y
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+CONFIG_CMD_SBI=y
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+CONFIG_SYSRESET=y
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+CONFIG_SYSRESET_SBI=y
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+CONFIG_CMD_POWEROFF=y
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+CONFIG_SYSRESET_CMD_POWEROFF=y
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--
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2.37.3
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|
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@ -0,0 +1,5 @@
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qemu-riscv64
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qemu-riscv64_smode
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qemu-riscv64_spl
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sifive_unleashed
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sifive_unmatched
|
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@ -5,9 +5,12 @@
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%bcond_with toolsonly
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%endif
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# Set it to "opensbi" (stable) or opensbi-unstable (unstable, git)
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%global opensbi opensbi-unstable
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Name: uboot-tools
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Version: 2022.10
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Release: 1%{?candidate:.%{candidate}}%{?dist}
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Release: 1%{?candidate:.%{candidate}}.0.riscv64%{?dist}
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Summary: U-Boot utilities
|
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License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
|
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URL: http://www.denx.de/wiki/U-Boot
|
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|
@ -15,6 +18,7 @@ URL: http://www.denx.de/wiki/U-Boot
|
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ExcludeArch: s390x
|
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Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2
|
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Source1: aarch64-boards
|
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Source2: riscv64-boards
|
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# Fedoraisms patches
|
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# Needed to find DT on boot partition that's not the first partition
|
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|
@ -31,6 +35,11 @@ Patch6: rpi-Copy-properties-from-firmware-DT-to-loaded-DT.patch
|
|||
Patch7: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
|
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Patch8: 0001-Revert-power-pmic-rk8xx-Support-sysreset-shutdown-me.patch
|
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|
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# RISC-V (riscv64) patches
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Patch20: 0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
|
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Patch21: 0002-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
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Patch22: 0003-Enable-sbi-command-and-SBI-sysreset.patch
|
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BuildRequires: bc
|
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BuildRequires: bison
|
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BuildRequires: dtc
|
||||
|
@ -51,6 +60,9 @@ BuildRequires: swig
|
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BuildRequires: arm-trusted-firmware-armv8
|
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%endif
|
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Requires: dtc
|
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%ifarch riscv64
|
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BuildRequires: %{opensbi}
|
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%endif
|
||||
|
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%description
|
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This package contains a few U-Boot utilities - mkimage for creating boot images
|
||||
|
@ -79,7 +91,11 @@ mkdir builds
|
|||
%make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-all O=builds/
|
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|
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%if %{with toolsonly}
|
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%ifarch aarch64
|
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%ifarch riscv64
|
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export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin
|
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%endif
|
||||
|
||||
%ifarch aarch64 riscv64
|
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for board in $(cat %{_arch}-boards)
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do
|
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echo "Building board: $board"
|
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|
@ -149,6 +165,19 @@ done
|
|||
install -p -m 0644 builds/apple_m1/u-boot-nodtb.bin %{buildroot}%{_datadir}/uboot/apple_m1/u-boot-nodtb.bin
|
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%endif
|
||||
|
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%ifarch riscv64
|
||||
for board in $(ls builds)
|
||||
do
|
||||
mkdir -p %{buildroot}%{_datadir}/uboot/$(echo $board)/
|
||||
for file in u-boot.bin u-boot.dtb u-boot.img u-boot-nodtb.bin u-boot-dtb.bin u-boot.itb u-boot-dtb.img u-boot.its spl/u-boot-spl.bin spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb spl/u-boot-spl-dtb.bin
|
||||
do
|
||||
if [ -f builds/$(echo $board)/$(echo $file) ]; then
|
||||
install -p -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/
|
||||
fi
|
||||
done
|
||||
done
|
||||
%endif
|
||||
|
||||
# Bit of a hack to remove binaries we don't use as they're large
|
||||
%ifarch aarch64
|
||||
for board in $(ls builds)
|
||||
|
@ -207,9 +236,17 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand
|
|||
%files -n uboot-images-armv8
|
||||
%{_datadir}/uboot/*
|
||||
%endif
|
||||
|
||||
%ifarch riscv64
|
||||
%files -n uboot-images-riscv64
|
||||
%{_datadir}/uboot/*
|
||||
%endif
|
||||
%endif
|
||||
|
||||
%changelog
|
||||
* Thu Nov 17 2022 David Abdurachmanov <davidlt@rivosinc.com> - 2022.10-1.0.riscv64
|
||||
- Add support for riscv64
|
||||
|
||||
* Mon Oct 10 2022 Peter Robinson <pbrobinson@fedoraproject.org> - 2022.10-1
|
||||
- Update to 2022.10 GA
|
||||
|
||||
|
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Loading…
Reference in New Issue