diff --git a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch index 3e76ea9..720b1ba 100644 --- a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch +++ b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch @@ -1,990 +1,30 @@ -From patchwork Tue May 12 18:47:08 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288721 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=d38K5udu; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest - SHA256) (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6Hv66Ygz9sRR - for ; Wed, 13 May 2020 04:47:55 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id B84F981CA7; - Tue, 12 May 2020 20:47:46 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="d38K5udu"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 58E8981CB4; Tue, 12 May 2020 20:47:46 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com - [210.118.77.11]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 5033481CA7 - for ; Tue, 12 May 2020 20:47:43 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) - by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184742euoutp01bc8b3eb5b03aea7061c9771d94376063~OXFqTZrdZ0824908249euoutp01M - for ; Tue, 12 May 2020 18:47:42 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com - 20200512184742euoutp01bc8b3eb5b03aea7061c9771d94376063~OXFqTZrdZ0824908249euoutp01M -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309262; - bh=y/xHx6cn6ZNuvX3V5jxpugf8Q65fZIBo5wp4jEitdVo=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=d38K5uduUnUgAuBY2HpLVidScZmwLS83XuAEP71VwqJPtHkIEcrtqnNuN+x7Vo5LB - xI47QIftGzVsub55jILxMD5WJglh2JRL6h/sha0zJZGbRvnGclE1yePigHBSvHJq8e - NKVp6Rgvvlb/0F3rQzneLiaVnOQ04AM1cU+Q0O5U= -Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTP id - 20200512184741eucas1p2f963249ca616e99f379cb8519a45c7df~OXFpSf8vj0944309443eucas1p2h; - Tue, 12 May 2020 18:47:41 +0000 (GMT) -Received: from eucas1p1.samsung.com ( [182.198.249.206]) by - eusmges3new.samsung.com (EUCPMTA) with SMTP id 06.03.60698.D4FEABE5; Tue, 12 - May 2020 19:47:41 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTPA id - 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9~OXFopWAVc0733307333eucas1p2p; - Tue, 12 May 2020 18:47:40 +0000 (GMT) -Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184740eusmtrp285c7f01d30cd705bf6708beea010fb5e~OXFootnX41654116541eusmtrp2e; - Tue, 12 May 2020 18:47:40 +0000 (GMT) -X-AuditID: cbfec7f5-a0fff7000001ed1a-48-5ebaef4d163d -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms1.samsung.com (EUCPMTA) with SMTP id 87.DA.08375.C4FEABE5; Tue, 12 - May 2020 19:47:40 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184740eusmtip1218b8e5fecda20fd55cc193294a6f3b1~OXFoEyWsp2574925749eusmtip16; - Tue, 12 May 2020 18:47:40 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 1/9] usb: xhci: Add missing cache flush in the scratchpad - array initialization -Date: Tue, 12 May 2020 20:47:08 +0200 -Message-Id: <20200512184716.2869-2-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHKsWRmVeSWpSXmKPExsWy7djPc7q+73fFGWxeLm2xccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGXc - XfWasWAKZ8XHpQeYGhjPsncxcnJICJhIrF/3BMjm4hASWMEo8fr8L1YI5wujxJmdXcwQzmdG - idPv17PAtNxZtJQRIrGcUWLemw8scC33Vj8EG8wmYCjRe7SPEcQWEQiQuPZzGlgHs8BRRok1 - +/+AjRIWSJbY+GYJmM0ioCpxsucAmM0rYCXx7u4iVoh18hKrNxxgBrE5Bawlrm8+BnaThMAq - dokV/6ZAveEiMXnjaqgGYYlXx7dAxWUk/u+czwTR0Mwo0bP7NjuEM4FR4v7xBYwQVdYSd879 - Yuti5AC6T1Ni/S59EFNCwFHi83MtCJNP4sZbQZBiZiBz0rbpzBBhXomONiGIGSoSv1dNZ4Kw - pSS6n/yHhpaHxIFJu8DOFxLoY5SY9NFzAqP8LIRVCxgZVzGKp5YW56anFhvnpZbrFSfmFpfm - pesl5+duYgSmmtP/jn/dwbjvT9IhRgEORiUe3oj6XXFCrIllxZW5hxglOJiVRHhbMnfGCfGm - JFZWpRblxxeV5qQWH2KU5mBREuc1XvQyVkggPbEkNTs1tSC1CCbLxMEp1cAY8FeRl+/HltTN - X4Xs903RVHy5e6dgqpeg0jm+4OVBkrPvpUVJPnj+KVdkzo41t/PuMjReEPlxUCtyWmyHz103 - rgXPZq0ykbWOfJ3YefagS9XPQu/PB+O5tq6w9/7zm4Vf6+bV1z8qDodnyLT/WPJqT6T6+32H - jgl/27XgeAnrlllibgaZdotvKrEUZyQaajEXFScCAAKlHx8xAwAA -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7o+73fFGUxZr2+xccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF - G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GXcXfWasWAKZ8XHpQeYGhjPsncx - cnJICJhI3Fm0lLGLkYtDSGApo8SCbWtZuhg5gBJSEvNblCBqhCX+XOtig6j5xCixZOleFpAE - m4ChRO/RPkYQW0QgROLF0StMIEXMAmcZJRZ1fmAFSQgLJErMbDgGZrMIqEqc7DkA1swrYCXx - 7u4iVogN8hKrNxxgBrE5Bawlrm8+BmYLAdXs+faObQIj3wJGhlWMIqmlxbnpucWGesWJucWl - eel6yfm5mxiBgb/t2M/NOxgvbQw+xCjAwajEw8tQuytOiDWxrLgy9xCjBAezkghvS+bOOCHe - lMTKqtSi/Pii0pzU4kOMpkBHTWSWEk3OB0ZlXkm8oamhuYWlobmxubGZhZI4b4fAwRghgfTE - ktTs1NSC1CKYPiYOTqkGRvHA5utdDK+71Gc8yncU/Jl1s8GwlfnWtf/fvVcf2j1n1dGNJtMn - +bzXEb/JdkYl/OLZA3Vvo7aKLFyzg7Gsd9N+h4PpR6bHn7zJ79VRWnHmnV1WVtDq6BmPbh3d - 8qTxqqDqXif96Ra5p80yGxK5+NgP7Gd22F52neeB/7I+A4//v1Y946i/MFmJpTgj0VCLuag4 - EQDJGyeQkgIAAA== -X-CMS-MailID: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9 -X-Msg-Generator: CA -X-RootMTR: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9 -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184740eucas1p2912f07b9e34cc769604d641adb0e13c9 -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean +From 47d0df70fbe5997770090aca05b07d774a19a722 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 10 Jun 2020 13:15:45 +0100 +Subject: [PATCH] USB host support for Raspberry Pi 4 board (64-bit) -In current code there is no cache flush after initializing the scratchpad -buffer array with the scratchpad buffer pointers. This leads to a failure -of the "slot enable" command on the rpi4 board (Broadcom STB PCIe -controller + VL805 USB hub) - the very first TRB transfer on the command -ring fails and there is a timeout while waiting for the command completion -event. After adding the missing cache flush everything seems to be working -as expected. - -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne +Signed-off-by: Peter Robinson --- -Changes since v1: - - none. ---- - drivers/usb/host/xhci-mem.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c -index 93450ee..729bdc3 100644 ---- a/drivers/usb/host/xhci-mem.c -+++ b/drivers/usb/host/xhci-mem.c -@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) - scratchpad->sp_array[i] = cpu_to_le64(ptr); - } - -+ xhci_flush_cache((uintptr_t)scratchpad->sp_array, -+ sizeof(u64) * num_sp); -+ - return 0; - - fail_sp3: - -From patchwork Tue May 12 18:47:09 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288726 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=grr5hJg0; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6J52FSkz9sSc - for ; Wed, 13 May 2020 04:48:05 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 031D381CCA; - Tue, 12 May 2020 20:47:52 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="grr5hJg0"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id DBE4481CCA; Tue, 12 May 2020 20:47:49 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com - [210.118.77.11]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 3D53381CC5 - for ; Tue, 12 May 2020 20:47:47 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) - by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184746euoutp01fb38409a07247ba29f423e8e26c681a3~OXFtquXqn0815408154euoutp01S - for ; Tue, 12 May 2020 18:47:46 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com - 20200512184746euoutp01fb38409a07247ba29f423e8e26c681a3~OXFtquXqn0815408154euoutp01S -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309266; - bh=mpc5rYw/U19wNz9z3l9qIGYqOM/GqAOeD9khN0UIZwU=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=grr5hJg01HyaYOSo5sRsqNi8H29+t1SJtvzpcW0TcS7Uq3xNGmFHYWcWw2hlEFBXm - SQcD5H70xlOq1k6aVxDV3EJK128Qww1iZyma0H7nEfCs1WuOaohM/qnzdBhfwcwftI - AmLAlKxzDpQym+Hg21E2PBd9E56u9ZhxeKuVbjNs= -Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTP id - 20200512184745eucas1p29454eee0ca9ecc030620e98c3cb0577f~OXFspLApW2836228362eucas1p2B; - Tue, 12 May 2020 18:47:45 +0000 (GMT) -Received: from eucas1p2.samsung.com ( [182.198.249.207]) by - eusmges3new.samsung.com (EUCPMTA) with SMTP id C6.03.60698.05FEABE5; Tue, 12 - May 2020 19:47:44 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTPA id - 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58~OXFrcGgkD0735407354eucas1p2X; - Tue, 12 May 2020 18:47:43 +0000 (GMT) -Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184743eusmtrp22630032f69ad78af217c4cc4e810fb3e~OXFrbdvJf1654916549eusmtrp2d; - Tue, 12 May 2020 18:47:43 +0000 (GMT) -X-AuditID: cbfec7f5-a0fff7000001ed1a-4c-5ebaef500edc -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms1.samsung.com (EUCPMTA) with SMTP id 48.DA.08375.F4FEABE5; Tue, 12 - May 2020 19:47:43 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184743eusmtip16a33a390496025d0cd045c1a3826c2c0~OXFqzC1Wy3146231462eusmtip1f; - Tue, 12 May 2020 18:47:43 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki , Sergey Temerkhanov - -Subject: [PATCH v3 2/9] usb: xhci: Use only 32-bit accesses in - xhci_writeq/xhci_readq -Date: Tue, 12 May 2020 20:47:09 +0200 -Message-Id: <20200512184716.2869-3-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRju2845O5qL05R8M8EYRRhecdQhLylJnh8ikpJSNFt5UPHappb1 - Q0NZzjuJGou8NGyhpKlrOW95NxLTJE1KUcMyRQu1RTPRnEfr3/M+l/d9+PhIvqgatyNjEpJZ - eYIsTkxYYvp+07Bz8I8WqVtrhxfd8KAep0vyIuj2pUKCnlhX4vSz3ikBvaS8i+jK4jmc1qu1 - BN2zdA+nq9UdAvqXTo/o5XaVwNeKUU8PEczDjHcYU65+jTEG9ZSAGZpsRkyBrgYx9boxjGka - vBNMXrL0imTjYlJZuavPVctoQ3EVnrRG3VrJ1hAZaFaYgyxIoCSge1mO5yBLUkQ9RfBdtUhw - w08Ekwuju8MaAlONUrAXaVQqESdoETR8LOH9i+hqX/DMLoJyh/y+AmTGNlQwjJtKdxJ8yojg - Te4IZhasqTBQjc4SZoxRx0G7odkJC6kz8HWwA+POOUDt806+GVtQnvChqZ9vXgRUnQDaCvMJ - zuQPBqMK57A1LA7odrvaw5ahgscFMhHktX4ScEMRgumBSsS5PGHy7fr2JnK7nyPUt7hytB9U - /NbzzDRQB2Bi+aCZ5m/D+/oyPkcLIVsp4tzH4E9NGY/DdpA7t7Xbn4G1vjoB90IFCDK7THgR - clD/P1aJUA2yZVMU8VGswiOBvemikMUrUhKiXK4nxjei7c8zuDlgbEYdG9e6EUUisZUwPL1F - KsJlqYq0+G4EJF9sI8yKMUhFwkhZ2m1WnhghT4ljFd3oCImJbYUejxeuiKgoWTIby7JJrHxP - 5ZEWdhno9GbOeQf7Vl+Jk8nnRLVIMhTnGHaoR+Kq6kppqzi7fMF7ZSKwp9d/3njKu0UyrZUG - Tc84TXaFfjOi1dHQi/OJY5rxG6VPqoZfHVWpIoICwvcHhkCAW2Rr+8RI+rBGmV13+Zzmi/Oj - GTj8WYhQFa/Or3a1d19tQ2xI5/ssqU2BGFNEy9xP8uUK2V8p3t8YOAMAAA== -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42I5/e/4XV3/97viDHb26llsnLGe1WJqT7zF - 3jf9bBY3frWxWqw9cpfd4k1bI6PFgslPWC22zVrOZnH4TTurxdJZ+9gtvm3Zxmjxdm8nuwOP - x6z7Z9k8ZjdcZPGYN+sEi8fOWXfZPc7e2cHo0bdlFaPH+i1XWTw2n64O4IjSsynKLy1JVcjI - Ly6xVYo2tDDSM7S00DMysdQzNDaPtTIyVdK3s0lJzcksSy3St0vQy9g5eSFrwWeBio8di9ka - GB/ydjFyckgImEhsamtj7GLk4hASWMoosWrtQiCHAyghJTG/RQmiRljiz7UuNoiaT4wSjVff - soAk2AQMJXqP9jGC2CICIRIvjl5hAiliFvjLKDGp9QkrSEJYIFTi7tP5YDaLgKrE8j+LmUBs - XgEriWen97FAbJCXWL3hADOIzSlgLXF98zEwWwioZs+3d2wTGPkWMDKsYhRJLS3OTc8tNtQr - TswtLs1L10vOz93ECIyBbcd+bt7BeGlj8CFGAQ5GJR5ehtpdcUKsiWXFlbmHGCU4mJVEeFsy - d8YJ8aYkVlalFuXHF5XmpBYfYjQFOmois5Rocj4wPvNK4g1NDc0tLA3Njc2NzSyUxHk7BA7G - CAmkJ5akZqemFqQWwfQxcXBKNTB6nbS75KLLcXaSEefxVQuf7fj8f9bj7/+W83UdTBPtbEo9 - LXT2+/znb9WWx/X7dl++fTu/uqBaPixV8t3/v6YG/SXmdQ/NeHqaT3MnmTe3rbNZkZFrr1IY - y//PRYDVYEtvSsrjr8UK0VdCpk42XPb0vaNeRErYDM4ZZm4ajV3LF4k56rzcN0uJpTgj0VCL - uag4EQCTL19flwIAAA== -X-CMS-MailID: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58 -X-Msg-Generator: CA -X-RootMTR: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58 -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184743eucas1p28e9d93ba5e46ed900a88bf0bf85fda58 -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -There might be hardware configurations where 64-bit data accesses -to XHCI registers are not supported properly. This patch removes -the readq/writeq so always two 32-bit accesses are used to read/write -64-bit XHCI registers, similarly as it is done in Linux kernel. - -This patch fixes operation of the XHCI controller on RPI4 Broadcom -BCM2711 SoC based board, where the VL805 USB XHCI controller is -connected to the PCIe Root Complex, which is attached to the system -through the SCB bridge. - -Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely -the 64-bit wide register accesses initiated by the CPU are not properly -translated to a sequence of 32-bit PCIe accesses. -xhci_readq(), for example, always returns same value in upper and lower -32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. - -Cc: Sergey Temerkhanov -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne ---- -Changes since v1: - - none. -Changes since RFC: - - dropped Kconfig option, switched to not using readq/writeq - unconditionally. ---- - include/usb/xhci.h | 8 -------- - 1 file changed, 8 deletions(-) - -diff --git a/include/usb/xhci.h b/include/usb/xhci.h -index 6017504..c16106a 100644 ---- a/include/usb/xhci.h -+++ b/include/usb/xhci.h -@@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) - */ - static inline u64 xhci_readq(__le64 volatile *regs) - { --#if BITS_PER_LONG == 64 -- return readq(regs); --#else - __u32 *ptr = (__u32 *)regs; - u64 val_lo = readl(ptr); - u64 val_hi = readl(ptr + 1); - return val_lo + (val_hi << 32); --#endif - } - - static inline void xhci_writeq(__le64 volatile *regs, const u64 val) - { --#if BITS_PER_LONG == 64 -- writeq(val, regs); --#else - __u32 *ptr = (__u32 *)regs; - u32 val_lo = lower_32_bits(val); - /* FIXME */ - u32 val_hi = upper_32_bits(val); - writel(val_lo, ptr); - writel(val_hi, ptr + 1); --#endif - } - - int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, - -From patchwork Tue May 12 18:47:10 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288728 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=MQb96qeW; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6JZ0HY9z9sRR - for ; Wed, 13 May 2020 04:48:29 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 97A5E81CE6; - Tue, 12 May 2020 20:47:55 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="MQb96qeW"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 91CEA81CD5; Tue, 12 May 2020 20:47:52 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com - [210.118.77.11]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id EC86281C9C - for ; Tue, 12 May 2020 20:47:49 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) - by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184749euoutp01f49ee1d587539ddc7a686993e968522f~OXFw3ZAYX0815408154euoutp01T - for ; Tue, 12 May 2020 18:47:49 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com - 20200512184749euoutp01f49ee1d587539ddc7a686993e968522f~OXFw3ZAYX0815408154euoutp01T -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309269; - bh=o2n59jAOXed94iksPXrzyyjRiAB6FlEj8rUQ47ogyyk=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=MQb96qeW8BGeMLYvoFF8R5AK1VxRLBF9DKrHdA78h1FGD56P/N3T9UWKZFfPK+zeT - 0f2oSHQ2MVqRnuwpxzTWSHmbVuBZJE89UYjb1wU+vXivuiwfqiftxIkx0H74WHDljA - QPw23KgCLp0pZQt4sPsJz2xniqkbi21z32ANnwxM= -Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by - eucas1p1.samsung.com (KnoxPortal) with ESMTP id - 20200512184748eucas1p11ef796b4c399aa64b9557a31eeeb908b~OXFwGTfiE2309523095eucas1p1z; - Tue, 12 May 2020 18:47:48 +0000 (GMT) -Received: from eucas1p1.samsung.com ( [182.198.249.206]) by - eusmges2new.samsung.com (EUCPMTA) with SMTP id 52.AA.60679.45FEABE5; Tue, 12 - May 2020 19:47:48 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTPA id - 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5~OXFvEnnod0735407354eucas1p2Z; - Tue, 12 May 2020 18:47:47 +0000 (GMT) -Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184747eusmtrp220606fb120fb3b6d130b61b70b1a907f~OXFvD_isr1654116541eusmtrp2g; - Tue, 12 May 2020 18:47:47 +0000 (GMT) -X-AuditID: cbfec7f4-0cbff7000001ed07-c4-5ebaef540342 -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms1.samsung.com (EUCPMTA) with SMTP id 89.DA.08375.35FEABE5; Tue, 12 - May 2020 19:47:47 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184747eusmtip1652b74d3fc922a12e92ef0d0910e99c5~OXFub85B-3146231462eusmtip1g; - Tue, 12 May 2020 18:47:46 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 3/9] pci: Move some PCIe register offset definitions to a - common header -Date: Tue, 12 May 2020 20:47:10 +0200 -Message-Id: <20200512184716.2869-4-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDKsWRmVeSWpSXmKPExsWy7djPc7oh73fFGTw6rm2xccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGVM - nqNYMF2y4vHC/4wNjM9Euhg5OSQETCSm/ZvDDmILCaxglOjZH9DFyAVkf2GUeLzoMzuE85lR - ou/UDXaYjlM9R1khEssZJQ4+P8UK0Q7Usmy+B4jNJmAo0Xu0jxHEFhEIkLj2cxojSAOzwFFG - iTX7/7CAJIQFYiTO77/MBGKzCKhKTL1xBKyBV8BKYs3S12wQ2+QlVm84wAxicwpYS1zffIwZ - ZJCEwDJ2iVW7F0Kd5CKx79h1RghbWOLV8S1QcRmJ/zvnM0E0NAM9t/s2O4QzgVHi/vEFUB3W - EnfO/QJaxwF0n6bE+l36EGFHiemPdoCFJQT4JG68FQQJMwOZk7ZNZ4YI80p0tAlBVKtI/F41 - nQnClpLofvKfBaLEQ2L5NAdIYPUB/d76iW0Co/wshF0LGBlXMYqnlhbnpqcWG+WllusVJ+YW - l+al6yXn525iBKaZ0/+Of9nBuOtP0iFGAQ5GJR5ehtpdcUKsiWXFlbmHGCU4mJVEeFsyd8YJ - 8aYkVlalFuXHF5XmpBYfYpTmYFES5zVe9DJWSCA9sSQ1OzW1ILUIJsvEwSnVwLh1z5TeG0az - +Xfd3FB0+/pjvrtznq13cFFY6DvDfpdPqclmFr4pB1beCCs7lOQ78cOhHwlnVjI6zEmc2Ozz - UzA48qrRrx/LPvqqt87Nqaz10/n2edvVDtvtE8Xe3rXad+vYkdXTZH6FOV5copT6IaCd1+u9 - COurmnJJL6c5pbV9++z8vrjw1O5UYinOSDTUYi4qTgQAvI6vdC8DAAA= -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xu7rB73fFGTxpUbXYOGM9q8XUnniL - vW/62Sxu/GpjtVh75C67xZu2RkaLBZOfsFpsm7WczeLwm3ZWi29btjFavN3bye7A7THr/lk2 - j9kNF1k85s06weKxc9Zddo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi - DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DImz1EsmC5Z8Xjhf8YGxmciXYyc - HBICJhKneo6ydjFycQgJLGWUOL/kGnsXIwdQQkpifosSRI2wxJ9rXWwQNZ8YJe61LGACSbAJ - GEr0Hu1jBLFFBEIkXhy9wgRSxCxwllFiUecHVpCEsECUxIvfjWBFLAKqElNvHAGzeQWsJNYs - fc0GsUFeYvWGA8wgNqeAtcT1zcfAbCGgmj3f3rFNYORbwMiwilEktbQ4Nz232FCvODG3uDQv - XS85P3cTIzDstx37uXkH46WNwYcYBTgYlXh4GWp3xQmxJpYVV+YeYpTgYFYS4W3J3BknxJuS - WFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnAmMwriTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliS - mp2aWpBaBNPHxMEp1cAo8NYxO8Jqj6PRV77edRqM6d/fPNh+ckp9/fKwsoWn/NSufp8boJey - O+/Wy/nTzpj1bt4798PtHSdmhmywaQj0KVYtD5qat1b7GMvEYBcra0Ze5hft2f6SH/t0Lumf - lXf9Pqv43uddiwVjUyRvrP5qZmy664CmlFb7nrstPeLfGxjWC3ooze9TYinOSDTUYi4qTgQA - d2ZzFZECAAA= -X-CMS-MailID: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5 -X-Msg-Generator: CA -X-RootMTR: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5 -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184747eucas1p25ed7fb872416271dd34806ccfb4197e5 -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Some PCI Express register offsets are currently defined in multiple -drivers, move them to a common header to avoid re-definitions and -as a pre-requisite for adding new PCIe driver. -While at it replace some spaces with tabs. - -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne ---- -Changes since v1: - - none. -Changes since RFC: - - whitespace clean up. ---- - drivers/pci/pci-rcar-gen3.c | 8 -------- - drivers/pci/pcie_intel_fpga.c | 3 --- - include/pci.h | 13 +++++++++++-- - 3 files changed, 11 insertions(+), 13 deletions(-) - -diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c -index 30eff67..393f1c9 100644 ---- a/drivers/pci/pci-rcar-gen3.c -+++ b/drivers/pci/pci-rcar-gen3.c -@@ -117,14 +117,6 @@ - #define RCAR_PCI_MAX_RESOURCES 4 - #define MAX_NR_INBOUND_MAPS 6 - --#define PCI_EXP_FLAGS 2 /* Capabilities register */ --#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ --#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ --#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ --#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ --#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ --#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -- - enum { - RCAR_PCI_ACCESS_READ, - RCAR_PCI_ACCESS_WRITE, -diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c -index 6a9f29c..69363a0 100644 ---- a/drivers/pci/pcie_intel_fpga.c -+++ b/drivers/pci/pcie_intel_fpga.c -@@ -65,9 +65,6 @@ - #define IS_ROOT_PORT(pcie, bdf) \ - ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) - --#define PCI_EXP_LNKSTA 18 /* Link Status */ --#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -- - /** - * struct intel_fpga_pcie - Intel FPGA PCIe controller state - * @bus: Pointer to the PCI bus -diff --git a/include/pci.h b/include/pci.h -index aff56b2..dfdbb32 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -471,10 +471,19 @@ - #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ - - /* PCI Express capabilities */ -+#define PCI_EXP_FLAGS 2 /* Capabilities register */ -+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ - #define PCI_EXP_DEVCAP 4 /* Device capabilities */ --#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ -+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ - #define PCI_EXP_DEVCTL 8 /* Device Control */ --#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -+#define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - - /* Include the ID list */ - - -From patchwork Tue May 12 18:47:11 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288729 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=DMPfLXHn; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6Jq5kVFz9sSW - for ; Wed, 13 May 2020 04:48:43 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 6DD0981CA0; - Tue, 12 May 2020 20:48:35 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="DMPfLXHn"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 1708981CCA; Tue, 12 May 2020 20:48:34 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com - [210.118.77.11]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 268AA81C8F - for ; Tue, 12 May 2020 20:48:31 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) - by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184830euoutp01ccbc955d4e553cfcc652df2a8a26a7bd~OXGXNrozu0823008230euoutp01U - for ; Tue, 12 May 2020 18:48:30 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com - 20200512184830euoutp01ccbc955d4e553cfcc652df2a8a26a7bd~OXGXNrozu0823008230euoutp01U -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309310; - bh=3E0AOgx9hU8sLyjssq8h9uGtoMBKiYQYmWKYKj8g+7M=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=DMPfLXHnOgmW1Z4KlAl/NdPP5dLcXH56gib60eMcKVBH/cg4pQkIlBSZPlg8WU47T - OSf3QryKG/0HgRi0epoYgVCWYqdtWu+elalkhjiDXrHEaN9KpotUASwVVmKc6vxZUq - sQhwySR6duVQzCazExVuqPC71RShDpAqqkiFjqrg= -Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTP id - 20200512184830eucas1p26b67732246d5cd7a6247fa6e114db6d0~OXGW73iC-0949309493eucas1p2v; - Tue, 12 May 2020 18:48:30 +0000 (GMT) -Received: from eucas1p2.samsung.com ( [182.198.249.207]) by - eusmges3new.samsung.com (EUCPMTA) with SMTP id 7D.03.60698.E7FEABE5; Tue, 12 - May 2020 19:48:30 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7~OXGVv7OF12080520805eucas1p1u; - Tue, 12 May 2020 18:48:29 +0000 (GMT) -Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184829eusmtrp262ea470daeba61b3d4efb349c6418007~OXGVvS8Ut1654916549eusmtrp2n; - Tue, 12 May 2020 18:48:29 +0000 (GMT) -X-AuditID: cbfec7f5-a29ff7000001ed1a-89-5ebaef7eefa5 -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms2.samsung.com (EUCPMTA) with SMTP id 22.F8.07950.D7FEABE5; Tue, 12 - May 2020 19:48:29 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184828eusmtip1a8d7ad1b8a25aeb694a863a0e7798f73~OXGVOX36p1659716597eusmtip1h; - Tue, 12 May 2020 18:48:28 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 4/9] rpi4: shorten a mapping for the DRAM -Date: Tue, 12 May 2020 20:47:11 +0200 -Message-Id: <20200512184716.2869-5-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRjm81x2XC5O0/JLLWPUj6J0YuQhpQv24/wKIQgzUpee3NBN2bxk - oS4Mzfs0dDIlh3jDvOVs3tPMqWFzpmiS1x9aZLMQU9KstXlm/Xue532f73le+AiEX4G5ERJZ - PCOXiWIEOBfVD22bzqV+7woVDhYfp16UNmNUcW4Y1WsuwKmZnQyMahyc51DmjEeA0j5dxii9 - phan3pgzMWqrTQ+otd4szpUDtGbRiNNlyvco/UwzgtKdmnkObZzrAHR+Wz2gm9umUFo3+jCI - COEGRDIxkkRG7n0pnCve2tWicUv4/W1LHq4ERiwbOBKQPA8/Npai2YBL8Mk6AFd/btjJDwBL - THMISzasRNXH2bcY2iftg1oAK7+asH+WpkIdYtvCSR+YZ8gHNuxCBsHp7RJgW0JIA4ANfbuo - beBMBsCcniLchlHyFPxdZNlrxSMvwkrLCmDjPOHzlv69Rx1Jf/hBN7QXDckaDlypWbGfcQ2O - j1fbDc5wdbjN3tUDWjorHFhDOoC53bMclqgAXBzW2h3+cG5sx1qDsPY7DZu7vFn5Kuxez0Jt - MiQPwpm1QzYZscIivRphZR58ksFnt0/CX/VqBxa7wZxlC8piGr6c+LSH+WQ+gB2tUSrgqfmf - pQWgHrgyCQppFKPwlTFJXgqRVJEgi/KKiJW2Auu3Gf0zvNkBXu3eHQAkAQROvOC0rlA+JkpU - JEsHACQQgQvvsaQzlM+LFCU/YOSxYfKEGEYxANwJVODK8638codPRonimWiGiWPk+1MHwtFN - CYQpQnVaT2nysfDE1aaIqtbArJWlneYF9eWFw7cmMt3zI/JC1lMLouP8/IzY5G2TIbVxqvCd - wXzEYEkp32whdEwVphuZnvFQjZWVI6iY+rYutIyf1SjXTtyQ3HybHmjYckraaA++J25AEi+o - xrizkuu6sv7Pr49W96fWVaVwBahCLPI5g8gVor/Jvg12MgMAAA== -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7q173fFGcx6xW2xccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF - G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GV8+7OApeABW8XP/71sDYxnWbsY - OTkkBEwkjm6/zNzFyMUhJLCUUaJjUzuQwwGUkJKY36IEUSMs8edaFxtEzSdGif+9b5hAEmwC - hhK9R/sYQWwRgRCJF0evMIEUMQucZZRY1PkBbIOwgI1E955JbCA2i4CqxN9J/8HivAJWEov+ - P2WE2CAvsXrDAWYQm1PAWuL65mNgthBQzZ5v79gmMPItYGRYxSiSWlqcm55bbKRXnJhbXJqX - rpecn7uJERj424793LKDsetd8CFGAQ5GJR7eiPpdcUKsiWXFlbmHGCU4mJVEeFsyd8YJ8aYk - VlalFuXHF5XmpBYfYjQFOmois5Rocj4wKvNK4g1NDc0tLA3Njc2NzSyUxHk7BA7GCAmkJ5ak - ZqemFqQWwfQxcXBKNTCeUDjUsfdYk+GanwELP95YN2/J9NfGstu3nn42YcH/6UqTTE3bU24L - K74vEv6+x/hg276183j4TsoumBXpvTTv7cVjU+IfTC3dfey+2rcNU7fGmcuxiewVihLapvRL - 0n1/s5XyjSCz0n3PbGavd9gQt2xnnWCOWl68jfxdD++dF5ce1wrYx2xorcRSnJFoqMVcVJwI - AKKisECSAgAA -X-CMS-MailID: 20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7 -X-Msg-Generator: CA -X-RootMTR: 20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7 -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184829eucas1p10c67592f9af7879f51eee9bff8fa76d7 -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Marek Szyprowski - -Remove the overlap between DRAM and device's IO area. - -Signed-off-by: Marek Szyprowski -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Nicolas Saenz Julienne ---- -Changes since v1: - - none. ---- - arch/arm/mach-bcm283x/init.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + arch/arm/mach-bcm283x/init.c | 20 +- + configs/rpi_4_defconfig | 9 + + configs/rpi_arm64_defconfig | 8 +- + drivers/pci/Kconfig | 9 + + drivers/pci/Makefile | 1 + + drivers/pci/pci-rcar-gen3.c | 8 - + drivers/pci/pcie_brcmstb.c | 623 ++++++++++++++++++++++++++++++++++ + drivers/pci/pcie_intel_fpga.c | 3 - + drivers/usb/host/xhci-mem.c | 3 + + include/linux/bitfield.h | 52 +++ + include/pci.h | 22 +- + include/usb/xhci.h | 8 - + 12 files changed, 740 insertions(+), 26 deletions(-) + create mode 100644 drivers/pci/pcie_brcmstb.c diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 9966d6c..4295356 100644 +index f4d00d892d..cf4c5b245d 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c -@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -- .size = 0xfe000000UL, -+ .size = 0xfc000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - -From patchwork Tue May 12 18:47:12 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288730 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=PpqM0F3J; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6K33sdWz9sSW - for ; Wed, 13 May 2020 04:48:55 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 305E681CD4; - Tue, 12 May 2020 20:48:38 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="PpqM0F3J"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 2729181CA1; Tue, 12 May 2020 20:48:35 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com - [210.118.77.12]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 520C381CA0 - for ; Tue, 12 May 2020 20:48:32 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) - by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184831euoutp0223716d2be7dd8466639bb75ecdcd79b0~OXGXwE2rE0645506455euoutp02c - for ; Tue, 12 May 2020 18:48:31 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com - 20200512184831euoutp0223716d2be7dd8466639bb75ecdcd79b0~OXGXwE2rE0645506455euoutp02c -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309311; - bh=1pvJmD4788qVg9pTe/vSEzdnItJirsmIW08n7dgVDSA=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=PpqM0F3JtuV/Gbbx4WZDA0/EUnzelZKHiPHcezW/bOT3ROKOpL5P+hTILHd2Fa9az - AgjMlAoSUTV5jgyC183yxJiA00nZs3FMJ0Bs5apO3yGnMQ0VplTKbdtZOYCjfPLsW9 - X1PqGYiWoAETAzfxMLvtiQYLn2baNQR7KG6BB4jc= -Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTP id - 20200512184831eucas1p28c8414af443b820cd0031316c0b5f158~OXGXgiZCQ0944309443eucas1p2q; - Tue, 12 May 2020 18:48:31 +0000 (GMT) -Received: from eucas1p2.samsung.com ( [182.198.249.207]) by - eusmges1new.samsung.com (EUCPMTA) with SMTP id 2E.FF.61286.F7FEABE5; Tue, 12 - May 2020 19:48:31 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184830eucas1p198b1439122e2da299c563726fe17f9ef~OXGXJNK8p2314823148eucas1p1B; - Tue, 12 May 2020 18:48:30 +0000 (GMT) -Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184830eusmtrp2079ea429a5356a2e5cc978b0d5f43d24~OXGXIonFW1654116541eusmtrp2p; - Tue, 12 May 2020 18:48:30 +0000 (GMT) -X-AuditID: cbfec7f2-f0bff7000001ef66-8a-5ebaef7f3368 -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms2.samsung.com (EUCPMTA) with SMTP id E2.F8.07950.E7FEABE5; Tue, 12 - May 2020 19:48:30 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184830eusmtip128dac35d637f9caa48c5da04fe7aeb84~OXGWqET-G2778327783eusmtip1U; - Tue, 12 May 2020 18:48:30 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 5/9] rpi4: add a mapping for the PCIe XHCI controller - MMIO registers (ARM 64bit) -Date: Tue, 12 May 2020 20:47:12 +0200 -Message-Id: <20200512184716.2869-6-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPKsWRmVeSWpSXmKPExsWy7djP87r173fFGXxfxWKxccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGV8 - WriNvWCTYMWOfbvYGxgX8HUxcnJICJhITDy4ka2LkYtDSGAFo0TT213MEM4XRokzu3YwQjif - GSXajuxjg2npnd7MBJFYzihx7fJ5FriWpYe+M4NUsQkYSvQe7WMEsUUEAiSu/ZwGNopZ4Cij - xJr9f1hAEsICqRKNrx6CjWURUJX4Nm82WJxXwEriSu8/qHXyEqs3HAAbyilgLXF98zFmiPgy - domli0UgbBeJ39tnM0HYwhKvjm9hh7BlJP7vnA92qoRAM6NEz+7b7BDOBEaJ+8cXMEJUWUvc - OfcLaBsH0HmaEut36UOEHSWWbO5iBQlLCPBJ3HgrCBJmBjInbZvODBHmlehoE4KoVpH4vWo6 - 1AlSEt1P/rNA2B4St/YcYIUEUB8wgP6dZ5zAKD8LYdkCRsZVjOKppcW56anFhnmp5XrFibnF - pXnpesn5uZsYgcnm9L/jn3Ywfr2UdIhRgINRiYeXoXZXnBBrYllxZe4hRgkOZiUR3pbMnXFC - vCmJlVWpRfnxRaU5qcWHGKU5WJTEeY0XvYwVEkhPLEnNTk0tSC2CyTJxcEo1MM6MW6vHlv9O - LFWw4mzJiaOX1tgbcVh+DyhbVxBTPOG2iGxd2Z4Xll4nbb/t4i7Uli7/c69kR8TPP/0y3085 - Vj6bYJ3UkaklyinuIOjU32D/wGfFROcjPf0LmWOyko9vzpQ+8m5a1vbG6Ci9qXytx2L3WDz5 - PG/nWzffGb6Vz5lVNPRa7Y9PUmIpzkg01GIuKk4EAHeTlcEyAwAA -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7p173fFGbxeo2WxccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF - G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GV8WriNvWCTYMWOfbvYGxgX8HUx - cnJICJhI9E5vZupi5OIQEljKKHGu/wJjFyMHUEJKYn6LEkSNsMSfa11sEDWfGCXO7z3LDJJg - EzCU6D3axwhiiwiESLw4egVsELPAWUaJRZ0fWEESwgLJEk17voPZLAKqEt/mzWYBsXkFrCSu - 9P5jg9ggL7F6wwGwoZwC1hLXNx8Ds4WAavZ8e8c2gZFvASPDKkaR1NLi3PTcYiO94sTc4tK8 - dL3k/NxNjMDA33bs55YdjF3vgg8xCnAwKvHwRtTvihNiTSwrrsw9xCjBwawkwtuSuTNOiDcl - sbIqtSg/vqg0J7X4EKMp0FETmaVEk/OBUZlXEm9oamhuYWlobmxubGahJM7bIXAwRkggPbEk - NTs1tSC1CKaPiYNTqoGx5PTNH9vfNYXt1fTI2Ri57W1dk3bLB5Oe1B677C7vZQ+UNDK97736 - GtxycMG/FZ1LPORF49uy7zIsCZ7yWaS86edL/cnPJy8yvPHwlfWjq88f3fuxPeLDtLv3DQwX - HQjYNnX2LFsJnrKN/Ie9Fuzg5Z80z6DQUyG07uzDQvtHUSKTnBo2Ki3xUmIpzkg01GIuKk4E - AGD+HDOSAgAA -X-CMS-MailID: 20200512184830eucas1p198b1439122e2da299c563726fe17f9ef -X-Msg-Generator: CA -X-RootMTR: 20200512184830eucas1p198b1439122e2da299c563726fe17f9ef -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184830eucas1p198b1439122e2da299c563726fe17f9ef -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Marek Szyprowski - -Create a non-cacheable mapping for the 0x600000000 physical memory region, -where MMIO registers for the PCIe XHCI controller are instantiated by the -PCIe bridge. - -Signed-off-by: Marek Szyprowski -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Nicolas Saenz Julienne ---- -Changes since v2: - - fixed typo MAX_MAP_MAX_ENTRIES -> MEM_MAP_MAX_ENTRIES -Changes since v1: - - none. ---- - arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- - 1 file changed, 15 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 4295356..9f5bca3 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -11,10 +11,15 @@ +@@ -12,10 +12,15 @@ #include #include @@ -1001,7 +41,7 @@ index 4295356..9f5bca3 100644 { .virt = 0x00000000UL, .phys = 0x00000000UL, -@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { +@@ -35,11 +40,11 @@ static struct mm_region bcm283x_mem_map[] = { } }; @@ -1010,21 +50,26 @@ index 4295356..9f5bca3 100644 { .virt = 0x00000000UL, .phys = 0x00000000UL, +- .size = 0xfe000000UL, ++ .size = 0xfc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { @@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { ++ }, { + .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, + .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { + }, { /* List terminator */ 0, - } -@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) +@@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) { int i; @@ -1033,638 +78,90 @@ index 4295356..9f5bca3 100644 mem_map[i].virt = pd[i].virt; mem_map[i].phys = pd[i].phys; mem_map[i].size = pd[i].size; - -From patchwork Tue May 12 18:47:13 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288732 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=OrqQU0UN; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6KH0ykgz9sSW - for ; Wed, 13 May 2020 04:49:07 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 43B8081CF5; - Tue, 12 May 2020 20:48:39 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="OrqQU0UN"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id A041C81CD4; Tue, 12 May 2020 20:48:36 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com - [210.118.77.12]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id AF9CA81CB4 - for ; Tue, 12 May 2020 20:48:33 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) - by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184833euoutp02024bfc004b3a38e7abe168cdd77f5dbb~OXGZmHDwG0461204612euoutp024 - for ; Tue, 12 May 2020 18:48:33 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com - 20200512184833euoutp02024bfc004b3a38e7abe168cdd77f5dbb~OXGZmHDwG0461204612euoutp024 -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309313; - bh=gVSWmpdQ36VgD8o/W/rduik6grJJCng+jGVfBPUAF8U=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=OrqQU0UN8Z7QKS+4Unt5PDDDw3i2iYhOJT4TdbEKloVbg23X7ARl1QJTAaFBBNzJT - 8AXLlGfGZj4mJo1gPBdQ/TOVDG7RDy4i/+ujixIckKJXDA+AjclrJdeEAcngq0Ulnn - NbOUAtPbCSEM0S/0RPnWwC90UpPAmcqGeCkVrazE= -Received: from eusmges2new.samsung.com (unknown [203.254.199.244]) by - eucas1p1.samsung.com (KnoxPortal) with ESMTP id - 20200512184833eucas1p1dc7466ebb73dd2f787e4253f171a3b9d~OXGZbAMzF2083120831eucas1p1w; - Tue, 12 May 2020 18:48:33 +0000 (GMT) -Received: from eucas1p2.samsung.com ( [182.198.249.207]) by - eusmges2new.samsung.com (EUCPMTA) with SMTP id F5.AA.60679.18FEABE5; Tue, 12 - May 2020 19:48:33 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad~OXGZA7swA2288022880eucas1p17; - Tue, 12 May 2020 18:48:32 +0000 (GMT) -Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184832eusmtrp2c7ee802f60d431184d93a34cbe4b5279~OXGZAXbrx1654916549eusmtrp2o; - Tue, 12 May 2020 18:48:32 +0000 (GMT) -X-AuditID: cbfec7f4-0e5ff7000001ed07-fd-5ebaef8142ae -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms2.samsung.com (EUCPMTA) with SMTP id A3.F8.07950.08FEABE5; Tue, 12 - May 2020 19:48:32 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184832eusmtip1ffa9d15a350dcc63557ad23be081cb76~OXGYefx_f2778327783eusmtip1V; - Tue, 12 May 2020 18:48:32 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 6/9] linux/bitfield.h: Add primitives for manipulating - bitfields both in host- and fixed-endian -Date: Tue, 12 May 2020 20:47:13 +0200 -Message-Id: <20200512184716.2869-7-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAKsWRmVeSWpSXmKPExsWy7djP87qN73fFGdy/yWqxccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BEcdmkpOZklqUW6dslcGW8 - v/6XuWCuSMXm151sDYzHBboYOTkkBEwkrv3+z9LFyMUhJLCCUeLqqz+MEM4XRom+t9+gnM+M - Em3XbrLAtGy428wOkVjOKPG0YSMbXMvD1X3sIFVsAoYSvUf7GEFsEYEAiWs/p4GNYhY4yiix - Zv8fsFHCAiUSs/9OZgWxWQRUJZbeOQXWwCtgJfH35FwmiHXyEqs3HGAGsTkFrCWubz7GDDJI - QmAVu8S60+uhbnKRmL9tJTuELSzx6vgWKFtG4v/O+UwQDc2MEj27b7NDOBMYJe4fX8AIUWUt - cefcL6AnOIDu05RYv0sfIuwo0Xb0KTtIWEKAT+LGW0GQMDOQOWnbdGaIMK9ER5sQRLWKxO9V - 06FulpLofvIf6jQPiebdl6Ah1McocXD2TqYJjPKzEJYtYGRcxSieWlqcm55abJSXWq5XnJhb - XJqXrpecn7uJEZhuTv87/mUH464/SYcYBTgYlXh4GWp3xQmxJpYVV+YeYpTgYFYS4W3J3Bkn - xJuSWFmVWpQfX1Sak1p8iFGag0VJnNd40ctYIYH0xJLU7NTUgtQimCwTB6dUA6ODfX6J8vRP - kS+KX7b+sr18ZKLND/H+CxvqW3meFD769EE8d07Cr1VxR9y0XX2uzm7Ya7jTOKjbT6fT7NTx - ctavcrxzXr8sF/94MOp3a0neVQeztyzlwSmL/z0VS1j6k2HvYg9180Vfo4KOzvp5jX/63V7/ - KbVNp0sWCu+TUPHIenjq2JX2Xy5KLMUZiYZazEXFiQAsWJztMwMAAA== -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xu7oN73fFGWxZpGGxccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF - G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GW8v/6XuWCuSMXm151sDYzHBboY - OTkkBEwkNtxtZu9i5OIQEljKKNG88z5jFyMHUEJKYn6LEkSNsMSfa11sILaQwCdGiQPbpUFs - NgFDid6jfYwgtohAiMSLo1eYQOYwC5xllFjU+YEVJCEsUCRxef86JhCbRUBVYumdU2ANvAJW - En9PzmWCWCAvsXrDAWYQm1PAWuL65mPMEMusJPZ8e8c2gZFvASPDKkaR1NLi3PTcYiO94sTc - 4tK8dL3k/NxNjMCw33bs55YdjF3vgg8xCnAwKvHwRtTvihNiTSwrrsw9xCjBwawkwtuSuTNO - iDclsbIqtSg/vqg0J7X4EKMp0FETmaVEk/OBMZlXEm9oamhuYWlobmxubGahJM7bIXAwRkgg - PbEkNTs1tSC1CKaPiYNTqoGRL+bltk22/7+9+eEy57X8YZkID4Uj5VoKoSuTez9IRTw9cJA9 - f+mEOlbeZyvTnFlM/r3fsWl2FUuAYz97waprdvs3vpx9QyUl8rbyZJloPYMp4k5TRTm2vecX - qjC8NG3F+bgO9kV25i0VwYy7Fnjm/ZmhHZI93Y7bduZik0DpvXJcJvwfj8opsRRnJBpqMRcV - JwIAdir705ECAAA= -X-CMS-MailID: 20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad -X-Msg-Generator: CA -X-RootMTR: 20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184832eucas1p1b75fca7f5ed42e3cb38f98410f51f1ad -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -From: Nicolas Saenz Julienne - -Imports Al Viro's original Linux commit 00b0c9b82663a, which contains -an in depth explanation and two fixes from Johannes Berg: - e7d4a95da86e0 "bitfield: fix *_encode_bits()", - 37a3862e12382 "bitfield: add u8 helpers". - -Signed-off-by: Nicolas Saenz Julienne -[s.nawrocki: added empty lines between functions and macros] -Signed-off-by: Sylwester Nawrocki ---- -Changes since v1: - - added empty lines between functions and macros. - -Changes since RFC: - - new patch. ---- - include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 50 insertions(+) - -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index 8b9d6ff..7acba4c 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -103,4 +103,54 @@ - (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ - }) - -+extern void __compiletime_error("value doesn't fit into mask") -+__field_overflow(void); -+extern void __compiletime_error("bad bitfield mask") -+__bad_mask(void); -+static __always_inline u64 field_multiplier(u64 field) -+{ -+ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) -+ __bad_mask(); -+ return field & -field; -+} -+static __always_inline u64 field_mask(u64 field) -+{ -+ return field / field_multiplier(field); -+} -+ -+#define ____MAKE_OP(type,base,to,from) \ -+static __always_inline __##type type##_encode_bits(base v, base field) \ -+{ \ -+ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ -+ __field_overflow(); \ -+ return to((v & field_mask(field)) * field_multiplier(field)); \ -+} \ -+static __always_inline __##type type##_replace_bits(__##type old, \ -+ base val, base field) \ -+{ \ -+ return (old & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline void type##p_replace_bits(__##type *p, \ -+ base val, base field) \ -+{ \ -+ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline base type##_get_bits(__##type v, base field) \ -+{ \ -+ return (from(v) & field)/field_multiplier(field); \ -+} -+ -+#define __MAKE_OP(size) \ -+ ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ -+ ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ -+ ____MAKE_OP(u##size,u##size,,) -+ -+____MAKE_OP(u8,u8,,) -+__MAKE_OP(16) -+__MAKE_OP(32) -+__MAKE_OP(64) -+ -+#undef __MAKE_OP -+#undef ____MAKE_OP -+ - #endif - -From patchwork Tue May 12 18:47:14 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288733 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=Fm50fcBL; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6KV3jXsz9sRR - for ; Wed, 13 May 2020 04:49:18 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 7663481CC1; - Tue, 12 May 2020 20:48:44 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="Fm50fcBL"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 497CE81CE3; Tue, 12 May 2020 20:48:41 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com - [210.118.77.11]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 53C8F81CD9 - for ; Tue, 12 May 2020 20:48:38 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) - by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184838euoutp019e25bda09342202a0eda043f595e3c22~OXGd7TgBd0706107061euoutp01m - for ; Tue, 12 May 2020 18:48:38 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com - 20200512184838euoutp019e25bda09342202a0eda043f595e3c22~OXGd7TgBd0706107061euoutp01m -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309318; - bh=HzMTU/TXuht/pqPHaK0Ik2xR+VGQDcf9rtO4VMSyKJM=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=Fm50fcBLGZyjlJzMo4Jk2kL21fNnnNiYQPGuvZ9uYJHcoSJzOfuJZKLNBoAFhG6Q1 - 7NBIjapXv/0ZFqIcyF8vg14dGk5aNjSHNtjyeLaSxxf0+jcM23co7gshLtNg2WB2Jv - 1m1YEKUU/fA0BznXct760bitBngMWoUq+d7qDQHM= -Received: from eusmges3new.samsung.com (unknown [203.254.199.245]) by - eucas1p1.samsung.com (KnoxPortal) with ESMTP id - 20200512184836eucas1p1135921d83070d86d6e8b1bb64b8f8be4~OXGczeB0p2080520805eucas1p1w; - Tue, 12 May 2020 18:48:36 +0000 (GMT) -Received: from eucas1p2.samsung.com ( [182.198.249.207]) by - eusmges3new.samsung.com (EUCPMTA) with SMTP id 7F.03.60698.48FEABE5; Tue, 12 - May 2020 19:48:36 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTPA id - 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985~OXGcRwgxc0943909439eucas1p25; - Tue, 12 May 2020 18:48:36 +0000 (GMT) -Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184836eusmtrp2d133993e54b8ae3b6e45209e4cf24ca5~OXGcRC2XF1654116541eusmtrp2q; - Tue, 12 May 2020 18:48:36 +0000 (GMT) -X-AuditID: cbfec7f5-a0fff7000001ed1a-92-5ebaef84302e -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms2.samsung.com (EUCPMTA) with SMTP id 64.F8.07950.48FEABE5; Tue, 12 - May 2020 19:48:36 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184835eusmtip109d2fc69bebbcdfc5800da0da0dc6fc3~OXGbx_UD72778327783eusmtip1W; - Tue, 12 May 2020 18:48:35 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 7/9] pci: Add some PCI Express capability register offset - definitions -Date: Tue, 12 May 2020 20:47:14 +0200 -Message-Id: <20200512184716.2869-8-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA0WSfUhTURjGObt323U6uV4FDysQhoUFaaLgJUUqpW4QaP1lxrSZFzXnB7vT - siBXyTS/MXQyQ6dBs6lpOYabzGqls0Qtxa9STDHF0kLLcqYt59X67/c+53nO+3A4GELUckVY - SrqClqdLZWKeADX22AeP5H0zxx1VLviTT6pbuWRlcTxpWSrjkeMbKi7Z8mqKTy6pbgFSe2+O - Sxo1Oh75cimfS/40GAG5bLnLP+5Kaab7eVSN8h1K1Wp6UcqkmeJT/ZMdgCo16AHVahhBqfa+ - G9FYrCAskZalZNPygPBLguTBolkks8v9mvK1GlGCdddC4IJBPBh+LankFwIBRuCNAFavlvHY - 4QeAM58+ok4XgX8HULUQtZeoaejisCYdgGrdEPdfQmfJ5zhdPDwQlnSXAid74dFw1F4FnCYE - 7waw+dnmzrWeeCwsGOjdCaD4AWhvuo84WYgfg1vvGzjsOh/Y1PZ8R3fBQ+FYew/C6g/5cP6B - H8uRcO2LhceyJ/xsM/BZ3g8dprqdqhC/A2Bx5wc+O5QDOG3TAtYVCicHNrbT2Ha9Q7DVHMDK - J+DKozXglCHuDseXPZwyso0VRjXCykJYoCJYty/8rVfvVhbBojkHyjIF+yre7j5pKYCWF/1o - OfDR/F+mBUAPvOksJi2JZoLS6av+jDSNyUpP8r+ckfYUbP+avj+2tQ7QtZlgBTgGxG7CmFxz - HMGVZjM5aVYAMUTsJcxLMcURwkRpznVanhEvz5LRjBXsw1CxtzCoYVFC4ElSBZ1K05m0fO+U - g7mIlOCg92jfROiKbSLLrf4cdabRivg9doQREZ0z4cGySNFJ02xeSU3RWcEUNbKuNtd7RNAJ - FaYW/akoEedmSArhMNpDtAXJt+fDJb+ar2z4etddOJ9rLpD0SqrGKmN835we2qoYlcQr/Vwj - U1eNwQp1m+bicEeTTr94UVESmz8cJ0aZZGngYUTOSP8C7G85NjEDAAA= -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7ot73fFGTRO47HYOGM9q8XUnniL - vW/62Sxu/GpjtVh75C67xZu2RkaLBZOfsFpsm7WczeLwm3ZWi29btjFavN3bye7A7THr/lk2 - j9kNF1k85s06weKxc9Zddo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi - DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DLOdz9iLtjHV9FwcjpzA+MP7i5G - Tg4JAROJ2Yv2MXUxcnEICSxllHj+p5+ti5EDKCElMb9FCaJGWOLPtS42iJpPjBITXm1gBEmw - CRhK9B7tA7NFBEIkXhy9AjaIWeAso8Sizg+sIAlhgQiJHXOusoDYLAKqEj9Xz2EGsXkFrCT+ - 3lrEBLFBXmL1hgNgcU4Ba4nrm4+B2UJANXu+vWObwMi3gJFhFaNIamlxbnpusZFecWJucWle - ul5yfu4mRmDgbzv2c8sOxq53wYcYBTgYlXh4I+p3xQmxJpYVV+YeYpTgYFYS4W3J3BknxJuS - WFmVWpQfX1Sak1p8iNEU6KiJzFKiyfnAqMwriTc0NTS3sDQ0NzY3NrNQEuftEDgYIySQnliS - mp2aWpBaBNPHxMEp1cCY/4XD7PPi+S+2KkXMPlP5dGW7dVZWdvNlA7N3Sw6+ZOOuq5RnEq38 - /Hri8TyzzOI1Zop5dQadajuPpBekXn9f6P/3t+Mlo5d+fKvCcsUu+u4L59j6PlMo6vszCVXn - A0d2PnB/kCX47mLjVS3XtoS1P7J82hflcfkF+dxsDLSex/XRxFGj5roSS3FGoqEWc1FxIgBl - vUv9kgIAAA== -X-CMS-MailID: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985 -X-Msg-Generator: CA -X-RootMTR: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985 -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184836eucas1p2f357a332cd99d6e287a74405d75c0985 -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Add PCI Express capability definitions required by the Broadcom -STB PCIe controller driver. - -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne ---- -Changes since v2: - - added Current Link Speed defines. -Changes since v1: - - none. -Changes since RFC: - - ensure the entries are added in order, sorted by ascending - address values. ---- - include/pci.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/include/pci.h b/include/pci.h -index dfdbb32..ff5f620 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -479,11 +479,20 @@ - #define PCI_EXP_DEVCTL 8 /* Device Control */ - #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ - #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ -+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ - #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ - #define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ -+#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ -+#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ -+#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ -+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ -+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ - #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ - #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ - - /* Include the ID list */ - - -From patchwork Tue May 12 18:47:15 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288734 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=BIPbrQ8g; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6Kj3M0tz9sRR - for ; Wed, 13 May 2020 04:49:29 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 185C181CF7; - Tue, 12 May 2020 20:48:49 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="BIPbrQ8g"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 26C8D81D0A; Tue, 12 May 2020 20:48:45 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com - [210.118.77.12]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 1403981CFD - for ; Tue, 12 May 2020 20:48:41 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) - by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184840euoutp0291a9b700643a42d241b5e145554cb765~OXGfyehRC0461204612euoutp027 - for ; Tue, 12 May 2020 18:48:40 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com - 20200512184840euoutp0291a9b700643a42d241b5e145554cb765~OXGfyehRC0461204612euoutp027 -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309320; - bh=TE9MyxK4mFntVW0fX+JmwIIwSpgKd4htbD5XCXxsM1I=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=BIPbrQ8gtigJfiy8ORfo+Qpp6HkymthVnUJBjoJlhoRKQAFXeIndDOOroFN8+Givz - 5kQXtvIJNzzZLnA1WeEtInnFBydhbpbY34BCuDFzq0lH7QCPH4ZHj7ScIRySxzJNEt - gdGeQ4yOBI/arQQSbBp77pL23dh1EFNbN/7gAdNw= -Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTP id - 20200512184839eucas1p2fd05e5c1731867685fef1171042b653c~OXGfJVP1W2380523805eucas1p2c; - Tue, 12 May 2020 18:48:39 +0000 (GMT) -Received: from eucas1p1.samsung.com ( [182.198.249.206]) by - eusmges1new.samsung.com (EUCPMTA) with SMTP id 0F.FF.61286.78FEABE5; Tue, 12 - May 2020 19:48:39 +0100 (BST) -Received: from eusmtrp1.samsung.com (unknown [182.198.249.138]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTPA id - 20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae~OXGegIxSM0944309443eucas1p2t; - Tue, 12 May 2020 18:48:38 +0000 (GMT) -Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by - eusmtrp1.samsung.com (KnoxPortal) with ESMTP id - 20200512184838eusmtrp1b8fcb72a4b1949c5b25111f77829cebe~OXGefeG9e0405704057eusmtrp1W; - Tue, 12 May 2020 18:48:38 +0000 (GMT) -X-AuditID: cbfec7f2-f0bff7000001ef66-94-5ebaef873740 -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms1.samsung.com (EUCPMTA) with SMTP id 9E.DA.08375.68FEABE5; Tue, 12 - May 2020 19:48:38 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184838eusmtip1e590ff27b66706ef16e7b7683ec1cc3d~OXGd_Ln563146531465eusmtip1X; - Tue, 12 May 2020 18:48:38 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 8/9] pci: Add driver for Broadcom BCM2711 SoC PCIe - controller -Date: Tue, 12 May 2020 20:47:15 +0200 -Message-Id: <20200512184716.2869-9-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTcRTH/Xkfu65m12n5S4XhKqgsHyh40bSC/rgRyQgMKpyueZmWTtnU - 0iiMytmcTrdKnWBm4TNdzTVfmLbyEaI9wLJSJBhCqQSViU5Wu95J/33O95zvOYfDIRDhfSyI - yFTmMSqlLEuM81HbyOrkQc2PPmnkQjdJPa0xY9RdXSo1sKjHqem1EozqeDXLoxZLrgOqwejA - KJupGadeLmow6o/VBqilgdu8I1to09wETtcVv0PpetMYSveaZnn0xEwPoCusbYA2W6dQumv8 - ioQ4yz+UzmRlFjCqiMQ0fkadqwPJfWgBl/WvzWgxMFUBLfAhIBkDn3VrUJaFZAuAL+xxWsB3 - 828AHxtmcC74BeCKed5702EsH0O5RDOAJY9WPHa3RdNygmWcjILlwxUbIwJICfyweg+wBoQc - drcdXHcbCMKfPAXN1sNsDUrugYsdeoRlARkHay1TCDdMBNufDG2wDxkPP3aNIGwfSDbx4ODQ - W89Gx+Cas8nD/vD7qJXHcQgcN+pQznADQF3/Fx4XVAI4N9rguUA8nJlcw9mNEHIfNPdFcPJR - 6HLewlgZkr5wesmPlRE3GmzVCCcLYGmJkKveDZ1t1Z4VgmCZ4y/KMQ2nmzu9uWNVAFjb/ACp - BCLT/2ENALSBQCZfna1g1FFK5lK4WpatzlcqwuU52Rbgfptx1+jPHrD8/rwdkAQQbxV4Xe2T - CjFZgbow2w4ggYgDBDcze6VCQbqssIhR5aSq8rMYtR0EE6g4UBDd+C1FSCpkecxFhsllVJtZ - b8InqBh0++ZJtMtarcsiSIqxDPkZOlun8OBtjuQDjV7zocvHd+iSQyIXUgoLqhrl1zD+emd0 - GhlW018lb2/MfX4nLKe+CMZLkwYUVlqpD3WezqyN3RlSHphgM+2dKN31OUG+XeI4+fWTwUdU - UI/56USCC3gkk2g8FyttLVO9OWPOE6PqDFnUfkSllv0DEe0vVDIDAAA= -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkkeLIzCtJLcpLzFFi42I5/e/4Xd2297viDGbcUrbYOGM9q8XUnniL - vW/62Sxu/GpjtVh75C67xZu2RkaLBZOfsFpsm7WczeLwm3ZWi29btjFavN3bye7A7THr/lk2 - j9kNF1k85s06weKxc9Zddo+zd3YwevRtWcXosX7LVRaPzaerAzii9GyK8ktLUhUy8otLbJWi - DS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DJm/1vLXLB4E2NF/8n1LA2MsyYy - djFyckgImEhM7j3B0sXIxSEksJRR4tmUu+xdjBxACSmJ+S1KEDXCEn+udbFB1HxilOib8JkZ - JMEmYCjRe7QPbJCIQIjEi6NXmECKmAXOMkos6vzACpIQFgiQuLD+PlgDi4CqxJu1/WA2r4CV - xMxNV5khNshLrN5wAMzmFLCWuL75GJgtBFSz59s7tgmMfAsYGVYxiqSWFuem5xYb6hUn5haX - 5qXrJefnbmIEBv+2Yz8372C8tDH4EKMAB6MSDy9D7a44IdbEsuLK3EOMEhzMSiK8LZk744R4 - UxIrq1KL8uOLSnNSiw8xmgIdNZFZSjQ5HxiZeSXxhqaG5haWhubG5sZmFkrivB0CB2OEBNIT - S1KzU1MLUotg+pg4OKUaGJPlvkyzyk+preH72cpxeeuD0O6oZUuNDc6o7P/6ZEOS840NPztO - zFocIGBSrq8toH7DTqlo+xFl5cUxn++VzqmJ1dnc+TTr4cFVZVYcppGhk4w3f/jD9fxs3+WL - Wnb8zSL+Ns2veIuTnb2qf8vebr9gOEl60xZ9E5XA+gz5i8fX7pF+yWCWpsRSnJFoqMVcVJwI - AL42I8OUAgAA -X-CMS-MailID: 20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae -X-Msg-Generator: CA -X-RootMTR: 20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184838eucas1p249588f9ee76dcb5a10209fcb7de01fae -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -This patch adds basic driver PCI Express controller found on Broadcom -set-top-box SoCs, e.g. BCM2711. -The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI -handling removed. The inbound access memory region is not currently -parsed from dma-ranges DT property and a fixed 3GB region is used. - -The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 -USB Host Controller. - -Signed-off-by: Nicolas Saenz Julienne -Signed-off-by: Sylwester Nawrocki ---- -Changes since v2: - - removed MDO_RD_DONE, MDIO_WT_DONE macro definitions, - - updated the Kconfig entry help text, - - reordered #include entries to match the coding style, - - s/udev/dev, - - s/ENODEV/EINVAL in brcm_pcie_probe() and brcm_pcie_config_address() - functions, - - Simplified brcm_pcie_mdio_{read, write} functions (readl_poll_timeout), - - shortened register bit fields macro definitions, - - dropped brcm_pcie_perst_set() and brcm_pcie_bridge_sw_init_set() - function in favour of direct clrbits_le32/setbits_le32 calls, - - use setbits_le32/clrbits_le32/clrsetbits_le32 instead of - readl(), u32p_replace_bits(), writel() sequence - - simplified brcm_pcie_config_address(), brcm_pcie_set_gen() functions, - - changed reset pulse delay to 100 us, - - Replaced FIELD_GET() with open coded bitwise operations, - - brcm_cpie_cfg_index() function merged into brcm_pcie_config_address(), - - use standard PCI PCI_EXP_LNKSTA_CLS_* link speed defines - - added kernel-doc function comments. - -Changes since v1: - - fixed argument in brcm_pcie_set_ssc() function call, - - changed rc_bar2_size assignment to value 0xC0000000, as in upstream - devicetree. -Changes since RFC: - - reworked to align with current Linux mainline version and u-boot - driver by Nicolas Saenz Julienne. ---- - drivers/pci/Kconfig | 9 + - drivers/pci/Makefile | 1 + - drivers/pci/pcie_brcmstb.c | 623 +++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 633 insertions(+) - create mode 100644 drivers/pci/pcie_brcmstb.c - +diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig +index f0301dc8bc..b42efe6072 100644 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +@@ -26,12 +30,17 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_DM_USB_GADGET=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="FSL" + CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index d16c2388af..0feea7f0be 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="usb start" ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y +@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_USB=y + CONFIG_DM_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_USB_DWC2=y + CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig -index 437cd9a..543bd46 100644 +index 6d8c22aacf..7e1e51d9ea 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig -@@ -197,4 +197,13 @@ config PCIE_MEDIATEK - Say Y here if you want to enable Gen2 PCIe controller, - which could be found on MT7623 SoC family. +@@ -205,4 +205,13 @@ config PCIE_ROCKCHIP + Say Y here if you want to enable PCIe controller support on + Rockchip SoCs. +config PCI_BRCMSTB + bool "Broadcom STB PCIe controller" @@ -1677,17 +174,37 @@ index 437cd9a..543bd46 100644 + of the controller. endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile -index c051ecc..3e53b1f 100644 +index 955351c5c2..3e1ff417d7 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile -@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o +@@ -43,4 +43,5 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o +obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o + obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o +diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c +index df7b37a592..1f51854ccc 100644 +--- a/drivers/pci/pci-rcar-gen3.c ++++ b/drivers/pci/pci-rcar-gen3.c +@@ -118,14 +118,6 @@ + #define RCAR_PCI_MAX_RESOURCES 4 + #define MAX_NR_INBOUND_MAPS 6 + +-#define PCI_EXP_FLAGS 2 /* Capabilities register */ +-#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +-#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +-#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +-#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +- + enum { + RCAR_PCI_ACCESS_READ, + RCAR_PCI_ACCESS_WRITE, diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c new file mode 100644 -index 0000000..dade79e +index 0000000000..dade79e9c8 --- /dev/null +++ b/drivers/pci/pcie_brcmstb.c @@ -0,0 +1,623 @@ @@ -2314,213 +831,163 @@ index 0000000..dade79e + .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct brcm_pcie), +}; +diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c +index aa1903e547..9f102c64c6 100644 +--- a/drivers/pci/pcie_intel_fpga.c ++++ b/drivers/pci/pcie_intel_fpga.c +@@ -67,9 +67,6 @@ + #define IS_ROOT_PORT(pcie, bdf) \ + ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) + +-#define PCI_EXP_LNKSTA 18 /* Link Status */ +-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +- + /** + * struct intel_fpga_pcie - Intel FPGA PCIe controller state + * @bus: Pointer to the PCI bus +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 2d968aafb0..f446520528 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) + scratchpad->sp_array[i] = cpu_to_le64(ptr); + } + ++ xhci_flush_cache((uintptr_t)scratchpad->sp_array, ++ sizeof(u64) * num_sp); ++ + return 0; + + fail_sp3: +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index 8b9d6fff00..7ad8b088ed 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -103,4 +103,56 @@ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + ++extern void __compiletime_error("value doesn't fit into mask") ++__field_overflow(void); ++extern void __compiletime_error("bad bitfield mask") ++__bad_mask(void); ++ ++static __always_inline u64 field_multiplier(u64 field) ++{ ++ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) ++ __bad_mask(); ++ return field & -field; ++} ++ ++static __always_inline u64 field_mask(u64 field) ++{ ++ return field / field_multiplier(field); ++} ++ ++#define ____MAKE_OP(type, base, to, from) \ ++static __always_inline __##type type##_encode_bits(base v, base field) \ ++{ \ ++ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ ++ __field_overflow(); \ ++ return to((v & field_mask(field)) * field_multiplier(field)); \ ++} \ ++static __always_inline __##type type##_replace_bits(__##type old, \ ++ base val, base field) \ ++{ \ ++ return (old & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline void type##p_replace_bits(__##type * p, \ ++ base val, base field) \ ++{ \ ++ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline base type##_get_bits(__##type v, base field) \ ++{ \ ++ return (from(v) & field) / field_multiplier(field); \ ++} ++ ++#define __MAKE_OP(size) \ ++ ____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \ ++ ____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \ ++ ____MAKE_OP(u##size, u##size, ,) ++ ++____MAKE_OP(u8, u8, ,) ++__MAKE_OP(16) ++__MAKE_OP(32) ++__MAKE_OP(64) ++ ++#undef __MAKE_OP ++#undef ____MAKE_OP ++ + #endif +diff --git a/include/pci.h b/include/pci.h +index 19c9244b94..281f353916 100644 +--- a/include/pci.h ++++ b/include/pci.h +@@ -471,10 +471,28 @@ + #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ + + /* PCI Express capabilities */ ++#define PCI_EXP_FLAGS 2 /* Capabilities register */ ++#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ ++#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ + #define PCI_EXP_DEVCAP 4 /* Device capabilities */ +-#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ ++#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ + #define PCI_EXP_DEVCTL 8 /* Device Control */ +-#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ ++#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ ++#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ ++#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ ++#define PCI_EXP_LNKSTA 18 /* Link Status */ ++#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ ++#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ ++#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ ++#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ ++#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ ++#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ ++#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ ++#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ ++#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ ++#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ + + /* Include the ID list */ + +diff --git a/include/usb/xhci.h b/include/usb/xhci.h +index 20e4a21066..1170c0ac69 100644 +--- a/include/usb/xhci.h ++++ b/include/usb/xhci.h +@@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) + */ + static inline u64 xhci_readq(__le64 volatile *regs) + { +-#if BITS_PER_LONG == 64 +- return readq(regs); +-#else + __u32 *ptr = (__u32 *)regs; + u64 val_lo = readl(ptr); + u64 val_hi = readl(ptr + 1); + return val_lo + (val_hi << 32); +-#endif + } + + static inline void xhci_writeq(__le64 volatile *regs, const u64 val) + { +-#if BITS_PER_LONG == 64 +- writeq(val, regs); +-#else + __u32 *ptr = (__u32 *)regs; + u32 val_lo = lower_32_bits(val); + /* FIXME */ + u32 val_hi = upper_32_bits(val); + writel(val_lo, ptr); + writel(val_hi, ptr + 1); +-#endif + } + + int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, +-- +2.26.2 -From patchwork Tue May 12 18:47:16 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Sylwester Nawrocki -X-Patchwork-Id: 1288735 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.a=rsa-sha256 - header.s=mail20170921 header.b=cv2KHkH+; - dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49M6Kw6S8rz9sRR - for ; Wed, 13 May 2020 04:49:40 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 6561C81D0C; - Tue, 12 May 2020 20:48:50 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; - unprotected) header.d=samsung.com header.i=@samsung.com header.b="cv2KHkH+"; - dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id C928581D0C; Tue, 12 May 2020 20:48:47 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com - [210.118.77.12]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id A273781CE3 - for ; Tue, 12 May 2020 20:48:44 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=samsung.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=s.nawrocki@samsung.com -Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) - by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id - 20200512184844euoutp02e55ba929fd9f79911a420a566ce0e756~OXGjzHTY40461204612euoutp028 - for ; Tue, 12 May 2020 18:48:44 +0000 (GMT) -DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com - 20200512184844euoutp02e55ba929fd9f79911a420a566ce0e756~OXGjzHTY40461204612euoutp028 -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; - s=mail20170921; t=1589309324; - bh=hzK/mVSsiHm3Pc+zxgVzX6oxEFhxHphU75wkCaQSwV4=; - h=From:To:Cc:Subject:Date:In-Reply-To:References:From; - b=cv2KHkH+WRTNWeHkLSgxvaKrbRdv4aXDBJ9rm82p9sUIKoZ2ZUWHIBjiSVlx4KkeE - fEVI2vFzo+mNlTVnEelEvDqFzVOXb6dvim6uuExIcjBm08RtCT6hIIYdvb01II9zw8 - 4YrLGyDb5u4RQ0w28BrdUJzxip35lr+/ro5y+Xgw= -Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by - eucas1p2.samsung.com (KnoxPortal) with ESMTP id - 20200512184843eucas1p2ba3d75b717bad767d94d483b4c7ce11d~OXGix0EoA0735307353eucas1p2x; - Tue, 12 May 2020 18:48:43 +0000 (GMT) -Received: from eucas1p1.samsung.com ( [182.198.249.206]) by - eusmges1new.samsung.com (EUCPMTA) with SMTP id CF.FF.61286.B8FEABE5; Tue, 12 - May 2020 19:48:43 +0100 (BST) -Received: from eusmtrp2.samsung.com (unknown [182.198.249.139]) by - eucas1p1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184842eucas1p1b2edc2128ddf134553805db77451648f~OXGhrdRbd2314823148eucas1p1D; - Tue, 12 May 2020 18:48:42 +0000 (GMT) -Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by - eusmtrp2.samsung.com (KnoxPortal) with ESMTP id - 20200512184842eusmtrp2c531b7ae799511a665083c7202f8cf1c~OXGhqxf_u1654916549eusmtrp2q; - Tue, 12 May 2020 18:48:42 +0000 (GMT) -X-AuditID: cbfec7f2-ef1ff7000001ef66-99-5ebaef8bc506 -Received: from eusmtip1.samsung.com ( [203.254.199.221]) by - eusmgms2.samsung.com (EUCPMTA) with SMTP id 35.F8.07950.98FEABE5; Tue, 12 - May 2020 19:48:41 +0100 (BST) -Received: from AMDC3061.digital.local (unknown [106.120.51.75]) by - eusmtip1.samsung.com (KnoxPortal) with ESMTPA id - 20200512184841eusmtip10bf41891c807e8917bd954874636d5ef~OXGhLVMJk2778327783eusmtip1X; - Tue, 12 May 2020 18:48:41 +0000 (GMT) -From: Sylwester Nawrocki -To: u-boot@lists.denx.de, mbrugger@suse.com, marex@denx.de, bmeng.cn@gmail.com -Cc: james.quinlan@broadcom.com, nsaenzjulienne@suse.de, sjg@chromium.org, - jh80.chung@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, - Sylwester Nawrocki -Subject: [PATCH v3 9/9] configs: Enable support for the XHCI controller on - RPI4 board (ARM 64-bit) -Date: Tue, 12 May 2020 20:47:16 +0200 -Message-Id: <20200512184716.2869-10-s.nawrocki@samsung.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20200512184716.2869-1-s.nawrocki@samsung.com> -X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTYRjG/XbO2Y7T2WlafqhgDIMUUkdGpxRNKDp/Cl3+CFJnO03Jqeyo - ZREtlXm/oJi2UMeMzKlt5ZrXYaw2K9FUugzULJBMmdjFC2q0th2t/37v8z4Pz8vHhyNCDRaE - Z2Tl0oosSaaIy0dNts3xwxUrA8nRb3t9yCdNeoxsqEwhzY4aLmnfUmFk98tZHulQ3QGkpn4e - I03qdi75wlGCketGEyCXzWW8kz6Uem6MS91XTqJUi/oVSvWrZ3nU2EwfoKqNOkDpje9Rqmf0 - ZhJ+kR8npTMz8mlFVHwqP326YRjLMfldn2i1Y0rQ6lsOvHFIxMB7IypQDvi4kHgE4JRFi7DD - KoCLPYUcdvjl2qzVcHcjXUPOHVc7gENjX7n/IssTHZjbxSXEsMpaDdwcQCTBD5t3PSUIYQWw - a/g36l74E1K4al7wMEochHXlhZ4KARELrYZBjK0LhZ2G54ibvV36xx6bpxoSD3mwaFMLWNMp - +KZxfYf94dKIkcdyCHT2t3LYQBGAlYPTPHaoBXBuRLOTiIUz41uuatx1XzjUD0SxciJcMDs4 - bhkSftC+vNctIy6sMzUirCyApSoh6w6D27pGDstBsGLeibJMwS9l7Sj7QtUATsxUgVoQqv5f - pgFABwLpPEYuoxlxFn0tkpHImbwsWeTlbPlT4Po3o39GfvaBtak0CyBwIPIVeN0aSBZiknym - QG4BEEdEAYLijP5koUAqKbhBK7JTFHmZNGMBwTgqChQc0S5eEhIySS59laZzaMXuloN7BymB - cKWgqiXttOJBRaU+xkboTQm+VRPbD3jhne+WnKU2wQG5jFvS9v3E6meDoAy90pEabN5TH5cQ - 0db7rXnKdMgAa5uRpo3l2LP7DUfrZn9sKJtrzr0+XxQUPVZ83P/ZGXviBeUnzT7d427oEzZw - W+wVptjWTlrVHevxxxhpSHaeCGXSJeIIRMFI/gJkR9I/MwMAAA== -X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsVy+t/xu7qd73fFGVxeZWOxccZ6VoupPfEW - e9/0s1nc+NXGarH2yF12izdtjYwWCyY/YbXYNms5m8XhN+2sFt+2bGO0eLu3k92B22PW/bNs - HrMbLrJ4zJt1gsVj56y77B5n7+xg9OjbsorRY/2Wqywem09XB3BE6dkU5ZeWpCpk5BeX2CpF - G1oY6RlaWugZmVjqGRqbx1oZmSrp29mkpOZklqUW6dsl6GXcnrqftWAbX8WF+TdYGxjn83Qx - cnJICJhIrNnzn7mLkYtDSGApo8TXHX1sXYwcQAkpifktShA1whJ/rnWxQdR8YpSY9PMgK0iC - TcBQovdoHyOILSIQIvHi6BUmkCJmgbOMEos6P4AVCQskSczvPccOYrMIqEpM6mpiA7F5Bawl - jm7YzQqxQV5i9YYDzCA2J1D8+uZjYLaQgJXEnm/v2CYw8i1gZFjFKJJaWpybnltspFecmFtc - mpeul5yfu4kRGPjbjv3csoOx613wIUYBDkYlHt6I+l1xQqyJZcWVuYcYJTiYlUR4WzJ3xgnx - piRWVqUW5ccXleakFh9iNAU6aiKzlGhyPjAq80riDU0NzS0sDc2NzY3NLJTEeTsEDsYICaQn - lqRmp6YWpBbB9DFxcEo1MJZuMOdQWFlcxNH1cnlrV4CI9YveFVpbur+ZL3998nbrx5IJO+5v - NQnONn+wO4m3/3tYYOTuoMvVPAmZDS/anbJea/5TzOpcFnR9x5G3L0zaRfS23RPYadWx1kVi - pvyV8/EB7wQLzOxvdPXy3agLUd4qc0Q9xNdok+uL3ZJbS/2Wpfa8TVjxTomlOCPRUIu5qDgR - ANQtnEOSAgAA -X-CMS-MailID: 20200512184842eucas1p1b2edc2128ddf134553805db77451648f -X-Msg-Generator: CA -X-RootMTR: 20200512184842eucas1p1b2edc2128ddf134553805db77451648f -X-EPHeader: CA -CMS-TYPE: 201P -X-CMS-RootMailID: 20200512184842eucas1p1b2edc2128ddf134553805db77451648f -References: <20200512184716.2869-1-s.nawrocki@samsung.com> - -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI -and USB commands. To get it working one has to call the following commands: -"pci enum; usb start;", thus such commands have been added to the default -"preboot" environment variable. One has to update their environment if it -is already configured to get this feature working out of the box. - -Signed-off-by: Marek Szyprowski -Signed-off-by: Sylwester Nawrocki ---- -Changes since v2: - - rpi_4_32b_defconfig, rpi_4_defconfig changes moved to separate - patch -Changes since v1: - - removed unneeded CONFIG_XHCI_64BIT_DWORD_ACCESS_ONLY entry. - -Changes since RFC: - - none. ---- - configs/rpi_arm64_defconfig | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index fea86be..f12d1e3 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_USE_PREBOOT=y --CONFIG_PREBOOT="usb start" -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y -@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_DWC2=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y diff --git a/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch b/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch index 0987100..8f28d1c 100644 --- a/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch +++ b/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch @@ -1,15 +1,17 @@ -From 32f17a93e08227c56a655f9b85977569e4e5daa2 Mon Sep 17 00:00:00 2001 +From 88725c4d036bab25c900cc3c962fc42d94e0ab69 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Wed, 1 Apr 2020 10:44:09 +0100 +Date: Wed, 10 Jun 2020 13:26:43 +0100 Subject: [PATCH] arm: rk3399: enable rng on rock960 and firefly3399 Signed-off-by: Peter Robinson --- - arch/arm/dts/rk3399-firefly-u-boot.dtsi | 4 ++++ - arch/arm/dts/rk3399-rock960-u-boot.dtsi | 4 ++++ - configs/firefly-rk3399_defconfig | 2 ++ - configs/rock960-rk3399_defconfig | 2 ++ - 4 files changed, 12 insertions(+) + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 4 ++++ + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 4 ++++ + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ + configs/firefly-rk3399_defconfig | 2 ++ + configs/rock960-rk3399_defconfig | 2 ++ + configs/rockpro64-rk3399_defconfig | 2 ++ + 6 files changed, 18 insertions(+) diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi index 38e0897db9..a6c7b913da 100644 @@ -24,7 +26,7 @@ index 38e0897db9..a6c7b913da 100644 + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi -index 82f2c311af..401ad02c45 100644 +index c190089e26..08292dbd39 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -24,3 +24,7 @@ @@ -35,51 +37,11 @@ index 82f2c311af..401ad02c45 100644 +&rng { + status = "okay"; +}; -diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig -index 4c9f1e189b..27306b434f 100644 ---- a/configs/firefly-rk3399_defconfig -+++ b/configs/firefly-rk3399_defconfig -@@ -34,6 +34,8 @@ CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_SF_DEFAULT_SPEED=20000000 - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -index ba4226e173..f823d0dabd 100644 ---- a/configs/rock960-rk3399_defconfig -+++ b/configs/rock960-rk3399_defconfig -@@ -35,6 +35,8 @@ CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_PMIC_RK8XX=y - CONFIG_REGULATOR_PWM=y --- -2.26.0 - -From 03a3e695cb24257e42a0a97abf7177ca788bedc4 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 1 Apr 2020 11:20:43 +0100 -Subject: [PATCH] arm: rk3399: enable rng on rockpro64 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ - configs/rockpro64-rk3399_defconfig | 2 ++ - 2 files changed, 6 insertions(+) - diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -index deaa3efd39..2e99ef71f4 100644 +index bac09df4a3..38fe3bb0ec 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -@@ -15,6 +15,10 @@ +@@ -25,6 +25,10 @@ }; }; @@ -90,11 +52,37 @@ index deaa3efd39..2e99ef71f4 100644 &vdd_center { regulator-min-microvolt = <950000>; regulator-max-microvolt = <950000>; +diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig +index 5bb54f5835..551687d6d0 100644 +--- a/configs/firefly-rk3399_defconfig ++++ b/configs/firefly-rk3399_defconfig +@@ -35,6 +35,8 @@ CONFIG_MMC_DW=y + CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_SF_DEFAULT_SPEED=20000000 + CONFIG_DM_ETH=y + CONFIG_ETH_DESIGNWARE=y +diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig +index 59a85c78a1..f31cb92884 100644 +--- a/configs/rock960-rk3399_defconfig ++++ b/configs/rock960-rk3399_defconfig +@@ -37,6 +37,8 @@ CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_DM_ETH=y + CONFIG_NVME=y + CONFIG_PCI=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig -index 8074e4665a..285dccebe5 100644 +index 807747485a..f778f0b640 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig -@@ -34,6 +34,8 @@ CONFIG_MMC_DW=y +@@ -40,6 +40,8 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y @@ -104,5 +92,5 @@ index 8074e4665a..285dccebe5 100644 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y -- -2.26.0 +2.26.2 diff --git a/initial-support-for-the-Pinebook-Pro-laptop-from.patch b/initial-support-for-the-Pinebook-Pro-laptop-from.patch deleted file mode 100644 index b8b6f34..0000000 --- a/initial-support-for-the-Pinebook-Pro-laptop-from.patch +++ /dev/null @@ -1,1573 +0,0 @@ -From a3e23dca57bff1043bd6c746458dae2dd446948e Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sun, 19 Apr 2020 10:31:53 +0100 -Subject: [PATCH 2/5] dt-bindings: input: adopt Linux gpio-keys binding - constants - -Sync the gpio-keys input bindings from linux 5.7-rc1. - -Signed-off-by: Peter Robinson ---- - include/dt-bindings/input/gpio-keys.h | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - create mode 100644 include/dt-bindings/input/gpio-keys.h - -diff --git a/include/dt-bindings/input/gpio-keys.h b/include/dt-bindings/input/gpio-keys.h -new file mode 100644 -index 0000000000..8962df79e7 ---- /dev/null -+++ b/include/dt-bindings/input/gpio-keys.h -@@ -0,0 +1,13 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * This header provides constants for gpio keys bindings. -+ */ -+ -+#ifndef _DT_BINDINGS_GPIO_KEYS_H -+#define _DT_BINDINGS_GPIO_KEYS_H -+ -+#define EV_ACT_ANY 0x00 /* asserted or deasserted */ -+#define EV_ACT_ASSERTED 0x01 /* asserted */ -+#define EV_ACT_DEASSERTED 0x02 /* deasserted */ -+ -+#endif /* _DT_BINDINGS_GPIO_KEYS_H */ --- -2.26.1 - -From 27f56eec1fa5baa4fc82ebb356a50826bb9f5643 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Sun, 19 Apr 2020 13:28:51 +0100 -Subject: [PATCH 4/5] arm: dts: rockchip: Add initial DT for Pinebook Pro - -Sync initial support for Pinebook Pro device tree from Linux 5.7-rc1. - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-pinebook-pro.dts | 1096 ++++++++++++++++++++++++++ - 2 files changed, 1097 insertions(+) - create mode 100644 arch/arm/dts/rk3399-pinebook-pro.dts - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 1325134bd4..c4d8ffb13c 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -129,6 +129,7 @@ - rk3399-nanopi-m4-2gb.dtb \ - rk3399-nanopi-neo4.dtb \ - rk3399-orangepi.dtb \ -+ rk3399-pinebook-pro.dtb \ - rk3399-puma-ddr1333.dtb \ - rk3399-puma-ddr1600.dtb \ - rk3399-puma-ddr1866.dtb \ -diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts -new file mode 100644 -index 0000000000..294d21bf45 ---- /dev/null -+++ b/arch/arm/dts/rk3399-pinebook-pro.dts -@@ -0,0 +1,1096 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2018 Akash Gajjar -+ * Copyright (c) 2020 Tobias Schramm -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Pine64 Pinebook Pro"; -+ compatible = "pine64,pinebook-pro", "rockchip,rk3399"; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ backlight: edp-backlight { -+ compatible = "pwm-backlight"; -+ power-supply = <&vcc_12v>; -+ pwms = <&pwm0 0 740740 0>; -+ }; -+ -+ edp_panel: edp-panel { -+ compatible = "boe,nv140fhmn49"; -+ backlight = <&backlight>; -+ enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&panel_en_gpio>; -+ power-supply = <&vcc3v3_panel>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ panel_in_edp: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&edp_out_panel>; -+ }; -+ }; -+ }; -+ }; -+ -+ /* -+ * Use separate nodes for gpio-keys to allow for selective deactivation -+ * of wakeup sources via sysfs without disabling the whole key -+ */ -+ gpio-key-lid { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lidbtn_gpio>; -+ -+ lid { -+ debounce-interval = <20>; -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; -+ label = "Lid"; -+ linux,code = ; -+ linux,input-type = ; -+ wakeup-event-action = ; -+ wakeup-source; -+ }; -+ }; -+ -+ gpio-key-power { -+ compatible = "gpio-keys"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwrbtn_gpio>; -+ -+ power { -+ debounce-interval = <20>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "Power"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwrled_gpio &slpled_gpio>; -+ -+ green-led { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_POWER; -+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ label = "green:power"; -+ }; -+ -+ red-led { -+ color = ; -+ default-state = "off"; -+ function = LED_FUNCTION_STANDBY; -+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ label = "red:standby"; -+ panic-indicator; -+ retain-state-suspended; -+ }; -+ }; -+ -+ /* Power sequence for SDIO WiFi module */ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h_gpio>; -+ post-power-on-delay-ms = <100>; -+ power-off-delay-us = <500000>; -+ -+ /* WL_REG_ON on module */ -+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ /* Audio components */ -+ es8316-sound { -+ compatible = "simple-audio-card"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_det_gpio>; -+ simple-audio-card,name = "rockchip,es8316-codec"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ -+ simple-audio-card,widgets = -+ "Microphone", "Mic Jack", -+ "Headphone", "Headphones", -+ "Speaker", "Speaker"; -+ simple-audio-card,routing = -+ "MIC1", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR", -+ "Speaker Amplifier INL", "HPOL", -+ "Speaker Amplifier INR", "HPOR", -+ "Speaker", "Speaker Amplifier OUTL", -+ "Speaker", "Speaker Amplifier OUTR"; -+ -+ simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; -+ simple-audio-card,aux-devs = <&speaker_amp>; -+ simple-audio-card,pin-switches = "Speaker"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&es8316>; -+ }; -+ }; -+ -+ speaker_amp: speaker-amplifier { -+ compatible = "simple-audio-amplifier"; -+ enable-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; -+ sound-name-prefix = "Speaker Amplifier"; -+ VCC-supply = <&pa_5v>; -+ }; -+ -+ /* Power tree */ -+ /* Root power source */ -+ vcc_sysin: vcc-sysin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sysin"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ /* Regulators supplied by vcc_sysin */ -+ /* LCD backlight supply */ -+ vcc_12v: vcc-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_12v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* Main 3.3 V supply */ -+ vcc3v3_sys: wifi_bat: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ /* 5 V USB power supply */ -+ vcc5v0_usb: pa_5v: vcc5v0-usb-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwr_5v_gpio>; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* RK3399 logic supply */ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ vin-supply = <&vcc_sysin>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ /* Regulators supplied by vcc3v3_sys */ -+ /* 0.9 V supply, always on */ -+ vcc_0v9: vcc-0v9 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ /* S3 1.8 V supply, switched by vcc1v8_s3 */ -+ vcca1v8_s3: vcc1v8-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcca1v8_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ /* micro SD card power */ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_pwr_h_gpio>; -+ regulator-name = "vcc3v0_sd"; -+ regulator-always-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* LCD panel power, called VCC3V3_S0 in schematic */ -+ vcc3v3_panel: vcc3v3-panel { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lcdvcc_en_gpio>; -+ regulator-name = "vcc3v3_panel"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-enable-ramp-delay = <100000>; -+ vin-supply = <&vcc3v3_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* M.2 adapter power, switched by vcc1v8_s3 */ -+ vcc3v3_ssd: vcc3v3-ssd { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_ssd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ /* Regulators supplied by vcc5v0_usb */ -+ /* USB 3 port power supply regulator */ -+ vcc5v0_otg: vcc5v0-otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en_gpio>; -+ regulator-name = "vcc5v0_otg"; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* Regulators supplied by vcc5v0_usb */ -+ /* Type C port power supply regulator */ -+ vbus_5vout: vbus_typec: vbus-5vout { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_typec0_en_gpio>; -+ regulator-name = "vbus_5vout"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* Regulators supplied by vcc_1v8 */ -+ /* Primary 0.9 V LDO */ -+ vcca0v9_s3: vcca0v9-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc0v9_s3"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_1v8>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ mains_charger: dc-charger { -+ compatible = "gpio-charger"; -+ charger-type = "mains"; -+ gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; -+ -+ /* Also triggered by USB charger */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&dc_det_gpio>; -+ }; -+}; -+ -+&cdn_dp { -+ status = "okay"; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&edp { -+ force-hpd; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&edp_hpd>; -+ status = "okay"; -+ -+ ports { -+ edp_out: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ edp_out_panel: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&panel_in_edp>; -+ }; -+ }; -+ }; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-falling-time-ns = <4>; -+ i2c-scl-rising-time-ns = <168>; -+ status = "okay"; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ interrupt-parent = <&gpio3>; -+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l_gpio>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sysin>; -+ vcc2-supply = <&vcc_sysin>; -+ vcc3-supply = <&vcc_sysin>; -+ vcc4-supply = <&vcc_sysin>; -+ vcc6-supply = <&vcc_sysin>; -+ vcc7-supply = <&vcc_sysin>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc_sysin>; -+ vcc10-supply = <&vcc_sysin>; -+ vcc11-supply = <&vcc_sysin>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vcc13-supply = <&vcc_sysin>; -+ vcc14-supply = <&vcc_sysin>; -+ -+ regulators { -+ /* rk3399 center logic supply */ -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: vcc_wl: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ /* not used */ -+ LDO_REG1 { -+ }; -+ -+ /* not used */ -+ LDO_REG2 { -+ }; -+ -+ vcc1v8_pmupll: LDO_REG3 { -+ regulator-name = "vcc1v8_pmupll"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-name = "vcc_sdio"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-name = "vcca3v0_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-name = "vcca1v8_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-name = "vcc3v3_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-name = "vcc3v3_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_gpio>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc_1v8>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_gpio>; -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc_1v8>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ i2c-scl-falling-time-ns = <4>; -+ i2c-scl-rising-time-ns = <168>; -+ status = "okay"; -+ -+ es8316: es8316@11 { -+ compatible = "everest,es8316"; -+ reg = <0x11>; -+ clocks = <&cru SCLK_I2S_8CH_OUT>; -+ clock-names = "mclk"; -+ #sound-dai-cells = <0>; -+ }; -+}; -+ -+&i2c3 { -+ i2c-scl-falling-time-ns = <15>; -+ i2c-scl-rising-time-ns = <450>; -+ status = "okay"; -+}; -+ -+&i2c4 { -+ i2c-scl-falling-time-ns = <20>; -+ i2c-scl-rising-time-ns = <600>; -+ status = "okay"; -+ -+ fusb0: fusb30x@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ fcs,int_n = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fusb0_int_gpio>; -+ vbus-supply = <&vbus_typec>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ data-role = "host"; -+ label = "USB-C"; -+ op-sink-microwatt = <1000000>; -+ power-role = "dual"; -+ sink-pdos = -+ ; -+ source-pdos = -+ ; -+ try-power-role = "sink"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usbc_hs: endpoint { -+ remote-endpoint = -+ <&u2phy0_typec_hs>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usbc_ss: endpoint { -+ remote-endpoint = -+ <&tcphy0_typec_ss>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ usbc_dp: endpoint { -+ remote-endpoint = -+ <&tcphy0_typec_dp>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2s1 { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_8ch_mclk_gpio>, <&i2s1_2ch_bus>; -+ rockchip,capture-channels = <8>; -+ rockchip,playback-channels = <8>; -+ status = "okay"; -+}; -+ -+&io_domains { -+ audio-supply = <&vcc_3v0>; -+ gpio1830-supply = <&vcc_3v0>; -+ sdmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ status = "okay"; -+}; -+ -+&pcie0 { -+ bus-scan-delay-ms = <1000>; -+ ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; -+ max-link-speed = <2>; -+ num-lanes = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_clkreqn_cpm>; -+ vpcie0v9-supply = <&vcca0v9_s3>; -+ vpcie1v8-supply = <&vcca1v8_s3>; -+ vpcie3v3-supply = <&vcc3v3_ssd>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ buttons { -+ pwrbtn_gpio: pwrbtn-gpio { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ lidbtn_gpio: lidbtn-gpio { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ dc-charger { -+ dc_det_gpio: dc-det-gpio { -+ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ es8316 { -+ hp_det_gpio: hp-det-gpio { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ fusb302x { -+ fusb0_int_gpio: fusb0-int-gpio { -+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ i2s1 { -+ i2s_8ch_mclk_gpio: i2s-8ch-mclk-gpio { -+ rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; -+ }; -+ }; -+ -+ lcd-panel { -+ lcdvcc_en_gpio: lcdvcc-en-gpio { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ panel_en_gpio: panel-en-gpio { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ lcd_panel_reset_gpio: lcd-panel-reset-gpio { -+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ leds { -+ pwrled_gpio: pwrled_gpio { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ slpled_gpio: slpled_gpio { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l_gpio: pmic-int-l-gpio { -+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_gpio: vsel1-gpio { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_gpio: vsel2-gpio { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ sdcard { -+ sdmmc0_pwr_h_gpio: sdmmc0-pwr-h-gpio { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h_gpio: wifi-enable-h-gpio { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb-typec { -+ vcc5v0_typec0_en_gpio: vcc5v0-typec0-en-gpio { -+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb2 { -+ pwr_5v_gpio: pwr-5v-gpio { -+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_host_en_gpio: vcc5v0-host-en-gpio { -+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ wireless-bluetooth { -+ bt_wake_gpio: bt-wake-gpio { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_gpio: bt-host-wake-gpio { -+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_reset_gpio: bt-reset-gpio { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&spi1 { -+ max-freq = <10000000>; -+ status = "okay"; -+ -+ spiflash: flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ m25p,fast-read; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy0_dp { -+ port { -+ tcphy0_typec_dp: endpoint { -+ remote-endpoint = <&usbc_dp>; -+ }; -+ }; -+}; -+ -+&tcphy0_usb3 { -+ port { -+ tcphy0_typec_ss: endpoint { -+ remote-endpoint = <&usbc_ss>; -+ }; -+ }; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ -+ u2phy0_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy0_host: host-port { -+ phy-supply = <&vcc5v0_otg>; -+ status = "okay"; -+ }; -+ -+ port { -+ u2phy0_typec_hs: endpoint { -+ remote-endpoint = <&usbc_hs>; -+ }; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+ -+ u2phy1_otg: otg-port { -+ status = "okay"; -+ }; -+ -+ u2phy1_host: host-port { -+ phy-supply = <&vcc5v0_otg>; -+ status = "okay"; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rk808 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ max-speed = <1500000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_gpio &bt_wake_gpio &bt_reset_gpio>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ vbat-supply = <&wifi_bat>; -+ vddio-supply = <&vcc_wl>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; --- -2.26.1 - -From 699fa59c59af63692269e133590d7664335b65ed Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 20 Apr 2020 20:07:04 +0100 -Subject: [PATCH 5/5] Add initial support for the Pinebook Pro laptop from - Pine64. - -Specification: -- Rockchip RK3399 -- 4GB Dual-Channel LPDDR4 -- eMMC socket -- mSD card slot -- 128Mbit (16Mb) SPI Flash -- AP6256 for 11AC WiFi + BT5 -- 14 inch 1920*1080 eDP MiPi display -- Camera -- USB 3.0, 2.0 ports -- Type-C port with alt-mode display (DP 1.2) and 15W charge -- DC 5V/3A -- optional PCIe slot for NVMe SSD drive - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 43 ++++++++++ - arch/arm/mach-rockchip/rk3399/Kconfig | 8 ++ - board/pine64/pinebook-pro-rk3399/Kconfig | 15 ++++ - board/pine64/pinebook-pro-rk3399/MAINTAINERS | 8 ++ - board/pine64/pinebook-pro-rk3399/Makefile | 1 + - .../pinebook-pro-rk3399/pinebook-pro-rk3399.c | 76 +++++++++++++++++ - configs/pinebook-pro-rk3399_defconfig | 84 +++++++++++++++++++ - include/configs/pinebook-pro-rk3399.h | 29 +++++++ - 8 files changed, 264 insertions(+) - create mode 100644 arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi - create mode 100644 board/pine64/pinebook-pro-rk3399/Kconfig - create mode 100644 board/pine64/pinebook-pro-rk3399/MAINTAINERS - create mode 100644 board/pine64/pinebook-pro-rk3399/Makefile - create mode 100644 board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c - create mode 100644 configs/pinebook-pro-rk3399_defconfig - create mode 100644 include/configs/pinebook-pro-rk3399.h - -diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -new file mode 100644 -index 0000000000..1a2e24d3ef ---- /dev/null -+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -@@ -0,0 +1,43 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Peter Robinson -+ */ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+ -+/ { -+ aliases { -+ spi0 = &spi1; -+ }; -+ -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+}; -+ -+&i2c0 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&rk808 { -+ u-boot,dm-pre-reloc; -+}; -+ -+&sdhci { -+ max-frequency = <25000000>; -+ u-boot,dm-pre-reloc; -+}; -+ -+&sdmmc { -+ max-frequency = <20000000>; -+ u-boot,dm-pre-reloc; -+}; -+ -+&spiflash { -+ u-boot,dm-pre-reloc; -+}; -+ -+&vdd_log { -+ regulator-init-microvolt = <950000>; -+}; -diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig -index 927bb62a9f..254b9c5b4d 100644 ---- a/arch/arm/mach-rockchip/rk3399/Kconfig -+++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -19,6 +19,13 @@ config TARGET_EVB_RK3399 - with full function and physical connectors support like Type-C ports, - USB.0 host ports, LVDS, JTAG, MAC, SD card, HDMI, USB-to-serial... - -+config TARGET_PINEBOOK_PRO_RK3399 -+ bool "Pinebook Pro" -+ help -+ Pinebook Pro is a laptop based on the Rockchip rk3399 SoC -+ with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, -+ 1920*1080 screen and all the usual laptop features. -+ - config TARGET_PUMA_RK3399 - bool "Theobroma Systems RK3399-Q7 (Puma)" - help -@@ -144,6 +151,7 @@ endif # BOOTCOUNT_LIMIT - - source "board/firefly/roc-pc-rk3399/Kconfig" - source "board/google/gru/Kconfig" -+source "board/pine64/pinebook-pro-rk3399/Kconfig" - source "board/pine64/rockpro64_rk3399/Kconfig" - source "board/rockchip/evb_rk3399/Kconfig" - source "board/theobroma-systems/puma_rk3399/Kconfig" -diff --git a/board/pine64/pinebook-pro-rk3399/Kconfig b/board/pine64/pinebook-pro-rk3399/Kconfig -new file mode 100644 -index 0000000000..3bb7ca448e ---- /dev/null -+++ b/board/pine64/pinebook-pro-rk3399/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_PINEBOOK_PRO_RK3399 -+ -+config SYS_BOARD -+ default "pinebook-pro-rk3399" -+ -+config SYS_VENDOR -+ default "pine64" -+ -+config SYS_CONFIG_NAME -+ default "pinebook-pro-rk3399" -+ -+config BOARD_SPECIFIC_OPTIONS -+ def_bool y -+ -+endif -diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS -new file mode 100644 -index 0000000000..7153eaf2e0 ---- /dev/null -+++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS -@@ -0,0 +1,8 @@ -+PINEBOOK_PRO -+M: Peter Robinson -+S: Maintained -+F: board/pine64/rk3399-pinebook-pro/ -+F: include/configs/rk3399-pinebook-pro.h -+F: arch/arm/dts/rk3399-pinebook-pro.dts -+F: arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -+F: configs/pinebook-pro-rk3399_defconfig -diff --git a/board/pine64/pinebook-pro-rk3399/Makefile b/board/pine64/pinebook-pro-rk3399/Makefile -new file mode 100644 -index 0000000000..2f692a12a6 ---- /dev/null -+++ b/board/pine64/pinebook-pro-rk3399/Makefile -@@ -0,0 +1 @@ -+obj-y += pinebook-pro-rk3399.o -diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c -new file mode 100644 -index 0000000000..01421cbac2 ---- /dev/null -+++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c -@@ -0,0 +1,76 @@ -+/* -+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd -+ * (C) Copyright 2020 Peter Robinson -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define GRF_IO_VSEL_BT565_SHIFT 0 -+#define PMUGRF_CON0_VSEL_SHIFT 8 -+ -+#ifndef CONFIG_SPL_BUILD -+int board_early_init_f(void) -+{ -+ struct udevice *regulator; -+ int ret; -+ -+ ret = regulator_get_by_platname("vcc5v0_usb", ®ulator); -+ if (ret) { -+ debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret); -+ goto out; -+ } -+ -+ ret = regulator_set_enable(regulator, true); -+ if (ret) -+ debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret); -+ -+out: -+ return 0; -+} -+#endif -+ -+#ifdef CONFIG_MISC_INIT_R -+static void setup_iodomain(void) -+{ -+ struct rk3399_grf_regs *grf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -+ struct rk3399_pmugrf_regs *pmugrf = -+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); -+ -+ /* BT565 is in 1.8v domain */ -+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); -+ -+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ -+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); -+} -+ -+int misc_init_r(void) -+{ -+ const u32 cpuid_offset = 0x7; -+ const u32 cpuid_length = 0x10; -+ u8 cpuid[cpuid_length]; -+ int ret; -+ -+ setup_iodomain(); -+ -+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); -+ if (ret) -+ return ret; -+ -+ ret = rockchip_cpuid_set(cpuid, cpuid_length); -+ if (ret) -+ return ret; -+ -+ return ret; -+} -+#endif -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -new file mode 100644 -index 0000000000..0e9f0ec250 ---- /dev/null -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -0,0 +1,84 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_TARGET_PINEBOOK_PRO_RK3399=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART=y -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" -+CONFIG_MISC_INIT_R=y -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_MTDPARTS=y -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_TIME=y -+CONFIG_CMD_USB=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_BOOTDELAY=3 -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_SPI_FLASH=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_DM_ETH=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_DM_PMIC_FAN53555=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+# CONFIG_USB_XHCI_ROCKCHIP is not set -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y -+CONFIG_DM_VIDEO=y -+CONFIG_VIDEO_BPP16=y -+CONFIG_VIDEO_BPP32=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_EDP=y -diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h -new file mode 100644 -index 0000000000..423d742a79 ---- /dev/null -+++ b/include/configs/pinebook-pro-rk3399.h -@@ -0,0 +1,29 @@ -+/* -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd -+ * Copyright (C) 2020 Peter Robinson -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __PINEBOOK_PRO_RK3399_H -+#define __PINEBOOK_PRO_RK3399_H -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdin=serial,usbkbd\0" \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#include -+ -+#if defined(CONFIG_ENV_IS_IN_MMC) -+#define CONFIG_SYS_MMC_ENV_DEV 0 -+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -+#define CONFIG_ENV_SECT_SIZE (8 * 1024) -+#endif -+ -+#undef CONFIG_SYS_SPI_U_BOOT_OFFS -+#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 -+ -+#define SDRAM_BANK_SIZE (2UL << 30) -+ -+#endif --- -2.26.1 -From 8239d91c6a120fb07df1f84c6441545856d968af Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 20 Apr 2020 22:43:05 +0100 -Subject: [PATCH] pinebook pro: enable rng for KASLR - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ++++ - configs/pinebook-pro-rk3399_defconfig | 2 ++ - 2 files changed, 6 insertions(+) - -diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -index 1a2e24d3ef..296321d697 100644 ---- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -@@ -24,6 +24,10 @@ - u-boot,dm-pre-reloc; - }; - -+&rng { -+ status = "okay"; -+}; -+ - &sdhci { - max-frequency = <25000000>; - u-boot,dm-pre-reloc; -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index 0e9f0ec250..c15c17a1b0 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -59,6 +59,8 @@ CONFIG_PMIC_RK8XX=y - CONFIG_DM_PMIC_FAN53555=y - CONFIG_REGULATOR_PWM=y - CONFIG_REGULATOR_RK8XX=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_PWM_ROCKCHIP=y - CONFIG_SYSRESET=y - CONFIG_USB=y --- -2.26.1 diff --git a/mmc-sdhci-Fix-HISPD-bit-handling.patch b/mmc-sdhci-Fix-HISPD-bit-handling.patch new file mode 100644 index 0000000..03e1123 --- /dev/null +++ b/mmc-sdhci-Fix-HISPD-bit-handling.patch @@ -0,0 +1,182 @@ +From patchwork Wed Jun 10 11:43:47 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Jagan Teki +X-Patchwork-Id: 1306828 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Authentication-Results: ozlabs.org; + dmarc=none (p=none dis=none) header.from=amarulasolutions.com +Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; + unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com + header.a=rsa-sha256 header.s=google header.b=Q+0/eSrJ; + dkim-atps=neutral +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 49hlWg1F7rz9sRW + for ; Wed, 10 Jun 2020 21:44:12 +1000 (AEST) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id E30A9813BC; + Wed, 10 Jun 2020 13:44:06 +0200 (CEST) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=amarulasolutions.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; + unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com + header.b="Q+0/eSrJ"; dkim-atps=neutral +Received: by phobos.denx.de (Postfix, from userid 109) + id 5063381578; Wed, 10 Jun 2020 13:44:05 +0200 (CEST) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, + DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham + autolearn_force=no version=3.4.2 +Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com + [IPv6:2607:f8b0:4864:20::1042]) + (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) + (No client certificate requested) + by phobos.denx.de (Postfix) with ESMTPS id 3B4D28006D + for ; Wed, 10 Jun 2020 13:44:01 +0200 (CEST) +Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) + header.from=amarulasolutions.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=jagan@amarulasolutions.com +Received: by mail-pj1-x1042.google.com with SMTP id jz3so753364pjb.0 + for ; Wed, 10 Jun 2020 04:44:01 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=amarulasolutions.com; s=google; + h=from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=O2V5XL3BREsrFDwBw4n7RZ8T6utX5AdnG2I6ivLZnCA=; + b=Q+0/eSrJuVhFqQmrlsBwCwCZAbCe2xEaqucnx2B5U1ugNqUWmowKDVxmV5llgcsrnJ + zliXEiVt8Az8b9zOxZM/0Tej8xH1pjdM08pw2sA/I0IEIg2fHq6zUioAR/MCZ4rbf9EN + j/l6kIrf0ADHDtPscUlgRaN0nVou3/T0cGpcA= +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version + :content-transfer-encoding; + bh=O2V5XL3BREsrFDwBw4n7RZ8T6utX5AdnG2I6ivLZnCA=; + b=U9gtAvMEdX23LPpZhHK26RY/0f9o9C22NUE5HjIBTjpytNzjSO+1cHxLPFk9lQyNzK + A0693YATc8RhLMFiRS1libP6Urk18kkSIzdwMfAYBN3jRuTRT88vPg3jKUJhK+p1R/Vz + kwzTq1MlBG8N2xNCzTM9ajfCl36013fN+MiLr9xkej7L+zLSpiBj+8z3MCmHKzj1hn1y + 2gOT5lVWyZydc/Ao516He/rhFhiRfGBf1w/KbCXfSg0x9kQ83UO4FPFPjDs3TiWm47PC + WS4+muMzuJIDAm+rZNt8iGY7igpHHzT51vBqF70ti3mCE1NFPQqzjWc4M8WuVFx84vh9 + LPjA== +X-Gm-Message-State: AOAM533ux1c2iDQS6fhMmnMScouMQxlbt1o1Hb7wwTLlbsql4mLEXoL/ + kq6k/AcVEksPK0a3hzH6EWbhMQ== +X-Google-Smtp-Source: ABdhPJxfGS37PA5Fx79Ub2piTMRhJFMfO0r/k3qlpvGvsVv9giEauDno4rbVNspBFxzzTtqDA1vwmw== +X-Received: by 2002:a17:90a:9484:: with SMTP id + s4mr2691977pjo.30.1591789439428; + Wed, 10 Jun 2020 04:43:59 -0700 (PDT) +Received: from localhost.localdomain ([2405:201:c809:c7d5:9daa:1b72:7bd0:50df]) + by smtp.gmail.com with ESMTPSA id y4sm12934672pfr.182.2020.06.10.04.43.54 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Wed, 10 Jun 2020 04:43:58 -0700 (PDT) +From: Jagan Teki +To: Peng Fan , Jaehoon Chung , + Kever Yang +Cc: Marc Zyngier , sunil@amarulasolutions.com, + u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, + linux-amarula@amarulasolutions.com, + Jagan Teki , + Robin Murphy +Subject: [PATCH v3] mmc: sdhci: Fix HISPD bit handling +Date: Wed, 10 Jun 2020 17:13:47 +0530 +Message-Id: <20200610114347.118501-1-jagan@amarulasolutions.com> +X-Mailer: git-send-email 2.25.1 +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.30rc1 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de +X-Virus-Status: Clean + +SDHCI HISPD bits need to be configured based on desired mmc +timings mode and some HISPD quirks. + +So, handle the HISPD bit based on the mmc computed selected +mode(timing parameter) rather than fixed mmc card clock +frequency. + +Linux handle the HISPD similar like this in below commit, + +commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling") + +This eventually fixed the mmc write issue observed in +rk3399 sdhci controller. + +Bug log for refernece, +=> gpt write mmc 0 $partitions +Writing GPT: mmc write failed +** Can't write to device 0 ** +** Can't write to device 0 ** +error! + +Cc: Robin Murphy +Cc: Kever Yang +Cc: Peng Fan +Reviewed-by: Jaehoon Chung +Tested-by: Marc Zyngier # nanopc-t4 +Tested-by: Suniel Mahesh # roc-rk3399-pc +Signed-off-by: Jagan Teki +--- +Changes for v3: +- use && for quirk check. + + drivers/mmc/sdhci.c | 23 +++++++++++++++-------- + 1 file changed, 15 insertions(+), 8 deletions(-) + +diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c +index 92cc8434af..a7db278a0e 100644 +--- a/drivers/mmc/sdhci.c ++++ b/drivers/mmc/sdhci.c +@@ -594,14 +594,21 @@ static int sdhci_set_ios(struct mmc *mmc) + ctrl &= ~SDHCI_CTRL_4BITBUS; + } + +- if (mmc->clock > 26000000) +- ctrl |= SDHCI_CTRL_HISPD; +- else +- ctrl &= ~SDHCI_CTRL_HISPD; +- +- if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) || +- (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) +- ctrl &= ~SDHCI_CTRL_HISPD; ++ if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) && ++ !(host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) { ++ if (mmc->selected_mode == MMC_HS || ++ mmc->selected_mode == SD_HS || ++ mmc->selected_mode == MMC_DDR_52 || ++ mmc->selected_mode == MMC_HS_200 || ++ mmc->selected_mode == MMC_HS_400 || ++ mmc->selected_mode == UHS_SDR25 || ++ mmc->selected_mode == UHS_SDR50 || ++ mmc->selected_mode == UHS_SDR104 || ++ mmc->selected_mode == UHS_DDR50) ++ ctrl |= SDHCI_CTRL_HISPD; ++ else ++ ctrl &= ~SDHCI_CTRL_HISPD; ++ } + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + diff --git a/rockchip-Pinebook-Pro-Fixes.patch b/rockchip-Pinebook-Pro-Fixes.patch new file mode 100644 index 0000000..0b0a2d7 --- /dev/null +++ b/rockchip-Pinebook-Pro-Fixes.patch @@ -0,0 +1,200 @@ +From e27621a7c2c0e090977c17f604093c720ca01fe4 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Mon, 8 Jun 2020 20:31:33 +0100 +Subject: [PATCH 1/3] rockchip: Pinebook Pro: enable rng to provide an entropy + source + +Enable the rng so UEFI can provide entropy for KASLR + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ++++ + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ + configs/pinebook-pro-rk3399_defconfig | 2 ++ + 3 files changed, 10 insertions(+) + +diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +index 1a2e24d3ef..296321d697 100644 +--- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +@@ -24,6 +24,10 @@ + u-boot,dm-pre-reloc; + }; + ++&rng { ++ status = "okay"; ++}; ++ + &sdhci { + max-frequency = <25000000>; + u-boot,dm-pre-reloc; +diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +index bac09df4a3..cb8991aa25 100644 +--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +@@ -19,6 +19,10 @@ + }; + }; + ++&rng { ++ status = "okay"; ++}; ++ + &spi1 { + spi_flash: flash@0 { + u-boot,dm-pre-reloc; +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index 0c129b9aeb..21eecf477c 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -54,6 +54,8 @@ CONFIG_DM_PMIC_FAN53555=y + CONFIG_PMIC_RK8XX=y + CONFIG_REGULATOR_PWM=y + CONFIG_REGULATOR_RK8XX=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_PWM_ROCKCHIP=y + CONFIG_RAM_RK3399_LPDDR4=y + CONFIG_DM_RESET=y +-- +2.26.2 + +From 99a3c9ba5a8ab7a94aa700649e031f53d498e857 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Mon, 8 Jun 2020 22:23:05 +0100 +Subject: [PATCH 2/3] rockchip: Pinebook Pro: Fix USB and the USB attached + keyboard + +The built in keyboard on the Pinebook Pro is attached via USB so +fix this up to ensure USB works as expected. + +Signed-off-by: Peter Robinson +--- + configs/pinebook-pro-rk3399_defconfig | 5 +++++ + include/configs/pinebook-pro-rk3399.h | 3 +++ + 2 files changed, 8 insertions(+) + +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index 21eecf477c..733463556a 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -61,6 +61,8 @@ CONFIG_RAM_RK3399_LPDDR4=y + CONFIG_DM_RESET=y + CONFIG_BAUDRATE=1500000 + CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="usb start" + CONFIG_ROCKCHIP_SPI=y + CONFIG_SYSRESET=y + CONFIG_USB=y +@@ -68,8 +70,11 @@ CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y + CONFIG_USB_DWC3=y + CONFIG_ROCKCHIP_USB2_PHY=y ++CONFIG_DM_KEYBOARD=y + CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y + CONFIG_USB_ETHER_ASIX=y +diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h +index 4bc8802d11..d910830582 100644 +--- a/include/configs/pinebook-pro-rk3399.h ++++ b/include/configs/pinebook-pro-rk3399.h +@@ -25,4 +25,7 @@ + + #define SDRAM_BANK_SIZE (2UL << 30) + ++#define CONFIG_USB_OHCI_NEW ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 ++ + #endif +-- +2.26.2 + +From 64d43a4f0a135486a9a524b107c853831e492eb6 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Mon, 8 Jun 2020 23:41:50 +0100 +Subject: [PATCH 3/3] rockchip: Pinebook Pro: Fix SPI flash and store env on it + +Some minor fixes for SPI flash on the Pinebook Pro and also +default to saving environment to the SPI flash as it's +guaranteed to be on board. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 6 +++++- + configs/pinebook-pro-rk3399_defconfig | 3 +++ + include/configs/pinebook-pro-rk3399.h | 9 --------- + 3 files changed, 8 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +index 296321d697..ded7db0aef 100644 +--- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +@@ -12,7 +12,11 @@ + }; + + chosen { +- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; ++ }; ++ ++ config { ++ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ + }; + }; + +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index 733463556a..18b2d74253 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -1,6 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_ENV_SIZE=0x8000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_TARGET_PINEBOOK_PRO_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +@@ -17,6 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_STACK_R=y + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 + CONFIG_SPL_MTD_SUPPORT=y ++CONFIG_SPL_SPI_LOAD=y + CONFIG_TPL=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GPIO=y +@@ -32,6 +34,7 @@ CONFIG_CMD_REGULATOR=y + CONFIG_SPL_OF_CONTROL=y + CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" + CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ROCKCHIP_GPIO=y + CONFIG_SYS_I2C_ROCKCHIP=y +diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h +index d910830582..d478b19917 100644 +--- a/include/configs/pinebook-pro-rk3399.h ++++ b/include/configs/pinebook-pro-rk3399.h +@@ -14,15 +14,6 @@ + + #include + +-#if defined(CONFIG_ENV_IS_IN_MMC) +-#define CONFIG_SYS_MMC_ENV_DEV 0 +-#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +-#define CONFIG_ENV_SECT_SIZE (8 * 1024) +-#endif +- +-#undef CONFIG_SYS_SPI_U_BOOT_OFFS +-#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 +- + #define SDRAM_BANK_SIZE (2UL << 30) + + #define CONFIG_USB_OHCI_NEW +-- +2.26.2 + diff --git a/rockpro64-limit-speed-on-mSD-slot.patch b/rockpro64-limit-speed-on-mSD-slot.patch deleted file mode 100644 index 789ea26..0000000 --- a/rockpro64-limit-speed-on-mSD-slot.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0b1a5b30d6d8ad2af9f5518b65fbbdc9e080d41d Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 20 Apr 2020 22:03:00 +0100 -Subject: [PATCH] rockpro64: limit speed on mSD slot - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -index deaa3efd39..e5e05f5a7f 100644 ---- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -@@ -19,6 +19,10 @@ - status = "okay"; - }; - -+&sdmmc { -+ max-frequency = <20000000>; -+}; -+ - &vdd_center { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; --- -2.26.1 - diff --git a/rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch b/rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch deleted file mode 100644 index 3b9726c..0000000 --- a/rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 50e353960a36f381f855b34b40117c64dc44ad33 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 12 May 2020 23:23:01 +0100 -Subject: [PATCH] config: Enable support for the XHCI controller on RPI4 board - -From: Marek Szyprowski - -This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI -and USB commands. To get it working one has to call the following commands: -"pci enum; usb start;", thus such commands have been added to the default -"preboot" environment variable. One has to update their environment if it -is already configured to get this feature working out of the box. - -Signed-off-by: Marek Szyprowski -Signed-off-by: Sylwester Nawrocki ---- - configs/rpi_4_defconfig | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index f1c8f5ef7d..b3e7037bf5 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_ARCH_FIXUP_FDT_MEMORY=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_DFU=y - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y - CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -@@ -27,12 +31,17 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_DM_USB_GADGET=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_GADGET=y - CONFIG_USB_GADGET_MANUFACTURER="FSL" - CONFIG_USB_GADGET_VENDOR_NUM=0x0525 --- -2.26.2 - diff --git a/rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch b/rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch deleted file mode 100644 index a9c00c3..0000000 --- a/rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch +++ /dev/null @@ -1,40 +0,0 @@ -From c9a14b02aea84a37407df7d295e0f76eb529f472 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 12 May 2020 11:29:00 +0100 -Subject: [PATCH] rpi4: enable ARCH_FIXUP_FDT_MEMORY - -Signed-off-by: Peter Robinson ---- - configs/rpi_4_32b_defconfig | 2 +- - configs/rpi_4_defconfig | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index dd7da1cf06..9a0437d376 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -7,7 +7,7 @@ - CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y --# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -+CONFIG_ARCH_FIXUP_FDT_MEMORY=y - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index 6eeec4592e..b3e7037bf5 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -7,7 +7,7 @@ - CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y --# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -+CONFIG_ARCH_FIXUP_FDT_MEMORY=y - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set --- -2.26.2 - diff --git a/sources b/sources index 926a830..e899314 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2020.07-rc2.tar.bz2) = d4ee96a76cde9305a8733602ce8f9505412f9118e5625f3154249d302445e1c9f970bcf38abb63536129885f3443d1c9fdf9c4e8851e2c1655050d1ebcea7bd2 +SHA512 (u-boot-2020.07-rc4.tar.bz2) = 81fb2cfaabe2e20addc174798fa7f6506d51bd32aafac6698758417575bd85bb95d476b619e8d78480c0ccef6424f8b6de59c76bc48a555b7b4105acf194f3f8 diff --git a/uboot-tools.spec b/uboot-tools.spec index 2c6e05f..012dcdb 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc2 +%global candidate rc4 Name: uboot-tools Version: 2020.07 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.3%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -23,22 +23,21 @@ Patch2: uefi-use-Fedora-specific-path-name.patch # Board fixes and enablement Patch4: usb-kbd-fixes.patch Patch5: dragonboard-fixes.patch +# mmc fix +Patch6: mmc-sdhci-Fix-HISPD-bit-handling.patch # Tegra improvements Patch10: arm-tegra-define-fdtfile-option-for-distro-boot.patch Patch11: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch -# Rockchips improvements -Patch12: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch -Patch13: initial-support-for-the-Pinebook-Pro-laptop-from.patch -Patch14: rockpro64-limit-speed-on-mSD-slot.patch # AllWinner improvements -Patch15: AllWinner-Pine64-bits.patch +Patch12: AllWinner-Pine64-bits.patch +# Rockchips improvements +Patch13: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch +Patch14: rockchip-Pinebook-Pro-Fixes.patch # RPi4 Patch16: USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch Patch17: usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch Patch18: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch -Patch19: rpi4-enable-ARCH_FIXUP_FDT_MEMORY.patch -Patch20: rpi4-Enable-support-for-the-XHCI-controller-on-RPI.patch BuildRequires: bc BuildRequires: dtc @@ -252,6 +251,10 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Wed Jun 10 2020 Peter Robinson - 2020.07-0.3.rc4 +- 2020.07 RC4 +- Minor updates and other fixes + * Tue May 12 2020 Peter Robinson - 2020.07-0.2.rc2 - 2020.07 RC2 - Minor device updates