drop sun9i boards which never had eth support anyway
This commit is contained in:
parent
82aabc8bb2
commit
53c3d27d79
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@ -1,4 +1,4 @@
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From d6aa8909c2099371333c83546d26d46a3b71ba48 Mon Sep 17 00:00:00 2001
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From 5322208dbdf97b2d618364fced3420d209a8dba0 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Wed, 10 Feb 2021 11:01:01 +0000
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Subject: [PATCH] arm: dts: allwinner: sync from linux for RGMII RX/TX delay
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@ -49,10 +49,8 @@ Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
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arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 2 +-
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arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts | 38 +++
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arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 12 +-
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arch/arm/dts/sun9i-a80-cubieboard4.dts | 61 +++--
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arch/arm/dts/sun9i-a80-optimus.dts | 50 +++-
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arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 2 +-
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43 files changed, 752 insertions(+), 338 deletions(-)
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41 files changed, 661 insertions(+), 318 deletions(-)
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diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
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index 883f217efb..e5e840b9fb 100644
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@ -2378,278 +2376,6 @@ index 15c22b06fc..47954551f5 100644
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};
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®_dcdc2 {
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diff --git a/arch/arm/dts/sun9i-a80-cubieboard4.dts b/arch/arm/dts/sun9i-a80-cubieboard4.dts
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index 85da85faf8..484b93df20 100644
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--- a/arch/arm/dts/sun9i-a80-cubieboard4.dts
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+++ b/arch/arm/dts/sun9i-a80-cubieboard4.dts
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@@ -89,31 +89,23 @@
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vga-dac {
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compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
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vdd-supply = <®_dcdc1>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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- #address-cells = <1>;
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- #size-cells = <0>;
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reg = <0>;
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- vga_dac_in: endpoint@0 {
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- reg = <0>;
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+ vga_dac_in: endpoint {
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remote-endpoint = <&tcon0_out_vga>;
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};
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};
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port@1 {
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- #address-cells = <1>;
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- #size-cells = <0>;
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reg = <1>;
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- vga_dac_out: endpoint@0 {
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- reg = <0>;
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+ vga_dac_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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@@ -133,12 +125,27 @@
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status = "okay";
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};
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+&gmac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac_rgmii_pins>;
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+ phy-handle = <&phy1>;
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+ phy-mode = "rgmii-id";
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+ phy-supply = <®_cldo1>;
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+ status = "okay";
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+};
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+
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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status = "okay";
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};
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+&mdio {
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+ phy1: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+};
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+
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@@ -183,10 +190,26 @@
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clocks = <&ac100_rtc 0>;
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};
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+&pio {
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+ vcc-pa-supply = <®_ldo_io1>;
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+ vcc-pb-supply = <®_aldo2>;
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+ vcc-pc-supply = <®_dcdc1>;
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+ vcc-pd-supply = <®_dc1sw>;
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+ vcc-pe-supply = <®_eldo2>;
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+ vcc-pf-supply = <®_dcdc1>;
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+ vcc-pg-supply = <®_ldo_io0>;
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+ vcc-ph-supply = <®_dcdc1>;
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+};
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+
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&r_ir {
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status = "okay";
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};
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+&r_pio {
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+ vcc-pl-supply = <®_dldo2>;
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+ vcc-pm-supply = <®_eldo3>;
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+};
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+
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&r_rsb {
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status = "okay";
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@@ -217,6 +240,10 @@
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/* unused */
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};
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+ reg_dc1sw: dc1sw {
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+ regulator-name = "vcc-pd";
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+ };
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+
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reg_dc5ldo: dc5ldo {
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regulator-always-on;
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regulator-min-microvolt = <800000>;
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@@ -271,7 +298,6 @@
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};
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reg_dldo2: dldo2 {
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- regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pl";
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@@ -290,14 +316,12 @@
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};
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reg_eldo3: eldo3 {
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- regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pm-codec-io1";
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};
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reg_ldo_io0: ldo_io0 {
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- regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pg";
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@@ -385,6 +409,14 @@
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*/
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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+ /*
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+ * The PHY requires 20ms after all voltages
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+ * are applied until core logic is ready and
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+ * 30ms after the reset pin is de-asserted.
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+ * Set a 100ms delay to account for PMIC
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+ * ramp time and board traces.
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+ */
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+ regulator-enable-ramp-delay = <100000>;
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regulator-name = "vcc-gmac-phy";
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};
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@@ -464,8 +496,7 @@
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};
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&tcon0_out {
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- tcon0_out_vga: endpoint@0 {
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- reg = <0>;
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+ tcon0_out_vga: endpoint {
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remote-endpoint = <&vga_dac_in>;
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};
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};
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diff --git a/arch/arm/dts/sun9i-a80-optimus.dts b/arch/arm/dts/sun9i-a80-optimus.dts
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index 58a199b0e4..5c3580d712 100644
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--- a/arch/arm/dts/sun9i-a80-optimus.dts
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+++ b/arch/arm/dts/sun9i-a80-optimus.dts
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@@ -82,7 +82,7 @@
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reg_usb1_vbus: usb1-vbus {
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compatible = "regulator-fixed";
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- pinctrl-names = "default";
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+ regulator-name = "usb1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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@@ -91,7 +91,7 @@
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reg_usb3_vbus: usb3-vbus {
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compatible = "regulator-fixed";
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- pinctrl-names = "default";
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+ regulator-name = "usb3-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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@@ -120,6 +120,21 @@
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status = "okay";
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};
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+&gmac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac_rgmii_pins>;
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+ phy-handle = <&phy1>;
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+ phy-mode = "rgmii-id";
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+ phy-supply = <®_cldo1>;
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+ status = "okay";
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+};
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+
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+&mdio {
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+ phy1: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+};
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+
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@@ -172,10 +187,26 @@
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clocks = <&ac100_rtc 0>;
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};
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+&pio {
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+ vcc-pa-supply = <®_ldo_io1>;
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+ vcc-pb-supply = <®_aldo2>;
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+ vcc-pc-supply = <®_dcdc1>;
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+ vcc-pd-supply = <®_dcdc1>;
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+ vcc-pe-supply = <®_eldo2>;
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+ vcc-pf-supply = <®_dcdc1>;
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+ vcc-pg-supply = <®_ldo_io0>;
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+ vcc-ph-supply = <®_dcdc1>;
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+};
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+
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&r_ir {
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status = "okay";
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};
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+&r_pio {
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+ vcc-pl-supply = <®_dldo2>;
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+ vcc-pm-supply = <®_eldo3>;
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+};
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+
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&r_rsb {
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status = "okay";
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@@ -213,6 +244,10 @@
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regulator-name = "vdd-cpus-09-usbh";
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};
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+ dc1sw {
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+ /* unused */
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+ };
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+
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reg_dcdc1: dcdc1 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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@@ -260,7 +295,6 @@
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};
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reg_dldo2: dldo2 {
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- regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pl";
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@@ -279,14 +313,12 @@
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};
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reg_eldo3: eldo3 {
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- regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pm-codec-io1";
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};
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reg_ldo_io0: ldo_io0 {
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- regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pg";
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@@ -374,6 +406,14 @@
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*/
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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+ /*
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+ * The PHY requires 20ms after all voltages
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+ * are applied until core logic is ready and
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+ * 30ms after the reset pin is de-asserted.
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+ * Set a 100ms delay to account for PMIC
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+ * ramp time and board traces.
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+ */
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+ regulator-enable-ramp-delay = <100000>;
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regulator-name = "vcc-gmac-phy";
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};
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diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
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index 39263e74fb..8e5cb3b3fd 100644
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--- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
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@ -132,10 +132,7 @@ udoo
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udoo_neo
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usbarmory
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UTOO_P66
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vexpress_ca15_tc2
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vexpress_ca9x4
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wandboard
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warp
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warp7
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Wexler_TAB7200
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Wits_Pro_A20_DKT
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