From 37df227bc0961f9f0dc4dafa9e983290dbdb2bc3 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 17 Oct 2021 15:57:39 +0100 Subject: [PATCH 01/28] Fixes for Rockchip devices Fix booting from MMC for Rockchip 3399 (rhbz #2014182) Enable new rk3399 devices (Leez, NanoPi-M4B, NanoPi-4S, NanoPi-T4) (rhbz #2009126) --- ...ockchip_sdhci-Add-support-for-RK3568.patch | 152 +++++++ ...hip_sdhci-add-phy-and-clock-config-f.patch | 406 ++++++++++++++++++ aarch64-boards | 3 + uboot-tools.spec | 10 +- 4 files changed, 569 insertions(+), 2 deletions(-) create mode 100644 0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch create mode 100644 0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch diff --git a/0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch b/0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch new file mode 100644 index 0000000..33dbf61 --- /dev/null +++ b/0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch @@ -0,0 +1,152 @@ +From e3e6018d0b67fbab3d05053688e53f5baac63bc3 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 14 Oct 2021 16:01:56 +0100 +Subject: [PATCH 1/2] Revert "mmc: rockchip_sdhci: Add support for RK3568" + +This reverts commit a63a57e59d864a1ca2b0acb5fadc5c3579c3e79c. +--- + drivers/mmc/rockchip_sdhci.c | 109 ----------------------------------- + 1 file changed, 109 deletions(-) + +diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c +index 1ac00587d4..eff134c8f5 100644 +--- a/drivers/mmc/rockchip_sdhci.c ++++ b/drivers/mmc/rockchip_sdhci.c +@@ -42,34 +42,6 @@ + ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ + PHYCTRL_DLLRDY_DONE) + +-/* Rockchip specific Registers */ +-#define DWCMSHC_EMMC_DLL_CTRL 0x800 +-#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) +-#define DWCMSHC_EMMC_DLL_RXCLK 0x804 +-#define DWCMSHC_EMMC_DLL_TXCLK 0x808 +-#define DWCMSHC_EMMC_DLL_STRBIN 0x80c +-#define DWCMSHC_EMMC_DLL_STATUS0 0x840 +-#define DWCMSHC_EMMC_DLL_STATUS1 0x844 +-#define DWCMSHC_EMMC_DLL_START BIT(0) +-#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 +-#define DWCMSHC_EMMC_DLL_START_POINT 16 +-#define DWCMSHC_EMMC_DLL_START_DEFAULT 5 +-#define DWCMSHC_EMMC_DLL_INC_VALUE 2 +-#define DWCMSHC_EMMC_DLL_INC 8 +-#define DWCMSHC_EMMC_DLL_DLYENA BIT(27) +-#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 +-#define DLL_STRBIN_TAPNUM_DEFAULT 0x3 +-#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) +-#define DWCMSHC_EMMC_DLL_LOCKED BIT(8) +-#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) +-#define DLL_RXCLK_NO_INVERTER 1 +-#define DLL_RXCLK_INVERTER 0 +-#define DWCMSHC_ENHANCED_STROBE BIT(8) +-#define DLL_LOCK_WO_TMOUT(x) \ +- ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ +- (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) +-#define ROCKCHIP_MAX_CLKS 3 +- + struct rockchip_sdhc_plat { + struct mmc_config cfg; + struct mmc mmc; +@@ -195,77 +167,6 @@ static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo + return 0; + } + +-static int rk3568_emmc_phy_init(struct udevice *dev) +-{ +- struct rockchip_sdhc *prv = dev_get_priv(dev); +- struct sdhci_host *host = &prv->host; +- u32 extra; +- +- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; +- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); +- +- return 0; +-} +- +-static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) +-{ +- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); +- int val, ret; +- u32 extra; +- +- if (clock > host->max_clk) +- clock = host->max_clk; +- if (clock) +- clk_set_rate(&priv->emmc_clk, clock); +- +- sdhci_set_clock(host->mmc, clock); +- +- if (clock >= 100 * MHz) { +- /* reset DLL */ +- sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); +- udelay(1); +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); +- +- /* Init DLL settings */ +- extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | +- DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | +- DWCMSHC_EMMC_DLL_START; +- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); +- +- ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, +- val, DLL_LOCK_WO_TMOUT(val), 1, 500); +- if (ret) +- return ret; +- +- extra = DWCMSHC_EMMC_DLL_DLYENA | +- DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; +- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); +- +- extra = DWCMSHC_EMMC_DLL_DLYENA | +- DLL_TXCLK_TAPNUM_DEFAULT | +- DLL_TXCLK_TAPNUM_FROM_SW; +- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); +- +- extra = DWCMSHC_EMMC_DLL_DLYENA | +- DLL_STRBIN_TAPNUM_DEFAULT; +- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); +- } else { +- /* reset the clock phase when the frequency is lower than 100MHz */ +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); +- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; +- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); +- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); +- } +- +- return 0; +-} +- +-static int rk3568_emmc_get_phy(struct udevice *dev) +-{ +- return 0; +-} +- + static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) + { + struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); +@@ -438,21 +339,11 @@ static const struct sdhci_data rk3399_data = { + .emmc_phy_init = rk3399_emmc_phy_init, + }; + +-static const struct sdhci_data rk3568_data = { +- .emmc_set_clock = rk3568_sdhci_emmc_set_clock, +- .get_phy = rk3568_emmc_get_phy, +- .emmc_phy_init = rk3568_emmc_phy_init, +-}; +- + static const struct udevice_id sdhci_ids[] = { + { + .compatible = "arasan,sdhci-5.1", + .data = (ulong)&rk3399_data, + }, +- { +- .compatible = "rockchip,rk3568-dwcmshc", +- .data = (ulong)&rk3568_data, +- }, + { } + }; + +-- +2.33.0 + diff --git a/0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch b/0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch new file mode 100644 index 0000000..20a827c --- /dev/null +++ b/0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch @@ -0,0 +1,406 @@ +From bb7b9097efc67ff6051f206e3ac9602dabbfc33e Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 14 Oct 2021 16:02:03 +0100 +Subject: [PATCH 2/2] Revert "mmc: rockchip_sdhci: add phy and clock config for + rk3399" + +This reverts commit ac804143cfd128d144403ef2434344988c3fde9f. +--- + drivers/mmc/rockchip_sdhci.c | 313 ++++------------------------------- + 1 file changed, 36 insertions(+), 277 deletions(-) + +diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c +index eff134c8f5..d95f8b2a15 100644 +--- a/drivers/mmc/rockchip_sdhci.c ++++ b/drivers/mmc/rockchip_sdhci.c +@@ -6,322 +6,90 @@ + */ + + #include +-#include + #include +-#include + #include +-#include + #include + #include +-#include + #include + #include +-#include "mmc_private.h" + #include +-#include +-#include +-#include ++#include + + /* 400KHz is max freq for card ID etc. Use that as min */ + #define EMMC_MIN_FREQ 400000 +-#define KHz (1000) +-#define MHz (1000 * KHz) +-#define SDHCI_TUNING_LOOP_COUNT 40 +- +-#define PHYCTRL_CALDONE_MASK 0x1 +-#define PHYCTRL_CALDONE_SHIFT 0x6 +-#define PHYCTRL_CALDONE_DONE 0x1 +-#define PHYCTRL_DLLRDY_MASK 0x1 +-#define PHYCTRL_DLLRDY_SHIFT 0x5 +-#define PHYCTRL_DLLRDY_DONE 0x1 +-#define PHYCTRL_FREQSEL_200M 0x0 +-#define PHYCTRL_FREQSEL_50M 0x1 +-#define PHYCTRL_FREQSEL_100M 0x2 +-#define PHYCTRL_FREQSEL_150M 0x3 +-#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \ +- ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ +- PHYCTRL_DLLRDY_DONE) + + struct rockchip_sdhc_plat { ++#if CONFIG_IS_ENABLED(OF_PLATDATA) ++ struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; ++#endif + struct mmc_config cfg; + struct mmc mmc; + }; + +-struct rockchip_emmc_phy { +- u32 emmcphy_con[7]; +- u32 reserved; +- u32 emmcphy_status; +-}; +- + struct rockchip_sdhc { + struct sdhci_host host; +- struct udevice *dev; + void *base; +- struct rockchip_emmc_phy *phy; +- struct clk emmc_clk; +-}; +- +-struct sdhci_data { +- int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock); +- int (*emmc_phy_init)(struct udevice *dev); +- int (*get_phy)(struct udevice *dev); +-}; +- +-static int rk3399_emmc_phy_init(struct udevice *dev) +-{ +- return 0; +-} +- +-static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) +-{ +- u32 caldone, dllrdy, freqsel; +- +- writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); +- writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); +- writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); +- +- /* +- * According to the user manual, calpad calibration +- * cycle takes more than 2us without the minimal recommended +- * value, so we may need a little margin here +- */ +- udelay(3); +- writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); +- +- /* +- * According to the user manual, it asks driver to +- * wait 5us for calpad busy trimming. But it seems that +- * 5us of caldone isn't enough for all cases. +- */ +- udelay(500); +- caldone = readl(&phy->emmcphy_status); +- caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; +- if (caldone != PHYCTRL_CALDONE_DONE) { +- printf("%s: caldone timeout.\n", __func__); +- return; +- } +- +- /* Set the frequency of the DLL operation */ +- if (clock < 75 * MHz) +- freqsel = PHYCTRL_FREQSEL_50M; +- else if (clock < 125 * MHz) +- freqsel = PHYCTRL_FREQSEL_100M; +- else if (clock < 175 * MHz) +- freqsel = PHYCTRL_FREQSEL_150M; +- else +- freqsel = PHYCTRL_FREQSEL_200M; +- +- /* Set the frequency of the DLL operation */ +- writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); +- writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); +- +- read_poll_timeout(readl, &phy->emmcphy_status, dllrdy, +- PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000); +-} +- +-static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) +-{ +- writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); +- writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); +-} +- +-static int rk3399_emmc_get_phy(struct udevice *dev) +-{ +- struct rockchip_sdhc *priv = dev_get_priv(dev); +- ofnode phy_node; +- void *grf_base; +- u32 grf_phy_offset, phandle; +- +- phandle = dev_read_u32_default(dev, "phys", 0); +- phy_node = ofnode_get_by_phandle(phandle); +- if (!ofnode_valid(phy_node)) { +- debug("Not found emmc phy device\n"); +- return -ENODEV; +- } +- +- grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); +- if (grf_base < 0) { +- printf("%s Get syscon grf failed", __func__); +- return -ENODEV; +- } +- grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); +- +- priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); +- +- return 0; +-} +- +-static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) +-{ +- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); +- int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ; +- +- if (cycle_phy) +- rk3399_emmc_phy_power_off(priv->phy); +- +- sdhci_set_clock(host->mmc, clock); +- +- if (cycle_phy) +- rk3399_emmc_phy_power_on(priv->phy, clock); +- +- return 0; +-} +- +-static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) +-{ +- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); +- struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); +- struct mmc *mmc = host->mmc; +- uint clock = mmc->tran_speed; +- u32 reg; +- +- if (!clock) +- clock = mmc->clock; +- +- if (data->emmc_set_clock) +- data->emmc_set_clock(host, clock); +- +- if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) { +- reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); +- reg &= ~SDHCI_CTRL_UHS_MASK; +- reg |= SDHCI_CTRL_HS400; +- sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); +- } else { +- sdhci_set_uhs_timing(host); +- } +- +- return 0; +-} +- +-static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) +-{ +- struct sdhci_host *host = dev_get_priv(mmc->dev); +- char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; +- struct mmc_cmd cmd; +- u32 ctrl, blk_size; +- int ret = 0; +- +- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); +- ctrl |= SDHCI_CTRL_EXEC_TUNING; +- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); +- +- sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); +- sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); +- +- blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); +- if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8) +- blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128); +- sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE); +- sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); +- +- cmd.cmdidx = opcode; +- cmd.resp_type = MMC_RSP_R1; +- cmd.cmdarg = 0; +- +- do { +- if (tuning_loop_counter-- == 0) +- break; +- +- mmc_send_cmd(mmc, &cmd, NULL); +- +- if (opcode == MMC_CMD_SEND_TUNING_BLOCK) +- /* +- * For tuning command, do not do busy loop. As tuning +- * is happening (CLK-DATA latching for setup/hold time +- * requirements), give time to complete +- */ +- udelay(1); +- +- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); +- } while (ctrl & SDHCI_CTRL_EXEC_TUNING); +- +- if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { +- printf("%s:Tuning failed\n", __func__); +- ret = -EIO; +- } +- +- if (tuning_loop_counter < 0) { +- ctrl &= ~SDHCI_CTRL_TUNED_CLK; +- sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2); +- } +- +- /* Enable only interrupts served by the SD controller */ +- sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE); +- /* Mask all sdhci interrupt sources */ +- sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); +- +- return ret; +-} +- +-static struct sdhci_ops rockchip_sdhci_ops = { +- .set_ios_post = rockchip_sdhci_set_ios_post, +- .platform_execute_tuning = &rockchip_sdhci_execute_tuning, + }; + +-static int rockchip_sdhci_probe(struct udevice *dev) ++static int arasan_sdhci_probe(struct udevice *dev) + { +- struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct rockchip_sdhc_plat *plat = dev_get_plat(dev); + struct rockchip_sdhc *prv = dev_get_priv(dev); +- struct mmc_config *cfg = &plat->cfg; + struct sdhci_host *host = &prv->host; ++ int max_frequency, ret; + struct clk clk; +- int ret; + +- host->max_clk = cfg->f_max; ++#if CONFIG_IS_ENABLED(OF_PLATDATA) ++ struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; ++ ++ host->name = dev->name; ++ host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); ++ max_frequency = dtplat->max_frequency; ++ ret = clk_get_by_driver_info(dev, dtplat->clocks, &clk); ++#else ++ max_frequency = dev_read_u32_default(dev, "max-frequency", 0); + ret = clk_get_by_index(dev, 0, &clk); ++#endif + if (!ret) { +- ret = clk_set_rate(&clk, host->max_clk); ++ ret = clk_set_rate(&clk, max_frequency); + if (IS_ERR_VALUE(ret)) + printf("%s clk set rate fail!\n", __func__); + } else { + printf("%s fail to get clk\n", __func__); + } + +- prv->emmc_clk = clk; +- prv->dev = dev; +- +- if (data->get_phy) { +- ret = data->get_phy(dev); +- if (ret) +- return ret; +- } +- +- if (data->emmc_phy_init) { +- ret = data->emmc_phy_init(dev); +- if (ret) +- return ret; +- } +- +- host->ops = &rockchip_sdhci_ops; + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; ++ host->max_clk = max_frequency; ++ /* ++ * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg ++ * doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't ++ * check for other bus-width values. ++ */ ++ if (host->bus_width == 8) ++ host->host_caps |= MMC_MODE_8BIT; + + host->mmc = &plat->mmc; + host->mmc->priv = &prv->host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + +- ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ); ++ ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); + if (ret) + return ret; + + return sdhci_probe(dev); + } + +-static int rockchip_sdhci_of_to_plat(struct udevice *dev) ++static int arasan_sdhci_of_to_plat(struct udevice *dev) + { +- struct rockchip_sdhc_plat *plat = dev_get_plat(dev); ++#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct sdhci_host *host = dev_get_priv(dev); +- struct mmc_config *cfg = &plat->cfg; +- int ret; + + host->name = dev->name; + host->ioaddr = dev_read_addr_ptr(dev); +- +- ret = mmc_of_parse(dev, cfg); +- if (ret) +- return ret; ++ host->bus_width = dev_read_u32_default(dev, "bus-width", 4); ++#endif + + return 0; + } +@@ -333,28 +101,19 @@ static int rockchip_sdhci_bind(struct udevice *dev) + return sdhci_bind(dev, &plat->mmc, &plat->cfg); + } + +-static const struct sdhci_data rk3399_data = { +- .emmc_set_clock = rk3399_sdhci_emmc_set_clock, +- .get_phy = rk3399_emmc_get_phy, +- .emmc_phy_init = rk3399_emmc_phy_init, +-}; +- +-static const struct udevice_id sdhci_ids[] = { +- { +- .compatible = "arasan,sdhci-5.1", +- .data = (ulong)&rk3399_data, +- }, ++static const struct udevice_id arasan_sdhci_ids[] = { ++ { .compatible = "arasan,sdhci-5.1" }, + { } + }; + + U_BOOT_DRIVER(arasan_sdhci_drv) = { +- .name = "rockchip_sdhci_5_1", ++ .name = "rockchip_rk3399_sdhci_5_1", + .id = UCLASS_MMC, +- .of_match = sdhci_ids, +- .of_to_plat = rockchip_sdhci_of_to_plat, ++ .of_match = arasan_sdhci_ids, ++ .of_to_plat = arasan_sdhci_of_to_plat, + .ops = &sdhci_ops, + .bind = rockchip_sdhci_bind, +- .probe = rockchip_sdhci_probe, ++ .probe = arasan_sdhci_probe, + .priv_auto = sizeof(struct rockchip_sdhc), + .plat_auto = sizeof(struct rockchip_sdhc_plat), + }; +-- +2.33.0 + diff --git a/aarch64-boards b/aarch64-boards index 15abee1..9e2fafa 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -18,6 +18,7 @@ khadas-vim khadas-vim2 khadas-vim3 khadas-vim3l +leez-rk3399 libretech-ac libretech_all_h3_cc_h5 libretech_all_h3_it_h5 @@ -29,11 +30,13 @@ nanopc-t4-rk3399 nanopi_a64 nanopi-k2 nanopi-m4-2gb-rk3399 +nanopi-m4b-rk3399 nanopi-m4-rk3399 nanopi_neo2 nanopi-neo4-rk3399 nanopi_neo_plus2 nanopi-r2s-rk3328 +nanopi-r4s-rk3399 odroid-c2 orangepi_3 orangepi_lite2 diff --git a/uboot-tools.spec b/uboot-tools.spec index 4a9c8f9..d3c5b0c 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2021.10 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 2%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -30,6 +30,8 @@ Patch11: 0001-Fix-BeagleAI-detection.patch Patch12: phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch Patch13: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch Patch14: 0001-enable-hs400-and-sdma-support.patch +Patch15: 0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch +Patch16: 0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch BuildRequires: bc BuildRequires: dtc @@ -124,7 +126,7 @@ do echo "Board: $board using rk3328" cp /usr/share/arm-trusted-firmware/rk3328/* builds/$(echo $board)/ fi - rk3399=(evb-rk3399 ficus-rk3399 firefly-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 nanopc-t4-rk3399 nanopi-m4-2gb-rk3399 nanopi-m4-rk3399 nanopi-neo4-rk3399 orangepi-rk3399 pinebook-pro-rk3399 puma-rk3399 rock960-rk3399 rock-pi-4c-rk3399 rock-pi-4-rk3399 rock-pi-n10-rk3399pro rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399) + rk3399=(evb-rk3399 ficus-rk3399 firefly-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 leez-rk3399 nanopc-t4-rk3399 nanopi-m4-2gb-rk3399 nanopi-m4b-rk3399 nanopi-m4-rk3399 nanopi-neo4-rk3399 nanopi-r4s-rk3399 orangepi-rk3399 pinebook-pro-rk3399 puma-rk3399 rock960-rk3399 rock-pi-4c-rk3399 rock-pi-4-rk3399 rock-pi-n10-rk3399pro rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399) if [[ " ${rk3399[*]} " == *" $board "* ]]; then echo "Board: $board using rk3399" cp /usr/share/arm-trusted-firmware/rk3399/* builds/$(echo $board)/ @@ -260,6 +262,10 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Thu Oct 14 2021 Peter Robinson - 2021.10-2 +- Fix booting from MMC for Rockchip 3399 (rhbz #2014182) +- Enable new rk3399 devices (Leez, NanoPi-M4B, NanoPi-4S, NanoPi-T4) (rhbz #2009126) + * Mon Oct 04 2021 Peter Robinson - 2021.10-1 - Update to 2021.10 From e708510df15ea218dc931bf71d0a1ca7bdf78b2c Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 27 Oct 2021 13:29:32 +0200 Subject: [PATCH 02/28] Drop vboot-utils build dependency The package contains tools to build and sign FIT (Flat Image Tree) images that are used in u-boot based Chromebooks. But it isn't really needded to build u-boot, since FIT images are not shipped in uboot-images-armv{7,8}. Also, the vboot-utils package has as build dependency the trousers-devel package and this gets pulled as a dependency to build u-boot as well. But the trousers package is really deprecated since TPM 1.2 chips aren't used anymore nowadays. Let's just drop that unneeded build dependency. --- uboot-tools.spec | 3 --- 1 file changed, 3 deletions(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index d3c5b0c..11083e7 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -55,9 +55,6 @@ BuildRequires: flex bison BuildRequires: openssl-devel BuildRequires: SDL-devel BuildRequires: swig -%ifarch %{arm} aarch64 -BuildRequires: vboot-utils -%endif %ifarch aarch64 BuildRequires: arm-trusted-firmware-armv8 %endif From 684d5792496141406e93b7cb7f0b8d0dced4131a Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 27 Oct 2021 13:43:20 +0100 Subject: [PATCH 03/28] Drop any vestigate of an idea we build U-Boot for Chromebooks, if someone gets the time it can be added back --- aarch64-chromebooks | 0 arm-chromebooks | 8 -------- uboot-tools.spec | 9 +++------ 3 files changed, 3 insertions(+), 14 deletions(-) delete mode 100644 aarch64-chromebooks delete mode 100644 arm-chromebooks diff --git a/aarch64-chromebooks b/aarch64-chromebooks deleted file mode 100644 index e69de29..0000000 diff --git a/arm-chromebooks b/arm-chromebooks deleted file mode 100644 index 899c823..0000000 --- a/arm-chromebooks +++ /dev/null @@ -1,8 +0,0 @@ -chromebit_mickey_defconfig -chromebook_jerry_defconfig -chromebook_minnie_defconfig -nyan-big_defconfig -peach-pi_defconfig -peach-pit_defconfig -snow_defconfig -spring_defconfig diff --git a/uboot-tools.spec b/uboot-tools.spec index 11083e7..bff1088 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,9 +10,7 @@ URL: http://www.denx.de/wiki/U-Boot ExcludeArch: s390x Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 Source1: arm-boards -Source2: arm-chromebooks -Source3: aarch64-boards -Source4: aarch64-chromebooks +Source2: aarch64-boards # Fedoraisms patches # Needed to find DT on boot partition that's not the first partition @@ -85,7 +83,7 @@ U-Boot firmware binaries for armv7 boards %prep %autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} -cp %SOURCE1 %SOURCE2 %SOURCE3 %SOURCE4 . +cp %SOURCE1 %SOURCE2 . %build mkdir builds @@ -242,8 +240,7 @@ cp -p board/warp7/README builds/docs/README.warp7 %files %doc README doc/README.kwbimage doc/README.distro doc/README.gpt %doc doc/README.odroid doc/README.rockchip doc/develop/uefi doc/uImage.FIT doc/arch/arm64.rst -%doc doc/chromium builds/docs/* -%doc doc/board/amlogic/ doc/board/rockchip/ +%doc builds/docs/* doc/board/amlogic/ doc/board/rockchip/ %{_bindir}/* %{_mandir}/man1/mkimage.1* %dir %{_datadir}/uboot/ From 9eb973e7d2ab74341c0eb7312576b6f016ec03d4 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 15 Nov 2021 18:24:46 +0000 Subject: [PATCH 04/28] upstream rk3399 MMC fix, build against new ATF for rk3399 suspend fix --- ...ockchip_sdhci-Add-support-for-RK3568.patch | 152 ------- ...hip_sdhci-add-phy-and-clock-config-f.patch | 406 ------------------ ...kchip-rk3399-enable-emmc-phy-for-spl.patch | 115 +++++ uboot-tools.spec | 8 +- 4 files changed, 120 insertions(+), 561 deletions(-) delete mode 100644 0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch delete mode 100644 0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch create mode 100644 dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch diff --git a/0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch b/0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch deleted file mode 100644 index 33dbf61..0000000 --- a/0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch +++ /dev/null @@ -1,152 +0,0 @@ -From e3e6018d0b67fbab3d05053688e53f5baac63bc3 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Thu, 14 Oct 2021 16:01:56 +0100 -Subject: [PATCH 1/2] Revert "mmc: rockchip_sdhci: Add support for RK3568" - -This reverts commit a63a57e59d864a1ca2b0acb5fadc5c3579c3e79c. ---- - drivers/mmc/rockchip_sdhci.c | 109 ----------------------------------- - 1 file changed, 109 deletions(-) - -diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c -index 1ac00587d4..eff134c8f5 100644 ---- a/drivers/mmc/rockchip_sdhci.c -+++ b/drivers/mmc/rockchip_sdhci.c -@@ -42,34 +42,6 @@ - ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ - PHYCTRL_DLLRDY_DONE) - --/* Rockchip specific Registers */ --#define DWCMSHC_EMMC_DLL_CTRL 0x800 --#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) --#define DWCMSHC_EMMC_DLL_RXCLK 0x804 --#define DWCMSHC_EMMC_DLL_TXCLK 0x808 --#define DWCMSHC_EMMC_DLL_STRBIN 0x80c --#define DWCMSHC_EMMC_DLL_STATUS0 0x840 --#define DWCMSHC_EMMC_DLL_STATUS1 0x844 --#define DWCMSHC_EMMC_DLL_START BIT(0) --#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 --#define DWCMSHC_EMMC_DLL_START_POINT 16 --#define DWCMSHC_EMMC_DLL_START_DEFAULT 5 --#define DWCMSHC_EMMC_DLL_INC_VALUE 2 --#define DWCMSHC_EMMC_DLL_INC 8 --#define DWCMSHC_EMMC_DLL_DLYENA BIT(27) --#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 --#define DLL_STRBIN_TAPNUM_DEFAULT 0x3 --#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) --#define DWCMSHC_EMMC_DLL_LOCKED BIT(8) --#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) --#define DLL_RXCLK_NO_INVERTER 1 --#define DLL_RXCLK_INVERTER 0 --#define DWCMSHC_ENHANCED_STROBE BIT(8) --#define DLL_LOCK_WO_TMOUT(x) \ -- ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ -- (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) --#define ROCKCHIP_MAX_CLKS 3 -- - struct rockchip_sdhc_plat { - struct mmc_config cfg; - struct mmc mmc; -@@ -195,77 +167,6 @@ static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo - return 0; - } - --static int rk3568_emmc_phy_init(struct udevice *dev) --{ -- struct rockchip_sdhc *prv = dev_get_priv(dev); -- struct sdhci_host *host = &prv->host; -- u32 extra; -- -- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; -- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); -- -- return 0; --} -- --static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) --{ -- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); -- int val, ret; -- u32 extra; -- -- if (clock > host->max_clk) -- clock = host->max_clk; -- if (clock) -- clk_set_rate(&priv->emmc_clk, clock); -- -- sdhci_set_clock(host->mmc, clock); -- -- if (clock >= 100 * MHz) { -- /* reset DLL */ -- sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); -- udelay(1); -- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); -- -- /* Init DLL settings */ -- extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | -- DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | -- DWCMSHC_EMMC_DLL_START; -- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); -- -- ret = read_poll_timeout(readl, host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, -- val, DLL_LOCK_WO_TMOUT(val), 1, 500); -- if (ret) -- return ret; -- -- extra = DWCMSHC_EMMC_DLL_DLYENA | -- DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; -- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); -- -- extra = DWCMSHC_EMMC_DLL_DLYENA | -- DLL_TXCLK_TAPNUM_DEFAULT | -- DLL_TXCLK_TAPNUM_FROM_SW; -- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); -- -- extra = DWCMSHC_EMMC_DLL_DLYENA | -- DLL_STRBIN_TAPNUM_DEFAULT; -- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); -- } else { -- /* reset the clock phase when the frequency is lower than 100MHz */ -- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); -- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; -- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); -- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); -- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); -- } -- -- return 0; --} -- --static int rk3568_emmc_get_phy(struct udevice *dev) --{ -- return 0; --} -- - static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) - { - struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); -@@ -438,21 +339,11 @@ static const struct sdhci_data rk3399_data = { - .emmc_phy_init = rk3399_emmc_phy_init, - }; - --static const struct sdhci_data rk3568_data = { -- .emmc_set_clock = rk3568_sdhci_emmc_set_clock, -- .get_phy = rk3568_emmc_get_phy, -- .emmc_phy_init = rk3568_emmc_phy_init, --}; -- - static const struct udevice_id sdhci_ids[] = { - { - .compatible = "arasan,sdhci-5.1", - .data = (ulong)&rk3399_data, - }, -- { -- .compatible = "rockchip,rk3568-dwcmshc", -- .data = (ulong)&rk3568_data, -- }, - { } - }; - --- -2.33.0 - diff --git a/0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch b/0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch deleted file mode 100644 index 20a827c..0000000 --- a/0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch +++ /dev/null @@ -1,406 +0,0 @@ -From bb7b9097efc67ff6051f206e3ac9602dabbfc33e Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Thu, 14 Oct 2021 16:02:03 +0100 -Subject: [PATCH 2/2] Revert "mmc: rockchip_sdhci: add phy and clock config for - rk3399" - -This reverts commit ac804143cfd128d144403ef2434344988c3fde9f. ---- - drivers/mmc/rockchip_sdhci.c | 313 ++++------------------------------- - 1 file changed, 36 insertions(+), 277 deletions(-) - -diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c -index eff134c8f5..d95f8b2a15 100644 ---- a/drivers/mmc/rockchip_sdhci.c -+++ b/drivers/mmc/rockchip_sdhci.c -@@ -6,322 +6,90 @@ - */ - - #include --#include - #include --#include - #include --#include - #include - #include --#include - #include - #include --#include "mmc_private.h" - #include --#include --#include --#include -+#include - - /* 400KHz is max freq for card ID etc. Use that as min */ - #define EMMC_MIN_FREQ 400000 --#define KHz (1000) --#define MHz (1000 * KHz) --#define SDHCI_TUNING_LOOP_COUNT 40 -- --#define PHYCTRL_CALDONE_MASK 0x1 --#define PHYCTRL_CALDONE_SHIFT 0x6 --#define PHYCTRL_CALDONE_DONE 0x1 --#define PHYCTRL_DLLRDY_MASK 0x1 --#define PHYCTRL_DLLRDY_SHIFT 0x5 --#define PHYCTRL_DLLRDY_DONE 0x1 --#define PHYCTRL_FREQSEL_200M 0x0 --#define PHYCTRL_FREQSEL_50M 0x1 --#define PHYCTRL_FREQSEL_100M 0x2 --#define PHYCTRL_FREQSEL_150M 0x3 --#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \ -- ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ -- PHYCTRL_DLLRDY_DONE) - - struct rockchip_sdhc_plat { -+#if CONFIG_IS_ENABLED(OF_PLATDATA) -+ struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; -+#endif - struct mmc_config cfg; - struct mmc mmc; - }; - --struct rockchip_emmc_phy { -- u32 emmcphy_con[7]; -- u32 reserved; -- u32 emmcphy_status; --}; -- - struct rockchip_sdhc { - struct sdhci_host host; -- struct udevice *dev; - void *base; -- struct rockchip_emmc_phy *phy; -- struct clk emmc_clk; --}; -- --struct sdhci_data { -- int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock); -- int (*emmc_phy_init)(struct udevice *dev); -- int (*get_phy)(struct udevice *dev); --}; -- --static int rk3399_emmc_phy_init(struct udevice *dev) --{ -- return 0; --} -- --static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) --{ -- u32 caldone, dllrdy, freqsel; -- -- writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); -- writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); -- writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); -- -- /* -- * According to the user manual, calpad calibration -- * cycle takes more than 2us without the minimal recommended -- * value, so we may need a little margin here -- */ -- udelay(3); -- writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); -- -- /* -- * According to the user manual, it asks driver to -- * wait 5us for calpad busy trimming. But it seems that -- * 5us of caldone isn't enough for all cases. -- */ -- udelay(500); -- caldone = readl(&phy->emmcphy_status); -- caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; -- if (caldone != PHYCTRL_CALDONE_DONE) { -- printf("%s: caldone timeout.\n", __func__); -- return; -- } -- -- /* Set the frequency of the DLL operation */ -- if (clock < 75 * MHz) -- freqsel = PHYCTRL_FREQSEL_50M; -- else if (clock < 125 * MHz) -- freqsel = PHYCTRL_FREQSEL_100M; -- else if (clock < 175 * MHz) -- freqsel = PHYCTRL_FREQSEL_150M; -- else -- freqsel = PHYCTRL_FREQSEL_200M; -- -- /* Set the frequency of the DLL operation */ -- writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); -- writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); -- -- read_poll_timeout(readl, &phy->emmcphy_status, dllrdy, -- PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000); --} -- --static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) --{ -- writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); -- writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); --} -- --static int rk3399_emmc_get_phy(struct udevice *dev) --{ -- struct rockchip_sdhc *priv = dev_get_priv(dev); -- ofnode phy_node; -- void *grf_base; -- u32 grf_phy_offset, phandle; -- -- phandle = dev_read_u32_default(dev, "phys", 0); -- phy_node = ofnode_get_by_phandle(phandle); -- if (!ofnode_valid(phy_node)) { -- debug("Not found emmc phy device\n"); -- return -ENODEV; -- } -- -- grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -- if (grf_base < 0) { -- printf("%s Get syscon grf failed", __func__); -- return -ENODEV; -- } -- grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); -- -- priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); -- -- return 0; --} -- --static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) --{ -- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); -- int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ; -- -- if (cycle_phy) -- rk3399_emmc_phy_power_off(priv->phy); -- -- sdhci_set_clock(host->mmc, clock); -- -- if (cycle_phy) -- rk3399_emmc_phy_power_on(priv->phy, clock); -- -- return 0; --} -- --static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) --{ -- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); -- struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); -- struct mmc *mmc = host->mmc; -- uint clock = mmc->tran_speed; -- u32 reg; -- -- if (!clock) -- clock = mmc->clock; -- -- if (data->emmc_set_clock) -- data->emmc_set_clock(host, clock); -- -- if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) { -- reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); -- reg &= ~SDHCI_CTRL_UHS_MASK; -- reg |= SDHCI_CTRL_HS400; -- sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); -- } else { -- sdhci_set_uhs_timing(host); -- } -- -- return 0; --} -- --static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) --{ -- struct sdhci_host *host = dev_get_priv(mmc->dev); -- char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; -- struct mmc_cmd cmd; -- u32 ctrl, blk_size; -- int ret = 0; -- -- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); -- ctrl |= SDHCI_CTRL_EXEC_TUNING; -- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); -- -- sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); -- sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); -- -- blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); -- if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8) -- blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128); -- sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE); -- sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); -- -- cmd.cmdidx = opcode; -- cmd.resp_type = MMC_RSP_R1; -- cmd.cmdarg = 0; -- -- do { -- if (tuning_loop_counter-- == 0) -- break; -- -- mmc_send_cmd(mmc, &cmd, NULL); -- -- if (opcode == MMC_CMD_SEND_TUNING_BLOCK) -- /* -- * For tuning command, do not do busy loop. As tuning -- * is happening (CLK-DATA latching for setup/hold time -- * requirements), give time to complete -- */ -- udelay(1); -- -- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); -- } while (ctrl & SDHCI_CTRL_EXEC_TUNING); -- -- if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { -- printf("%s:Tuning failed\n", __func__); -- ret = -EIO; -- } -- -- if (tuning_loop_counter < 0) { -- ctrl &= ~SDHCI_CTRL_TUNED_CLK; -- sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2); -- } -- -- /* Enable only interrupts served by the SD controller */ -- sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE); -- /* Mask all sdhci interrupt sources */ -- sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); -- -- return ret; --} -- --static struct sdhci_ops rockchip_sdhci_ops = { -- .set_ios_post = rockchip_sdhci_set_ios_post, -- .platform_execute_tuning = &rockchip_sdhci_execute_tuning, - }; - --static int rockchip_sdhci_probe(struct udevice *dev) -+static int arasan_sdhci_probe(struct udevice *dev) - { -- struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct rockchip_sdhc_plat *plat = dev_get_plat(dev); - struct rockchip_sdhc *prv = dev_get_priv(dev); -- struct mmc_config *cfg = &plat->cfg; - struct sdhci_host *host = &prv->host; -+ int max_frequency, ret; - struct clk clk; -- int ret; - -- host->max_clk = cfg->f_max; -+#if CONFIG_IS_ENABLED(OF_PLATDATA) -+ struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; -+ -+ host->name = dev->name; -+ host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); -+ max_frequency = dtplat->max_frequency; -+ ret = clk_get_by_driver_info(dev, dtplat->clocks, &clk); -+#else -+ max_frequency = dev_read_u32_default(dev, "max-frequency", 0); - ret = clk_get_by_index(dev, 0, &clk); -+#endif - if (!ret) { -- ret = clk_set_rate(&clk, host->max_clk); -+ ret = clk_set_rate(&clk, max_frequency); - if (IS_ERR_VALUE(ret)) - printf("%s clk set rate fail!\n", __func__); - } else { - printf("%s fail to get clk\n", __func__); - } - -- prv->emmc_clk = clk; -- prv->dev = dev; -- -- if (data->get_phy) { -- ret = data->get_phy(dev); -- if (ret) -- return ret; -- } -- -- if (data->emmc_phy_init) { -- ret = data->emmc_phy_init(dev); -- if (ret) -- return ret; -- } -- -- host->ops = &rockchip_sdhci_ops; - host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; -+ host->max_clk = max_frequency; -+ /* -+ * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg -+ * doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't -+ * check for other bus-width values. -+ */ -+ if (host->bus_width == 8) -+ host->host_caps |= MMC_MODE_8BIT; - - host->mmc = &plat->mmc; - host->mmc->priv = &prv->host; - host->mmc->dev = dev; - upriv->mmc = host->mmc; - -- ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ); -+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); - if (ret) - return ret; - - return sdhci_probe(dev); - } - --static int rockchip_sdhci_of_to_plat(struct udevice *dev) -+static int arasan_sdhci_of_to_plat(struct udevice *dev) - { -- struct rockchip_sdhc_plat *plat = dev_get_plat(dev); -+#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct sdhci_host *host = dev_get_priv(dev); -- struct mmc_config *cfg = &plat->cfg; -- int ret; - - host->name = dev->name; - host->ioaddr = dev_read_addr_ptr(dev); -- -- ret = mmc_of_parse(dev, cfg); -- if (ret) -- return ret; -+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4); -+#endif - - return 0; - } -@@ -333,28 +101,19 @@ static int rockchip_sdhci_bind(struct udevice *dev) - return sdhci_bind(dev, &plat->mmc, &plat->cfg); - } - --static const struct sdhci_data rk3399_data = { -- .emmc_set_clock = rk3399_sdhci_emmc_set_clock, -- .get_phy = rk3399_emmc_get_phy, -- .emmc_phy_init = rk3399_emmc_phy_init, --}; -- --static const struct udevice_id sdhci_ids[] = { -- { -- .compatible = "arasan,sdhci-5.1", -- .data = (ulong)&rk3399_data, -- }, -+static const struct udevice_id arasan_sdhci_ids[] = { -+ { .compatible = "arasan,sdhci-5.1" }, - { } - }; - - U_BOOT_DRIVER(arasan_sdhci_drv) = { -- .name = "rockchip_sdhci_5_1", -+ .name = "rockchip_rk3399_sdhci_5_1", - .id = UCLASS_MMC, -- .of_match = sdhci_ids, -- .of_to_plat = rockchip_sdhci_of_to_plat, -+ .of_match = arasan_sdhci_ids, -+ .of_to_plat = arasan_sdhci_of_to_plat, - .ops = &sdhci_ops, - .bind = rockchip_sdhci_bind, -- .probe = rockchip_sdhci_probe, -+ .probe = arasan_sdhci_probe, - .priv_auto = sizeof(struct rockchip_sdhc), - .plat_auto = sizeof(struct rockchip_sdhc_plat), - }; --- -2.33.0 - diff --git a/dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch b/dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch new file mode 100644 index 0000000..3ef5b53 --- /dev/null +++ b/dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch @@ -0,0 +1,115 @@ +From patchwork Mon Nov 1 04:43:47 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Yifeng Zhao +X-Patchwork-Id: 1548950 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No 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+X-ATTACHMENT-NUM: 0 +X-UNIQUE-TAG: <8beb59827f65d556787d36e0068aa9cb> +X-System-Flag: 0 +From: Yifeng Zhao +To: Kever Yang +Cc: sjg , Peter Robinson , + Philipp Tomsich , + u-boot@lists.denx.de, Jack Mitchell , + Yifeng Zhao +Subject: [PATCH] dts: rockchip: rk3399: enable emmc phy for spl +Date: Mon, 1 Nov 2021 12:43:47 +0800 +Message-Id: <20211101044347.17822-1-yifeng.zhao@rock-chips.com> +X-Mailer: git-send-email 2.17.1 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de +X-Virus-Status: Clean + +adapting commit ac804143cf ("mmc: rockchip_sdhci: add phy and clock +config for rk3399") to fix the issue "Not found emmc phy device". + +Signed-off-by: Yifeng Zhao +--- + + arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi +index 73922c328a..716b9a433a 100644 +--- a/arch/arm/dts/rk3399-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-u-boot.dtsi +@@ -88,6 +88,10 @@ + u-boot,dm-pre-reloc; + }; + ++&emmc_phy { ++ u-boot,dm-pre-reloc; ++}; ++ + &grf { + u-boot,dm-pre-reloc; + }; diff --git a/uboot-tools.spec b/uboot-tools.spec index bff1088..d77e112 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2021.10 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Release: 3%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -28,8 +28,7 @@ Patch11: 0001-Fix-BeagleAI-detection.patch Patch12: phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch Patch13: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch Patch14: 0001-enable-hs400-and-sdma-support.patch -Patch15: 0001-Revert-mmc-rockchip_sdhci-Add-support-for-RK3568.patch -Patch16: 0002-Revert-mmc-rockchip_sdhci-add-phy-and-clock-config-f.patch +Patch15: dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch BuildRequires: bc BuildRequires: dtc @@ -256,6 +255,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Mon Nov 15 2021 Peter Robinson - 2021.10-3 +- Fixes for rk3399 devices + * Thu Oct 14 2021 Peter Robinson - 2021.10-2 - Fix booting from MMC for Rockchip 3399 (rhbz #2014182) - Enable new rk3399 devices (Leez, NanoPi-M4B, NanoPi-4S, NanoPi-T4) (rhbz #2009126) From 89bd41507ecefd2f18fdfc7cc8d2993a7c24b772 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 15 Nov 2021 21:11:49 +0000 Subject: [PATCH 05/28] 2022.01 RC2 --- AllWinner-PineTab.patch | 45 ----------------------------------------- sources | 2 +- uboot-tools.spec | 11 +++++----- 3 files changed, 7 insertions(+), 51 deletions(-) delete mode 100644 AllWinner-PineTab.patch diff --git a/AllWinner-PineTab.patch b/AllWinner-PineTab.patch deleted file mode 100644 index 04b6896..0000000 --- a/AllWinner-PineTab.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 6bf15552c2b6becb48ce7732120e0ddb2078cb1a Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 14 Apr 2020 09:53:07 +0100 -Subject: [PATCH 9/9] initial pinetab support - -Signed-off-by: Peter Robinson ---- - configs/pinetab_defconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - create mode 100644 configs/pinetab_defconfig - -diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig -new file mode 100644 -index 0000000000..5b9620f3e5 ---- /dev/null -+++ b/configs/pinetab_defconfig -@@ -0,0 +1,26 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_SPL=y -+CONFIG_MACH_SUN50I=y -+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y -+CONFIG_DRAM_CLK=552 -+CONFIG_DRAM_ZQ=3881949 -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -+CONFIG_R_I2C_ENABLE=y -+CONFIG_SPL_SPI_SUNXI=y -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_USE_PREBOOT=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_SPL_EFI_PARTITION is not set -+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab" -+CONFIG_OF_LIST="sun50i-a64-pinetab" -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_SUNXI=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y --- -2.26.0 diff --git a/sources b/sources index f64b4ca..24f086d 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2021.10.tar.bz2) = be5be1c9a54b270307a04177d5577a21c57a02b307bf8b63d0fa2655d1f025c7ce010dca6a1f7f60d4e639c2e6fb6f0a292a2e5d190f1fad478eb12dd786c9da +SHA512 (u-boot-2022.01-rc2.tar.bz2) = 1caaff097270ee205cf63cca0d66c6161ff03d927275dc7f757b39d59a52a21e7d81d5391570e649a196d9ba114536539cef688cdc43690a2e53d321f22fec43 diff --git a/uboot-tools.spec b/uboot-tools.spec index d77e112..b2cb2a9 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -#global candidate rc5 +%global candidate rc2 Name: uboot-tools -Version: 2021.10 -Release: 3%{?candidate:.%{candidate}}%{?dist} +Version: 2022.01 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -20,8 +20,6 @@ Patch1: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch Patch2: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch3: rpi-fallback-to-max-clock-for-mmc.patch Patch4: rpi-bcm2835_sdhost-firmware-managed-clock.patch -# AllWinner improvements -Patch10: AllWinner-PineTab.patch # TI fixes Patch11: 0001-Fix-BeagleAI-detection.patch # Rockchips improvements @@ -255,6 +253,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Mon Nov 15 2021 Peter Robinson - 2022.01-0.1.rc2 +- Update to 2022.01 RC2 + * Mon Nov 15 2021 Peter Robinson - 2021.10-3 - Fixes for rk3399 devices From c08df485fa1f3244af7c43a53c6c8cc457c84426 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 15 Nov 2021 22:12:48 +0000 Subject: [PATCH 06/28] Update names of shipped docs --- uboot-tools.spec | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index b2cb2a9..80cf5fe 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -227,7 +227,6 @@ cp -p board/solidrun/clearfog/README builds/docs/README.clearfog cp -p board/solidrun/mx6cuboxi/README builds/docs/README.mx6cuboxi cp -p board/sunxi/README.sunxi64 builds/docs/README.sunxi64 cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand -cp -p board/ti/am335x/README builds/docs/README.am335x cp -p board/ti/omap5_uevm/README builds/docs/README.omap5_uevm cp -p board/udoo/README builds/docs/README.udoo cp -p board/wandboard/README builds/docs/README.wandboard @@ -235,9 +234,9 @@ cp -p board/warp/README builds/docs/README.warp cp -p board/warp7/README builds/docs/README.warp7 %files -%doc README doc/README.kwbimage doc/README.distro doc/README.gpt +%doc README doc/README.kwbimage doc/develop/distro.rst doc/README.gpt %doc doc/README.odroid doc/README.rockchip doc/develop/uefi doc/uImage.FIT doc/arch/arm64.rst -%doc builds/docs/* doc/board/amlogic/ doc/board/rockchip/ +%doc builds/docs/* doc/board/amlogic/ doc/board/rockchip/ doc/board/ti/am335x_evm.rst %{_bindir}/* %{_mandir}/man1/mkimage.1* %dir %{_datadir}/uboot/ From d98cfa77d6c02521b70378e27f2baff27bcfad6c Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 20 Dec 2021 19:55:40 +0000 Subject: [PATCH 07/28] 2022.01 RC4 --- 0001-Fix-BeagleAI-detection.patch | 29 ----- 0001-enable-hs400-and-sdma-support.patch | 158 ----------------------- sources | 2 +- uboot-tools.spec | 17 +-- 4 files changed, 10 insertions(+), 196 deletions(-) delete mode 100644 0001-Fix-BeagleAI-detection.patch delete mode 100644 0001-enable-hs400-and-sdma-support.patch diff --git a/0001-Fix-BeagleAI-detection.patch b/0001-Fix-BeagleAI-detection.patch deleted file mode 100644 index dfd96cc..0000000 --- a/0001-Fix-BeagleAI-detection.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 1849ef423238aeb1732eb3b8e67eb46bc21401c7 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Thu, 10 Sep 2020 14:24:12 +0100 -Subject: [PATCH] Fix BeagleAI detection - -Signed-off-by: Peter Robinson ---- - board/ti/am57xx/board.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c -index 7809875510..3232812a97 100644 ---- a/board/ti/am57xx/board.c -+++ b/board/ti/am57xx/board.c -@@ -527,8 +527,10 @@ void do_board_detect(void) - - rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, - CONFIG_EEPROM_CHIP_ADDRESS); -- if (rc) -+ if (rc) { - printf("ti_i2c_eeprom_init failed %d\n", rc); -+ ti_i2c_eeprom_am_set("BBONE-AI", "A"); -+ } - - #ifdef CONFIG_SUPPORT_EMMC_BOOT - rc = board_bootmode_has_emmc(); --- -2.26.2 - diff --git a/0001-enable-hs400-and-sdma-support.patch b/0001-enable-hs400-and-sdma-support.patch deleted file mode 100644 index 782366f..0000000 --- a/0001-enable-hs400-and-sdma-support.patch +++ /dev/null @@ -1,158 +0,0 @@ -From 42aa88db46fa88db52bbb5a96fc0eaebe695110e Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 30 Aug 2021 18:20:39 +0100 -Subject: [PATCH] enable hs400 and sdma support - -Signed-off-by: Peter Robinson ---- - configs/firefly-rk3399_defconfig | 2 ++ - configs/nanopc-t4-rk3399_defconfig | 2 ++ - configs/nanopi-m4-2gb-rk3399_defconfig | 2 ++ - configs/nanopi-m4-rk3399_defconfig | 2 ++ - configs/nanopi-m4b-rk3399_defconfig | 2 ++ - configs/nanopi-neo4-rk3399_defconfig | 2 ++ - configs/nanopi-r4s-rk3399_defconfig | 2 ++ - configs/pinebook-pro-rk3399_defconfig | 1 + - configs/rock960-rk3399_defconfig | 1 + - configs/rockpro64-rk3399_defconfig | 2 ++ - 10 files changed, 18 insertions(+) - -diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig -index 2ca2ac35e4..84ee690a2d 100644 ---- a/configs/firefly-rk3399_defconfig -+++ b/configs/firefly-rk3399_defconfig -@@ -33,7 +33,9 @@ CONFIG_MISC=y - CONFIG_ROCKCHIP_EFUSE=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_SF_DEFAULT_SPEED=20000000 - CONFIG_DM_ETH=y -diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig -index a94f428def..722377803e 100644 ---- a/configs/nanopc-t4-rk3399_defconfig -+++ b/configs/nanopc-t4-rk3399_defconfig -@@ -30,7 +30,9 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig -index c9833fdb85..384d7da80c 100644 ---- a/configs/nanopi-m4-2gb-rk3399_defconfig -+++ b/configs/nanopi-m4-2gb-rk3399_defconfig -@@ -29,7 +29,9 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig -index 2b2fcac366..b6b8ca8d3a 100644 ---- a/configs/nanopi-m4-rk3399_defconfig -+++ b/configs/nanopi-m4-rk3399_defconfig -@@ -29,7 +29,9 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig -index 6d3afe1b63..3f83877e0a 100644 ---- a/configs/nanopi-m4b-rk3399_defconfig -+++ b/configs/nanopi-m4b-rk3399_defconfig -@@ -29,7 +29,9 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig -index 1bf5d1d095..6412cb2d7e 100644 ---- a/configs/nanopi-neo4-rk3399_defconfig -+++ b/configs/nanopi-neo4-rk3399_defconfig -@@ -29,7 +29,9 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig -index 351d2eb553..7b527d47fa 100644 ---- a/configs/nanopi-r4s-rk3399_defconfig -+++ b/configs/nanopi-r4s-rk3399_defconfig -@@ -29,7 +29,9 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index f97d5e872b..b0e68c9591 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -46,6 +46,7 @@ CONFIG_MISC=y - CONFIG_ROCKCHIP_EFUSE=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -index 0233e0ea52..624d718f9f 100644 ---- a/configs/rock960-rk3399_defconfig -+++ b/configs/rock960-rk3399_defconfig -@@ -36,6 +36,7 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig -index ae11a8f5eb..b4e7e9700a 100644 ---- a/configs/rockpro64-rk3399_defconfig -+++ b/configs/rockpro64-rk3399_defconfig -@@ -39,7 +39,9 @@ CONFIG_MISC=y - CONFIG_ROCKCHIP_EFUSE=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_HS400_SUPPORT=y - CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y - CONFIG_SF_DEFAULT_BUS=1 - CONFIG_SPI_FLASH_GIGADEVICE=y --- -2.31.1 - diff --git a/sources b/sources index 24f086d..b98988f 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.01-rc2.tar.bz2) = 1caaff097270ee205cf63cca0d66c6161ff03d927275dc7f757b39d59a52a21e7d81d5391570e649a196d9ba114536539cef688cdc43690a2e53d321f22fec43 +SHA512 (u-boot-2022.01-rc4.tar.bz2) = 2b07f52794056926125ca0327999c06939c19c9bbcfa2b3ea6809a2298adee1323f22f142aed57297be07541662f1d909af23393f78d7718ff6963d0552119b7 diff --git a/uboot-tools.spec b/uboot-tools.spec index 80cf5fe..f06fbe0 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc2 +%global candidate rc4 Name: uboot-tools Version: 2022.01 -Release: 0.1%{?candidate:.%{candidate}}%{?dist} +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -15,18 +15,16 @@ Source2: aarch64-boards # Fedoraisms patches # Needed to find DT on boot partition that's not the first partition Patch1: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch + # Board fixes and enablement # RPi - uses RPI firmware device tree for HAT support Patch2: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch3: rpi-fallback-to-max-clock-for-mmc.patch Patch4: rpi-bcm2835_sdhost-firmware-managed-clock.patch -# TI fixes -Patch11: 0001-Fix-BeagleAI-detection.patch # Rockchips improvements -Patch12: phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch -Patch13: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch -Patch14: 0001-enable-hs400-and-sdma-support.patch -Patch15: dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch +Patch5: phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch +Patch6: dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch +Patch7: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch BuildRequires: bc BuildRequires: dtc @@ -252,6 +250,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Mon Dec 20 2021 Peter Robinson - 2022.01-0.2.rc4 +- Update to 2022.01 RC4 + * Mon Nov 15 2021 Peter Robinson - 2022.01-0.1.rc2 - Update to 2022.01 RC2 From 1457c7c78ebb2d23e20d86501c3afb0505019e19 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 5 Jan 2022 15:01:52 +0000 Subject: [PATCH 08/28] fixes for UEFI and improved upstream fix for PHY shutdown lockups --- aarch64-boards | 2 + ...-hang-when-multiple-controllers-exit.patch | 233 -------- uboot-tools.spec | 18 +- ...oll-frequency-to-improve-performance.patch | 178 ++++++ ...k-power-on-and-init-counts-in-uclass.patch | 556 ++++++++++++++++++ 5 files changed, 747 insertions(+), 240 deletions(-) delete mode 100644 phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch create mode 100644 v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch create mode 100644 v3-phy-Track-power-on-and-init-counts-in-uclass.patch diff --git a/aarch64-boards b/aarch64-boards index 9e2fafa..50427ad 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -1,5 +1,6 @@ a64-olinuxino amarula_a64_relic +apple_m1 bananapi_m2_plus_h5 bananapi_m64 beelink_gs1 @@ -35,6 +36,7 @@ nanopi-m4-rk3399 nanopi_neo2 nanopi-neo4-rk3399 nanopi_neo_plus2 +nanopi_r1s_h5 nanopi-r2s-rk3328 nanopi-r4s-rk3399 odroid-c2 diff --git a/phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch b/phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch deleted file mode 100644 index 81f1cdb..0000000 --- a/phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch +++ /dev/null @@ -1,233 +0,0 @@ -From patchwork Tue Apr 6 15:10:59 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Icenowy Zheng -X-Patchwork-Id: 1462876 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dkim=fail reason="signature verification failed" (1024-bit key; - unprotected) header.d=mymailcheap.com header.i=@mymailcheap.com - header.a=rsa-sha256 header.s=default header.b=unszVtqT; - dkim=fail reason="signature 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v=1; a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; - t=1617721874; bh=qb5gt5o7M9qjdJd67A3WHGZp/76w4s4FS6+u1VuEh/o=; - h=From:To:Cc:Subject:Date:From; - b=mWwYCh9AM8eRWm9hiEqirytotj/G/C1p9r2fd0zUxPhS0UQH+kw6L3RWZnsfmXAYq - HmYFiM3ktIfwevqQw89tOi8c2ktb49iYOyHXkfi8hTZl1dNsJDS94uyzBiHYY+U7x5 - P0aTRRaL5C8ua2c1GedoPx06nrARO/KMEFy39rxI= -From: Icenowy Zheng -To: Simon Glass , Kever Yang , - Frank Wang , - Jagan Teki -Cc: u-boot@lists.denx.de, - Icenowy Zheng -Subject: [PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers - exit -Date: Tue, 6 Apr 2021 23:10:59 +0800 -Message-Id: <20210406151059.1187379-1-icenowy@aosc.io> -X-Mailer: git-send-email 2.30.2 -MIME-Version: 1.0 -X-Rspamd-Server: mail20.mymailcheap.com -X-Spamd-Result: default: False [4.90 / 20.00]; RCVD_VIA_SMTP_AUTH(0.00)[]; - ARC_NA(0.00)[]; R_DKIM_ALLOW(0.00)[aosc.io:s=default]; - RECEIVED_SPAMHAUS_PBL(0.00)[59.41.163.135:received]; - FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; - R_MISSING_CHARSET(2.50)[]; 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They will -both do init and power_on operations when the controller is brought up -and both do power_off and exit when the controller is stopped. However, -the PHY uclass of U-Boot is not as sane as we thought -- they won't -maintain a status mark for PHYs, and thus the functions of the PHYs -could be called for multiple times. Calling init/power_on for multiple -times have no severe problems, however calling power_off/exit for -multiple times have a problem -- the first exit call will stop the PHY -clock, and power_off/exit calls after it still trying to write to PHY -registers. The write operation to PHY registers will fail because clock -is already stopped. - -Adapt the count mechanism from phy-sun4i-usb to both init/exit and -power_on/power_off functions to phy-rockchip-inno-usb2 to fix this -problem. With this stopping USB controllers (manually or before booting -a kernel) will work. - -Signed-off-by: Icenowy Zheng -Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver") ---- - drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21 +++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -index 62b8ba3a4a..be9cc99d90 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -62,6 +62,8 @@ struct rockchip_usb2phy { - void *reg_base; - struct clk phyclk; - const struct rockchip_usb2phy_cfg *phy_cfg; -+ int init_count; -+ int power_on_count; - }; - - static inline int property_enable(void *reg_base, -@@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy *phy) - struct rockchip_usb2phy *priv = dev_get_priv(parent); - const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); - -+ priv->power_on_count++; -+ if (priv->power_on_count != 1) -+ return 0; -+ - property_enable(priv->reg_base, &port_cfg->phy_sus, false); - - /* waiting for the utmi_clk to become stable */ -@@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct phy *phy) - struct rockchip_usb2phy *priv = dev_get_priv(parent); - const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); - -+ priv->power_on_count--; -+ if (priv->power_on_count != 0) -+ return 0; -+ - property_enable(priv->reg_base, &port_cfg->phy_sus, true); - - return 0; -@@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy *phy) - const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); - int ret; - -+ priv->init_count++; -+ if (priv->init_count != 1) -+ return 0; -+ - ret = clk_enable(&priv->phyclk); - if (ret) { - dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret); -@@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy *phy) - struct udevice *parent = dev_get_parent(phy->dev); - struct rockchip_usb2phy *priv = dev_get_priv(parent); - -+ priv->init_count--; -+ if (priv->init_count != 0) -+ return 0; -+ - clk_disable(&priv->phyclk); - - return 0; -@@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct udevice *dev) - return ret; - } - -+ priv->power_on_count = 0; -+ priv->init_count = 0; -+ - return 0; - } - diff --git a/uboot-tools.spec b/uboot-tools.spec index f06fbe0..92d15ee 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2022.01 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.3%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -17,14 +17,15 @@ Source2: aarch64-boards Patch1: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch # Board fixes and enablement +Patch2: v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch # RPi - uses RPI firmware device tree for HAT support -Patch2: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch -Patch3: rpi-fallback-to-max-clock-for-mmc.patch -Patch4: rpi-bcm2835_sdhost-firmware-managed-clock.patch +Patch3: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch +Patch4: rpi-fallback-to-max-clock-for-mmc.patch +Patch5: rpi-bcm2835_sdhost-firmware-managed-clock.patch # Rockchips improvements -Patch5: phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch -Patch6: dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch -Patch7: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch +Patch6: v3-phy-Track-power-on-and-init-counts-in-uclass.patch +Patch7: dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch +Patch8: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch BuildRequires: bc BuildRequires: dtc @@ -250,6 +251,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Wed Jan 05 2022 Peter Robinson - 2022.01-0.3.rc4 +- Upstream fixes for PHY and UEFI + * Mon Dec 20 2021 Peter Robinson - 2022.01-0.2.rc4 - Update to 2022.01 RC4 diff --git a/v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch b/v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch new file mode 100644 index 0000000..5eb366c --- /dev/null +++ b/v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch @@ -0,0 +1,178 @@ +From patchwork Wed Dec 22 22:51:26 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Thomas Watson +X-Patchwork-Id: 1572368 +X-Patchwork-Delegate: marek.vasut@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: bilbo.ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=icloud.com header.i=@icloud.com header.a=rsa-sha256 + header.s=1a1hai header.b=SkTQ1vLj; + dkim-atps=neutral +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JK8Mc4B31z9s0r + for ; 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Wed, 22 Dec 2021 23:52:23 +0100 (CET) +Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) + header.from=icloud.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=twatson52@icloud.com +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=icloud.com; + s=1a1hai; t=1640213541; + bh=9Gu/RsbBH8Lwy0caxjtXwguQwc3tOXLqzye8cafMd78=; + h=From:To:Subject:Date:Message-Id:MIME-Version; + b=SkTQ1vLjDZUB4S3pQ+QOuMAQs7y78hvdCVG59JmuiBtL/pLL9IskzfDYEEVxmBQ8j + QIbZXSdaHlAH3tL3ajaqL0+IJp7J/yQ5/wpmmTsRMBdk0xcgSGilBCve35DMoKYFu1 + YSaXYI8GDtaBL5R9EGZAW6SekyeIWfyy03PQpawqJpTlqUNZuLdrr9mGRF/q2fbSHd + Fr4qzePCKzk3GsUhdfkh8hEDS4lOGVAPa3K2mGEpK6K/+Gv3rCckgYrV5IAJQ8YpdP + SCmRL3N03P5wkt5WiYasawJW4pcx92J2RXtyikC9fc6p67bGXkUJA+8dOtxlOyBY8E + 8TrKBWY9cvKTw== +Received: from jacobs-p52.memphis.edu + (99-122-90-201.lightspeed.mmphtn.sbcglobal.net [99.122.90.201]) + by st43p00im-ztbu10073601.me.com (Postfix) with ESMTPSA id 283205A0974; + Wed, 22 Dec 2021 22:52:21 +0000 (UTC) +From: Thomas Watson +To: u-boot@lists.denx.de +Cc: Thomas Watson , + Marek Vasut +Subject: [PATCH v2] console: usb: kbd: Limit poll frequency to improve + performance +Date: Wed, 22 Dec 2021 16:51:26 -0600 +Message-Id: <20211222225124.7154-1-twatson52@icloud.com> +X-Mailer: git-send-email 2.31.1 +MIME-Version: 1.0 +X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425, 18.0.790 + definitions=2021-12-22_02:2021-12-22, + 2021-12-22 signatures=0 +X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 + malwarescore=0 + phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 + mlxlogscore=934 adultscore=0 classifier=spam adjust=0 reason=mlx + scancount=1 engine=8.0.1-2009150000 definitions=main-2112220119 +X-Mailman-Approved-At: Thu, 23 Dec 2021 00:15:58 +0100 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.38 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de +X-Virus-Status: Clean + +Using the XHCI driver, the function `usb_kbd_poll_for_event` takes +30-40ms to run. The exact time is dependent on the polling interval the +keyboard requests in its descriptor, and likely cannot be significantly +reduced without major rework to the XHCI driver. + +The U-Boot EFI console service sets a timer to poll the keyboard every 5 +microseconds, and this timer is checked every time a block is read off +disk. The net effect is that, on my system, loading a ~40MiB kernel and +initrd takes about 62 seconds with a slower keyboard and 53 seconds +with a faster one, with the vast majority of the time spent polling the +keyboard. + +To solve this problem, this patch adds a 20ms delay between consecutive +calls to `usb_kbd_poll_for_event`. This is sufficient to reduce the +total loading time to under half a second for both keyboards, and does +not impact the perceived keystroke latency. + +Signed-off-by: Thomas Watson +--- +This revision wraps the comment at 80 characters and also should not +have been corrupted by my e-mail client. + + common/usb_kbd.c | 20 +++++++++++++++----- + 1 file changed, 15 insertions(+), 5 deletions(-) + +diff --git a/common/usb_kbd.c b/common/usb_kbd.c +index afad260d3d..5408c821b4 100644 +--- a/common/usb_kbd.c ++++ b/common/usb_kbd.c +@@ -118,7 +118,7 @@ struct usb_kbd_pdata { + extern int __maybe_unused net_busy_flag; + + /* The period of time between two calls of usb_kbd_testc(). */ +-static unsigned long __maybe_unused kbd_testc_tms; ++static unsigned long kbd_testc_tms; + + /* Puts character in the queue and sets up the in and out pointer. */ + static void usb_kbd_put_queue(struct usb_kbd_pdata *data, u8 c) +@@ -394,21 +394,31 @@ static int usb_kbd_testc(struct stdio_dev *sdev) + struct usb_device *usb_kbd_dev; + struct usb_kbd_pdata *data; + ++ /* ++ * Polling the keyboard for an event can take dozens of milliseconds. ++ * Add a delay between polls to avoid blocking activity which polls ++ * rapidly, like the UEFI console timer. ++ */ ++ unsigned long poll_delay = CONFIG_SYS_HZ / 50; ++ + #ifdef CONFIG_CMD_NET + /* + * If net_busy_flag is 1, NET transfer is running, + * then we check key-pressed every second (first check may be + * less than 1 second) to improve TFTP booting performance. + */ +- if (net_busy_flag && (get_timer(kbd_testc_tms) < CONFIG_SYS_HZ)) +- return 0; +- kbd_testc_tms = get_timer(0); ++ if (net_busy_flag) ++ poll_delay = CONFIG_SYS_HZ; + #endif ++ + dev = stdio_get_by_name(sdev->name); + usb_kbd_dev = (struct usb_device *)dev->priv; + data = usb_kbd_dev->privptr; + +- usb_kbd_poll_for_event(usb_kbd_dev); ++ if (get_timer(kbd_testc_tms) >= poll_delay) { ++ usb_kbd_poll_for_event(usb_kbd_dev); ++ kbd_testc_tms = get_timer(0); ++ } + + return !(data->usb_in_pointer == data->usb_out_pointer); + } diff --git a/v3-phy-Track-power-on-and-init-counts-in-uclass.patch b/v3-phy-Track-power-on-and-init-counts-in-uclass.patch new file mode 100644 index 0000000..d6cc31d --- /dev/null +++ b/v3-phy-Track-power-on-and-init-counts-in-uclass.patch @@ -0,0 +1,556 @@ +From patchwork Thu Dec 30 19:36:51 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Alper Nebi Yasak +X-Patchwork-Id: 1574229 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: bilbo.ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 + header.s=20210112 header.b=cK81Bg2I; + dkim-atps=neutral +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest + SHA256) + (No client certificate requested) + by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JPz7X0bFyz9s0r + for ; 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+ Thu, 30 Dec 2021 11:37:11 -0800 (PST) +From: Alper Nebi Yasak +To: u-boot@lists.denx.de +Cc: Frank Wang , + Andre Przywara , Tom Rini , + Simon Glass , Neil Armstrong , + Grant Likely , + Joe Hershberger , + Peter Robinson , + Jagan Teki , + Patrick Delaunay , + Grant Likely , Icenowy Zheng , + Alper Nebi Yasak +Subject: [PATCH v3] phy: Track power-on and init counts in uclass +Date: Thu, 30 Dec 2021 22:36:51 +0300 +Message-Id: <20211230193652.33514-1-alpernebiyasak@gmail.com> +X-Mailer: git-send-email 2.34.1 +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.38 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de +X-Virus-Status: Clean + +On boards using the RK3399 SoC, the USB OHCI and EHCI controllers share +the same PHY device instance. While these controllers are being stopped +they both attempt to power-off and deinitialize it, but trying to +power-off the deinitialized PHY device results in a hang. This usually +happens just before booting an OS, and can be explicitly triggered by +running "usb start; usb stop" in the U-Boot shell. + +Implement a uclass-wide counting mechanism for PHY initialization and +power state change requests, so that we don't power-off/deinitialize a +PHY instance until all of its users want it done. The Allwinner A10 USB +PHY driver does this counting in-driver, remove those parts in favour of +this in-uclass implementation. + +The sandbox PHY operations test needs some changes since the uclass will +no longer call into the drivers for actions matching its tracked state +(e.g. powering-off a powered-off PHY). Update that test, and add a new +one which simulates multiple users of a single PHY. + +The major complication here is that PHY handles aren't deduplicated per +instance, so the obvious idea of putting the counts in the PHY handles +don't immediately work. It seems possible to bind a child udevice per +PHY instance to the PHY provider and deduplicate the handles in each +child's uclass-private areas, like in the CLK framework. An alternative +approach could be to use those bound child udevices themselves as the +PHY handles. Instead, to avoid the architectural changes those would +require, this patch solves things by dynamically allocating a list of +structs (one per instance) in the provider's uclass-private area. + +Signed-off-by: Alper Nebi Yasak +Reviewed-by: Simon Glass +--- + +Changes in v3: +- Add tag: "Reviewed-by: Simon Glass " +- Add comment for phy_counts struct + +v2: https://patchwork.ozlabs.org/project/uboot/patch/20211224130549.20276-1-alpernebiyasak@gmail.com/ + +Changes in v2: +- Rename {phy_,}id_priv -> {phy_,}counts +- Split phy_get_uclass_priv -> phy_{alloc,get}_counts +- Allocate counts (or return error) in generic_phy_get_by_*() +- Remove now-unnecessary null checks for counts of valid phy handles + +v1: https://patchwork.ozlabs.org/project/uboot/patch/20211210200124.19226-1-alpernebiyasak@gmail.com/ + + drivers/phy/allwinner/phy-sun4i-usb.c | 9 -- + drivers/phy/phy-uclass.c | 137 ++++++++++++++++++++++++++ + test/dm/phy.c | 83 +++++++++++++++- + 3 files changed, 215 insertions(+), 14 deletions(-) + +diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c +index ab2a5d17fcff..86c589a65fd3 100644 +--- a/drivers/phy/allwinner/phy-sun4i-usb.c ++++ b/drivers/phy/allwinner/phy-sun4i-usb.c +@@ -125,7 +125,6 @@ struct sun4i_usb_phy_info { + + struct sun4i_usb_phy_plat { + void __iomem *pmu; +- int power_on_count; + int gpio_vbus; + int gpio_vbus_det; + int gpio_id_det; +@@ -225,10 +224,6 @@ static int sun4i_usb_phy_power_on(struct phy *phy) + initial_usb_scan_delay = 0; + } + +- usb_phy->power_on_count++; +- if (usb_phy->power_on_count != 1) +- return 0; +- + if (usb_phy->gpio_vbus >= 0) + gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP); + +@@ -240,10 +235,6 @@ static int sun4i_usb_phy_power_off(struct phy *phy) + struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); + struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; + +- usb_phy->power_on_count--; +- if (usb_phy->power_on_count != 0) +- return 0; +- + if (usb_phy->gpio_vbus >= 0) + gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE); + +diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c +index 59683a080cd7..cec46c2c4103 100644 +--- a/drivers/phy/phy-uclass.c ++++ b/drivers/phy/phy-uclass.c +@@ -11,12 +11,96 @@ + #include + #include + #include ++#include ++ ++/** ++ * struct phy_counts - Init and power-on counts of a single PHY port ++ * ++ * This structure is used to keep track of PHY initialization and power ++ * state change requests, so that we don't power off and deinitialize a ++ * PHY instance until all of its users want it done. Otherwise, multiple ++ * consumers using the same PHY port can cause problems (e.g. one might ++ * call power_off() after another's exit() and hang indefinitely). ++ * ++ * @id: The PHY ID within a PHY provider ++ * @power_on_count: Times generic_phy_power_on() was called for this ID ++ * without a matching generic_phy_power_off() afterwards ++ * @init_count: Times generic_phy_init() was called for this ID ++ * without a matching generic_phy_exit() afterwards ++ * @list: Handle for a linked list of these structures corresponding to ++ * ports of the same PHY provider ++ */ ++struct phy_counts { ++ unsigned long id; ++ int power_on_count; ++ int init_count; ++ struct list_head list; ++}; + + static inline struct phy_ops *phy_dev_ops(struct udevice *dev) + { + return (struct phy_ops *)dev->driver->ops; + } + ++static struct phy_counts *phy_get_counts(struct phy *phy) ++{ ++ struct list_head *uc_priv; ++ struct phy_counts *counts; ++ ++ if (!generic_phy_valid(phy)) ++ return NULL; ++ ++ uc_priv = dev_get_uclass_priv(phy->dev); ++ list_for_each_entry(counts, uc_priv, list) ++ if (counts->id == phy->id) ++ return counts; ++ ++ return NULL; ++} ++ ++static int phy_alloc_counts(struct phy *phy) ++{ ++ struct list_head *uc_priv; ++ struct phy_counts *counts; ++ ++ if (!generic_phy_valid(phy)) ++ return 0; ++ if (phy_get_counts(phy)) ++ return 0; ++ ++ uc_priv = dev_get_uclass_priv(phy->dev); ++ counts = kzalloc(sizeof(*counts), GFP_KERNEL); ++ if (!counts) ++ return -ENOMEM; ++ ++ counts->id = phy->id; ++ counts->power_on_count = 0; ++ counts->init_count = 0; ++ list_add(&counts->list, uc_priv); ++ ++ return 0; ++} ++ ++static int phy_uclass_pre_probe(struct udevice *dev) ++{ ++ struct list_head *uc_priv = dev_get_uclass_priv(dev); ++ ++ INIT_LIST_HEAD(uc_priv); ++ ++ return 0; ++} ++ ++static int phy_uclass_pre_remove(struct udevice *dev) ++{ ++ struct list_head *uc_priv = dev_get_uclass_priv(dev); ++ struct phy_counts *counts, *next; ++ ++ list_for_each_entry_safe(counts, next, uc_priv, list) ++ kfree(counts); ++ ++ return 0; ++} ++ + static int generic_phy_xlate_offs_flags(struct phy *phy, + struct ofnode_phandle_args *args) + { +@@ -88,6 +172,12 @@ int generic_phy_get_by_index_nodev(ofnode node, int index, struct phy *phy) + goto err; + } + ++ ret = phy_alloc_counts(phy); ++ if (ret) { ++ debug("phy_alloc_counts() failed: %d\n", ret); ++ goto err; ++ } ++ + return 0; + + err: +@@ -118,6 +208,7 @@ int generic_phy_get_by_name(struct udevice *dev, const char *phy_name, + + int generic_phy_init(struct phy *phy) + { ++ struct phy_counts *counts; + struct phy_ops const *ops; + int ret; + +@@ -126,10 +217,19 @@ int generic_phy_init(struct phy *phy) + ops = phy_dev_ops(phy->dev); + if (!ops->init) + return 0; ++ ++ counts = phy_get_counts(phy); ++ if (counts->init_count > 0) { ++ counts->init_count++; ++ return 0; ++ } ++ + ret = ops->init(phy); + if (ret) + dev_err(phy->dev, "PHY: Failed to init %s: %d.\n", + phy->dev->name, ret); ++ else ++ counts->init_count = 1; + + return ret; + } +@@ -154,6 +254,7 @@ int generic_phy_reset(struct phy *phy) + + int generic_phy_exit(struct phy *phy) + { ++ struct phy_counts *counts; + struct phy_ops const *ops; + int ret; + +@@ -162,16 +263,28 @@ int generic_phy_exit(struct phy *phy) + ops = phy_dev_ops(phy->dev); + if (!ops->exit) + return 0; ++ ++ counts = phy_get_counts(phy); ++ if (counts->init_count == 0) ++ return 0; ++ if (counts->init_count > 1) { ++ counts->init_count--; ++ return 0; ++ } ++ + ret = ops->exit(phy); + if (ret) + dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n", + phy->dev->name, ret); ++ else ++ counts->init_count = 0; + + return ret; + } + + int generic_phy_power_on(struct phy *phy) + { ++ struct phy_counts *counts; + struct phy_ops const *ops; + int ret; + +@@ -180,16 +293,26 @@ int generic_phy_power_on(struct phy *phy) + ops = phy_dev_ops(phy->dev); + if (!ops->power_on) + return 0; ++ ++ counts = phy_get_counts(phy); ++ if (counts->power_on_count > 0) { ++ counts->power_on_count++; ++ return 0; ++ } ++ + ret = ops->power_on(phy); + if (ret) + dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n", + phy->dev->name, ret); ++ else ++ counts->power_on_count = 1; + + return ret; + } + + int generic_phy_power_off(struct phy *phy) + { ++ struct phy_counts *counts; + struct phy_ops const *ops; + int ret; + +@@ -198,10 +321,21 @@ int generic_phy_power_off(struct phy *phy) + ops = phy_dev_ops(phy->dev); + if (!ops->power_off) + return 0; ++ ++ counts = phy_get_counts(phy); ++ if (counts->power_on_count == 0) ++ return 0; ++ if (counts->power_on_count > 1) { ++ counts->power_on_count--; ++ return 0; ++ } ++ + ret = ops->power_off(phy); + if (ret) + dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n", + phy->dev->name, ret); ++ else ++ counts->power_on_count = 0; + + return ret; + } +@@ -316,4 +450,7 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk) + UCLASS_DRIVER(phy) = { + .id = UCLASS_PHY, + .name = "phy", ++ .pre_probe = phy_uclass_pre_probe, ++ .pre_remove = phy_uclass_pre_remove, ++ .per_device_auto = sizeof(struct list_head), + }; +diff --git a/test/dm/phy.c b/test/dm/phy.c +index ecbd47bf12fd..df4c73fc701f 100644 +--- a/test/dm/phy.c ++++ b/test/dm/phy.c +@@ -79,12 +79,15 @@ static int dm_test_phy_ops(struct unit_test_state *uts) + ut_assertok(generic_phy_power_off(&phy1)); + + /* +- * test operations after exit(). +- * The sandbox phy driver does not allow it. ++ * Test power_on() failure after exit(). ++ * The sandbox phy driver does not allow power-on/off after ++ * exit, but the uclass counts power-on/init calls and skips ++ * calling the driver's ops when e.g. powering off an already ++ * powered-off phy. + */ + ut_assertok(generic_phy_exit(&phy1)); + ut_assert(generic_phy_power_on(&phy1) != 0); +- ut_assert(generic_phy_power_off(&phy1) != 0); ++ ut_assertok(generic_phy_power_off(&phy1)); + + /* + * test normal operations again (after re-init) +@@ -99,6 +102,17 @@ static int dm_test_phy_ops(struct unit_test_state *uts) + */ + ut_assertok(generic_phy_reset(&phy1)); + ++ /* ++ * Test power_off() failure after exit(). ++ * For this we need to call exit() while the phy is powered-on, ++ * so that the uclass actually calls the driver's power-off() ++ * and reports the resulting failure. ++ */ ++ ut_assertok(generic_phy_power_on(&phy1)); ++ ut_assertok(generic_phy_exit(&phy1)); ++ ut_assert(generic_phy_power_off(&phy1) != 0); ++ ut_assertok(generic_phy_power_on(&phy1)); ++ + /* PHY2 has a known problem with power off */ + ut_assertok(generic_phy_init(&phy2)); + ut_assertok(generic_phy_power_on(&phy2)); +@@ -106,8 +120,8 @@ static int dm_test_phy_ops(struct unit_test_state *uts) + + /* PHY3 has a known problem with power off and power on */ + ut_assertok(generic_phy_init(&phy3)); +- ut_asserteq(-EIO, generic_phy_power_off(&phy3)); +- ut_asserteq(-EIO, generic_phy_power_off(&phy3)); ++ ut_asserteq(-EIO, generic_phy_power_on(&phy3)); ++ ut_assertok(generic_phy_power_off(&phy3)); + + return 0; + } +@@ -145,3 +159,62 @@ static int dm_test_phy_bulk(struct unit_test_state *uts) + return 0; + } + DM_TEST(dm_test_phy_bulk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); ++ ++static int dm_test_phy_multi_exit(struct unit_test_state *uts) ++{ ++ struct phy phy1_method1; ++ struct phy phy1_method2; ++ struct phy phy1_method3; ++ struct udevice *parent; ++ ++ /* Get the same phy instance in 3 different ways. */ ++ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, ++ "gen_phy_user", &parent)); ++ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method1)); ++ ut_asserteq(0, phy1_method1.id); ++ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method2)); ++ ut_asserteq(0, phy1_method2.id); ++ ut_asserteq_ptr(phy1_method1.dev, phy1_method1.dev); ++ ++ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, ++ "gen_phy_user1", &parent)); ++ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method3)); ++ ut_asserteq(0, phy1_method3.id); ++ ut_asserteq_ptr(phy1_method1.dev, phy1_method3.dev); ++ ++ /* ++ * Test using the same PHY from different handles. ++ * In non-test code these could be in different drivers. ++ */ ++ ++ /* ++ * These must only call the driver's ops at the first init() ++ * and power_on(). ++ */ ++ ut_assertok(generic_phy_init(&phy1_method1)); ++ ut_assertok(generic_phy_init(&phy1_method2)); ++ ut_assertok(generic_phy_power_on(&phy1_method1)); ++ ut_assertok(generic_phy_power_on(&phy1_method2)); ++ ut_assertok(generic_phy_init(&phy1_method3)); ++ ut_assertok(generic_phy_power_on(&phy1_method3)); ++ ++ /* ++ * These must not call the driver's ops as other handles still ++ * want the PHY powered-on and initialized. ++ */ ++ ut_assertok(generic_phy_power_off(&phy1_method3)); ++ ut_assertok(generic_phy_exit(&phy1_method3)); ++ ++ /* ++ * We would get an error here if the generic_phy_exit() above ++ * actually called the driver's exit(), as the sandbox driver ++ * doesn't allow power-off() after exit(). ++ */ ++ ut_assertok(generic_phy_power_off(&phy1_method1)); ++ ut_assertok(generic_phy_power_off(&phy1_method2)); ++ ut_assertok(generic_phy_exit(&phy1_method1)); ++ ut_assertok(generic_phy_exit(&phy1_method2)); ++ ++ return 0; ++} ++DM_TEST(dm_test_phy_multi_exit, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); From cc4e21b64cc58ab75818fba7cb84051d7122e084 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 11 Jan 2022 10:04:15 +0000 Subject: [PATCH 09/28] 2022.01 --- ...to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch | 244 ++++++++++++++++++ uboot-tools.spec | 8 +- 2 files changed, 250 insertions(+), 2 deletions(-) create mode 100644 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch diff --git a/0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch b/0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch new file mode 100644 index 0000000..0f762d9 --- /dev/null +++ b/0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch @@ -0,0 +1,244 @@ +From 53f3d6e9219a36f375e27150b8ec1088624f1aa0 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 21 Dec 2021 17:25:35 +0000 +Subject: [PATCH] udoo_neo: Move to DM for REGUALTOR/PMIC/I2C drivers + +This moves over the PMIC power init to DM and the associated i2c and +regulator bits. + +Signed-off-by: Peter Robinson +--- + board/udoo/neo/neo.c | 139 +++---------------------------------- + configs/udoo_neo_defconfig | 10 +-- + include/configs/udoo_neo.h | 5 -- + 3 files changed, 15 insertions(+), 139 deletions(-) + +diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c +index 5e40583ab4..9e2a66996c 100644 +--- a/board/udoo/neo/neo.c ++++ b/board/udoo/neo/neo.c +@@ -51,11 +51,6 @@ enum { + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ +- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ +- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ +- PAD_CTL_ODE) +- + #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +@@ -83,135 +78,25 @@ int dram_init(void) + return 0; + } + +-#ifdef CONFIG_SYS_I2C_MXC +-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +-/* I2C1 for PMIC */ +-static struct i2c_pads_info i2c_pad_info1 = { +- .scl = { +- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, +- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, +- .gp = IMX_GPIO_NR(1, 0), +- }, +- .sda = { +- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, +- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, +- .gp = IMX_GPIO_NR(1, 1), +- }, +-}; +-#endif +- +-#if CONFIG_IS_ENABLED(POWER_LEGACY) + int power_init_board(void) + { +- struct pmic *p; +- int ret; +- unsigned int reg, rev_id; +- +- ret = power_pfuze3000_init(PFUZE3000_I2C_BUS); +- if (ret) +- return ret; +- +- p = pmic_get("PFUZE3000"); +- ret = pmic_probe(p); +- if (ret) +- return ret; ++ struct udevice *dev; ++ int ret, dev_id, rev_id; + +- pmic_reg_read(p, PFUZE3000_DEVICEID, ®); +- pmic_reg_read(p, PFUZE3000_REVID, &rev_id); +- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); +- +- /* disable Low Power Mode during standby mode */ +- pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); +- reg |= 0x1; +- ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); +- if (ret) ++ ret = pmic_get("pfuze3000@8", &dev); ++ if (ret == -ENODEV) ++ return 0; ++ if (ret != 0) + return ret; + +- ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc); +- if (ret) +- return ret; ++ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); ++ rev_id = pmic_reg_read(dev, PFUZE3000_REVID); ++ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + +- ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc); +- if (ret) +- return ret; +- +- ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc); +- if (ret) +- return ret; +- +- ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc); +- if (ret) +- return ret; +- +- /* set SW1A standby voltage 0.975V */ +- pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®); +- reg &= ~0x3f; +- reg |= PFUZE3000_SW1AB_SETP(9750); +- ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); +- if (ret) +- return ret; +- +- /* set SW1B standby voltage 0.975V */ +- pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®); +- reg &= ~0x3f; +- reg |= PFUZE3000_SW1AB_SETP(9750); +- ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); +- if (ret) +- return ret; +- +- /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */ +- pmic_reg_read(p, PFUZE3000_SW1ACONF, ®); +- reg &= ~0xc0; +- reg |= 0x40; +- ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg); +- if (ret) +- return ret; +- +- /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */ +- pmic_reg_read(p, PFUZE3000_SW1BCONF, ®); +- reg &= ~0xc0; +- reg |= 0x40; +- ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg); +- if (ret) +- return ret; +- +- /* set VDD_ARM_IN to 1.350V */ +- pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®); +- reg &= ~0x3f; +- reg |= PFUZE3000_SW1AB_SETP(13500); +- ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg); +- if (ret) +- return ret; +- +- /* set VDD_SOC_IN to 1.350V */ +- pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); +- reg &= ~0x3f; +- reg |= PFUZE3000_SW1AB_SETP(13500); +- ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); +- if (ret) +- return ret; +- +- /* set DDR_1_5V to 1.350V */ +- pmic_reg_read(p, PFUZE3000_SW3VOLT, ®); +- reg &= ~0x0f; +- reg |= PFUZE3000_SW3_SETP(13500); +- ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg); +- if (ret) +- return ret; +- +- /* set VGEN2_1V5 to 1.5V */ +- pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®); +- reg &= ~0x0f; +- reg |= PFUZE3000_VLDO_SETP(15000); +- /* enable */ +- reg |= 0x10; +- ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg); +- if (ret) +- return ret; ++ pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + + return 0; + } +-#endif + + static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +@@ -294,10 +179,6 @@ int board_init(void) + gpio_request(IMX_GPIO_NR(4, 16), "ncp692"); + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + +-#ifdef CONFIG_SYS_I2C_MXC +- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +-#endif +- + setup_fec(); + + return 0; +diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig +index ca08de1bd4..9177bdba65 100644 +--- a/configs/udoo_neo_defconfig ++++ b/configs/udoo_neo_defconfig +@@ -10,8 +10,9 @@ CONFIG_ENV_SIZE=0x2000 + CONFIG_ENV_OFFSET=0x80000 + CONFIG_MX6SX=y + CONFIG_TARGET_UDOO_NEO=y +-CONFIG_SYS_I2C_MXC_I2C1=y ++CONFIG_DM_I2C=y + CONFIG_DM_GPIO=y ++CONFIG_DM_MMC=y + CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic" + CONFIG_SPL_TEXT_BASE=0x00908000 + CONFIG_SPL_MMC=y +@@ -39,8 +40,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SYS_MMC_ENV_DEV=1 + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_BOUNCE_BUFFER=y +-CONFIG_SYS_I2C_LEGACY=y +-CONFIG_SPL_SYS_I2C_LEGACY=y + CONFIG_SYS_I2C_MXC=y + CONFIG_FSL_USDHC=y + CONFIG_PHYLIB=y +@@ -52,11 +51,12 @@ CONFIG_FEC_MXC=y + CONFIG_MII=y + CONFIG_PINCTRL=y + CONFIG_PINCTRL_IMX6=y +-CONFIG_POWER_LEGACY=y +-CONFIG_POWER_I2C=y ++CONFIG_DM_PMIC=y ++CONFIG_DM_PMIC_PFUZE100=y + CONFIG_DM_REGULATOR=y + CONFIG_DM_REGULATOR_ANATOP=y + CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_PFUZE100=y + CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_STORAGE=y +diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h +index 3a7cb050b1..ac13c3e57f 100644 +--- a/include/configs/udoo_neo.h ++++ b/include/configs/udoo_neo.h +@@ -68,9 +68,4 @@ + #define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +-/* PMIC */ +-#define CONFIG_POWER_PFUZE3000 +-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +-#define PFUZE3000_I2C_BUS 0 +- + #endif /* __CONFIG_H */ +-- +2.34.1 + diff --git a/uboot-tools.spec b/uboot-tools.spec index 92d15ee..9bf773b 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc4 +#global candidate rc4 Name: uboot-tools Version: 2022.01 -Release: 0.3%{?candidate:.%{candidate}}%{?dist} +Release: 1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -26,6 +26,7 @@ Patch5: rpi-bcm2835_sdhost-firmware-managed-clock.patch Patch6: v3-phy-Track-power-on-and-init-counts-in-uclass.patch Patch7: dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch Patch8: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch +Patch9: 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch BuildRequires: bc BuildRequires: dtc @@ -251,6 +252,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Mon Jan 10 2022 Peter Robinson - 2022.01-1 +- Update to 2022.01 + * Wed Jan 05 2022 Peter Robinson - 2022.01-0.3.rc4 - Upstream fixes for PHY and UEFI From c1b0bbe3612ec6e8fd38b805ec0eb9c1e5cbefad Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 11 Jan 2022 10:11:22 +0000 Subject: [PATCH 10/28] Upload source --- sources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sources b/sources index b98988f..d632a51 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.01-rc4.tar.bz2) = 2b07f52794056926125ca0327999c06939c19c9bbcfa2b3ea6809a2298adee1323f22f142aed57297be07541662f1d909af23393f78d7718ff6963d0552119b7 +SHA512 (u-boot-2022.01.tar.bz2) = d83c62bd8f0f51664d2aca329a3ce1379cfd1dfff439dccd6cfc2cb33cfef89a2b01855c97716f591b5550bfdf99e2f3aef7efa33f2e7834c820648f9eef3825 From b27a96095d4528e556dc251c7a196d9936f48123 Mon Sep 17 00:00:00 2001 From: Fedora Release Engineering Date: Sat, 22 Jan 2022 03:22:08 +0000 Subject: [PATCH 11/28] - Rebuilt for https://fedoraproject.org/wiki/Fedora_36_Mass_Rebuild Signed-off-by: Fedora Release Engineering --- uboot-tools.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 9bf773b..fffbf72 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2022.01 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 2%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -252,6 +252,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Sat Jan 22 2022 Fedora Release Engineering - 2022.01-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_36_Mass_Rebuild + * Mon Jan 10 2022 Peter Robinson - 2022.01-1 - Update to 2022.01 From 18e07ba9f6f80abd4ed2fe126836bcda8171371f Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 2 Feb 2022 23:04:35 +0000 Subject: [PATCH 12/28] 2022.04 RC1 --- ...kchip-rk3399-enable-emmc-phy-for-spl.patch | 115 ---- sources | 2 +- uboot-tools.spec | 13 +- ...k-power-on-and-init-counts-in-uclass.patch | 556 ------------------ 4 files changed, 8 insertions(+), 678 deletions(-) delete mode 100644 dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch delete mode 100644 v3-phy-Track-power-on-and-init-counts-in-uclass.patch diff --git a/dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch b/dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch deleted file mode 100644 index 3ef5b53..0000000 --- a/dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch +++ /dev/null @@ -1,115 +0,0 @@ -From patchwork Mon Nov 1 04:43:47 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Yifeng Zhao -X-Patchwork-Id: 1548950 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 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-X-SENDER-IP: 58.22.7.114 -X-ATTACHMENT-NUM: 0 -X-UNIQUE-TAG: <8beb59827f65d556787d36e0068aa9cb> -X-System-Flag: 0 -From: Yifeng Zhao -To: Kever Yang -Cc: sjg , Peter Robinson , - Philipp Tomsich , - u-boot@lists.denx.de, Jack Mitchell , - Yifeng Zhao -Subject: [PATCH] dts: rockchip: rk3399: enable emmc phy for spl -Date: Mon, 1 Nov 2021 12:43:47 +0800 -Message-Id: <20211101044347.17822-1-yifeng.zhao@rock-chips.com> -X-Mailer: git-send-email 2.17.1 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de -X-Virus-Status: Clean - -adapting commit ac804143cf ("mmc: rockchip_sdhci: add phy and clock -config for rk3399") to fix the issue "Not found emmc phy device". - -Signed-off-by: Yifeng Zhao ---- - - arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi -index 73922c328a..716b9a433a 100644 ---- a/arch/arm/dts/rk3399-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-u-boot.dtsi -@@ -88,6 +88,10 @@ - u-boot,dm-pre-reloc; - }; - -+&emmc_phy { -+ u-boot,dm-pre-reloc; -+}; -+ - &grf { - u-boot,dm-pre-reloc; - }; diff --git a/sources b/sources index d632a51..870dc09 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.01.tar.bz2) = d83c62bd8f0f51664d2aca329a3ce1379cfd1dfff439dccd6cfc2cb33cfef89a2b01855c97716f591b5550bfdf99e2f3aef7efa33f2e7834c820648f9eef3825 +SHA512 (u-boot-2022.04-rc1.tar.bz2) = 95421d9ed69f46b727e9bbe53f8ecbd66a6779512c97342b02eb440adac175e6abeebbf5664f256397518e39602b9eee70a2b66ca21c2f13a3331bab755b9735 diff --git a/uboot-tools.spec b/uboot-tools.spec index fffbf72..0185254 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -#global candidate rc4 +%global candidate rc1 Name: uboot-tools -Version: 2022.01 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Version: 2022.04 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -23,10 +23,8 @@ Patch3: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch4: rpi-fallback-to-max-clock-for-mmc.patch Patch5: rpi-bcm2835_sdhost-firmware-managed-clock.patch # Rockchips improvements -Patch6: v3-phy-Track-power-on-and-init-counts-in-uclass.patch -Patch7: dts-rockchip-rk3399-enable-emmc-phy-for-spl.patch Patch8: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch -Patch9: 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch +# Patch9: 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch BuildRequires: bc BuildRequires: dtc @@ -252,6 +250,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Wed Feb 02 2022 Peter Robinson - 2022.04-0.1.rc1 +- Update to 2022.04 RC1 + * Sat Jan 22 2022 Fedora Release Engineering - 2022.01-2 - Rebuilt for https://fedoraproject.org/wiki/Fedora_36_Mass_Rebuild diff --git a/v3-phy-Track-power-on-and-init-counts-in-uclass.patch b/v3-phy-Track-power-on-and-init-counts-in-uclass.patch deleted file mode 100644 index d6cc31d..0000000 --- a/v3-phy-Track-power-on-and-init-counts-in-uclass.patch +++ /dev/null @@ -1,556 +0,0 @@ -From patchwork Thu Dec 30 19:36:51 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Alper Nebi Yasak -X-Patchwork-Id: 1574229 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: bilbo.ozlabs.org; - dkim=pass (2048-bit key; - unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 - header.s=20210112 header.b=cK81Bg2I; - dkim-atps=neutral -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) 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Patrick Delaunay , - Grant Likely , Icenowy Zheng , - Alper Nebi Yasak -Subject: [PATCH v3] phy: Track power-on and init counts in uclass -Date: Thu, 30 Dec 2021 22:36:51 +0300 -Message-Id: <20211230193652.33514-1-alpernebiyasak@gmail.com> -X-Mailer: git-send-email 2.34.1 -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.38 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de -X-Virus-Status: Clean - -On boards using the RK3399 SoC, the USB OHCI and EHCI controllers share -the same PHY device instance. While these controllers are being stopped -they both attempt to power-off and deinitialize it, but trying to -power-off the deinitialized PHY device results in a hang. This usually -happens just before booting an OS, and can be explicitly triggered by -running "usb start; usb stop" in the U-Boot shell. - -Implement a uclass-wide counting mechanism for PHY initialization and -power state change requests, so that we don't power-off/deinitialize a -PHY instance until all of its users want it done. The Allwinner A10 USB -PHY driver does this counting in-driver, remove those parts in favour of -this in-uclass implementation. - -The sandbox PHY operations test needs some changes since the uclass will -no longer call into the drivers for actions matching its tracked state -(e.g. powering-off a powered-off PHY). Update that test, and add a new -one which simulates multiple users of a single PHY. - -The major complication here is that PHY handles aren't deduplicated per -instance, so the obvious idea of putting the counts in the PHY handles -don't immediately work. It seems possible to bind a child udevice per -PHY instance to the PHY provider and deduplicate the handles in each -child's uclass-private areas, like in the CLK framework. An alternative -approach could be to use those bound child udevices themselves as the -PHY handles. Instead, to avoid the architectural changes those would -require, this patch solves things by dynamically allocating a list of -structs (one per instance) in the provider's uclass-private area. - -Signed-off-by: Alper Nebi Yasak -Reviewed-by: Simon Glass ---- - -Changes in v3: -- Add tag: "Reviewed-by: Simon Glass " -- Add comment for phy_counts struct - -v2: https://patchwork.ozlabs.org/project/uboot/patch/20211224130549.20276-1-alpernebiyasak@gmail.com/ - -Changes in v2: -- Rename {phy_,}id_priv -> {phy_,}counts -- Split phy_get_uclass_priv -> phy_{alloc,get}_counts -- Allocate counts (or return error) in generic_phy_get_by_*() -- Remove now-unnecessary null checks for counts of valid phy handles - -v1: https://patchwork.ozlabs.org/project/uboot/patch/20211210200124.19226-1-alpernebiyasak@gmail.com/ - - drivers/phy/allwinner/phy-sun4i-usb.c | 9 -- - drivers/phy/phy-uclass.c | 137 ++++++++++++++++++++++++++ - test/dm/phy.c | 83 +++++++++++++++- - 3 files changed, 215 insertions(+), 14 deletions(-) - -diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c -index ab2a5d17fcff..86c589a65fd3 100644 ---- a/drivers/phy/allwinner/phy-sun4i-usb.c -+++ b/drivers/phy/allwinner/phy-sun4i-usb.c -@@ -125,7 +125,6 @@ struct sun4i_usb_phy_info { - - struct sun4i_usb_phy_plat { - void __iomem *pmu; -- int power_on_count; - int gpio_vbus; - int gpio_vbus_det; - int gpio_id_det; -@@ -225,10 +224,6 @@ static int sun4i_usb_phy_power_on(struct phy *phy) - initial_usb_scan_delay = 0; - } - -- usb_phy->power_on_count++; -- if (usb_phy->power_on_count != 1) -- return 0; -- - if (usb_phy->gpio_vbus >= 0) - gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP); - -@@ -240,10 +235,6 @@ static int sun4i_usb_phy_power_off(struct phy *phy) - struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); - struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; - -- usb_phy->power_on_count--; -- if (usb_phy->power_on_count != 0) -- return 0; -- - if (usb_phy->gpio_vbus >= 0) - gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE); - -diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c -index 59683a080cd7..cec46c2c4103 100644 ---- a/drivers/phy/phy-uclass.c -+++ b/drivers/phy/phy-uclass.c -@@ -11,12 +11,96 @@ - #include - #include - #include -+#include -+ -+/** -+ * struct phy_counts - Init and power-on counts of a single PHY port -+ * -+ * This structure is used to keep track of PHY initialization and power -+ * state change requests, so that we don't power off and deinitialize a -+ * PHY instance until all of its users want it done. Otherwise, multiple -+ * consumers using the same PHY port can cause problems (e.g. one might -+ * call power_off() after another's exit() and hang indefinitely). -+ * -+ * @id: The PHY ID within a PHY provider -+ * @power_on_count: Times generic_phy_power_on() was called for this ID -+ * without a matching generic_phy_power_off() afterwards -+ * @init_count: Times generic_phy_init() was called for this ID -+ * without a matching generic_phy_exit() afterwards -+ * @list: Handle for a linked list of these structures corresponding to -+ * ports of the same PHY provider -+ */ -+struct phy_counts { -+ unsigned long id; -+ int power_on_count; -+ int init_count; -+ struct list_head list; -+}; - - static inline struct phy_ops *phy_dev_ops(struct udevice *dev) - { - return (struct phy_ops *)dev->driver->ops; - } - -+static struct phy_counts *phy_get_counts(struct phy *phy) -+{ -+ struct list_head *uc_priv; -+ struct phy_counts *counts; -+ -+ if (!generic_phy_valid(phy)) -+ return NULL; -+ -+ uc_priv = dev_get_uclass_priv(phy->dev); -+ list_for_each_entry(counts, uc_priv, list) -+ if (counts->id == phy->id) -+ return counts; -+ -+ return NULL; -+} -+ -+static int phy_alloc_counts(struct phy *phy) -+{ -+ struct list_head *uc_priv; -+ struct phy_counts *counts; -+ -+ if (!generic_phy_valid(phy)) -+ return 0; -+ if (phy_get_counts(phy)) -+ return 0; -+ -+ uc_priv = dev_get_uclass_priv(phy->dev); -+ counts = kzalloc(sizeof(*counts), GFP_KERNEL); -+ if (!counts) -+ return -ENOMEM; -+ -+ counts->id = phy->id; -+ counts->power_on_count = 0; -+ counts->init_count = 0; -+ list_add(&counts->list, uc_priv); -+ -+ return 0; -+} -+ -+static int phy_uclass_pre_probe(struct udevice *dev) -+{ -+ struct list_head *uc_priv = dev_get_uclass_priv(dev); -+ -+ INIT_LIST_HEAD(uc_priv); -+ -+ return 0; -+} -+ -+static int phy_uclass_pre_remove(struct udevice *dev) -+{ -+ struct list_head *uc_priv = dev_get_uclass_priv(dev); -+ struct phy_counts *counts, *next; -+ -+ list_for_each_entry_safe(counts, next, uc_priv, list) -+ kfree(counts); -+ -+ return 0; -+} -+ - static int generic_phy_xlate_offs_flags(struct phy *phy, - struct ofnode_phandle_args *args) - { -@@ -88,6 +172,12 @@ int generic_phy_get_by_index_nodev(ofnode node, int index, struct phy *phy) - goto err; - } - -+ ret = phy_alloc_counts(phy); -+ if (ret) { -+ debug("phy_alloc_counts() failed: %d\n", ret); -+ goto err; -+ } -+ - return 0; - - err: -@@ -118,6 +208,7 @@ int generic_phy_get_by_name(struct udevice *dev, const char *phy_name, - - int generic_phy_init(struct phy *phy) - { -+ struct phy_counts *counts; - struct phy_ops const *ops; - int ret; - -@@ -126,10 +217,19 @@ int generic_phy_init(struct phy *phy) - ops = phy_dev_ops(phy->dev); - if (!ops->init) - return 0; -+ -+ counts = phy_get_counts(phy); -+ if (counts->init_count > 0) { -+ counts->init_count++; -+ return 0; -+ } -+ - ret = ops->init(phy); - if (ret) - dev_err(phy->dev, "PHY: Failed to init %s: %d.\n", - phy->dev->name, ret); -+ else -+ counts->init_count = 1; - - return ret; - } -@@ -154,6 +254,7 @@ int generic_phy_reset(struct phy *phy) - - int generic_phy_exit(struct phy *phy) - { -+ struct phy_counts *counts; - struct phy_ops const *ops; - int ret; - -@@ -162,16 +263,28 @@ int generic_phy_exit(struct phy *phy) - ops = phy_dev_ops(phy->dev); - if (!ops->exit) - return 0; -+ -+ counts = phy_get_counts(phy); -+ if (counts->init_count == 0) -+ return 0; -+ if (counts->init_count > 1) { -+ counts->init_count--; -+ return 0; -+ } -+ - ret = ops->exit(phy); - if (ret) - dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n", - phy->dev->name, ret); -+ else -+ counts->init_count = 0; - - return ret; - } - - int generic_phy_power_on(struct phy *phy) - { -+ struct phy_counts *counts; - struct phy_ops const *ops; - int ret; - -@@ -180,16 +293,26 @@ int generic_phy_power_on(struct phy *phy) - ops = phy_dev_ops(phy->dev); - if (!ops->power_on) - return 0; -+ -+ counts = phy_get_counts(phy); -+ if (counts->power_on_count > 0) { -+ counts->power_on_count++; -+ return 0; -+ } -+ - ret = ops->power_on(phy); - if (ret) - dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n", - phy->dev->name, ret); -+ else -+ counts->power_on_count = 1; - - return ret; - } - - int generic_phy_power_off(struct phy *phy) - { -+ struct phy_counts *counts; - struct phy_ops const *ops; - int ret; - -@@ -198,10 +321,21 @@ int generic_phy_power_off(struct phy *phy) - ops = phy_dev_ops(phy->dev); - if (!ops->power_off) - return 0; -+ -+ counts = phy_get_counts(phy); -+ if (counts->power_on_count == 0) -+ return 0; -+ if (counts->power_on_count > 1) { -+ counts->power_on_count--; -+ return 0; -+ } -+ - ret = ops->power_off(phy); - if (ret) - dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n", - phy->dev->name, ret); -+ else -+ counts->power_on_count = 0; - - return ret; - } -@@ -316,4 +450,7 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk) - UCLASS_DRIVER(phy) = { - .id = UCLASS_PHY, - .name = "phy", -+ .pre_probe = phy_uclass_pre_probe, -+ .pre_remove = phy_uclass_pre_remove, -+ .per_device_auto = sizeof(struct list_head), - }; -diff --git a/test/dm/phy.c b/test/dm/phy.c -index ecbd47bf12fd..df4c73fc701f 100644 ---- a/test/dm/phy.c -+++ b/test/dm/phy.c -@@ -79,12 +79,15 @@ static int dm_test_phy_ops(struct unit_test_state *uts) - ut_assertok(generic_phy_power_off(&phy1)); - - /* -- * test operations after exit(). -- * The sandbox phy driver does not allow it. -+ * Test power_on() failure after exit(). -+ * The sandbox phy driver does not allow power-on/off after -+ * exit, but the uclass counts power-on/init calls and skips -+ * calling the driver's ops when e.g. powering off an already -+ * powered-off phy. - */ - ut_assertok(generic_phy_exit(&phy1)); - ut_assert(generic_phy_power_on(&phy1) != 0); -- ut_assert(generic_phy_power_off(&phy1) != 0); -+ ut_assertok(generic_phy_power_off(&phy1)); - - /* - * test normal operations again (after re-init) -@@ -99,6 +102,17 @@ static int dm_test_phy_ops(struct unit_test_state *uts) - */ - ut_assertok(generic_phy_reset(&phy1)); - -+ /* -+ * Test power_off() failure after exit(). -+ * For this we need to call exit() while the phy is powered-on, -+ * so that the uclass actually calls the driver's power-off() -+ * and reports the resulting failure. -+ */ -+ ut_assertok(generic_phy_power_on(&phy1)); -+ ut_assertok(generic_phy_exit(&phy1)); -+ ut_assert(generic_phy_power_off(&phy1) != 0); -+ ut_assertok(generic_phy_power_on(&phy1)); -+ - /* PHY2 has a known problem with power off */ - ut_assertok(generic_phy_init(&phy2)); - ut_assertok(generic_phy_power_on(&phy2)); -@@ -106,8 +120,8 @@ static int dm_test_phy_ops(struct unit_test_state *uts) - - /* PHY3 has a known problem with power off and power on */ - ut_assertok(generic_phy_init(&phy3)); -- ut_asserteq(-EIO, generic_phy_power_off(&phy3)); -- ut_asserteq(-EIO, generic_phy_power_off(&phy3)); -+ ut_asserteq(-EIO, generic_phy_power_on(&phy3)); -+ ut_assertok(generic_phy_power_off(&phy3)); - - return 0; - } -@@ -145,3 +159,62 @@ static int dm_test_phy_bulk(struct unit_test_state *uts) - return 0; - } - DM_TEST(dm_test_phy_bulk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); -+ -+static int dm_test_phy_multi_exit(struct unit_test_state *uts) -+{ -+ struct phy phy1_method1; -+ struct phy phy1_method2; -+ struct phy phy1_method3; -+ struct udevice *parent; -+ -+ /* Get the same phy instance in 3 different ways. */ -+ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, -+ "gen_phy_user", &parent)); -+ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method1)); -+ ut_asserteq(0, phy1_method1.id); -+ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method2)); -+ ut_asserteq(0, phy1_method2.id); -+ ut_asserteq_ptr(phy1_method1.dev, phy1_method1.dev); -+ -+ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, -+ "gen_phy_user1", &parent)); -+ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method3)); -+ ut_asserteq(0, phy1_method3.id); -+ ut_asserteq_ptr(phy1_method1.dev, phy1_method3.dev); -+ -+ /* -+ * Test using the same PHY from different handles. -+ * In non-test code these could be in different drivers. -+ */ -+ -+ /* -+ * These must only call the driver's ops at the first init() -+ * and power_on(). -+ */ -+ ut_assertok(generic_phy_init(&phy1_method1)); -+ ut_assertok(generic_phy_init(&phy1_method2)); -+ ut_assertok(generic_phy_power_on(&phy1_method1)); -+ ut_assertok(generic_phy_power_on(&phy1_method2)); -+ ut_assertok(generic_phy_init(&phy1_method3)); -+ ut_assertok(generic_phy_power_on(&phy1_method3)); -+ -+ /* -+ * These must not call the driver's ops as other handles still -+ * want the PHY powered-on and initialized. -+ */ -+ ut_assertok(generic_phy_power_off(&phy1_method3)); -+ ut_assertok(generic_phy_exit(&phy1_method3)); -+ -+ /* -+ * We would get an error here if the generic_phy_exit() above -+ * actually called the driver's exit(), as the sandbox driver -+ * doesn't allow power-off() after exit(). -+ */ -+ ut_assertok(generic_phy_power_off(&phy1_method1)); -+ ut_assertok(generic_phy_power_off(&phy1_method2)); -+ ut_assertok(generic_phy_exit(&phy1_method1)); -+ ut_assertok(generic_phy_exit(&phy1_method2)); -+ -+ return 0; -+} -+DM_TEST(dm_test_phy_multi_exit, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); From 93f0ff8c4feb17229dc4e47f61a3aa4224bb3ec0 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 15 Feb 2022 16:48:19 +0000 Subject: [PATCH 13/28] 2022.04 RC2 --- aarch64-boards | 1 + sources | 2 +- uboot-tools.spec | 8 +- ...oll-frequency-to-improve-performance.patch | 178 ------------------ 4 files changed, 7 insertions(+), 182 deletions(-) delete mode 100644 v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch diff --git a/aarch64-boards b/aarch64-boards index 50427ad..de5f479 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -76,6 +76,7 @@ roc-pc-rk3399 rpi_3 rpi_4 rpi_arm64 +starqltechn sopine_baseboard tanix_tx6 teres_i diff --git a/sources b/sources index 870dc09..6267dad 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.04-rc1.tar.bz2) = 95421d9ed69f46b727e9bbe53f8ecbd66a6779512c97342b02eb440adac175e6abeebbf5664f256397518e39602b9eee70a2b66ca21c2f13a3331bab755b9735 +SHA512 (u-boot-2022.04-rc2.tar.bz2) = 34af2d91a86e6864615ab09a2da7ec752beb56808d9eea652d425476cd1bbdf84d4e5f98740254f7cd91a04f11712d073450e74f4e07ae4180d845cb38620ee3 diff --git a/uboot-tools.spec b/uboot-tools.spec index 0185254..e04730a 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc1 +%global candidate rc2 Name: uboot-tools Version: 2022.04 -Release: 0.1%{?candidate:.%{candidate}}%{?dist} +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -17,7 +17,6 @@ Source2: aarch64-boards Patch1: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch # Board fixes and enablement -Patch2: v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch # RPi - uses RPI firmware device tree for HAT support Patch3: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch4: rpi-fallback-to-max-clock-for-mmc.patch @@ -250,6 +249,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Tue Feb 15 2022 Peter Robinson - 2022.04-0.2.rc2 +- Update to 2022.04 RC2 + * Wed Feb 02 2022 Peter Robinson - 2022.04-0.1.rc1 - Update to 2022.04 RC1 diff --git a/v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch b/v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch deleted file mode 100644 index 5eb366c..0000000 --- a/v2-console-usb-kbd-Limit-poll-frequency-to-improve-performance.patch +++ /dev/null @@ -1,178 +0,0 @@ -From patchwork Wed Dec 22 22:51:26 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Thomas Watson -X-Patchwork-Id: 1572368 -X-Patchwork-Delegate: marek.vasut@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: bilbo.ozlabs.org; - dkim=pass (2048-bit key; - unprotected) header.d=icloud.com header.i=@icloud.com header.a=rsa-sha256 - header.s=1a1hai header.b=SkTQ1vLj; - dkim-atps=neutral -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JK8Mc4B31z9s0r - for ; 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Wed, 22 Dec 2021 23:52:23 +0100 (CET) -Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) - header.from=icloud.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=twatson52@icloud.com -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=icloud.com; - s=1a1hai; t=1640213541; - bh=9Gu/RsbBH8Lwy0caxjtXwguQwc3tOXLqzye8cafMd78=; - h=From:To:Subject:Date:Message-Id:MIME-Version; - b=SkTQ1vLjDZUB4S3pQ+QOuMAQs7y78hvdCVG59JmuiBtL/pLL9IskzfDYEEVxmBQ8j - QIbZXSdaHlAH3tL3ajaqL0+IJp7J/yQ5/wpmmTsRMBdk0xcgSGilBCve35DMoKYFu1 - YSaXYI8GDtaBL5R9EGZAW6SekyeIWfyy03PQpawqJpTlqUNZuLdrr9mGRF/q2fbSHd - Fr4qzePCKzk3GsUhdfkh8hEDS4lOGVAPa3K2mGEpK6K/+Gv3rCckgYrV5IAJQ8YpdP - SCmRL3N03P5wkt5WiYasawJW4pcx92J2RXtyikC9fc6p67bGXkUJA+8dOtxlOyBY8E - 8TrKBWY9cvKTw== -Received: from jacobs-p52.memphis.edu - (99-122-90-201.lightspeed.mmphtn.sbcglobal.net [99.122.90.201]) - by st43p00im-ztbu10073601.me.com (Postfix) with ESMTPSA id 283205A0974; - Wed, 22 Dec 2021 22:52:21 +0000 (UTC) -From: Thomas Watson -To: u-boot@lists.denx.de -Cc: Thomas Watson , - Marek Vasut -Subject: [PATCH v2] console: usb: kbd: Limit poll frequency to improve - performance -Date: Wed, 22 Dec 2021 16:51:26 -0600 -Message-Id: <20211222225124.7154-1-twatson52@icloud.com> -X-Mailer: git-send-email 2.31.1 -MIME-Version: 1.0 -X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.425, 18.0.790 - definitions=2021-12-22_02:2021-12-22, - 2021-12-22 signatures=0 -X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 - malwarescore=0 - phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 - mlxlogscore=934 adultscore=0 classifier=spam adjust=0 reason=mlx - scancount=1 engine=8.0.1-2009150000 definitions=main-2112220119 -X-Mailman-Approved-At: Thu, 23 Dec 2021 00:15:58 +0100 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.38 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de -X-Virus-Status: Clean - -Using the XHCI driver, the function `usb_kbd_poll_for_event` takes -30-40ms to run. The exact time is dependent on the polling interval the -keyboard requests in its descriptor, and likely cannot be significantly -reduced without major rework to the XHCI driver. - -The U-Boot EFI console service sets a timer to poll the keyboard every 5 -microseconds, and this timer is checked every time a block is read off -disk. The net effect is that, on my system, loading a ~40MiB kernel and -initrd takes about 62 seconds with a slower keyboard and 53 seconds -with a faster one, with the vast majority of the time spent polling the -keyboard. - -To solve this problem, this patch adds a 20ms delay between consecutive -calls to `usb_kbd_poll_for_event`. This is sufficient to reduce the -total loading time to under half a second for both keyboards, and does -not impact the perceived keystroke latency. - -Signed-off-by: Thomas Watson ---- -This revision wraps the comment at 80 characters and also should not -have been corrupted by my e-mail client. - - common/usb_kbd.c | 20 +++++++++++++++----- - 1 file changed, 15 insertions(+), 5 deletions(-) - -diff --git a/common/usb_kbd.c b/common/usb_kbd.c -index afad260d3d..5408c821b4 100644 ---- a/common/usb_kbd.c -+++ b/common/usb_kbd.c -@@ -118,7 +118,7 @@ struct usb_kbd_pdata { - extern int __maybe_unused net_busy_flag; - - /* The period of time between two calls of usb_kbd_testc(). */ --static unsigned long __maybe_unused kbd_testc_tms; -+static unsigned long kbd_testc_tms; - - /* Puts character in the queue and sets up the in and out pointer. */ - static void usb_kbd_put_queue(struct usb_kbd_pdata *data, u8 c) -@@ -394,21 +394,31 @@ static int usb_kbd_testc(struct stdio_dev *sdev) - struct usb_device *usb_kbd_dev; - struct usb_kbd_pdata *data; - -+ /* -+ * Polling the keyboard for an event can take dozens of milliseconds. -+ * Add a delay between polls to avoid blocking activity which polls -+ * rapidly, like the UEFI console timer. -+ */ -+ unsigned long poll_delay = CONFIG_SYS_HZ / 50; -+ - #ifdef CONFIG_CMD_NET - /* - * If net_busy_flag is 1, NET transfer is running, - * then we check key-pressed every second (first check may be - * less than 1 second) to improve TFTP booting performance. - */ -- if (net_busy_flag && (get_timer(kbd_testc_tms) < CONFIG_SYS_HZ)) -- return 0; -- kbd_testc_tms = get_timer(0); -+ if (net_busy_flag) -+ poll_delay = CONFIG_SYS_HZ; - #endif -+ - dev = stdio_get_by_name(sdev->name); - usb_kbd_dev = (struct usb_device *)dev->priv; - data = usb_kbd_dev->privptr; - -- usb_kbd_poll_for_event(usb_kbd_dev); -+ if (get_timer(kbd_testc_tms) >= poll_delay) { -+ usb_kbd_poll_for_event(usb_kbd_dev); -+ kbd_testc_tms = get_timer(0); -+ } - - return !(data->usb_in_pointer == data->usb_out_pointer); - } From e06a81622d476c077573e504e78c97f92d123778 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 15 Feb 2022 17:06:52 +0000 Subject: [PATCH 14/28] BR: libuuid-devel --- uboot-tools.spec | 1 + 1 file changed, 1 insertion(+) diff --git a/uboot-tools.spec b/uboot-tools.spec index e04730a..1a4127c 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -46,6 +46,7 @@ BuildRequires: python3-libfdt BuildRequires: flex bison BuildRequires: openssl-devel BuildRequires: SDL-devel +BuildRequires: libuuid-devel BuildRequires: swig %ifarch aarch64 BuildRequires: arm-trusted-firmware-armv8 From be009d93163e00efee372cde135e84a36921acc0 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 15 Feb 2022 18:51:20 +0000 Subject: [PATCH 15/28] add gnutls-devel --- uboot-tools.spec | 1 + 1 file changed, 1 insertion(+) diff --git a/uboot-tools.spec b/uboot-tools.spec index 1a4127c..2125458 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -47,6 +47,7 @@ BuildRequires: flex bison BuildRequires: openssl-devel BuildRequires: SDL-devel BuildRequires: libuuid-devel +BuildRequires: gnutls-devel BuildRequires: swig %ifarch aarch64 BuildRequires: arm-trusted-firmware-armv8 From 359979e25b7a54bdfb46b6162dca116fbea6325d Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 19 Feb 2022 11:11:28 +0100 Subject: [PATCH 16/28] Add support for another rk3399 device --- aarch64-boards | 1 + ...nitial-support-for-the-PinePhone-Pro.patch | 886 ++++++++++++++++++ uboot-tools.spec | 5 +- 3 files changed, 890 insertions(+), 2 deletions(-) create mode 100644 rockchip-Add-initial-support-for-the-PinePhone-Pro.patch diff --git a/aarch64-boards b/aarch64-boards index de5f479..a38107c 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -58,6 +58,7 @@ pine64-lts pine64_plus pinebook pinebook-pro-rk3399 +pinephone-pro-rk3399 pine_h64 pinephone pinetab diff --git a/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch new file mode 100644 index 0000000..3dc7614 --- /dev/null +++ b/rockchip-Add-initial-support-for-the-PinePhone-Pro.patch @@ -0,0 +1,886 @@ +From: Martijn Braam +Subject: [PATCH] rockchip: Add initial support for the PinePhone Pro +Date: Thu, 21 Oct 2021 19:18:43 +0200 + +This is a new device by PINE64 that's very similar to the Pinebook Pro +that's already supported. + +Specification: +- Rockchip RK3399 +- 4GB Dual-Channel LPDDR4 +- 128GB eMMC +- mSD card slot +- AP6255 for 802.11ac WiFi and Bluetooth +- 6 inch 720*1440 DSI display +- Quectel EG25g usb modem +- Type-C port with alt-mode display (DP 1.2) and PD charging. + +Signed-off-by: Martijn Braam +--- + + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++ + arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++ + arch/arm/mach-rockchip/rk3399/Kconfig | 8 + + board/pine64/pinephone-pro-rk3399/Kconfig | 15 + + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + + board/pine64/pinephone-pro-rk3399/Makefile | 1 + + .../pinephone-pro-rk3399.c | 57 ++ + configs/pinephone-pro-rk3399_defconfig | 92 ++++ + include/configs/pinephone-pro-rk3399.h | 23 + + 10 files changed, 769 insertions(+) + create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts + create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig + create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS + create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile + create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c + create mode 100644 configs/pinephone-pro-rk3399_defconfig + create mode 100644 include/configs/pinephone-pro-rk3399.h + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index ed3d360bb1..3206370226 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-nanopi-r4s.dtb \ + rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ ++ rk3399-pinephone-pro.dtb \ + rk3399-puma-haikou.dtb \ + rk3399-roc-pc.dtb \ + rk3399-roc-pc-mezzanine.dtb \ +diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +new file mode 100644 +index 0000000000..9d44db5978 +--- /dev/null ++++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +@@ -0,0 +1,44 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Peter Robinson ++ * Copyright (C) 2021 Martijn Braam ++ */ ++ ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++ ++/ { ++ aliases { ++ spi0 = &spi1; ++ }; ++ ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ }; ++ ++ config { ++ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ ++ }; ++}; ++ ++&i2c0 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&rk818 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&rng { ++ status = "okay"; ++}; ++ ++&sdhci { ++ max-frequency = <25000000>; ++ u-boot,dm-pre-reloc; ++}; ++ ++&sdmmc { ++ max-frequency = <20000000>; ++ u-boot,dm-pre-reloc; ++}; +diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts +new file mode 100644 +index 0000000000..3fe1845ced +--- /dev/null ++++ b/arch/arm/dts/rk3399-pinephone-pro.dts +@@ -0,0 +1,520 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Martijn Braam ++ */ ++ ++/dts-v1/; ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "Pine64 PinePhone Pro"; ++ compatible = "pine64,pinephone-pro", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ }; ++ ++ /* Power tree */ ++ /* Root power source */ ++ vcc_sysin: vcc-sysin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sysin"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ /* Main 3.3v supply */ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_sysin>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ rk818: pmic@1c { ++ compatible = "rockchip,rk818"; ++ reg = <0x1c>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sysin>; ++ vcc2-supply = <&vcc_sysin>; ++ vcc3-supply = <&vcc_sysin>; ++ vcc4-supply = <&vcc_sysin>; ++ vcc6-supply = <&vcc_sysin>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc_sysin>; ++ vcc9-supply = <&vcc3v3_sys>; ++ ++ regulators { ++ vdd_cpu_l: DCDC_REG1 { ++ regulator-name = "vdd_cpu_1"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_center: DCDC_REG2 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG1 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v0_touch: LDO_REG2 { ++ regulator-name = "vcc3v0_touch"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG3 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_power_on: LDO_REG4 { ++ regulator-name = "vcc_power_on"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG5 { ++ regulator-name = "vcc_3v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG7 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s3: LDO_REG8 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_sd: LDO_REG9 { ++ regulator-name = "vcc_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ boost_otg: DCDC_BOOST { ++ regulator-name = "boost_otg"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <5000000>; ++ }; ++ }; ++ ++ otg_switch: OTG_SWITCH { ++ regulator-name = "otg_switch"; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_pin>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_pin>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ i2c-scl-rising-time-ns = <300>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2c4 { ++ i2c-scl-rising-time-ns = <600>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ ++ fusb0: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ status = "okay"; ++ }; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ bt656-supply = <&vcc1v8_dvp>; ++ audio-supply = <&vcca1v8_codec>; ++ sdmmc-supply = <&vcc_sd>; ++ gpio1830-supply = <&vcc_3v0>; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bt { ++ bt_enable_h: bt-enable-h { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ buttons { ++ pwrbtn: pwrbtn { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ fusb302x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ leds { ++ work_led_pin: work-led-pin { ++ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ diy_led_pin: diy-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_perst: pcie-perst { ++ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_pwr_en: pcie-pwr-en { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_pin: vsel1-pin { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_pin: vsel2-pin { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ sdcard { ++ sdmmc0_pwr_h: sdmmc0-pwr-h { ++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb-typec { ++ vcc5v0_typec_en: vcc5v0_typec_en { ++ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdio0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ disable-wp; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; ++ vmmc-supply = <&vcc3v3_s3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ non-removable; ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; +diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig +index 17628f9171..3ba603ca80 100644 +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399 + with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, + 1920*1080 screen and all the usual laptop features. + ++config TARGET_PINEPHONE_PRO_RK3399 ++ bool "PinePhone Pro" ++ help ++ PinePhone Pro is a phone based on the Rockchip rk3399 SoC ++ with 4Gb RAM, onboard eMMC, USB-C, a headphone jack, ++ 720x1440 screen and an external Quectel USB modem. ++ + config TARGET_PUMA_RK3399 + bool "Theobroma Systems RK3399-Q7 (Puma)" + help +@@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT + source "board/firefly/roc-pc-rk3399/Kconfig" + source "board/google/gru/Kconfig" + source "board/pine64/pinebook-pro-rk3399/Kconfig" ++source "board/pine64/pinephone-pro-rk3399/Kconfig" + source "board/pine64/rockpro64_rk3399/Kconfig" + source "board/rockchip/evb_rk3399/Kconfig" + source "board/theobroma-systems/puma_rk3399/Kconfig" +diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig +new file mode 100644 +index 0000000000..13d6465ae6 +--- /dev/null ++++ b/board/pine64/pinephone-pro-rk3399/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_PINEPHONE_PRO_RK3399 ++ ++config SYS_BOARD ++ default "pinephone-pro-rk3399" ++ ++config SYS_VENDOR ++ default "pine64" ++ ++config SYS_CONFIG_NAME ++ default "pinephone-pro-rk3399" ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ ++endif +diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS +new file mode 100644 +index 0000000000..9ca4fc4cbe +--- /dev/null ++++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS +@@ -0,0 +1,8 @@ ++PINEPHONE_PRO ++M: Martijn Braam ++S: Maintained ++F: board/pine64/rk3399-pinephone-pro/ ++F: include/configs/rk3399-pinephone-pro.h ++F: arch/arm/dts/rk3399-pinephone-pro.dts ++F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi ++F: configs/pinephone-pro-rk3399_defconfig +diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile +new file mode 100644 +index 0000000000..8d9203053e +--- /dev/null ++++ b/board/pine64/pinephone-pro-rk3399/Makefile +@@ -0,0 +1 @@ ++obj-y += pinephone-pro-rk3399.o +diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +new file mode 100644 +index 0000000000..8efeb6ea3d +--- /dev/null ++++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c +@@ -0,0 +1,57 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2019 Vasily Khoruzhick ++ * (C) Copyright 2021 Martijn Braam ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GRF_IO_VSEL_BT565_SHIFT 0 ++#define PMUGRF_CON0_VSEL_SHIFT 8 ++ ++#ifdef CONFIG_MISC_INIT_R ++static void setup_iodomain(void) ++{ ++ struct rk3399_grf_regs *grf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ struct rk3399_pmugrf_regs *pmugrf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); ++ ++ /* BT565 is in 1.8v domain */ ++ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); ++ ++ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ ++ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); ++} ++ ++int misc_init_r(void) ++{ ++ const u32 cpuid_offset = 0x7; ++ const u32 cpuid_length = 0x10; ++ u8 cpuid[cpuid_length]; ++ int ret; ++ ++ setup_iodomain(); ++ ++ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_cpuid_set(cpuid, cpuid_length); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_setup_macaddr(); ++ ++ return ret; ++} ++ ++#endif +diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig +new file mode 100644 +index 0000000000..2cf80f7d35 +--- /dev/null ++++ b/configs/pinephone-pro-rk3399_defconfig +@@ -0,0 +1,92 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x8000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_PINEPHONE_PRO_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI_SUPPORT=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_BOOTDELAY=3 ++CONFIG_USE_PREBOOT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_MTD_SUPPORT=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_DM_KEYBOARD=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_DM_ETH=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_DM_PMIC_FAN53555=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_DM_RESET=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_EDP=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y +diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h +new file mode 100644 +index 0000000000..fefa793fdd +--- /dev/null ++++ b/include/configs/pinephone-pro-rk3399.h +@@ -0,0 +1,23 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2016 Rockchip Electronics Co., Ltd ++ * Copyright (C) 2020 Peter Robinson ++ * Copyright (C) 2021 Martijn Braam ++ */ ++ ++#ifndef __PINEPHONE_PRO_RK3399_H ++#define __PINEPHONE_PRO_RK3399_H ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdin=serial,usbkbd\0" \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++ ++#define CONFIG_USB_OHCI_NEW ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 ++ ++#endif diff --git a/uboot-tools.spec b/uboot-tools.spec index 2125458..7a267f5 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -23,6 +23,7 @@ Patch4: rpi-fallback-to-max-clock-for-mmc.patch Patch5: rpi-bcm2835_sdhost-firmware-managed-clock.patch # Rockchips improvements Patch8: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch +Patch9: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch # Patch9: 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch BuildRequires: bc @@ -117,7 +118,7 @@ do echo "Board: $board using rk3328" cp /usr/share/arm-trusted-firmware/rk3328/* builds/$(echo $board)/ fi - rk3399=(evb-rk3399 ficus-rk3399 firefly-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 leez-rk3399 nanopc-t4-rk3399 nanopi-m4-2gb-rk3399 nanopi-m4b-rk3399 nanopi-m4-rk3399 nanopi-neo4-rk3399 nanopi-r4s-rk3399 orangepi-rk3399 pinebook-pro-rk3399 puma-rk3399 rock960-rk3399 rock-pi-4c-rk3399 rock-pi-4-rk3399 rock-pi-n10-rk3399pro rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399) + rk3399=(evb-rk3399 ficus-rk3399 firefly-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 leez-rk3399 nanopc-t4-rk3399 nanopi-m4-2gb-rk3399 nanopi-m4b-rk3399 nanopi-m4-rk3399 nanopi-neo4-rk3399 nanopi-r4s-rk3399 orangepi-rk3399 pinebook-pro-rk3399 pinephone-pro-rk3399 puma-rk3399 rock960-rk3399 rock-pi-4c-rk3399 rock-pi-4-rk3399 rock-pi-n10-rk3399pro rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399) if [[ " ${rk3399[*]} " == *" $board "* ]]; then echo "Board: $board using rk3399" cp /usr/share/arm-trusted-firmware/rk3399/* builds/$(echo $board)/ @@ -128,7 +129,7 @@ do %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" O=builds/$(echo $board)/ # build spi images for rockchip boards with SPI flash - rkspi=(evb-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 nanopc-t4-rk3399 pinebook-pro-rk3399 rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399) + rkspi=(evb-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 nanopc-t4-rk3399 pinebook-pro-rk3399 pinephone-pro-rk3399 rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399) if [[ " ${rkspi[*]} " == *" $board "* ]]; then echo "Board: $board with SPI flash" builds/$(echo $board)/tools/mkimage -n rk3399 -T rkspi -d builds/$(echo $board)/tpl/u-boot-tpl.bin:builds/$(echo $board)/spl/u-boot-spl.bin builds/$(echo $board)/idbloader.spi From 6706eb16a4eced58eb53b2f702c8196673a84f78 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 8 Mar 2022 09:53:45 +0000 Subject: [PATCH 17/28] 2022.04 RC3 --- sources | 2 +- uboot-tools.spec | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/sources b/sources index 6267dad..67d2217 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.04-rc2.tar.bz2) = 34af2d91a86e6864615ab09a2da7ec752beb56808d9eea652d425476cd1bbdf84d4e5f98740254f7cd91a04f11712d073450e74f4e07ae4180d845cb38620ee3 +SHA512 (u-boot-2022.04-rc3.tar.bz2) = 0c6c2534709045461872a348b988863197743b58732b6ba6a25069dd31de96312b699c571f9af4bcf40d9cdbe920cf6378efde876669e5e421a405e4d15359ec diff --git a/uboot-tools.spec b/uboot-tools.spec index 7a267f5..65c0415 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc2 +%global candidate rc3 Name: uboot-tools Version: 2022.04 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.3%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -252,6 +252,10 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Tue Mar 08 2022 Peter Robinson - 2022.04-0.3.rc3 +- Update to 2022.04 RC3 +- Enable new Rockchip devices + * Tue Feb 15 2022 Peter Robinson - 2022.04-0.2.rc2 - Update to 2022.04 RC2 From 1b64b89c2dd5779207d6721d1f98dfd21f2c7d4c Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 11 Mar 2022 14:40:53 +0000 Subject: [PATCH 18/28] Add the ability to do a tools only build, drop old el7 support --- uboot-tools.spec | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 65c0415..bd1a217 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,4 +1,5 @@ %global candidate rc3 +%bcond_without toolsonly Name: uboot-tools Version: 2022.04 @@ -27,28 +28,19 @@ Patch9: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch # Patch9: 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch BuildRequires: bc +BuildRequires: bison BuildRequires: dtc -BuildRequires: make -BuildRequires: perl-interpreter -# Requirements for building on el7 -%if 0%{?rhel} == 7 -BuildRequires: devtoolset-7-build -BuildRequires: devtoolset-7-binutils -BuildRequires: devtoolset-7-gcc -BuildRequires: python2-devel -BuildRequires: python2-setuptools -BuildRequires: python2-libfdt -%else +BuildRequires: flex BuildRequires: gcc +BuildRequires: gnutls-devel +BuildRequires: libuuid-devel +BuildRequires: make +BuildRequires: openssl-devel +BuildRequires: perl-interpreter BuildRequires: python3-devel BuildRequires: python3-setuptools BuildRequires: python3-libfdt -%endif -BuildRequires: flex bison -BuildRequires: openssl-devel BuildRequires: SDL-devel -BuildRequires: libuuid-devel -BuildRequires: gnutls-devel BuildRequires: swig %ifarch aarch64 BuildRequires: arm-trusted-firmware-armv8 @@ -59,6 +51,7 @@ Requires: dtc This package contains a few U-Boot utilities - mkimage for creating boot images and fw_printenv/fw_setenv for manipulating the boot environment variables. +%if %{with toolsonly} %ifarch aarch64 %package -n uboot-images-armv8 Summary: U-Boot firmware images for aarch64 boards @@ -76,6 +69,7 @@ BuildArch: noarch %description -n uboot-images-armv7 U-Boot firmware binaries for armv7 boards %endif +%endif %prep %autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} @@ -85,14 +79,10 @@ cp %SOURCE1 %SOURCE2 . %build mkdir builds -%if 0%{?rhel} == 7 -#Enabling DTS for .el7 -%{?enable_devtoolset7:%{enable_devtoolset7}} -%endif - %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-only_defconfig O=builds/ %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-all O=builds/ +%if %{with toolsonly} # U-Boot device firmwares don't currently support LTO %define _lto_cflags %{nil} @@ -148,6 +138,7 @@ do fi done +%endif %endif %install @@ -155,6 +146,7 @@ mkdir -p %{buildroot}%{_bindir} mkdir -p %{buildroot}%{_mandir}/man1 mkdir -p %{buildroot}%{_datadir}/uboot/ +%if %{with toolsonly} %ifarch aarch64 for board in $(ls builds) do @@ -208,6 +200,7 @@ do fi done %endif +%endif for tool in bmp_logo dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc img2srec mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder ubsha1 xway-swap-bytes kwboot do @@ -241,6 +234,7 @@ cp -p board/warp7/README builds/docs/README.warp7 %{_mandir}/man1/mkimage.1* %dir %{_datadir}/uboot/ +%if %{with toolsonly} %ifarch aarch64 %files -n uboot-images-armv8 %{_datadir}/uboot/* @@ -250,6 +244,7 @@ cp -p board/warp7/README builds/docs/README.warp7 %files -n uboot-images-armv7 %{_datadir}/uboot/* %endif +%endif %changelog * Tue Mar 08 2022 Peter Robinson - 2022.04-0.3.rc3 From 2a3a46103d3c40bd3214a62c6af6f831e1a552e4 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 28 Mar 2022 17:37:15 +0100 Subject: [PATCH 19/28] 2022.04 RC5 --- sources | 2 +- uboot-tools.spec | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/sources b/sources index 67d2217..20a29f2 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.04-rc3.tar.bz2) = 0c6c2534709045461872a348b988863197743b58732b6ba6a25069dd31de96312b699c571f9af4bcf40d9cdbe920cf6378efde876669e5e421a405e4d15359ec +SHA512 (u-boot-2022.04-rc5.tar.bz2) = 9450786f7decedc9ccd6973c2d3a1554edc10dcc64285e3793341291d003bf7676e8a9f146191b1db7869d1855a1da5c8dcbd02a76c828ad9a95f78297bf0d5e diff --git a/uboot-tools.spec b/uboot-tools.spec index bd1a217..594f15f 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,9 +1,9 @@ -%global candidate rc3 +%global candidate rc5 %bcond_without toolsonly Name: uboot-tools Version: 2022.04 -Release: 0.3%{?candidate:.%{candidate}}%{?dist} +Release: 0.4%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -247,6 +247,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Mon Mar 28 2022 Peter Robinson - 2022.04-0.4.rc5 +- Update to 2022.04 RC5 + * Tue Mar 08 2022 Peter Robinson - 2022.04-0.3.rc3 - Update to 2022.04 RC3 - Enable new Rockchip devices From 7b988dd8fc35fbfb1de902e64573577726a6671d Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 28 Mar 2022 17:48:50 +0100 Subject: [PATCH 20/28] Upload fixes source, add ncurses-devel --- sources | 2 +- uboot-tools.spec | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/sources b/sources index 20a29f2..ebcb769 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.04-rc5.tar.bz2) = 9450786f7decedc9ccd6973c2d3a1554edc10dcc64285e3793341291d003bf7676e8a9f146191b1db7869d1855a1da5c8dcbd02a76c828ad9a95f78297bf0d5e +SHA512 (u-boot-2022.04-rc5.tar.bz2) = 6fbd2eeb0155ba3ab0460bc0a31ab5434f059b1f8eb7a182ee147583c8b827ef9979601fd147bfe9f617998433a2292cd2491f5a03cfc8bf90127fc45e585f1a diff --git a/uboot-tools.spec b/uboot-tools.spec index 594f15f..905a847 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -35,6 +35,7 @@ BuildRequires: gcc BuildRequires: gnutls-devel BuildRequires: libuuid-devel BuildRequires: make +BuildRequires: ncurses-devel BuildRequires: openssl-devel BuildRequires: perl-interpreter BuildRequires: python3-devel From b6626c87f42b02118991723ca64ef29a21e1f139 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 29 Mar 2022 21:36:14 +0100 Subject: [PATCH 21/28] cleanup some old patches --- ...to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch | 244 ------------------ dragonboard-fixes.patch | 115 --------- uboot-tools.spec | 1 - 3 files changed, 360 deletions(-) delete mode 100644 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch delete mode 100644 dragonboard-fixes.patch diff --git a/0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch b/0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch deleted file mode 100644 index 0f762d9..0000000 --- a/0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch +++ /dev/null @@ -1,244 +0,0 @@ -From 53f3d6e9219a36f375e27150b8ec1088624f1aa0 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 21 Dec 2021 17:25:35 +0000 -Subject: [PATCH] udoo_neo: Move to DM for REGUALTOR/PMIC/I2C drivers - -This moves over the PMIC power init to DM and the associated i2c and -regulator bits. - -Signed-off-by: Peter Robinson ---- - board/udoo/neo/neo.c | 139 +++---------------------------------- - configs/udoo_neo_defconfig | 10 +-- - include/configs/udoo_neo.h | 5 -- - 3 files changed, 15 insertions(+), 139 deletions(-) - -diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c -index 5e40583ab4..9e2a66996c 100644 ---- a/board/udoo/neo/neo.c -+++ b/board/udoo/neo/neo.c -@@ -51,11 +51,6 @@ enum { - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - --#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ -- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ -- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ -- PAD_CTL_ODE) -- - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -@@ -83,135 +78,25 @@ int dram_init(void) - return 0; - } - --#ifdef CONFIG_SYS_I2C_MXC --#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) --/* I2C1 for PMIC */ --static struct i2c_pads_info i2c_pad_info1 = { -- .scl = { -- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, -- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, -- .gp = IMX_GPIO_NR(1, 0), -- }, -- .sda = { -- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, -- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, -- .gp = IMX_GPIO_NR(1, 1), -- }, --}; --#endif -- --#if CONFIG_IS_ENABLED(POWER_LEGACY) - int power_init_board(void) - { -- struct pmic *p; -- int ret; -- unsigned int reg, rev_id; -- -- ret = power_pfuze3000_init(PFUZE3000_I2C_BUS); -- if (ret) -- return ret; -- -- p = pmic_get("PFUZE3000"); -- ret = pmic_probe(p); -- if (ret) -- return ret; -+ struct udevice *dev; -+ int ret, dev_id, rev_id; - -- pmic_reg_read(p, PFUZE3000_DEVICEID, ®); -- pmic_reg_read(p, PFUZE3000_REVID, &rev_id); -- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); -- -- /* disable Low Power Mode during standby mode */ -- pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); -- reg |= 0x1; -- ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); -- if (ret) -+ ret = pmic_get("pfuze3000@8", &dev); -+ if (ret == -ENODEV) -+ return 0; -+ if (ret != 0) - return ret; - -- ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc); -- if (ret) -- return ret; -+ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); -+ rev_id = pmic_reg_read(dev, PFUZE3000_REVID); -+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - -- ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc); -- if (ret) -- return ret; -- -- ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc); -- if (ret) -- return ret; -- -- ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc); -- if (ret) -- return ret; -- -- /* set SW1A standby voltage 0.975V */ -- pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®); -- reg &= ~0x3f; -- reg |= PFUZE3000_SW1AB_SETP(9750); -- ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); -- if (ret) -- return ret; -- -- /* set SW1B standby voltage 0.975V */ -- pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®); -- reg &= ~0x3f; -- reg |= PFUZE3000_SW1AB_SETP(9750); -- ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); -- if (ret) -- return ret; -- -- /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */ -- pmic_reg_read(p, PFUZE3000_SW1ACONF, ®); -- reg &= ~0xc0; -- reg |= 0x40; -- ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg); -- if (ret) -- return ret; -- -- /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */ -- pmic_reg_read(p, PFUZE3000_SW1BCONF, ®); -- reg &= ~0xc0; -- reg |= 0x40; -- ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg); -- if (ret) -- return ret; -- -- /* set VDD_ARM_IN to 1.350V */ -- pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®); -- reg &= ~0x3f; -- reg |= PFUZE3000_SW1AB_SETP(13500); -- ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg); -- if (ret) -- return ret; -- -- /* set VDD_SOC_IN to 1.350V */ -- pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); -- reg &= ~0x3f; -- reg |= PFUZE3000_SW1AB_SETP(13500); -- ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); -- if (ret) -- return ret; -- -- /* set DDR_1_5V to 1.350V */ -- pmic_reg_read(p, PFUZE3000_SW3VOLT, ®); -- reg &= ~0x0f; -- reg |= PFUZE3000_SW3_SETP(13500); -- ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg); -- if (ret) -- return ret; -- -- /* set VGEN2_1V5 to 1.5V */ -- pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®); -- reg &= ~0x0f; -- reg |= PFUZE3000_VLDO_SETP(15000); -- /* enable */ -- reg |= 0x10; -- ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg); -- if (ret) -- return ret; -+ pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); - - return 0; - } --#endif - - static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -@@ -294,10 +179,6 @@ int board_init(void) - gpio_request(IMX_GPIO_NR(4, 16), "ncp692"); - gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); - --#ifdef CONFIG_SYS_I2C_MXC -- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); --#endif -- - setup_fec(); - - return 0; -diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig -index ca08de1bd4..9177bdba65 100644 ---- a/configs/udoo_neo_defconfig -+++ b/configs/udoo_neo_defconfig -@@ -10,8 +10,9 @@ CONFIG_ENV_SIZE=0x2000 - CONFIG_ENV_OFFSET=0x80000 - CONFIG_MX6SX=y - CONFIG_TARGET_UDOO_NEO=y --CONFIG_SYS_I2C_MXC_I2C1=y -+CONFIG_DM_I2C=y - CONFIG_DM_GPIO=y -+CONFIG_DM_MMC=y - CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic" - CONFIG_SPL_TEXT_BASE=0x00908000 - CONFIG_SPL_MMC=y -@@ -39,8 +40,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_SYS_MMC_ENV_DEV=1 - CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y - CONFIG_BOUNCE_BUFFER=y --CONFIG_SYS_I2C_LEGACY=y --CONFIG_SPL_SYS_I2C_LEGACY=y - CONFIG_SYS_I2C_MXC=y - CONFIG_FSL_USDHC=y - CONFIG_PHYLIB=y -@@ -52,11 +51,12 @@ CONFIG_FEC_MXC=y - CONFIG_MII=y - CONFIG_PINCTRL=y - CONFIG_PINCTRL_IMX6=y --CONFIG_POWER_LEGACY=y --CONFIG_POWER_I2C=y -+CONFIG_DM_PMIC=y -+CONFIG_DM_PMIC_PFUZE100=y - CONFIG_DM_REGULATOR=y - CONFIG_DM_REGULATOR_ANATOP=y - CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_PFUZE100=y - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_USB_STORAGE=y -diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h -index 3a7cb050b1..ac13c3e57f 100644 ---- a/include/configs/udoo_neo.h -+++ b/include/configs/udoo_neo.h -@@ -68,9 +68,4 @@ - #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - --/* PMIC */ --#define CONFIG_POWER_PFUZE3000 --#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 --#define PFUZE3000_I2C_BUS 0 -- - #endif /* __CONFIG_H */ --- -2.34.1 - diff --git a/dragonboard-fixes.patch b/dragonboard-fixes.patch deleted file mode 100644 index c49ea50..0000000 --- a/dragonboard-fixes.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 8b0274a733cd1ce39ad9ad18e1bd8efdd02a40b7 Mon Sep 17 00:00:00 2001 -From: Rob Clark -Date: Wed, 21 Jun 2017 14:21:15 -0400 -Subject: [PATCH 1/3] WIP: fix usb - ---- - common/usb_storage.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/common/usb_storage.c b/common/usb_storage.c -index d92ebb6eb19..9df3c3daaf4 100644 ---- a/common/usb_storage.c -+++ b/common/usb_storage.c -@@ -1016,7 +1016,7 @@ static int usb_request_sense(struct scsi_cmd *srb, struct us_data *ss) - - static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) - { -- int retries = 10; -+ int retries = 20; - - do { - memset(&srb->cmd[0], 0, 12); -@@ -1039,7 +1039,7 @@ static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) - if ((srb->sense_buf[2] == 0x02) && - (srb->sense_buf[12] == 0x3a)) - return -1; -- mdelay(100); -+ mdelay(250); - } while (retries--); - - return -1; --- -2.19.1 - -From 7bf41d74ca9d58bc2243b7688f8987c1d373ea56 Mon Sep 17 00:00:00 2001 -From: Rob Clark -Date: Mon, 3 Jul 2017 08:34:37 -0400 -Subject: [PATCH 2/3] HACK: disable emmc - -Hitting some timeout which makes boot take much longer. And -uefi/boot/rootfs partitions will be on sd-card or usb disk, etc, -so we can just ignore emmc. ---- - arch/arm/dts/dragonboard410c.dts | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts -index fa348bc621e..bfe7f15d5ed 100644 ---- a/arch/arm/dts/dragonboard410c.dts -+++ b/arch/arm/dts/dragonboard410c.dts -@@ -106,6 +106,7 @@ - #phy-cells = <0>; - }; - -+/* - sdhci@07824000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x11c 0x7824000 0x800>; -@@ -115,6 +116,7 @@ - clock = <&clkc 0>; - clock-frequency = <100000000>; - }; -+*/ - - sdhci@07864000 { - compatible = "qcom,sdhci-msm-v4"; --- -2.19.1 - -From 871fe802cf3ab593b9332c4f36ab2b3f179d51ae Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 4 Sep 2018 12:21:59 +0100 -Subject: [PATCH 3/3] add options for dm410c config - ---- - configs/dragonboard410c_defconfig | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig -index a55abaf8df5..4ece0cafbe4 100644 ---- a/configs/dragonboard410c_defconfig -+++ b/configs/dragonboard410c_defconfig -@@ -7,6 +7,8 @@ CONFIG_NR_DRAM_BANKS=1 - # CONFIG_ANDROID_BOOT_IMAGE is not set - CONFIG_FIT=y - CONFIG_OF_BOARD_SETUP=y -+CONFIG_FAT_WRITE=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -41,6 +43,13 @@ CONFIG_DM_PMIC=y - CONFIG_PMIC_PM8916=y - CONFIG_MSM_SERIAL=y - CONFIG_SPMI_MSM=y -+CONFIG_DM_ETH=y -+CONFIG_DM_KEYBOARD=y -+CONFIG_DM_VIDEO=y -+# CONFG_VIDEO_BPP8 is not set -+CONFIG_NO_FB_CLEAR=y -+CONFIG_VIDEO_SIMPLE=y -+CONFIG_USB_KEYBOARD=y - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_USB_EHCI_HCD=y -@@ -57,5 +66,6 @@ CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_ASIX=y - CONFIG_USB_ETHER_ASIX88179=y - CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y - CONFIG_USB_ETHER_SMSC95XX=y - CONFIG_OF_LIBFDT_OVERLAY=y --- -2.19.1 - diff --git a/uboot-tools.spec b/uboot-tools.spec index 905a847..ef878b5 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -25,7 +25,6 @@ Patch5: rpi-bcm2835_sdhost-firmware-managed-clock.patch # Rockchips improvements Patch8: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch Patch9: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch -# Patch9: 0001-udoo_neo-Move-to-DM-for-REGUALTOR-PMIC-I2C-drivers.patch BuildRequires: bc BuildRequires: bison From ab63b190498296c2b1cf3d9dc612b9980fd353a7 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 4 Apr 2022 15:37:35 +0100 Subject: [PATCH 22/28] 2022.04 GA --- sources | 2 +- uboot-tools.spec | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/sources b/sources index ebcb769..f3d74be 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.04-rc5.tar.bz2) = 6fbd2eeb0155ba3ab0460bc0a31ab5434f059b1f8eb7a182ee147583c8b827ef9979601fd147bfe9f617998433a2292cd2491f5a03cfc8bf90127fc45e585f1a +SHA512 (u-boot-2022.04.tar.bz2) = 113056e542db049eea3b1d1ccbbe52c79539a2f9bb6129d284ec9200dcffec7bd5969821913a9899631575b80991c84ad01bc845b4bba614e42e54466d9f0d64 diff --git a/uboot-tools.spec b/uboot-tools.spec index ef878b5..e147faf 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,9 +1,9 @@ -%global candidate rc5 +#global candidate rc0 %bcond_without toolsonly Name: uboot-tools Version: 2022.04 -Release: 0.4%{?candidate:.%{candidate}}%{?dist} +Release: 1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -247,6 +247,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Mon Apr 04 2022 Peter Robinson - 2022.04-1 +- Update to 2022.04 GA + * Mon Mar 28 2022 Peter Robinson - 2022.04-0.4.rc5 - Update to 2022.04 RC5 From 9cc572a2b0851d79b4457e7591564fb6797da32c Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 26 Apr 2022 12:49:33 +0100 Subject: [PATCH 23/28] Drop ARMv7 builds --- arm-boards | 141 ----------------------------------------------- uboot-tools.spec | 62 +++------------------ 2 files changed, 7 insertions(+), 196 deletions(-) delete mode 100644 arm-boards diff --git a/arm-boards b/arm-boards deleted file mode 100644 index a6b85e5..0000000 --- a/arm-boards +++ /dev/null @@ -1,141 +0,0 @@ -A10-OLinuXino-Lime -A10s-OLinuXino-M -A13-OLinuXino -A13-OLinuXinoM -A20-Olimex-SOM-EVB -A20-OLinuXino-Lime -A20-OLinuXino-Lime2 -A20-OLinuXino_MICRO -am335x_evm -am57xx_evm -Ampe_A76 -apalis_imx6 -arndale -Auxtek-T003 -Auxtek-T004 -ba10_tv_box -Bananapi -bananapi_m1_plus -bananapi_m2_berry -Bananapi_m2m -bananapi_m2_plus_h3 -Bananapi_M2_Ultra -bananapi_m2_zero -Bananapro -chiliboard -CHIP -Chuwi_V7_CW0825 -clearfog -cm_fx6 -Colombus -colorfly_e708_q1 -CSQ_CS908 -Cubieboard -Cubieboard2 -Cubieboard4 -Cubietruck -Cubietruck_plus -db-mv784mp-gp -difrnce_dit4350 -dserve_dsrv9703c -evb-rk3229 -firefly-rk3288 -helios4 -Hummingbird_A31 -Hyundai_A7HD -i12-tvbox -icnova-a20-swac -inet1 -iNet_3F -iNet_3W -inet86dz -iNet_86VS -inet97fv2 -inet98v_rev2 -inet9f_rev03 -inet_q972 -Itead_Ibox_A20 -jesurun_q5 -jetson-tk1 -Lamobo_R1 -libretech_all_h3_cc_h2_plus -Linksprite_pcDuino -Linksprite_pcDuino3 -Linksprite_pcDuino3_Nano -liteboard -marsboard -Marsboard_A10 -Mele_A1000 -Mele_A1000G_quad -Mele_I7 -Mele_M3 -Mele_M5 -Mele_M9 -Mini-X -mk802 -mk802_a10s -mk802ii -MK808C -MSI_Primo73 -MSI_Primo81 -mx6cuboxi -nanopi_m1 -nanopi_m1_plus -nanopi_neo -novena -odroid -odroid-xu3 -omap3_beagle -omap4_panda -omap5_uevm -Orangepi -orangepi_2 -orangepi_lite -Orangepi_mini -orangepi_one -orangepi_pc -orangepi_pc_plus -orangepi_plus -orangepi_plus2e -orangepi_r1 -orangepi_zero -origen -paz00 -pinecube -polaroid_mid2809pxe04 -pov_protab2_ips9 -q8_a13_tablet -q8_a23_tablet_800x480 -q8_a33_tablet_1024x600 -q8_a33_tablet_800x480 -qemu_arm -r7-tv-dongle -riotboard -rock -rock2 -rock-pi-n8-rk3288 -rpi_2 -rpi_3_32b -rpi_4_32b -Sinlinx_SinA31s -Sinovoip_BPI_M2 -Sinovoip_BPI_M3 -stih410-b2260 -stm32mp15_basic -sunxi_Gemei_G9 -tbs_a711 -tinker-rk3288 -tinker-s-rk3288 -trimslice -turris_omnia -udoo -udoo_neo -usbarmory -UTOO_P66 -wandboard -warp7 -Wexler_TAB7200 -Wits_Pro_A20_DKT -xilinx_zynq_virt -Yones_Toptech_BS1078_V2 -zeropi diff --git a/uboot-tools.spec b/uboot-tools.spec index e147faf..c2904dd 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -10,8 +10,7 @@ URL: http://www.denx.de/wiki/U-Boot ExcludeArch: s390x Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 -Source1: arm-boards -Source2: aarch64-boards +Source1: aarch64-boards # Fedoraisms patches # Needed to find DT on boot partition that's not the first partition @@ -60,21 +59,12 @@ BuildArch: noarch %description -n uboot-images-armv8 U-Boot firmware binaries for aarch64 boards %endif - -%ifarch %{arm} -%package -n uboot-images-armv7 -Summary: U-Boot firmware images for armv7 boards -BuildArch: noarch - -%description -n uboot-images-armv7 -U-Boot firmware binaries for armv7 boards -%endif %endif %prep %autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} -cp %SOURCE1 %SOURCE2 . +cp %SOURCE1 . %build mkdir builds @@ -86,7 +76,7 @@ mkdir builds # U-Boot device firmwares don't currently support LTO %define _lto_cflags %{nil} -%ifarch aarch64 %{arm} +%ifarch aarch64 for board in $(cat %{_arch}-boards) do echo "Building board: $board" @@ -124,18 +114,6 @@ do echo "Board: $board with SPI flash" builds/$(echo $board)/tools/mkimage -n rk3399 -T rkspi -d builds/$(echo $board)/tpl/u-boot-tpl.bin:builds/$(echo $board)/spl/u-boot-spl.bin builds/$(echo $board)/idbloader.spi fi - # build spi, and uart images for mvebu boards - # mvebu=(clearfog helios4 turris_omnia) - if [[ " ${mvebu[*]} " == *" $board "* ]]; then - for target in spi uart - do - echo "Board: $board Target: $target" - sed -i -e '/CONFIG_MVEBU_SPL_BOOT_DEVICE_/d' configs/$(echo $board)_defconfig - echo CONFIG_MVEBU_SPL_BOOT_DEVICE_${target^^}=y >> configs/$(echo $board)_defconfig - make $(echo $board)_defconfig O=builds/$(echo $board-$target)/ - %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" O=builds/$(echo $board-$target)/ - done - fi done %endif @@ -160,21 +138,8 @@ do done %endif -%ifarch %{arm} -for board in $(ls builds) -do - mkdir -p %{buildroot}%{_datadir}/uboot/$(echo $board)/ - for file in MLO SPL spl/arndale-spl.bin spl/origen-spl.bin spl/*spl.bin u-boot.bin u-boot.dtb u-boot-dtb-tegra.bin u-boot.img u-boot.imx u-boot-spl.kwb u-boot-rockchip.bin u-boot-sunxi-with-spl.bin spl/boot.bin - do - if [ -f builds/$(echo $board)/$(echo $file) ]; then - install -p -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/ - fi - done -done -%endif - # Bit of a hack to remove binaries we don't use as they're large -%ifarch aarch64 %{arm} +%ifarch aarch64 for board in $(ls builds) do rm -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot.dtb @@ -214,22 +179,14 @@ install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} # Copy some useful docs over mkdir -p builds/docs cp -p board/hisilicon/hikey/README builds/docs/README.hikey -cp -p board/Marvell/db-88f6820-gp/README builds/docs/README.mvebu-db-88f6820 cp -p board/rockchip/evb_rk3399/README builds/docs/README.evb_rk3399 -cp -p board/solidrun/clearfog/README builds/docs/README.clearfog -cp -p board/solidrun/mx6cuboxi/README builds/docs/README.mx6cuboxi cp -p board/sunxi/README.sunxi64 builds/docs/README.sunxi64 cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand -cp -p board/ti/omap5_uevm/README builds/docs/README.omap5_uevm -cp -p board/udoo/README builds/docs/README.udoo -cp -p board/wandboard/README builds/docs/README.wandboard -cp -p board/warp/README builds/docs/README.warp -cp -p board/warp7/README builds/docs/README.warp7 %files -%doc README doc/README.kwbimage doc/develop/distro.rst doc/README.gpt -%doc doc/README.odroid doc/README.rockchip doc/develop/uefi doc/uImage.FIT doc/arch/arm64.rst -%doc builds/docs/* doc/board/amlogic/ doc/board/rockchip/ doc/board/ti/am335x_evm.rst +%doc README doc/develop/distro.rst doc/README.gpt +%doc doc/README.rockchip doc/develop/uefi doc/uImage.FIT doc/arch/arm64.rst +%doc builds/docs/* doc/board/amlogic/ doc/board/rockchip/ %{_bindir}/* %{_mandir}/man1/mkimage.1* %dir %{_datadir}/uboot/ @@ -239,11 +196,6 @@ cp -p board/warp7/README builds/docs/README.warp7 %files -n uboot-images-armv8 %{_datadir}/uboot/* %endif - -%ifarch %{arm} -%files -n uboot-images-armv7 -%{_datadir}/uboot/* -%endif %endif %changelog From f02cd136917e1f13b8e1a9f44b7f1d1c6e0bfc81 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 27 Apr 2022 01:39:32 +0100 Subject: [PATCH 24/28] 2022.07 RC1 --- sources | 2 +- uboot-tools.spec | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/sources b/sources index f3d74be..20973a8 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.04.tar.bz2) = 113056e542db049eea3b1d1ccbbe52c79539a2f9bb6129d284ec9200dcffec7bd5969821913a9899631575b80991c84ad01bc845b4bba614e42e54466d9f0d64 +SHA512 (u-boot-2022.07-rc1.tar.bz2) = f3b3c2fbcf2542cd17feef8374f07bce9300f4491b5c1d7194a791d7b4279062de74b639b043f250ef416e1c345e40d7b72f51f3f1d8687670dda30ebb31a5f6 diff --git a/uboot-tools.spec b/uboot-tools.spec index c2904dd..6fedab7 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,9 +1,9 @@ -#global candidate rc0 +%global candidate rc1 %bcond_without toolsonly Name: uboot-tools Version: 2022.04 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -199,6 +199,9 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %endif %changelog +* Tue Apr 26 2022 Peter Robinson - 2022.04-0.1.rc1 +- Update to 2022.07 RC1 + * Mon Apr 04 2022 Peter Robinson - 2022.04-1 - Update to 2022.04 GA From 41e28cf922a394ef8d663a2182fd2c5075964fc3 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 27 Apr 2022 01:49:46 +0100 Subject: [PATCH 25/28] fix version --- uboot-tools.spec | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 6fedab7..38940ec 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ %bcond_without toolsonly Name: uboot-tools -Version: 2022.04 +Version: 2022.07 Release: 0.1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ @@ -199,7 +199,7 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %endif %changelog -* Tue Apr 26 2022 Peter Robinson - 2022.04-0.1.rc1 +* Tue Apr 26 2022 Peter Robinson - 2022.07-0.1.rc1 - Update to 2022.07 RC1 * Mon Apr 04 2022 Peter Robinson - 2022.04-1 From f0b776d4d6e0fdd9c371767b0260ce7239848d46 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 13 May 2022 19:24:42 +0100 Subject: [PATCH 26/28] 2022.07 RC2 Signed-off-by: Peter Robinson --- sources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sources b/sources index 20973a8..32f1aa8 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.07-rc1.tar.bz2) = f3b3c2fbcf2542cd17feef8374f07bce9300f4491b5c1d7194a791d7b4279062de74b639b043f250ef416e1c345e40d7b72f51f3f1d8687670dda30ebb31a5f6 +SHA512 (u-boot-2022.07-rc2.tar.bz2) = c3b0aab1e2de4ac48af1a5b5147f3afa4296dc3f264d15da43421ff58207bb5bb17b99d0a571361e76150804fc3f78bd16f2bc623cb8324c48e6834440b247c2 From 0e7b56408159f830f0ec13240a464153a6002c25 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 14 May 2022 10:17:26 +0100 Subject: [PATCH 27/28] 2022.07 RC2 --- uboot-tools.spec | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/uboot-tools.spec b/uboot-tools.spec index 38940ec..be83aa7 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,9 +1,9 @@ -%global candidate rc1 +%global candidate rc2 %bcond_without toolsonly Name: uboot-tools Version: 2022.07 -Release: 0.1%{?candidate:.%{candidate}}%{?dist} +Release: 0.2%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -199,6 +199,9 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %endif %changelog +* Sat May 14 2022 Peter Robinson - 2022.07-0.2.rc2 +- Update to 2022.07 RC2 + * Tue Apr 26 2022 Peter Robinson - 2022.07-0.1.rc1 - Update to 2022.07 RC1 From fa86e10d711ab526e20279a2654491c0f37c383e Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 25 May 2022 15:46:30 +0100 Subject: [PATCH 28/28] 2022.07 RC3 --- sources | 2 +- uboot-tools.spec | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/sources b/sources index 32f1aa8..7182c58 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2022.07-rc2.tar.bz2) = c3b0aab1e2de4ac48af1a5b5147f3afa4296dc3f264d15da43421ff58207bb5bb17b99d0a571361e76150804fc3f78bd16f2bc623cb8324c48e6834440b247c2 +SHA512 (u-boot-2022.07-rc3.tar.bz2) = 1ebc19ca9828f38e5568a3415281917a12d086f3e4e23749441faf77771612526d95a84af5433057f6caa09b424aff9d4709d2d223cbe98f7d6356049c3b0d3c diff --git a/uboot-tools.spec b/uboot-tools.spec index be83aa7..2fb5fee 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,9 +1,9 @@ -%global candidate rc2 +%global candidate rc3 %bcond_without toolsonly Name: uboot-tools Version: 2022.07 -Release: 0.2%{?candidate:.%{candidate}}%{?dist} +Release: 0.3%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -199,6 +199,9 @@ cp -p board/sunxi/README.nand builds/docs/README.sunxi-nand %endif %changelog +* Wed May 25 2022 Peter Robinson - 2022.07-0.3.rc3 +- Update to 2022.07 RC3 + * Sat May 14 2022 Peter Robinson - 2022.07-0.2.rc2 - Update to 2022.07 RC2