Updates for NVIDIA Jetson platforms
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@ -1,71 +1,141 @@
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From patchwork Mon Apr 15 09:32:39 2019
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Subject: [U-Boot, v5,
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27/27] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
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X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com>
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X-Patchwork-Id: 1085538
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X-Patchwork-Submitter: Tom Warren <tomcwarren3959@gmail.com>
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X-Patchwork-Id: 1261582
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X-Patchwork-Delegate: twarren@nvidia.com
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Message-Id: <20190415093239.27509-28-thierry.reding@gmail.com>
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To: Tom Warren <twarren@nvidia.com>,
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Simon Glass <sjg@chromium.org>
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Cc: u-boot@lists.denx.de, Jon Hunter <jonathanh@nvidia.com>
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Date: Mon, 15 Apr 2019 11:32:39 +0200
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From: Thierry Reding <thierry.reding@gmail.com>
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
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<twarren@nvidia.com>
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Subject: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
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Date: Wed, 25 Mar 2020 11:21:51 -0700
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Message-ID: <1585160511-15347-1-git-send-email-tomcwarren3959@gmail.com>
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From: Thierry Reding <treding@nvidia.com>
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From: Tom Warren <twarren@nvidia.com>
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The Jetson Nano Developer Kit is a Tegra X1 based development board. It
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is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
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of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
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The Jetson Nano Developer Kit is a Tegra X1-based development board. It
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is similar to Jetson TX1 but it is not pin compatible. It features 4GB
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of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
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used for storage.
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HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
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and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
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Ethernet controller provides onboard network connectivity.
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Ethernet controller provides onboard network connectivity. NVMe support
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has also been added. Env save is at the end of QSPI (4MB-8K).
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A 40-pin header on the board can be used to extend the capabilities and
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exposed interfaces of the Jetson Nano.
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Signed-off-by: Thierry Reding <treding@nvidia.com>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
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---
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Changes in v5:
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- add "ethernet" alias and store an empty MAC address as placeholder
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retry send-email to see if it shows up in Patchwork
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Changes in v3:
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- rename "Development Kit" to "Developer Kit"
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- drop alias for non-existent eMMC interface
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- import pinmux from A02 spreadsheet
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- drop preboot support for now
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- fixup text base
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arch/arm/dts/Makefile | 3 +-
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arch/arm/dts/tegra210-p3450-0000.dts | 135 +++++++++
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arch/arm/mach-tegra/tegra210/Kconfig | 7 +
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board/nvidia/p3450-0000/Kconfig | 12 +
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board/nvidia/p3450-0000/MAINTAINERS | 6 +
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board/nvidia/p3450-0000/Makefile | 8 +
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board/nvidia/p3450-0000/p3450-0000.c | 198 +++++++++++++
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.../p3450-0000/pinmux-config-p3450-0000.h | 265 ++++++++++++++++++
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configs/p3450-0000_defconfig | 55 ++++
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include/configs/p3450-0000.h | 34 +++
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10 files changed, 722 insertions(+), 1 deletion(-)
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arch/arm/dts/Makefile | 3 +-
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arch/arm/dts/tegra210-p3450-0000.dts | 147 +++++++++++++++++++++++++++++
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arch/arm/mach-tegra/board2.c | 25 +++++
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arch/arm/mach-tegra/tegra210/Kconfig | 7 ++
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board/nvidia/p3450-0000/Kconfig | 12 +++
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board/nvidia/p3450-0000/MAINTAINERS | 6 ++
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board/nvidia/p3450-0000/Makefile | 8 ++
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board/nvidia/p3450-0000/p3450-0000.c | 178 +++++++++++++++++++++++++++++++++++
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configs/p3450-0000_defconfig | 64 +++++++++++++
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include/configs/p3450-0000.h | 46 +++++++++
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10 files changed, 495 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts
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create mode 100644 board/nvidia/p3450-0000/Kconfig
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create mode 100644 board/nvidia/p3450-0000/MAINTAINERS
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create mode 100644 board/nvidia/p3450-0000/Makefile
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create mode 100644 board/nvidia/p3450-0000/p3450-0000.c
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create mode 100644 board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
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create mode 100644 configs/p3450-0000_defconfig
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create mode 100644 include/configs/p3450-0000.h
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 8167cdb4e856..f8d3441663c0 100644
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index 9c593b2..820ee97 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -127,7 +127,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-e2220-1170.dtb \
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tegra210-p2371-0000.dtb \
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tegra210-p2371-2180.dtb \
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@ -77,10 +147,14 @@ index 8167cdb4e856..f8d3441663c0 100644
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armada-3720-db.dtb \
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diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts
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new file mode 100644
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index 000000000000..d45ee9afc016
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index 0000000..9ef744a
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--- /dev/null
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+++ b/arch/arm/dts/tegra210-p3450-0000.dts
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@@ -0,0 +1,135 @@
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@@ -0,0 +1,147 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
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+ */
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+/dts-v1/;
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+
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+#include "tegra210.dtsi"
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@ -99,7 +173,8 @@ index 000000000000..d45ee9afc016
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+ i2c2 = "/i2c@7000c400";
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+ i2c3 = "/i2c@7000c500";
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+ i2c4 = "/i2c@7000c700";
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+ sdhci0 = "/sdhci@700b0000";
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+ mmc0 = "/sdhci@700b0600";
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+ mmc1 = "/sdhci@700b0000";
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+ spi0 = "/spi@70410000";
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+ usb0 = "/usb@7d000000";
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+ };
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@ -174,6 +249,12 @@ index 000000000000..d45ee9afc016
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+ bus-width = <4>;
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+ };
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+
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+ sdhci@700b0600 {
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+ status = "okay";
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+ bus-width = <8>;
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+ non-removable;
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+ };
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+
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+ i2c@7000c400 {
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+ status = "okay";
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+ clock-frequency = <400000>;
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@ -196,6 +277,7 @@ index 000000000000..d45ee9afc016
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+
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+ spi@70410000 {
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+ status = "okay";
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+ spi-max-frequency = <80000000>;
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+ };
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+
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+ usb@7d000000 {
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@ -216,8 +298,44 @@ index 000000000000..d45ee9afc016
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+ };
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+ };
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+};
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diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
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index 787ff97..224efc9 100644
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--- a/arch/arm/mach-tegra/board2.c
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+++ b/arch/arm/mach-tegra/board2.c
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@@ -217,6 +217,31 @@ int board_early_init_f(void)
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arch_timer_init();
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#endif
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+#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
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+ /*
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+ * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
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+ * We do this because earlier bootloaders have enabled power to
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+ * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
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+ * results in power being back-driven into the SD-card and SDMMC1
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+ * HW, which is 'bad' as per the HW team.
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+ *
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+ * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
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+ * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
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+ * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
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+ * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
|
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+ * voltage turns off. Since the SDCard voltage is no longer there, the
|
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+ * SDMMC CLK/DAT lines are backdriving into what essentially is a
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+ * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
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+ *
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+ * Note that this can probably be removed when we change over to storing
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+ * all BL components on QSPI on Nano, and U-Boot then becomes the first
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+ * one to turn on SDMMC1 power. Another fix would be to have CBoot
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+ * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
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+ */
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+ reset_set_enable(PERIPH_ID_SDMMC1, 1);
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+ clock_set_enable(PERIPH_ID_SDMMC1, 0);
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+#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
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+
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pinmux_init();
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board_init_uart_f();
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|
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diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
|
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index 250738aed312..ea28392c0f3a 100644
|
||||
index 3637473..97ed8e0 100644
|
||||
--- a/arch/arm/mach-tegra/tegra210/Kconfig
|
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+++ b/arch/arm/mach-tegra/tegra210/Kconfig
|
||||
@@ -35,6 +35,12 @@ config TARGET_P2571
|
||||
@ -233,7 +351,7 @@ index 250738aed312..ea28392c0f3a 100644
|
||||
endchoice
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||||
|
||||
config SYS_SOC
|
||||
@@ -47,5 +53,6 @@ source "board/nvidia/e2220-1170/Kconfig"
|
||||
@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
|
||||
source "board/nvidia/p2371-0000/Kconfig"
|
||||
source "board/nvidia/p2371-2180/Kconfig"
|
||||
source "board/nvidia/p2571/Kconfig"
|
||||
@ -242,7 +360,7 @@ index 250738aed312..ea28392c0f3a 100644
|
||||
endif
|
||||
diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig
|
||||
new file mode 100644
|
||||
index 000000000000..7a08cd88675f
|
||||
index 0000000..7a08cd8
|
||||
--- /dev/null
|
||||
+++ b/board/nvidia/p3450-0000/Kconfig
|
||||
@@ -0,0 +1,12 @@
|
||||
@ -260,7 +378,7 @@ index 000000000000..7a08cd88675f
|
||||
+endif
|
||||
diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS
|
||||
new file mode 100644
|
||||
index 000000000000..40700066bf39
|
||||
index 0000000..4070006
|
||||
--- /dev/null
|
||||
+++ b/board/nvidia/p3450-0000/MAINTAINERS
|
||||
@@ -0,0 +1,6 @@
|
||||
@ -272,7 +390,7 @@ index 000000000000..40700066bf39
|
||||
+F: configs/p3450-0000_defconfig
|
||||
diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile
|
||||
new file mode 100644
|
||||
index 000000000000..993c506d8200
|
||||
index 0000000..993c506
|
||||
--- /dev/null
|
||||
+++ b/board/nvidia/p3450-0000/Makefile
|
||||
@@ -0,0 +1,8 @@
|
||||
@ -286,19 +404,18 @@ index 000000000000..993c506d8200
|
||||
+obj-y += p3450-0000.o
|
||||
diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c
|
||||
new file mode 100644
|
||||
index 000000000000..432179e92605
|
||||
index 0000000..f4212ab
|
||||
--- /dev/null
|
||||
+++ b/board/nvidia/p3450-0000/p3450-0000.c
|
||||
@@ -0,0 +1,198 @@
|
||||
@@ -0,0 +1,178 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2018
|
||||
+ * (C) Copyright 2018-2019
|
||||
+ * NVIDIA Corporation <www.nvidia.com>
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <env.h>
|
||||
+#include <fdtdec.h>
|
||||
+#include <i2c.h>
|
||||
+#include <linux/libfdt.h>
|
||||
@ -307,7 +424,6 @@ index 000000000000..432179e92605
|
||||
+#include <asm/arch/gpio.h>
|
||||
+#include <asm/arch/pinmux.h>
|
||||
+#include "../p2571/max77620_init.h"
|
||||
+#include "pinmux-config-p3450-0000.h"
|
||||
+
|
||||
+void pin_mux_mmc(void)
|
||||
+{
|
||||
@ -351,24 +467,6 @@ index 000000000000..432179e92605
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Routine: pinmux_init
|
||||
+ * Description: Do individual peripheral pinmux configs
|
||||
+ */
|
||||
+void pinmux_init(void)
|
||||
+{
|
||||
+ pinmux_clear_tristate_input_clamping();
|
||||
+
|
||||
+ gpio_config_table(p3450_0000_gpio_inits,
|
||||
+ ARRAY_SIZE(p3450_0000_gpio_inits));
|
||||
+
|
||||
+ pinmux_config_pingrp_table(p3450_0000_pingrps,
|
||||
+ ARRAY_SIZE(p3450_0000_pingrps));
|
||||
+
|
||||
+ pinmux_config_drvgrp_table(p3450_0000_drvgrps,
|
||||
+ ARRAY_SIZE(p3450_0000_drvgrps));
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_PCI_TEGRA
|
||||
+int tegra_pcie_board_init(void)
|
||||
+{
|
||||
@ -488,283 +586,12 @@ index 000000000000..432179e92605
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
|
||||
new file mode 100644
|
||||
index 000000000000..722da4973542
|
||||
--- /dev/null
|
||||
+++ b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
|
||||
@@ -0,0 +1,265 @@
|
||||
+/*
|
||||
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+/*
|
||||
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
+ *
|
||||
+ * To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
+ * Run "board-to-uboot.py p3450-0000".
|
||||
+ */
|
||||
+
|
||||
+#ifndef _PINMUX_CONFIG_P3450_0000_H_
|
||||
+#define _PINMUX_CONFIG_P3450_0000_H_
|
||||
+
|
||||
+#define GPIO_INIT(_port, _gpio, _init) \
|
||||
+ { \
|
||||
+ .gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
+ .init = TEGRA_GPIO_INIT_##_init, \
|
||||
+ }
|
||||
+
|
||||
+static const struct tegra_gpio_config p3450_0000_gpio_inits[] = {
|
||||
+ /* port, pin, init_val */
|
||||
+ GPIO_INIT(A, 5, IN),
|
||||
+ GPIO_INIT(A, 6, OUT1),
|
||||
+ GPIO_INIT(B, 4, IN),
|
||||
+ GPIO_INIT(B, 5, IN),
|
||||
+ GPIO_INIT(B, 6, IN),
|
||||
+ GPIO_INIT(B, 7, IN),
|
||||
+ GPIO_INIT(C, 0, IN),
|
||||
+ GPIO_INIT(C, 1, IN),
|
||||
+ GPIO_INIT(C, 2, IN),
|
||||
+ GPIO_INIT(C, 3, IN),
|
||||
+ GPIO_INIT(C, 4, IN),
|
||||
+ GPIO_INIT(E, 6, IN),
|
||||
+ GPIO_INIT(G, 2, IN),
|
||||
+ GPIO_INIT(G, 3, IN),
|
||||
+ GPIO_INIT(H, 0, OUT0),
|
||||
+ GPIO_INIT(H, 2, IN),
|
||||
+ GPIO_INIT(H, 3, OUT0),
|
||||
+ GPIO_INIT(H, 4, OUT0),
|
||||
+ GPIO_INIT(H, 5, IN),
|
||||
+ GPIO_INIT(H, 6, IN),
|
||||
+ GPIO_INIT(H, 7, OUT0),
|
||||
+ GPIO_INIT(I, 0, OUT0),
|
||||
+ GPIO_INIT(I, 1, IN),
|
||||
+ GPIO_INIT(I, 2, OUT0),
|
||||
+ GPIO_INIT(J, 4, IN),
|
||||
+ GPIO_INIT(J, 5, IN),
|
||||
+ GPIO_INIT(J, 6, IN),
|
||||
+ GPIO_INIT(J, 7, IN),
|
||||
+ GPIO_INIT(S, 5, IN),
|
||||
+ GPIO_INIT(S, 7, OUT0),
|
||||
+ GPIO_INIT(T, 0, OUT0),
|
||||
+ GPIO_INIT(V, 0, IN),
|
||||
+ GPIO_INIT(V, 1, IN),
|
||||
+ GPIO_INIT(X, 3, OUT1),
|
||||
+ GPIO_INIT(X, 4, IN),
|
||||
+ GPIO_INIT(X, 5, IN),
|
||||
+ GPIO_INIT(X, 6, IN),
|
||||
+ GPIO_INIT(Y, 1, IN),
|
||||
+ GPIO_INIT(Y, 2, IN),
|
||||
+ GPIO_INIT(Z, 0, IN),
|
||||
+ GPIO_INIT(Z, 2, IN),
|
||||
+ GPIO_INIT(Z, 3, OUT0),
|
||||
+ GPIO_INIT(BB, 0, IN),
|
||||
+ GPIO_INIT(CC, 4, IN),
|
||||
+ GPIO_INIT(DD, 0, IN),
|
||||
+};
|
||||
+
|
||||
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
+ { \
|
||||
+ .pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
+ .func = PMUX_FUNC_##_mux, \
|
||||
+ .pull = PMUX_PULL_##_pull, \
|
||||
+ .tristate = PMUX_TRI_##_tri, \
|
||||
+ .io = PMUX_PIN_##_io, \
|
||||
+ .od = PMUX_PIN_OD_##_od, \
|
||||
+ .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
+ }
|
||||
+
|
||||
+static const struct pmux_pingrp_config p3450_0000_pingrps[] = {
|
||||
+ /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
+ PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
+ PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
+ PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PA6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI2_MOSI_PB4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI2_MISO_PB5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI2_SCK_PB6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI2_CS0_PB7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART3_RTS_PD3, UARTC, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DMIC3_CLK_PE4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART2_RX_PG1, UARTB, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART2_RTS_PG2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART2_CTS_PG3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(NFC_INT_PI1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART4_CTS_PI7, UARTD, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(DAP4_FS_PJ4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP4_DIN_PJ5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP4_DOUT_PJ6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP4_SCLK_PJ7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM_AF_EN_PS5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART1_RX_PU1, UARTA, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART1_RTS_PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(UART1_CTS_PU3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(LCD_BL_PWM_PV0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(TOUCH_RST_PV6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(ALS_PROX_INT_PX3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(BUTTON_VOL_DOWN_PX7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(LCD_TE_PY2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(CLK_32K_OUT_PY5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PZ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(DVFS_CLK_PBB2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
+ PINCFG(HDMI_INT_DP_HPD_PCC1, DP, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(USB_VBUS_EN0_PCC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(DP_HPD0_PCC6, DP, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
+ PINCFG(SPI2_CS1_PDD0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CPU_PWR_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
+ PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
+};
|
||||
+
|
||||
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
+ { \
|
||||
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
+ .slwf = _slwf, \
|
||||
+ .slwr = _slwr, \
|
||||
+ .drvup = _drvup, \
|
||||
+ .drvdn = _drvdn, \
|
||||
+ .lpmd = PMUX_LPMD_##_lpmd, \
|
||||
+ .schmt = PMUX_SCHMT_##_schmt, \
|
||||
+ .hsm = PMUX_HSM_##_hsm, \
|
||||
+ }
|
||||
+
|
||||
+static const struct pmux_drvgrp_config p3450_0000_drvgrps[] = {
|
||||
+};
|
||||
+
|
||||
+#endif /* PINMUX_CONFIG_P3450_0000_H */
|
||||
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
|
||||
new file mode 100644
|
||||
index 000000000000..3a95028279d3
|
||||
index 0000000..c861d13
|
||||
--- /dev/null
|
||||
+++ b/configs/p3450-0000_defconfig
|
||||
@@ -0,0 +1,55 @@
|
||||
@@ -0,0 +1,64 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_TEGRA=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x80080000
|
||||
@ -797,9 +624,10 @@ index 000000000000..3a95028279d3
|
||||
+CONFIG_DFU_SF=y
|
||||
+CONFIG_SYS_I2C_TEGRA=y
|
||||
+CONFIG_SPI_FLASH=y
|
||||
+CONFIG_SPI_FLASH_MACRONIX=y
|
||||
+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
|
||||
+CONFIG_SF_DEFAULT_MODE=0
|
||||
+CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
+CONFIG_SPI_FLASH_WINBOND=y
|
||||
+CONFIG_RTL8169=y
|
||||
+CONFIG_PCI=y
|
||||
+CONFIG_DM_PCI=y
|
||||
@ -807,6 +635,7 @@ index 000000000000..3a95028279d3
|
||||
+CONFIG_PCI_TEGRA=y
|
||||
+CONFIG_SYS_NS16550=y
|
||||
+CONFIG_TEGRA114_SPI=y
|
||||
+CONFIG_TEGRA210_QSPI=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_DM_USB=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
@ -820,15 +649,22 @@ index 000000000000..3a95028279d3
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+# CONFIG_ENV_IS_IN_MMC is not set
|
||||
+CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
+CONFIG_ENV_SIZE=0x2000
|
||||
+CONFIG_ENV_SECT_SIZE=0x1000
|
||||
+CONFIG_ENV_OFFSET=0xFFFFE000
|
||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
+CONFIG_DISABLE_SDMMC1_EARLY=y
|
||||
+CONFIG_NVME=y
|
||||
diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
|
||||
new file mode 100644
|
||||
index 000000000000..ee819b7573b0
|
||||
index 0000000..7f05beb
|
||||
--- /dev/null
|
||||
+++ b/include/configs/p3450-0000.h
|
||||
@@ -0,0 +1,34 @@
|
||||
@@ -0,0 +1,46 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+/*
|
||||
+ * (C) Copyright 2018-2019 NVIDIA Corporation. All rights reserved.
|
||||
+ * (C) Copyright 2018-2019 NVIDIA Corporation.
|
||||
+ */
|
||||
+
|
||||
+#ifndef _P3450_0000_H
|
||||
@ -844,15 +680,27 @@ index 000000000000..ee819b7573b0
|
||||
+/* Board-specific serial config */
|
||||
+#define CONFIG_TEGRA_ENABLE_UARTA
|
||||
+
|
||||
+/* Only MMC1/PXE/DHCP for now, add USB back in later when supported */
|
||||
+/* Only MMC/PXE/DHCP for now, add USB back in later when supported */
|
||||
+#define BOOT_TARGET_DEVICES(func) \
|
||||
+ func(MMC, mmc, 1) \
|
||||
+ func(MMC, mmc, 0) \
|
||||
+ func(PXE, pxe, na) \
|
||||
+ func(DHCP, dhcp, na)
|
||||
+
|
||||
+/* SPI */
|
||||
+/* Environment at end of QSPI, in the VER partition */
|
||||
+#define CONFIG_ENV_SPI_MAX_HZ 48000000
|
||||
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
|
||||
+
|
||||
+#define CONFIG_PREBOOT
|
||||
+
|
||||
+#define BOARD_EXTRA_ENV_SETTINGS \
|
||||
+ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
|
||||
+ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
|
||||
+ "source ${scriptaddr}; " \
|
||||
+ "fi\0"
|
||||
+
|
||||
+/* General networking support */
|
||||
+#include "tegra-common-usb-gadget.h"
|
||||
+#include "tegra-common-post.h"
|
||||
+
|
||||
|
394
Misc-fixes-for-Tegra.patch
Normal file
394
Misc-fixes-for-Tegra.patch
Normal file
@ -0,0 +1,394 @@
|
||||
From patchwork Thu Mar 26 22:20:43 2020
|
||||
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|
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|
||||
X-Patchwork-Id: 1262377
|
||||
X-Patchwork-Delegate: twarren@nvidia.com
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||||
Return-Path: <u-boot-bounces@lists.denx.de>
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
||||
<twarren@nvidia.com>, <vishruthj@nvidia.com>
|
||||
Subject: [PATCH 1/3] ARM: tegra: p2771-0000: enable PIE relocation
|
||||
Date: Thu, 26 Mar 2020 15:20:43 -0700
|
||||
Message-ID: <1585261245-1740-2-git-send-email-tomcwarren3959@gmail.com>
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|
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From: Vishruth <vishruthj@nvidia.com>
|
||||
|
||||
U-Boot is configured to build as position independent executable. Enable
|
||||
relocation of RELA section required to work with different load
|
||||
addresses.
|
||||
|
||||
Signed-off-by: Vishruth <vishruthj@nvidia.com>
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
configs/p2771-0000-000_defconfig | 1 +
|
||||
configs/p2771-0000-500_defconfig | 1 +
|
||||
2 files changed, 2 insertions(+)
|
||||
|
||||
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
|
||||
index 06f12e2..e347a77 100644
|
||||
--- a/configs/p2771-0000-000_defconfig
|
||||
+++ b/configs/p2771-0000-000_defconfig
|
||||
@@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
+CONFIG_POSITION_INDEPENDENT=y
|
||||
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
|
||||
index 1a14a92..0803b26 100644
|
||||
--- a/configs/p2771-0000-500_defconfig
|
||||
+++ b/configs/p2771-0000-500_defconfig
|
||||
@@ -36,3 +36,4 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
+CONFIG_POSITION_INDEPENDENT=y
|
||||
|
||||
From patchwork Thu Mar 26 22:20:44 2020
|
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id <B5e7d2ac00005>; Thu, 26 Mar 2020 15:20:48 -0700
|
||||
From: <tomcwarren3959@gmail.com>
|
||||
To: <u-boot@lists.denx.de>
|
||||
CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
||||
<twarren@nvidia.com>, <vishruthj@nvidia.com>
|
||||
Subject: [PATCH 2/3] fdt: Fix 'system' command
|
||||
Date: Thu, 26 Mar 2020 15:20:44 -0700
|
||||
Message-ID: <1585261245-1740-3-git-send-email-tomcwarren3959@gmail.com>
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From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
'fdt systemsetup' wasn't working, due to the fact that the 'set' command
|
||||
was being parsed in do_fdt() by only testing for the leading 's' instead
|
||||
of "se", which kept the "sys" test further down from executing. Changed
|
||||
to test for "se" instead, now 'fdt systemsetup' works (to test the
|
||||
ft_system_setup proc w/o having to boot a kernel).
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
cmd/fdt.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/cmd/fdt.c b/cmd/fdt.c
|
||||
index 25a6ed4..36cc726 100644
|
||||
--- a/cmd/fdt.c
|
||||
+++ b/cmd/fdt.c
|
||||
@@ -286,7 +286,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
/*
|
||||
* Set the value of a property in the working_fdt.
|
||||
*/
|
||||
- } else if (argv[1][0] == 's') {
|
||||
+ } else if (strncmp(argv[1], "se", 2) == 0) {
|
||||
char *pathp; /* path */
|
||||
char *prop; /* property */
|
||||
int nodeoffset; /* node offset from libfdt */
|
||||
|
||||
From patchwork Thu Mar 26 22:20:45 2020
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Content-Type: text/plain; charset="utf-8"
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X-Patchwork-Submitter: Tom Warren <tomcwarren3959@gmail.com>
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X-Patchwork-Id: 1262379
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X-Patchwork-Delegate: twarren@nvidia.com
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From: <tomcwarren3959@gmail.com>
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To: <u-boot@lists.denx.de>
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
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<twarren@nvidia.com>, <vishruthj@nvidia.com>
|
||||
Subject: [PATCH 3/3] ARM: tegra: p2371-2180: add I2C nodes to DT
|
||||
Date: Thu, 26 Mar 2020 15:20:45 -0700
|
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Message-ID: <1585261245-1740-4-git-send-email-tomcwarren3959@gmail.com>
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|
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From: Stephen Warren <swarren@nvidia.com>
|
||||
|
||||
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
|
||||
camera board EEPROM, etc. With this change, you can now probe all I2C devices
|
||||
on a TX1 board.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
arch/arm/dts/tegra210-p2371-2180.dts | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts
|
||||
index c2f497c..d982b5f 100644
|
||||
--- a/arch/arm/dts/tegra210-p2371-2180.dts
|
||||
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
|
||||
@@ -12,6 +12,9 @@
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000d000";
|
||||
+ i2c2 = "/i2c@7000c400";
|
||||
+ i2c3 = "/i2c@7000c500";
|
||||
+ i2c5 = "/i2c@546c0c00";
|
||||
mmc0 = "/sdhci@700b0600";
|
||||
mmc1 = "/sdhci@700b0000";
|
||||
usb0 = "/usb@7d000000";
|
||||
@@ -33,6 +36,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ i2c@546c0c00 {
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <400000>;
|
||||
+ };
|
||||
+
|
||||
padctl@7009f000 {
|
||||
pinctrl-0 = <&padctl_default>;
|
||||
pinctrl-names = "default";
|
||||
@@ -85,6 +93,16 @@
|
||||
non-removable;
|
||||
};
|
||||
|
||||
+ i2c@7000c400 {
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <400000>;
|
||||
+ };
|
||||
+
|
||||
+ i2c@7000c500 {
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <400000>;
|
||||
+ };
|
||||
+
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
@ -0,0 +1,55 @@
|
||||
From a63eb1bdcd25246b2c637c7846917dc6dc607725 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Robinson <pbrobinson@gmail.com>
|
||||
Date: Thu, 18 Apr 2019 15:44:59 +0100
|
||||
Subject: [PATCH] add BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 because tx2
|
||||
variants
|
||||
|
||||
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
||||
---
|
||||
include/config_distro_bootcmd.h | 2 ++
|
||||
include/configs/tegra186-common.h | 7 ++++++-
|
||||
2 files changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
|
||||
index fc0935fa21..fd1c5f5afa 100644
|
||||
--- a/include/config_distro_bootcmd.h
|
||||
+++ b/include/config_distro_bootcmd.h
|
||||
@@ -118,8 +118,10 @@
|
||||
"setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \
|
||||
"fi; "
|
||||
#else
|
||||
+#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK
|
||||
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
|
||||
#endif
|
||||
+#endif
|
||||
|
||||
|
||||
#define BOOTENV_SHARED_EFI \
|
||||
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
|
||||
index 5c3ad35c76..d5f21e0907 100644
|
||||
--- a/include/configs/tegra186-common.h
|
||||
+++ b/include/configs/tegra186-common.h
|
||||
@@ -20,6 +20,12 @@
|
||||
/* Generic Interrupt Controller */
|
||||
#define CONFIG_GICV2
|
||||
|
||||
+#undef FDTFILE
|
||||
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
|
||||
+ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
|
||||
+ "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \
|
||||
+ "fi; "
|
||||
+
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
@@ -49,7 +55,6 @@
|
||||
"scriptaddr=0x90000000\0" \
|
||||
"pxefile_addr_r=0x90100000\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
- "fdtfile=" FDTFILE "\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
|
||||
--
|
||||
2.26.0
|
||||
|
@ -1,7 +1,12 @@
|
||||
From 1e93c98419e6a1ea62ef697ed915617024eb6da0 Mon Sep 17 00:00:00 2001
|
||||
From ce2493a9dec8af2dd57839e337b002d256d2a842 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Robinson <pbrobinson@gmail.com>
|
||||
Date: Thu, 18 Apr 2019 14:03:33 +0100
|
||||
Subject: [PATCH] arm: tegra: defaine fdtfile for all devices
|
||||
Date: Tue, 31 Mar 2020 10:38:41 +0100
|
||||
Subject: [PATCH] arm: tegra: define fdtfile option for distro boot
|
||||
|
||||
For booting via UEFI we need to define the fdtfile option so
|
||||
bootefi has the option to load a fdtfile from disk. For arm64
|
||||
the kernel dtb is located in a vendor directory so we define
|
||||
that as nvidia for that architecture.
|
||||
|
||||
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
||||
---
|
||||
@ -15,10 +20,10 @@ Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
||||
7 files changed, 12 insertions(+)
|
||||
|
||||
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
|
||||
index 84f671d00c..c3e16d8cfc 100644
|
||||
index f2cdd9c019..997b50394b 100644
|
||||
--- a/include/configs/tegra-common.h
|
||||
+++ b/include/configs/tegra-common.h
|
||||
@@ -56,6 +56,12 @@
|
||||
@@ -55,6 +55,12 @@
|
||||
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
|
||||
|
||||
@ -32,7 +37,7 @@ index 84f671d00c..c3e16d8cfc 100644
|
||||
* Physical Memory Map
|
||||
*/
|
||||
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
|
||||
index 1aa4412645..0c44a7673b 100644
|
||||
index d3a7045697..9d751b6740 100644
|
||||
--- a/include/configs/tegra114-common.h
|
||||
+++ b/include/configs/tegra114-common.h
|
||||
@@ -50,6 +50,7 @@
|
||||
@ -44,7 +49,7 @@ index 1aa4412645..0c44a7673b 100644
|
||||
"ramdisk_addr_r=0x83100000\0"
|
||||
|
||||
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
|
||||
index 3530684164..29da06c8f7 100644
|
||||
index 522993b958..0eb8f92809 100644
|
||||
--- a/include/configs/tegra124-common.h
|
||||
+++ b/include/configs/tegra124-common.h
|
||||
@@ -52,6 +52,7 @@
|
||||
@ -68,7 +73,7 @@ index b4936cc731..5c3ad35c76 100644
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
|
||||
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
|
||||
index e58477e289..73c94d993b 100644
|
||||
index 1e31d82574..fdd8996955 100644
|
||||
--- a/include/configs/tegra20-common.h
|
||||
+++ b/include/configs/tegra20-common.h
|
||||
@@ -51,6 +51,7 @@
|
||||
@ -80,7 +85,7 @@ index e58477e289..73c94d993b 100644
|
||||
"ramdisk_addr_r=0x03100000\0"
|
||||
|
||||
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
|
||||
index 1c533118ad..69e446ed58 100644
|
||||
index 1b8e94b60c..2226effe16 100644
|
||||
--- a/include/configs/tegra210-common.h
|
||||
+++ b/include/configs/tegra210-common.h
|
||||
@@ -46,6 +46,7 @@
|
||||
@ -88,11 +93,11 @@ index 1c533118ad..69e446ed58 100644
|
||||
"pxefile_addr_r=0x90100000\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
+ "fdtfile=" FDTFILE "\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
"fdt_addr_r=0x83000000\0" \
|
||||
"ramdisk_addr_r=0x83200000\0"
|
||||
|
||||
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
|
||||
index 2d8948d9d9..27696009cd 100644
|
||||
index 54bc6756ab..6c5dc24b26 100644
|
||||
--- a/include/configs/tegra30-common.h
|
||||
+++ b/include/configs/tegra30-common.h
|
||||
@@ -47,6 +47,7 @@
|
||||
@ -104,59 +109,5 @@ index 2d8948d9d9..27696009cd 100644
|
||||
"ramdisk_addr_r=0x83100000\0"
|
||||
|
||||
--
|
||||
2.21.0
|
||||
From 267dc15aa8f247362b04387d6a1ab01d94d41aef Mon Sep 17 00:00:00 2001
|
||||
From: Peter Robinson <pbrobinson@gmail.com>
|
||||
Date: Thu, 18 Apr 2019 15:44:59 +0100
|
||||
Subject: [PATCH] add BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 because tx2
|
||||
variants
|
||||
|
||||
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
||||
---
|
||||
include/config_distro_bootcmd.h | 2 ++
|
||||
include/configs/tegra186-common.h | 7 ++++++-
|
||||
2 files changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
|
||||
index 4993303f4d..cd317bb457 100644
|
||||
--- a/include/config_distro_bootcmd.h
|
||||
+++ b/include/config_distro_bootcmd.h
|
||||
@@ -118,8 +118,10 @@
|
||||
"setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \
|
||||
"fi; "
|
||||
#else
|
||||
+#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK
|
||||
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
|
||||
#endif
|
||||
+#endif
|
||||
|
||||
|
||||
#define BOOTENV_SHARED_EFI \
|
||||
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
|
||||
index 5c3ad35c76..d5f21e0907 100644
|
||||
--- a/include/configs/tegra186-common.h
|
||||
+++ b/include/configs/tegra186-common.h
|
||||
@@ -20,6 +20,12 @@
|
||||
/* Generic Interrupt Controller */
|
||||
#define CONFIG_GICV2
|
||||
|
||||
+#undef FDTFILE
|
||||
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
|
||||
+ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
|
||||
+ "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \
|
||||
+ "fi; "
|
||||
+
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
@@ -49,7 +55,6 @@
|
||||
"scriptaddr=0x90000000\0" \
|
||||
"pxefile_addr_r=0x90100000\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
- "fdtfile=" FDTFILE "\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
|
||||
--
|
||||
2.21.0
|
||||
2.26.0
|
||||
|
461
mmc-t210-fix-autocal-and-400KHz-clock.patch
Normal file
461
mmc-t210-fix-autocal-and-400KHz-clock.patch
Normal file
@ -0,0 +1,461 @@
|
||||
From patchwork Thu Mar 26 22:30:21 2020
|
||||
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|
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|
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X-Patchwork-Id: 1262385
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
|
||||
<twarren@nvidia.com>, <jh80.chung@samsung.com>
|
||||
Subject: [PATCH 1/2] mmc: t210: Add autocal and tap/trim updates for SDMMC1/3
|
||||
Date: Thu, 26 Mar 2020 15:30:21 -0700
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|
||||
From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
|
||||
autocal values need to be set to condition the signals correctly before
|
||||
talking to the SD-card. This is the same as what's being done in CBoot,
|
||||
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
|
||||
init, so needs to be repeated here. Also set autocal and tap/trim for
|
||||
SDMMC3, although no T210 boards use it for SD-card at this time.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
Changes for v2:
|
||||
- Added clocks.h include for TEGRA30 to fix T30 32-bit builds
|
||||
|
||||
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 20 +++++--
|
||||
drivers/mmc/tegra_mmc.c | 84 ++++++++++++++++++++++++++---
|
||||
2 files changed, 92 insertions(+), 12 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
||||
index a2b6f63..a8bfa46 100644
|
||||
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
||||
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* (C) Copyright 2009 SAMSUNG Electronics
|
||||
* Minkyu Kang <mk7.kang@samsung.com>
|
||||
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
|
||||
+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA_MMC_H_
|
||||
@@ -52,7 +52,7 @@ struct tegra_mmc {
|
||||
unsigned char admaerr; /* offset 54h */
|
||||
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
|
||||
unsigned long admaaddr; /* offset 58h-5Fh */
|
||||
- unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
|
||||
+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
|
||||
unsigned short slotintstatus; /* offset FCh */
|
||||
unsigned short hcver; /* HOST Version */
|
||||
unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
|
||||
@@ -127,11 +127,23 @@ struct tegra_mmc {
|
||||
|
||||
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
|
||||
|
||||
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
|
||||
+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
|
||||
#define MEMCOMP_PADCTRL_VREF 7
|
||||
-#define AUTO_CAL_ENABLED (1 << 29)
|
||||
+#define AUTO_CAL_ENABLE (1 << 29)
|
||||
+#if defined(CONFIG_TEGRA210)
|
||||
+#define AUTO_CAL_ACTIVE (1 << 31)
|
||||
+#define AUTO_CAL_START (1 << 31)
|
||||
+#define AUTO_CAL_PD_OFFSET (0x7D << 8)
|
||||
+#define AUTO_CAL_PU_OFFSET (0 << 0)
|
||||
+#define IO_TRIM_BYPASS_MASK (1 << 2)
|
||||
+#define TRIM_VAL_SHIFT 24
|
||||
+#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
|
||||
+#define TAP_VAL_SHIFT 16
|
||||
+#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
|
||||
+#else
|
||||
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
|
||||
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
|
||||
+#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __TEGRA_MMC_H_ */
|
||||
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
|
||||
index f022e93..73ac58c 100644
|
||||
--- a/drivers/mmc/tegra_mmc.c
|
||||
+++ b/drivers/mmc/tegra_mmc.c
|
||||
@@ -3,7 +3,7 @@
|
||||
* (C) Copyright 2009 SAMSUNG Electronics
|
||||
* Minkyu Kang <mk7.kang@samsung.com>
|
||||
* Jaehoon Chung <jh80.chung@samsung.com>
|
||||
- * Portions Copyright 2011-2016 NVIDIA Corporation
|
||||
+ * Portions Copyright 2011-2019 NVIDIA Corporation
|
||||
*/
|
||||
|
||||
#include <bouncebuf.h>
|
||||
@@ -15,6 +15,9 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-tegra/tegra_mmc.h>
|
||||
#include <linux/err.h>
|
||||
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
|
||||
+#include <asm/arch/clock.h>
|
||||
+#endif
|
||||
|
||||
struct tegra_mmc_plat {
|
||||
struct mmc_config cfg;
|
||||
@@ -30,6 +33,7 @@ struct tegra_mmc_priv {
|
||||
struct gpio_desc wp_gpio; /* Write Protect GPIO */
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
+ int mmc_id; /* peripheral id */
|
||||
};
|
||||
|
||||
static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
|
||||
@@ -446,16 +450,19 @@ static int tegra_mmc_set_ios(struct udevice *dev)
|
||||
|
||||
static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
|
||||
{
|
||||
-#if defined(CONFIG_TEGRA30)
|
||||
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
|
||||
u32 val;
|
||||
+ u16 clk_con;
|
||||
+ int timeout;
|
||||
+ int id = priv->mmc_id;
|
||||
|
||||
- debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
|
||||
+ debug("%s: sdmmc address = %p, id = %d\n", __func__,
|
||||
+ priv->reg, id);
|
||||
|
||||
/* Set the pad drive strength for SDMMC1 or 3 only */
|
||||
- if (priv->reg != (void *)0x78000000 &&
|
||||
- priv->reg != (void *)0x78000400) {
|
||||
+ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
|
||||
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
|
||||
- __func__);
|
||||
+ __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -464,11 +471,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
|
||||
val |= MEMCOMP_PADCTRL_VREF;
|
||||
writel(val, &priv->reg->sdmemcmppadctl);
|
||||
|
||||
+ /* Disable SD Clock Enable before running auto-cal as per TRM */
|
||||
+ clk_con = readw(&priv->reg->clkcon);
|
||||
+ debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
|
||||
+ clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
|
||||
+ writew(clk_con, &priv->reg->clkcon);
|
||||
+
|
||||
val = readl(&priv->reg->autocalcfg);
|
||||
val &= 0xFFFF0000;
|
||||
- val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
|
||||
+ val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
|
||||
writel(val, &priv->reg->autocalcfg);
|
||||
-#endif
|
||||
+ val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
|
||||
+ writel(val, &priv->reg->autocalcfg);
|
||||
+ debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
|
||||
+ udelay(1);
|
||||
+ timeout = 100; /* 10 mSec max (100*100uS) */
|
||||
+ do {
|
||||
+ val = readl(&priv->reg->autocalsts);
|
||||
+ udelay(100);
|
||||
+ } while ((val & AUTO_CAL_ACTIVE) && --timeout);
|
||||
+ val = readl(&priv->reg->autocalsts);
|
||||
+ debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
|
||||
+ __func__, val, timeout);
|
||||
+
|
||||
+ /* Re-enable SD Clock Enable when auto-cal is done */
|
||||
+ clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
|
||||
+ writew(clk_con, &priv->reg->clkcon);
|
||||
+ clk_con = readw(&priv->reg->clkcon);
|
||||
+ debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
|
||||
+
|
||||
+ if (timeout == 0) {
|
||||
+ printf("%s: Warning: Autocal timed out!\n", __func__);
|
||||
+ /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
|
||||
+ }
|
||||
+
|
||||
+#if defined(CONFIG_TEGRA210)
|
||||
+ u32 tap_value, trim_value;
|
||||
+
|
||||
+ /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
|
||||
+ val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
|
||||
+ val &= IO_TRIM_BYPASS_MASK;
|
||||
+ if (id == PERIPH_ID_SDMMC1) {
|
||||
+ tap_value = 4; /* default */
|
||||
+ if (val)
|
||||
+ tap_value = 3;
|
||||
+ trim_value = 2;
|
||||
+ } else { /* SDMMC3 */
|
||||
+ tap_value = 3;
|
||||
+ trim_value = 3;
|
||||
+ }
|
||||
+
|
||||
+ val = readl(&priv->reg->venclkctl);
|
||||
+ val &= ~TRIM_VAL_MASK;
|
||||
+ val |= (trim_value << TRIM_VAL_SHIFT);
|
||||
+ val &= ~TAP_VAL_MASK;
|
||||
+ val |= (tap_value << TAP_VAL_SHIFT);
|
||||
+ writel(val, &priv->reg->venclkctl);
|
||||
+ debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
|
||||
+#endif /* T210 */
|
||||
+#endif /* T30/T210 */
|
||||
}
|
||||
|
||||
static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
|
||||
@@ -514,6 +575,13 @@ static int tegra_mmc_init(struct udevice *dev)
|
||||
unsigned int mask;
|
||||
debug(" tegra_mmc_init called\n");
|
||||
|
||||
+#if defined(CONFIG_TEGRA210)
|
||||
+ priv->mmc_id = clock_decode_periph_id(dev);
|
||||
+ if (priv->mmc_id == PERIPH_ID_NONE) {
|
||||
+ printf("%s: Missing/invalid peripheral ID\n", __func__);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+#endif
|
||||
tegra_mmc_reset(priv, mmc);
|
||||
|
||||
#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
|
||||
|
||||
From patchwork Thu Mar 26 22:30:22 2020
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|
||||
Subject: [PATCH 2/2] mmc: t210: Fix 'bad' SD-card clock when doing 400KHz
|
||||
card detect
|
||||
Date: Thu, 26 Mar 2020 15:30:22 -0700
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From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
According to the HW team, for some reason the normal clock select code
|
||||
picks what appears to be a perfectly valid 375KHz SD card clock, based
|
||||
on the CAR clock source and SDMMC1 controller register settings (CAR =
|
||||
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
|
||||
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
|
||||
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
|
||||
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
|
||||
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
|
||||
T210 when the requested clock is <= 400KHz. Note that as far as I can
|
||||
tell, the other requests for clocks in the Tegra MMC driver result in
|
||||
valid SD clocks.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
Changes for v2:
|
||||
- None
|
||||
|
||||
arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 +-
|
||||
drivers/mmc/tegra_mmc.c | 18 ++++++++++++++++++
|
||||
2 files changed, 19 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
||||
index a8bfa46..70dcf4a 100644
|
||||
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
||||
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
|
||||
@@ -130,9 +130,9 @@ struct tegra_mmc {
|
||||
/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
|
||||
#define MEMCOMP_PADCTRL_VREF 7
|
||||
#define AUTO_CAL_ENABLE (1 << 29)
|
||||
-#if defined(CONFIG_TEGRA210)
|
||||
#define AUTO_CAL_ACTIVE (1 << 31)
|
||||
#define AUTO_CAL_START (1 << 31)
|
||||
+#if defined(CONFIG_TEGRA210)
|
||||
#define AUTO_CAL_PD_OFFSET (0x7D << 8)
|
||||
#define AUTO_CAL_PU_OFFSET (0 << 0)
|
||||
#define IO_TRIM_BYPASS_MASK (1 << 2)
|
||||
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
|
||||
index 73ac58c..03110ba 100644
|
||||
--- a/drivers/mmc/tegra_mmc.c
|
||||
+++ b/drivers/mmc/tegra_mmc.c
|
||||
@@ -376,6 +376,24 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
|
||||
|
||||
rate = clk_set_rate(&priv->clk, clock);
|
||||
div = (rate + clock - 1) / clock;
|
||||
+
|
||||
+#if defined(CONFIG_TEGRA210)
|
||||
+ if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
|
||||
+ /* clock_adjust_periph_pll_div() chooses a 'bad' clock
|
||||
+ * on SDMMC1 T210, so skip it here and force a clock
|
||||
+ * that's been spec'd in the table in the TRM for
|
||||
+ * card-detect (400KHz).
|
||||
+ */
|
||||
+ uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
|
||||
+ CLOCK_ID_PERIPH, 24727273, NULL);
|
||||
+ div = 62;
|
||||
+
|
||||
+ debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
|
||||
+ __func__, effective_rate, div, clock);
|
||||
+ } else
|
||||
+ clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, clock,
|
||||
+ &div);
|
||||
+#endif
|
||||
debug("div = %d\n", div);
|
||||
|
||||
writew(0, &priv->reg->clkcon);
|
116
mtd-spi-Add-Macronix-MX25U3235F-device.patch
Normal file
116
mtd-spi-Add-Macronix-MX25U3235F-device.patch
Normal file
@ -0,0 +1,116 @@
|
||||
From patchwork Thu Mar 26 21:59:01 2020
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|
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|
||||
Subject: [PATCH] mtd: spi: Add Macronix MX25U3235F device
|
||||
Date: Thu, 26 Mar 2020 14:59:01 -0700
|
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Message-ID: <1585259941-28879-1-git-send-email-tomcwarren3959@gmail.com>
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From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
Add Macronix MX25U3235F flash device description.
|
||||
This is a 4MiB part.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
drivers/mtd/spi/spi-nor-ids.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
|
||||
index 973b6f8..abdf560 100644
|
||||
--- a/drivers/mtd/spi/spi-nor-ids.c
|
||||
+++ b/drivers/mtd/spi/spi-nor-ids.c
|
||||
@@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = {
|
||||
{ INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
|
||||
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
|
||||
+ { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
|
||||
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
|
||||
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
|
310
net-tegra-Misc-network-fixes.patch
Normal file
310
net-tegra-Misc-network-fixes.patch
Normal file
@ -0,0 +1,310 @@
|
||||
From patchwork Thu Mar 26 22:59:13 2020
|
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<twarren@nvidia.com>, <joe.hershberger@ni.com>
|
||||
Subject: [PATCH 1/2] net: rt8169: WAR for DHCP not getting IP after kernel
|
||||
boot/reboot
|
||||
Date: Thu, 26 Mar 2020 15:59:13 -0700
|
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|
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|
||||
From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
This is a WAR for DHCP failure after rebooting from the L4T kernel. The
|
||||
r8169.c kernel driver is setting bit 19 of the rt816x HW register 0xF0,
|
||||
which goes by FuncEvent and MISC in various driver source/datasheets.
|
||||
That bit is called RxDv_Gated_En in the r8169.c kernel driver. Clear it
|
||||
here at the end of probe to ensure that U-Boot can get an IP assigned
|
||||
via DHCP.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
drivers/net/rtl8169.c | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
|
||||
index 5ccdfdd..ff89e28 100644
|
||||
--- a/drivers/net/rtl8169.c
|
||||
+++ b/drivers/net/rtl8169.c
|
||||
@@ -237,6 +237,9 @@ enum RTL8169_register_content {
|
||||
|
||||
/*_TBICSRBit*/
|
||||
TBILinkOK = 0x02000000,
|
||||
+
|
||||
+ /* FuncEvent/Misc */
|
||||
+ RxDv_Gated_En = 0x80000,
|
||||
};
|
||||
|
||||
static struct {
|
||||
@@ -1207,6 +1210,19 @@ static int rtl8169_eth_probe(struct udevice *dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * WAR for DHCP failure after rebooting from kernel.
|
||||
+ * Clear RxDv_Gated_En bit which was set by kernel driver.
|
||||
+ * Without this, U-Boot can't get an IP via DHCP.
|
||||
+ * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
|
||||
+ * the r8169.c kernel driver.
|
||||
+ */
|
||||
+
|
||||
+ u32 val = RTL_R32(FuncEvent);
|
||||
+ debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
|
||||
+ val &= ~RxDv_Gated_En;
|
||||
+ RTL_W32(FuncEvent, val);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
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From patchwork Thu Mar 26 22:59:14 2020
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|
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|
||||
Subject: [PATCH 2/2] tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all
|
||||
Jetson boards
|
||||
Date: Thu, 26 Mar 2020 15:59:14 -0700
|
||||
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|
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|
||||
|
||||
From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
This allows the user to set $serverip in the environment before
|
||||
executing a DHCP request. If they do, U-Boot will use that IP rather
|
||||
than using the IP in the DHCP response.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
Acked-by: Stephen Warren <swarren@nvidia.com>
|
||||
---
|
||||
configs/e2220-1170_defconfig | 1 +
|
||||
configs/p2371-0000_defconfig | 1 +
|
||||
configs/p2371-2180_defconfig | 1 +
|
||||
configs/p2571_defconfig | 1 +
|
||||
configs/p2771-0000-000_defconfig | 1 +
|
||||
configs/p2771-0000-500_defconfig | 1 +
|
||||
6 files changed, 6 insertions(+)
|
||||
|
||||
diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig
|
||||
index 1639040..951ed1d 100644
|
||||
--- a/configs/e2220-1170_defconfig
|
||||
+++ b/configs/e2220-1170_defconfig
|
||||
@@ -43,3 +43,4 @@ CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
|
||||
index 2070199..7081719 100644
|
||||
--- a/configs/p2371-0000_defconfig
|
||||
+++ b/configs/p2371-0000_defconfig
|
||||
@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
|
||||
index 8c808ae..c70217c 100644
|
||||
--- a/configs/p2371-2180_defconfig
|
||||
+++ b/configs/p2371-2180_defconfig
|
||||
@@ -52,3 +52,4 @@ CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
|
||||
index 721c5c5..43c24b8 100644
|
||||
--- a/configs/p2571_defconfig
|
||||
+++ b/configs/p2571_defconfig
|
||||
@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
|
||||
index e347a77..8bf8419 100644
|
||||
--- a/configs/p2771-0000-000_defconfig
|
||||
+++ b/configs/p2771-0000-000_defconfig
|
||||
@@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
|
||||
index 0803b26..1f40333 100644
|
||||
--- a/configs/p2771-0000-500_defconfig
|
||||
+++ b/configs/p2771-0000-500_defconfig
|
||||
@@ -37,3 +37,4 @@ CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
+CONFIG_BOOTP_PREFER_SERVERIP=y
|
453
qspi-t210-fix-claim_bus-and-clock-tap-delays.patch
Normal file
453
qspi-t210-fix-claim_bus-and-clock-tap-delays.patch
Normal file
@ -0,0 +1,453 @@
|
||||
From patchwork Thu Mar 26 22:42:00 2020
|
||||
Content-Type: text/plain; charset="utf-8"
|
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|
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X-Patchwork-Submitter: Tom Warren <tomcwarren3959@gmail.com>
|
||||
X-Patchwork-Id: 1262404
|
||||
X-Patchwork-Delegate: twarren@nvidia.com
|
||||
Return-Path: <u-boot-bounces@lists.denx.de>
|
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Subject: [PATCH 1/3] qspi: t210: Fix claim_bus's use of the wrong bus/device
|
||||
Date: Thu, 26 Mar 2020 15:42:00 -0700
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Message-ID: <1585262522-6127-2-git-send-email-tomcwarren3959@gmail.com>
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From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
claim_bus() is passed a udevice *dev, which is the bus device's parent.
|
||||
In this driver, claim_bus assumed it was the bus, which caused the
|
||||
'priv' info pointer to be wrong, and periph_id was incorrect. This in
|
||||
turn caused the periph clock call to assign the wrong clock (PLLM
|
||||
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
|
||||
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
|
||||
working w/this errant clock, but it was moot as QSPI wasn't active
|
||||
unless you probed it, and that wasn't happening until I posted a patch
|
||||
to enable env save to QSPI for Nano (coming soon).
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
Changes in v2:
|
||||
- None
|
||||
|
||||
drivers/spi/tegra210_qspi.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
|
||||
index d82ecaa..2a77126 100644
|
||||
--- a/drivers/spi/tegra210_qspi.c
|
||||
+++ b/drivers/spi/tegra210_qspi.c
|
||||
@@ -2,7 +2,8 @@
|
||||
/*
|
||||
* NVIDIA Tegra210 QSPI controller driver
|
||||
*
|
||||
- * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
|
||||
+ * (C) Copyright 2015-2019 NVIDIA Corporation <www.nvidia.com>
|
||||
+ *
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@@ -137,8 +138,9 @@ static int tegra210_qspi_probe(struct udevice *bus)
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int tegra210_qspi_claim_bus(struct udevice *bus)
|
||||
+static int tegra210_qspi_claim_bus(struct udevice *dev)
|
||||
{
|
||||
+ struct udevice *bus = dev->parent;
|
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
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struct qspi_regs *regs = priv->regs;
|
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|
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Subject: [PATCH 2/3] qspi: t210: Fix QSPI clock and tap delays
|
||||
Date: Thu, 26 Mar 2020 15:42:01 -0700
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Message-ID: <1585262522-6127-3-git-send-email-tomcwarren3959@gmail.com>
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From: Tom Warren <twarren@nvidia.com>
|
||||
|
||||
When claim_bus was setting the clock, it reset the QSPI controller,
|
||||
which wipes out any tap delays set by previous bootloaders (nvtboot,
|
||||
CBoot for example on Nano). Instead of doing that in claim_bus, which
|
||||
gets called a lot, moved clock setting to probe(), and set tap delays
|
||||
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
|
||||
save works reliably again.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
Changes in v2:
|
||||
- None
|
||||
|
||||
drivers/spi/tegra210_qspi.c | 19 ++++++++++++-------
|
||||
1 file changed, 12 insertions(+), 7 deletions(-)
|
||||
|
||||
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
|
||||
index 2a77126..4284ea9 100644
|
||||
--- a/drivers/spi/tegra210_qspi.c
|
||||
+++ b/drivers/spi/tegra210_qspi.c
|
||||
@@ -42,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#define QSPI_CMD1_BITLEN_SHIFT 0
|
||||
|
||||
/* COMMAND2 */
|
||||
-#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
|
||||
-#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
|
||||
-#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
|
||||
-#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
|
||||
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
|
||||
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
|
||||
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
|
||||
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
|
||||
|
||||
/* TRANSFER STATUS */
|
||||
#define QSPI_XFER_STS_RDY BIT(30)
|
||||
@@ -127,14 +127,22 @@ static int tegra210_qspi_probe(struct udevice *bus)
|
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
priv->regs = (struct qspi_regs *)plat->base;
|
||||
+ struct qspi_regs *regs = priv->regs;
|
||||
|
||||
priv->last_transaction_us = timer_get_us();
|
||||
priv->freq = plat->frequency;
|
||||
priv->periph_id = plat->periph_id;
|
||||
|
||||
+ debug("%s: Freq = %u, id = %d\n", __func__, priv->freq, priv->periph_id);
|
||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
||||
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
|
||||
|
||||
+ /* Set tap delays here, clock change above resets QSPI controller */
|
||||
+ u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
|
||||
+ (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
|
||||
+ writel(reg, ®s->command2);
|
||||
+ debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2));
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -144,9 +152,6 @@ static int tegra210_qspi_claim_bus(struct udevice *dev)
|
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
||||
struct qspi_regs *regs = priv->regs;
|
||||
|
||||
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
||||
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
|
||||
-
|
||||
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
|
||||
|
||||
/* Set master mode and sw controlled CS */
|
||||
|
||||
From patchwork Thu Mar 26 22:42:02 2020
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CC: <swarren@nvidia.com>, <treding@nvidia.com>, <jonathanh@nvidia.com>,
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<twarren@nvidia.com>, <jagan@amarulasolutions.com>
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Subject: [PATCH 3/3] qspi: t210: Use dev_read calls to get FDT data like
|
||||
base, freq
|
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Date: Thu, 26 Mar 2020 15:42:02 -0700
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From: Tom Warren <twarren@nvidia.com>
|
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|
||||
This Tegra QSPI driver hadn't been brought up to date with how
|
||||
DM drivers are fetching data from the FDT now, and was pulling
|
||||
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
|
||||
to work the same way it does in the tegra114 SPI driver, using
|
||||
dev_read_ functions.
|
||||
|
||||
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
||||
---
|
||||
Changes in v2:
|
||||
- New
|
||||
|
||||
drivers/spi/tegra210_qspi.c | 10 ++++------
|
||||
1 file changed, 4 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
|
||||
index 4284ea9..466d572 100644
|
||||
--- a/drivers/spi/tegra210_qspi.c
|
||||
+++ b/drivers/spi/tegra210_qspi.c
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* NVIDIA Tegra210 QSPI controller driver
|
||||
*
|
||||
- * (C) Copyright 2015-2019 NVIDIA Corporation <www.nvidia.com>
|
||||
+ * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
*/
|
||||
|
||||
@@ -97,10 +97,8 @@ struct tegra210_qspi_priv {
|
||||
static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
|
||||
{
|
||||
struct tegra_spi_platdata *plat = bus->platdata;
|
||||
- const void *blob = gd->fdt_blob;
|
||||
- int node = dev_of_offset(bus);
|
||||
|
||||
- plat->base = devfdt_get_addr(bus);
|
||||
+ plat->base = dev_read_addr(bus);
|
||||
plat->periph_id = clock_decode_periph_id(bus);
|
||||
|
||||
if (plat->periph_id == PERIPH_ID_NONE) {
|
||||
@@ -110,9 +108,9 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
|
||||
}
|
||||
|
||||
/* Use 500KHz as a suitable default */
|
||||
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
|
||||
500000);
|
||||
- plat->deactivate_delay_us = fdtdec_get_int(blob, node,
|
||||
+ plat->deactivate_delay_us = dev_read_u32_default(bus,
|
||||
"spi-deactivate-delay", 0);
|
||||
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
|
||||
__func__, plat->base, plat->periph_id, plat->frequency,
|
2026
t210-miscellaneous-patches.patch
Normal file
2026
t210-miscellaneous-patches.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -24,8 +24,17 @@ Patch2: uefi-use-Fedora-specific-path-name.patch
|
||||
Patch4: usb-kbd-fixes.patch
|
||||
Patch5: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
|
||||
Patch6: dragonboard-fixes.patch
|
||||
Patch7: ARM-tegra-Add-NVIDIA-Jetson-Nano.patch
|
||||
Patch8: arm-tegra-defaine-fdtfile-for-all-devices.patch
|
||||
|
||||
Patch10: mtd-spi-Add-Macronix-MX25U3235F-device.patch
|
||||
Patch11: Misc-fixes-for-Tegra.patch
|
||||
Patch12: mmc-t210-fix-autocal-and-400KHz-clock.patch
|
||||
Patch13: qspi-t210-fix-claim_bus-and-clock-tap-delays.patch
|
||||
Patch14: net-tegra-Misc-network-fixes.patch
|
||||
Patch15: t210-miscellaneous-patches.patch
|
||||
# http://patchwork.ozlabs.org/patch/1261582/
|
||||
Patch16: ARM-tegra-Add-NVIDIA-Jetson-Nano.patch
|
||||
Patch17: arm-tegra-define-fdtfile-option-for-distro-boot.patch
|
||||
Patch18: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch
|
||||
|
||||
BuildRequires: bc
|
||||
BuildRequires: dtc
|
||||
@ -249,6 +258,7 @@ cp -p board/warp7/README builds/docs/README.warp7
|
||||
%changelog
|
||||
* Tue Mar 31 2020 Peter Robinson <pbrobinson@fedoraproject.org> 2020.04-0.6-rc4
|
||||
- 2020.04 RC4
|
||||
- Updates for NVIDIA Jetson platforms
|
||||
|
||||
* Thu Mar 26 2020 Peter Robinson <pbrobinson@fedoraproject.org> 2020.04-0.5-rc3
|
||||
- Fix ext4 alignment issue seen on some NXP i.MX devices
|
||||
|
Loading…
Reference in New Issue
Block a user