add hyp support to cubietruck image
- enables kvm support
This commit is contained in:
Dennis Gilmore
parent
1619496436
commit
3ed96a195b
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@ -0,0 +1,31 @@
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From 007880c8871c9d7a87fa61017c5ce3f7040c38bb Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <marc.zyngier@arm.com>
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Date: Sat, 7 Dec 2013 11:19:16 +0000
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Subject: [PATCH 39/40] sunxi: fix SRAM_B/SRAM_D memory map
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Move the B and D SRAM bank to their actual location (or at least
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where the documentation pretends they are).
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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---
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arch/arm/include/asm/arch-sunxi/cpu.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
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index 7400559..a987e51d 100644
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--- a/arch/arm/include/asm/arch-sunxi/cpu.h
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+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
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@@ -15,8 +15,8 @@
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#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
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#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
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#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
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-#define SUNXI_SRAM_D_BASE 0x01c00000
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-#define SUNXI_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */
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+#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
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+#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
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#define SUNXI_SRAMC_BASE 0x01c00000
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#define SUNXI_DRAMC_BASE 0x01c01000
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--
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1.9.0
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@ -0,0 +1,227 @@
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From 1c257eac296e162e8c445796ef1bfb3e4095d7ba Mon Sep 17 00:00:00 2001
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From: Dennis Gilmore <dennis@ausil.us>
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Date: Sat, 26 Apr 2014 23:35:09 -0500
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Subject: [PATCH 40/40] sunxi: add hyp support on sun7i roll 2 patches sent
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upstream into one
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sunxi: HYP/non-sec: add sun7i PSCI backend
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So far, only supporting the CPU_ON method.
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Other functions can be added later.
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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sunxi: HYP/non-sec: configure CNTFRQ on all CPUs
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CNTFRQ needs to be properly configured on all CPUs. Otherwise,
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virtual machines hoping to find valuable information on secondary
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CPUs will be disapointed...
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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---
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arch/arm/cpu/armv7/sunxi/Makefile | 3 +
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arch/arm/cpu/armv7/sunxi/psci.S | 162 ++++++++++++++++++++++++++++++++++++++
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include/configs/sun7i.h | 7 ++
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3 files changed, 172 insertions(+)
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create mode 100644 arch/arm/cpu/armv7/sunxi/psci.S
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diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
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index a64bfa1..03e49ca 100644
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--- a/arch/arm/cpu/armv7/sunxi/Makefile
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+++ b/arch/arm/cpu/armv7/sunxi/Makefile
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@@ -23,3 +23,6 @@ ifdef CONFIG_SPL_FEL
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obj-y += start.o
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endif
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endif
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+ifdef CONFIG_ARMV7_PSCI
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+obj-y += psci.o
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+endif
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diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
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new file mode 100644
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index 0000000..0084c81
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--- /dev/null
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+++ b/arch/arm/cpu/armv7/sunxi/psci.S
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@@ -0,0 +1,162 @@
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+/*
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+ * Copyright (C) 2013 - ARM Ltd
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+ * Author: Marc Zyngier <marc.zyngier@arm.com>
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+ *
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+ * Based on code by Carl van Schaik <carl@ok-labs.com>.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include <config.h>
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+#include <asm/psci.h>
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+#include <asm/arch/cpu.h>
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+
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+/*
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+ * Memory layout:
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+ *
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+ * SECURE_RAM to text_end :
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+ * ._secure_text section
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+ * text_end to ALIGN_PAGE(text_end):
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+ * nothing
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+ * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
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+ * 1kB of stack per CPU (4 CPUs max).
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+ */
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+
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+ .pushsection ._secure.text, "ax"
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+
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+ .arch_extension sec
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+
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+#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
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+#define TEN_MS (10 * ONE_MS)
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+
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+.macro timer_wait reg, ticks
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+ @ Program CNTP_TVAL
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+ movw \reg, #(\ticks & 0xffff)
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+ movt \reg, #(\ticks >> 16)
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+ mcr p15, 0, \reg, c14, c2, 0
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+ isb
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+ @ Enable physical timer, mask interrupt
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+ mov \reg, #3
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+ mcr p15, 0, \reg, c14, c2, 1
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+ @ Poll physical timer until ISTATUS is on
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+1: isb
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+ mrc p15, 0, \reg, c14, c2, 1
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+ ands \reg, \reg, #4
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+ bne 1b
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+ @ Disable timer
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+ mov \reg, #0
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+ mcr p15, 0, \reg, c14, c2, 1
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+ isb
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+.endm
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+
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+.globl psci_arch_init
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+psci_arch_init:
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+ mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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+ bic r5, r5, #1 @ Secure mode
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+ mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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+ isb
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+
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+ mrc p15, 0, r4, c0, c0, 5 @ MPIDR
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+ and r4, r4, #3 @ cpu number in cluster
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+ mov r5, #400 @ 1kB of stack per CPU
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+ mul r4, r4, r5
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+
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+ adr r5, text_end @ end of text
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+ add r5, r5, #0x2000 @ Skip two pages
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+ lsr r5, r5, #12 @ Align to start of page
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+ lsl r5, r5, #12
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+ sub sp, r5, r4 @ here's our stack!
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+
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+ bx lr
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+
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+ @ r1 = target CPU
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+ @ r2 = target PC
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+.globl psci_cpu_on
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+psci_cpu_on:
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+ adr r0, _target_pc
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+ str r2, [r0]
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+ dsb
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+
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+ movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
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+ movt r0, #(SUNXI_CPUCFG_BASE >> 16)
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+
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+ @ CPU mask
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+ and r1, r1, #3 @ only care about first cluster
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+ mov r4, #1
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+ lsl r4, r4, r1
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+
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+ adr r6, _sunxi_cpu_entry
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+ str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
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+
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+ @ Assert reset on target CPU
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+ mov r6, #0
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+ lsl r5, r1, #6 @ 64 bytes per CPU
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+ add r5, r5, #0x40 @ Offset from base
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+ add r5, r5, r0 @ CPU control block
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+ str r6, [r5] @ Reset CPU
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+
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+ @ l1 invalidate
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+ ldr r6, [r0, #0x184]
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+ bic r6, r6, r4
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+ str r6, [r0, #0x184]
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+
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+ @ Lock CPU
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+ ldr r6, [r0, #0x1e4]
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+ bic r6, r6, r4
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+ str r6, [r0, #0x1e4]
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+
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+ @ Release power clamp
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+ movw r6, #0x1ff
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+ movt r6, #0
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+1: lsrs r6, r6, #1
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+ str r6, [r0, #0x1b0]
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+ bne 1b
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+
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+ timer_wait r1, TEN_MS
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+
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+ @ Clear power gating
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+ ldr r6, [r0, #0x1b4]
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+ bic r6, r6, #1
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+ str r6, [r0, #0x1b4]
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+
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+ @ Deassert reset on target CPU
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+ mov r6, #3
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+ str r6, [r5]
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+
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+ @ Unlock CPU
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+ ldr r6, [r0, #0x1e4]
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+ orr r6, r6, r4
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+ str r6, [r0, #0x1e4]
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+
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+ mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
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+ mov pc, lr
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+
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+_target_pc:
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+ .word 0
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+
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+_sunxi_cpu_entry:
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+ @ Set SMP bit
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+ mrc p15, 0, r0, c1, c0, 1
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+ orr r0, r0, #0x40
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+ mcr p15, 0, r0, c1, c0, 1
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+ isb
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+
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+ bl _nonsec_init
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+ bl psci_arch_init
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+
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+ adr r0, _target_pc
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+ ldr r0, [r0]
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+ b _do_nonsec_entry
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+
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+text_end:
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+ .popsection
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diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
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index 9b693f7..f82431c 100644
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--- a/include/configs/sun7i.h
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+++ b/include/configs/sun7i.h
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@@ -16,6 +16,13 @@
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#define CONFIG_SYS_PROMPT "sun7i# "
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+#define CONFIG_ARMV7_VIRT 1
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+#define CONFIG_ARMV7_NONSEC 1
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+#define CONFIG_ARMV7_PSCI 1
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+#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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+#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
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+#define CONFIG_SYS_CLK_FREQ 24000000
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+
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/*
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* Include common sunxi configuration where most the settings are
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*/
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--
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1.9.0
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@ -2,7 +2,7 @@
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Name: uboot-tools
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Version: 2014.04
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Release: 3%{?candidate:.%{candidate}}%{?dist}
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Release: 4%{?candidate:.%{candidate}}%{?dist}
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Summary: U-Boot utilities
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Group: Development/Tools
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@ -50,6 +50,8 @@ Patch44: 0035-ARM-convert-arch_fixup_memory_node-to-a-generic-FDT-.patch
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Patch45: 0036-ARM-HYP-non-sec-PSCI-emit-DT-nodes.patch
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Patch46: 0037-PXE-syslinux-implenets-some-keywords-found-in-config.patch
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Patch47: 0038-PXE-distros-implementing-syslinux-will-be-using-raw-.patch
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Patch48: 0039-sunxi-fix-SRAM_B-SRAM_D-memory-map.patch
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Patch49: 0040-sunxi-add-hyp-support-on-sun7i.patch
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%ifnarch %{arm}
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BuildRequires: gcc-arm-linux-gnu
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@ -154,6 +156,8 @@ u-boot bootloader binaries for armv7 boards
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%patch45 -p1
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%patch46 -p1
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%patch47 -p1
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%patch48 -p1
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%patch49 -p1
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mkdir builds
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# convert fedora logo to bmp for use in u-boot
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@ -410,6 +414,10 @@ rm -rf $RPM_BUILD_ROOT
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%endif
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%changelog
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* Sat Apr 26 2014 Dennis Gilmore <dennis@ausil.us> - 2014.04-4
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- add hyp support to cubietruck image
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- enables kvm support
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* Thu Apr 24 2014 Dennis Gilmore <dennis@ausil.us> - 2014.04-3
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- add cubietruck u-boot image
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