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Add support for riscv64 

This should provide support for SiFive Unmatched based on meta-sifive
2021.09 release.

One commit was skipped: changing LED to blue color before jumping to
linux in extlinux.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
This commit is contained in:
David Abdurachmanov 2021-10-08 15:04:12 +03:00
parent 6487c37f16
commit 39e079acde
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
11 changed files with 582 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
0001-riscv-SiFive-Unleashed-booti-compressed-kernel-suppo.patch Normal file
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@ -0,0 +1,26 @@
From 664e08aa6f8d989fd9ca4c1c7a2109736f0fd5ac Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:30:49 +0000
Subject: [PATCH 1/9] riscv: SiFive Unleashed booti compressed kernel support
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
include/configs/sifive-unleashed.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index b6c29f8c..db0ebaf9 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -71,6 +71,8 @@
"script_size_f=0x1000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
+ "kernel_comp_addr_r=0x90300000\0" \
+ "kernel_comp_size=0x4000000\0" \
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
--
2.32.0

89
0002-riscv-SiFive-Unmatched-initilize-PWM.patch Normal file
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@ -0,0 +1,89 @@
From 17b935b5f5e580f21838e97ab129d345b46e67b0 Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Fri, 8 Oct 2021 11:43:57 +0000
Subject: [PATCH 2/9] riscv: SiFive Unmatched initilize PWM
The orignal patch:
https://github.com/sifive/meta-sifive/blob/2021.09/recipes-bsp/u-boot/files/riscv64/0010-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
board/sifive/unmatched/spl.c | 2 ++
board/sifive/unmatched/unmatched.c | 48 ++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index d5663274..3c3b22de 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -89,6 +89,8 @@ int spl_board_init_f(void)
goto end;
}
+ pwm_device_init();
+
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index d90b252b..7983f781 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -10,6 +10,54 @@
#include <cpu_func.h>
#include <dm.h>
#include <asm/sections.h>
+#include <linux/io.h>
+#include <asm/arch/eeprom.h>
+
+struct pwm_sifive_regs {
+ unsigned int cfg; /* PWM configuration register */
+ unsigned int pad0; /* Reserved */
+ unsigned int cnt; /* PWM count register */
+ unsigned int pad1; /* Reserved */
+ unsigned int pwms; /* Scaled PWM count register */
+ unsigned int pad2; /* Reserved */
+ unsigned int pad3; /* Reserved */
+ unsigned int pad4; /* Reserved */
+ unsigned int cmp0; /* PWM 0 compare register */
+ unsigned int cmp1; /* PWM 1 compare register */
+ unsigned int cmp2; /* PWM 2 compare register */
+ unsigned int cmp3; /* PWM 3 compare register */
+};
+
+#define PWM0_BASE 0x10020000
+#define PWM1_BASE 0x10021000
+#define PWM_CFG_INIT 0x1000
+#define PWM_CMP_ENABLE_VAL 0x0
+#define PWM_CMP_DISABLE_VAL 0xffff
+
+void pwm_device_init(void)
+{
+ struct pwm_sifive_regs *pwm0, *pwm1;
+ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
+ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
+ /* Set the 3-color PWM LEDs to yellow in SPL */
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
+
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
+ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
+ so here sets the initial value of PWM_COMP0 as DISABLE */
+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
+ else
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+}
void *board_fdt_blob_setup(void)
{
--
2.32.0

58
0003-riscv-SiFive-Unmatched-set-LED-to-purple.patch Normal file
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@ -0,0 +1,58 @@
From 423fac5606d039b3729109fdf1029c43dd15604d Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Fri, 8 Oct 2021 11:45:30 +0000
Subject: [PATCH 3/9] riscv: SiFive Unmatched set LED to purple
Original patch:
https://github.com/sifive/meta-sifive/blob/2021.09/recipes-bsp/u-boot/files/riscv64/0011-board-sifive-Set-LED-s-color-to-purple-in-the-U-boot.patch
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
board/sifive/unmatched/unmatched.c | 14 ++++++++++++++
configs/sifive_unmatched_defconfig | 1 +
2 files changed, 15 insertions(+)
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index 7983f781..da306975 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -39,6 +39,7 @@ void pwm_device_init(void)
struct pwm_sifive_regs *pwm0, *pwm1;
pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+#ifdef CONFIG_SPL_BUILD
writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
/* Set the 3-color PWM LEDs to yellow in SPL */
writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
@@ -57,6 +58,19 @@ void pwm_device_init(void)
writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+#else
+ /* Set the 3-color PWM LEDs to purple in U-boot */
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp3);
+#endif
+
+}
+
+int board_early_init_f(void)
+{
+ pwm_device_init();
+ return 0;
}
void *board_fdt_blob_setup(void)
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 1dde98e0..ddc3c60e 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -42,3 +42,4 @@ CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_BOARD_EARLY_INIT_F=y
--
2.32.0

129
0004-riscv-SiFive-Unmatched-set-85C-as-the-limit.patch Normal file
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@ -0,0 +1,129 @@
From 2cb1bcadbe813abf10c4eccc0faf98feeaba064a Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Fri, 8 Oct 2021 11:48:06 +0000
Subject: [PATCH 4/9] riscv: SiFive Unmatched set 85C as the limit
Origin patch:
https://github.com/sifive/meta-sifive/blob/2021.09/recipes-bsp/u-boot/files/riscv64/0013-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
Fixed a typo in TMP451_RETMOE_THERM_LIMIT_INIT_VALUE
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++
drivers/misc/Kconfig | 10 ++++++++++
include/configs/sifive-unmatched.h | 3 +++
scripts/config_whitelist.txt | 1 +
4 files changed, 43 insertions(+)
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 3c3b22de..c7b65b9f 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -10,6 +10,8 @@
#include <spl.h>
#include <misc.h>
#include <log.h>
+#include <config.h>
+#include <i2c.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
@@ -25,6 +27,27 @@
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
+#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19
+#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55
+
+static inline int init_tmp451_remote_therm_limit(void)
+{
+ struct udevice *dev;
+ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM,
+ CONFIG_SYS_I2C_TMP451_ADDR,
+ CONFIG_SYS_I2C_TMP451_ADDR_LEN,
+ &dev);
+
+ if (!ret)
+ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET,
+ &r_therm_limit,
+ sizeof(unsigned char));
+ return ret;
+}
+
static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
{
int ret;
@@ -91,6 +114,12 @@ int spl_board_init_f(void)
pwm_device_init();
+ ret = init_tmp451_remote_therm_limit();
+ if (ret) {
+ debug("TMP451 remote THERM limit init failed: %d\n", ret);
+ goto end;
+ }
+
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 997b7132..2878313b 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -404,6 +404,10 @@ config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
default 0
+config SYS_I2C_TMP451_ADDR
+ hex "Chip address of the TMP451 device"
+ default 0
+
config SYS_I2C_EEPROM_BUS
int "I2C bus of the EEPROM device."
default 0
@@ -429,6 +433,12 @@ config SYS_I2C_EEPROM_ADDR_LEN
help
Note: This is NOT the chip address length!
+config SYS_I2C_TMP451_ADDR_LEN
+ int "Length in bytes of the TMP451 memory array address"
+ default 1
+ help
+ Note: This is NOT the chip address length!
+
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
default 0
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index bea0eebe..31513058 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -87,6 +87,9 @@
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1
+#define CONFIG_SYS_TMP451_BUS_NUM 0
+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c
+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1
#define CONFIG_ID_EEPROM
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index a9c2380d..20c7209a 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3179,6 +3179,7 @@ CONFIG_SYS_TIMER_COUNTER
CONFIG_SYS_TIMER_COUNTS_DOWN
CONFIG_SYS_TIMER_PRESCALER
CONFIG_SYS_TIMER_RATE
+CONFIG_SYS_TMP451_BUS_NUM
CONFIG_SYS_TMPVIRT
CONFIG_SYS_TMRINTR_MASK
CONFIG_SYS_TMRINTR_NO
--
2.32.0

29
0005-riscv-sifive-unmatched-leave-128MiB-for-ramdisk.patch Normal file
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@ -0,0 +1,29 @@
From 009845162b7f450d8ed3ffbbfffc828f362273a1 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Mon, 13 Sep 2021 03:15:35 -0700
Subject: [PATCH 5/9] riscv: sifive: unmatched: leave 128MiB for ramdisk
The current configuration only allows 125MiB, but the max allowed size should
be 128MiB.
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
include/configs/sifive-unmatched.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 31513058..10b71f75 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -70,7 +70,7 @@
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
- "kernel_comp_addr_r=0x90000000\0" \
+ "kernel_comp_addr_r=0x90300000\0" \
"kernel_comp_size=0x4000000\0" \
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
--
2.32.0

35
0006-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch Normal file
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@ -0,0 +1,35 @@
From 0bce0ec557d222de6b75c9af5c9020ae5244cddd Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Mon, 13 Sep 2021 03:22:32 -0700
Subject: [PATCH 6/9] riscv: sifive: unmatched: disable FDT and initrd
relocation
Same as on SiFive Unleashed we need to disable fdt and initrd relocation. Tom
Rini mentined 18 days ago that it's most likely due to RISC-V lacking
`arch_lmb_reserve` implementation.
The patch seems to be submitted now:
[PATCH 09/12] lmb: riscv: Add arch_lmb_reserve()
https://lists.denx.de/pipermail/u-boot/2021-September/460333.html
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
include/configs/sifive-unmatched.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 10b71f75..3ed3318d 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -65,6 +65,8 @@
"name=system,size=-,bootable,type=${type_guid_gpt_system};"
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x84000000\0" \
"fdt_addr_r=0x88000000\0" \
"scriptaddr=0x88100000\0" \
--
2.32.0

26
0007-riscv-add-compressed-kernel-support-for-qemu-riscv.patch Normal file
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@ -0,0 +1,26 @@
From 0f680a1e121c91be46ed1c159102536f50ee7448 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:52:13 +0000
Subject: [PATCH 7/9] riscv: add compressed kernel support for qemu-riscv
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
include/configs/qemu-riscv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index bbeea96e..0ede2a51 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -64,6 +64,8 @@
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
+ "kernel_comp_addr_r=0x90300000\0" \
+ "kernel_comp_size=0x4000000\0" \
BOOTENV
#endif
--
2.32.0

62
0008-riscv-set-NRCPUS-to-32.patch Normal file
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@ -0,0 +1,62 @@
From b166bb28f5ead9fc3fd125a8bf8895bd6de1f4d1 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:54:54 +0000
Subject: [PATCH 8/9] riscv: set NRCPUS to 32
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
configs/qemu-riscv64_defconfig | 1 +
configs/qemu-riscv64_smode_defconfig | 1 +
configs/qemu-riscv64_spl_defconfig | 1 +
configs/sifive_unleashed_defconfig | 1 +
configs/sifive_unmatched_defconfig | 1 +
5 files changed, 5 insertions(+)
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index daf5d655..aa79abc1 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -13,3 +13,4 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_NR_CPUS=32
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 4a6416e2..ebe35d4c 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -16,3 +16,4 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_NR_CPUS=32
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 429d4d81..8d08d50c 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -16,3 +16,4 @@ CONFIG_CMD_SBI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_NR_CPUS=32
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index fd686dfa..d0c53888 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -28,3 +28,4 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
CONFIG_DM_RESET=y
+CONFIG_NR_CPUS=32
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index ddc3c60e..c3f247fd 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -43,3 +43,4 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_NR_CPUS=32
--
2.32.0

67
0009-riscv-add-CONFIG_CMD_GPT_RENAME.patch Normal file
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@ -0,0 +1,67 @@
From d51fba4178a64d77d20880bd20c05b3b9cd11c10 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:58:16 +0000
Subject: [PATCH 9/9] riscv: add CONFIG_CMD_GPT_RENAME
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
configs/qemu-riscv64_defconfig | 2 ++
configs/qemu-riscv64_smode_defconfig | 2 ++
configs/qemu-riscv64_spl_defconfig | 2 ++
configs/sifive_unleashed_defconfig | 2 ++
configs/sifive_unmatched_defconfig | 2 ++
5 files changed, 10 insertions(+)
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index aa79abc1..625e7295 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -14,3 +14,5 @@ CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index ebe35d4c..fde8c0f5 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -17,3 +17,5 @@ CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 8d08d50c..8795edee 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -17,3 +17,5 @@ CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index d0c53888..8e40eead 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -29,3 +29,5 @@ CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
CONFIG_DM_RESET=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index c3f247fd..513c58a4 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -44,3 +44,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
--
2.32.0

5
riscv64-boards Normal file
View File

@ -0,0 +1,5 @@
qemu-riscv64
qemu-riscv64_smode
qemu-riscv64_spl
sifive_unleashed
sifive_unmatched

59
uboot-tools.spec
View File

@ -1,8 +1,11 @@
#global candidate rc5
# Set it to "opensbi" (stable) or opensbi-unstable (unstable, git)
%global opensbi opensbi-unstable
Name: uboot-tools
Version: 2021.10
Release: 1%{?candidate:.%{candidate}}%{?dist}
Release: 1%{?candidate:.%{candidate}}.0.riscv64%{?dist}
Summary: U-Boot utilities
License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
URL: http://www.denx.de/wiki/U-Boot
@ -13,6 +16,7 @@ Source1: arm-boards
Source2: arm-chromebooks
Source3: aarch64-boards
Source4: aarch64-chromebooks
Source5: riscv64-boards
# Fedoraisms patches
# Needed to find DT on boot partition that's not the first partition
@ -31,6 +35,17 @@ Patch12: phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.patch
Patch13: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch
Patch14: 0001-enable-hs400-and-sdma-support.patch
# RISC-V (riscv64) patches
Patch40: 0001-riscv-SiFive-Unleashed-booti-compressed-kernel-suppo.patch
Patch41: 0002-riscv-SiFive-Unmatched-initilize-PWM.patch
Patch42: 0003-riscv-SiFive-Unmatched-set-LED-to-purple.patch
Patch43: 0004-riscv-SiFive-Unmatched-set-85C-as-the-limit.patch
Patch44: 0005-riscv-sifive-unmatched-leave-128MiB-for-ramdisk.patch
Patch45: 0006-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch
Patch46: 0007-riscv-add-compressed-kernel-support-for-qemu-riscv.patch
Patch47: 0008-riscv-set-NRCPUS-to-32.patch
Patch48: 0009-riscv-add-CONFIG_CMD_GPT_RENAME.patch
BuildRequires: bc
BuildRequires: dtc
BuildRequires: make
@ -73,6 +88,9 @@ BuildArch: noarch
%description -n uboot-images-armv8
U-Boot firmware binaries for aarch64 boards
%endif
%ifarch riscv64
BuildRequires: %{opensbi}
%endif
%ifarch %{arm}
%package -n uboot-images-armv7
@ -83,10 +101,20 @@ BuildArch: noarch
U-Boot firmware binaries for armv7 boards
%endif
%ifarch riscv64
%package -n uboot-images-riscv64
Summary: u-boot bootloader images for riscv64 boards
Requires: uboot-tools
BuildArch: noarch
%description -n uboot-images-riscv64
u-boot bootloader binaries for riscv64 boards
%endif
%prep
%autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}}
cp %SOURCE1 %SOURCE2 %SOURCE3 %SOURCE4 .
cp %SOURCE1 %SOURCE2 %SOURCE3 %SOURCE4 %SOURCE5 .
%build
mkdir builds
@ -102,7 +130,11 @@ mkdir builds
# U-Boot device firmwares don't currently support LTO
%define _lto_cflags %{nil}
%ifarch aarch64 %{arm}
%ifarch riscv64
export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin
%endif
%ifarch aarch64 %{arm} riscv64
for board in $(cat %{_arch}-boards)
do
echo "Building board: $board"
@ -215,6 +247,19 @@ do
done
%endif
%ifarch riscv64
for board in $(cat %{_arch}-boards)
do
mkdir -p $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/
for file in u-boot.bin u-boot.dtb u-boot.img u-boot-nodtb.bin u-boot-dtb.bin u-boot.itb u-boot-dtb.img u-boot.its spl/u-boot-spl.bin spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb spl/u-boot-spl-dtb.bin
do
if [ -f builds/$(echo $board)/$(echo $file) ]; then
install -p -m 0644 builds/$(echo $board)/$(echo $file) $RPM_BUILD_ROOT%{_datadir}/uboot/$(echo $board)/
fi
done
done
%endif
for tool in bmp_logo dumpimage env/fw_printenv fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc img2srec mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder ubsha1 xway-swap-bytes kwboot
do
install -p -m 0755 builds/tools/$tool %{buildroot}%{_bindir}
@ -259,7 +304,15 @@ cp -p board/warp7/README builds/docs/README.warp7
%{_datadir}/uboot/*
%endif
%ifarch riscv64
%files -n uboot-images-riscv64
%{_datadir}/uboot/*
%endif
%changelog
* Fri Oct 07 2021 David Abdurachmanov <david.abdurachmanov@gmail.com> - 2021.10-1.0.riscv64
- Add support for riscv64
* Mon Oct 04 2021 Peter Robinson <pbrobinson@fedoraproject.org> - 2021.10-1
- Update to 2021.10