From 3084c0898aab2a267ca34f94291b9ce9c9409877 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 14 Apr 2020 10:17:48 +0100 Subject: [PATCH] 2020.04 --- AllWinner-Pine64-bits.patch | 2173 +++++++++++++++++++++++++++++++++++ aarch64-boards | 2 + sources | 2 +- uboot-tools.spec | 14 +- 4 files changed, 2185 insertions(+), 6 deletions(-) create mode 100644 AllWinner-Pine64-bits.patch diff --git a/AllWinner-Pine64-bits.patch b/AllWinner-Pine64-bits.patch new file mode 100644 index 0000000..27f95f8 --- /dev/null +++ b/AllWinner-Pine64-bits.patch @@ -0,0 +1,2173 @@ +From 2c213379d9ec786480a655f8c5687b2df376017f Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 12:27:15 +0000 +Subject: [PATCH 1/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.6-rc1 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64.dtsi | 472 ++++++++++++++++++++++++++++------- + 1 file changed, 387 insertions(+), 85 deletions(-) + +diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi +index ff41abc96a..862b47dc9d 100644 +--- a/arch/arm/dts/sun50i-a64.dtsi ++++ b/arch/arm/dts/sun50i-a64.dtsi +@@ -1,46 +1,7 @@ +-/* +- * Copyright (C) 2016 ARM Ltd. +- * based on the Allwinner H3 dtsi: +- * Copyright (C) 2015 Jens Kuske +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2016 ARM Ltd. ++// based on the Allwinner H3 dtsi: ++// Copyright (C) 2015 Jens Kuske + + #include + #include +@@ -49,6 +10,7 @@ + #include + #include + #include ++#include + + / { + interrupt-parent = <&gic>; +@@ -84,35 +46,47 @@ + #size-cells = <0>; + + cpu0: cpu@0 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + cpu1: cpu@1 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + cpu2: cpu@2 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + cpu3: cpu@3 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + L2: l2-cache { +@@ -139,15 +113,16 @@ + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; +- clock-output-names = "osc32k"; ++ clock-output-names = "ext-osc32k"; + }; + +- iosc: internal-osc-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16000000>; +- clock-accuracy = <300000000>; +- clock-output-names = "iosc"; ++ pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { +@@ -155,6 +130,30 @@ + method = "smc"; + }; + ++ sound: sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "sun50i-a64-audio"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,frame-master = <&cpudai>; ++ simple-audio-card,bitclock-master = <&cpudai>; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,aux-devs = <&codec_analog>; ++ simple-audio-card,routing = ++ "Left DAC", "AIF1 Slot 0 Left", ++ "Right DAC", "AIF1 Slot 0 Right", ++ "AIF1 Slot 0 Left ADC", "Left ADC", ++ "AIF1 Slot 0 Right ADC", "Right ADC"; ++ status = "disabled"; ++ ++ cpudai: simple-audio-card,cpu { ++ sound-dai = <&dai>; ++ }; ++ ++ link_codec: simple-audio-card,codec { ++ sound-dai = <&codec>; ++ }; ++ }; ++ + sound_spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; +@@ -175,6 +174,7 @@ + + timer { + compatible = "arm,armv8-timer"; ++ allwinner,erratum-unknown1; + interrupts = , + ; + }; + ++ thermal-zones { ++ cpu_thermal: cpu0-thermal { ++ /* milliseconds */ ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 0>; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert0>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ map1 { ++ trip = <&cpu_alert1>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ ++ trips { ++ cpu_alert0: cpu_alert0 { ++ /* milliCelsius */ ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_alert1: cpu_alert1 { ++ /* milliCelsius */ ++ temperature = <90000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_crit: cpu_crit { ++ /* milliCelsius */ ++ temperature = <110000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu0_thermal: gpu0-thermal { ++ /* milliseconds */ ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 1>; ++ }; ++ ++ gpu1_thermal: gpu1-thermal { ++ /* milliseconds */ ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 2>; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + +- de2@1000000 { ++ bus@1000000 { + compatible = "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&de2_sram 1>; +@@ -202,10 +265,10 @@ + display_clocks: clock@0 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0 0x100000>; +- clocks = <&ccu CLK_DE>, +- <&ccu CLK_BUS_DE>; +- clock-names = "mod", +- "bus"; ++ clocks = <&ccu CLK_BUS_DE>, ++ <&ccu CLK_DE>; ++ clock-names = "bus", ++ "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -225,11 +288,19 @@ + #size-cells = <0>; + + mixer0_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <1>; + +- mixer0_out_tcon0: endpoint { ++ mixer0_out_tcon0: endpoint@0 { ++ reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; ++ ++ mixer0_out_tcon1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&tcon1_in_mixer0>; ++ }; + }; + }; + }; +@@ -248,9 +319,17 @@ + #size-cells = <0>; + + mixer1_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <1>; + +- mixer1_out_tcon1: endpoint { ++ mixer1_out_tcon0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&tcon0_in_mixer1>; ++ }; ++ ++ mixer1_out_tcon1: endpoint@1 { ++ reg = <1>; + remote-endpoint = <&tcon1_in_mixer1>; + }; + }; +@@ -259,8 +338,7 @@ + }; + + syscon: syscon@1c00000 { +- compatible = "allwinner,sun50i-a64-system-control", +- "syscon"; ++ compatible = "allwinner,sun50i-a64-system-control"; + reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; +@@ -278,6 +356,20 @@ + reg = <0x0000 0x28000>; + }; + }; ++ ++ sram_c1: sram@1d00000 { ++ compatible = "mmio-sram"; ++ reg = <0x01d00000 0x40000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x01d00000 0x40000>; ++ ++ ve_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-a64-sram-c1", ++ "allwinner,sun4i-a10-sram-c1"; ++ reg = <0x000000 0x40000>; ++ }; ++ }; + }; + + dma: dma-controller@1c02000 { +@@ -299,6 +391,7 @@ + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; ++ #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + +@@ -315,12 +408,23 @@ + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; ++ ++ tcon0_in_mixer1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&mixer1_out_tcon0>; ++ }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; ++ ++ tcon0_out_dsi: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dsi_in_tcon0>; ++ allwinner,tcon-channel = <1>; ++ }; + }; + }; + }; +@@ -340,9 +444,17 @@ + #size-cells = <0>; + + tcon1_in: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <0>; + +- tcon1_in_mixer1: endpoint { ++ tcon1_in_mixer0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&mixer0_out_tcon1>; ++ }; ++ ++ tcon1_in_mixer1: endpoint@1 { ++ reg = <1>; + remote-endpoint = <&mixer1_out_tcon1>; + }; + }; +@@ -360,6 +472,17 @@ + }; + }; + ++ video-codec@1c0e000 { ++ compatible = "allwinner,sun50i-a64-video-engine"; ++ reg = <0x01c0e000 0x1000>; ++ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, ++ <&ccu CLK_DRAM_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ interrupts = ; ++ allwinner,sram = <&ve_sram 1>; ++ }; ++ + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun50i-a64-mmc"; + reg = <0x01c0f000 0x1000>; +@@ -405,6 +528,21 @@ + sid: eeprom@1c14000 { + compatible = "allwinner,sun50i-a64-sid"; + reg = <0x1c14000 0x400>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ ths_calibration: thermal-sensor-calibration@34 { ++ reg = <0x34 0x8>; ++ }; ++ }; ++ ++ crypto: crypto@1c15000 { ++ compatible = "allwinner,sun50i-a64-crypto"; ++ reg = <0x01c15000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_CE>; + }; + + usb_otg: usb@1c19000 { +@@ -417,6 +555,7 @@ + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; ++ dr_mode = "otg"; + status = "disabled"; + }; + +@@ -491,7 +630,7 @@ + ccu: clock@1c20000 { + compatible = "allwinner,sun50i-a64-ccu"; + reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&osc32k>; ++ clocks = <&osc24M>, <&rtc 0>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -503,22 +642,45 @@ + interrupts = , + , + ; +- clocks = <&ccu 58>; ++ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; ++ clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + +- i2c0_pins: i2c0_pins { ++ csi_pins: csi-pins { ++ pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", ++ "PE7", "PE8", "PE9", "PE10", "PE11"; ++ function = "csi"; ++ }; ++ ++ /omit-if-no-ref/ ++ csi_mclk_pin: csi-mclk-pin { ++ pins = "PE1"; ++ function = "csi"; ++ }; ++ ++ i2c0_pins: i2c0-pins { + pins = "PH0", "PH1"; + function = "i2c0"; + }; + +- i2c1_pins: i2c1_pins { ++ i2c1_pins: i2c1-pins { + pins = "PH2", "PH3"; + function = "i2c1"; + }; + ++ /omit-if-no-ref/ ++ lcd_rgb666_pins: lcd-rgb666-pins { ++ pins = "PD0", "PD1", "PD2", "PD3", "PD4", ++ "PD5", "PD6", "PD7", "PD8", "PD9", ++ "PD10", "PD11", "PD12", "PD13", ++ "PD14", "PD15", "PD16", "PD17", ++ "PD18", "PD19", "PD20", "PD21"; ++ function = "lcd0"; ++ }; ++ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; +@@ -551,19 +713,19 @@ + bias-pull-up; + }; + +- pwm_pin: pwm_pin { ++ pwm_pin: pwm-pin { + pins = "PD22"; + function = "pwm"; + }; + +- rmii_pins: rmii_pins { ++ rmii_pins: rmii-pins { + pins = "PD10", "PD11", "PD13", "PD14", "PD17", + "PD18", "PD19", "PD20", "PD22", "PD23"; + function = "emac"; + drive-strength = <40>; + }; + +- rgmii_pins: rgmii_pins { ++ rgmii_pins: rgmii-pins { + pins = "PD8", "PD9", "PD10", "PD11", "PD12", + "PD13", "PD15", "PD16", "PD17", "PD18", + "PD19", "PD20", "PD21", "PD22", "PD23"; +@@ -571,17 +733,17 @@ + drive-strength = <40>; + }; + +- spdif_tx_pin: spdif { ++ spdif_tx_pin: spdif-tx-pin { + pins = "PH8"; + function = "spdif"; + }; + +- spi0_pins: spi0 { ++ spi0_pins: spi0-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + +- spi1_pins: spi1 { ++ spi1_pins: spi1-pins { + pins = "PD0", "PD1", "PD2", "PD3"; + function = "spi1"; + }; +@@ -591,12 +753,12 @@ + function = "uart0"; + }; + +- uart1_pins: uart1_pins { ++ uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + +- uart1_rts_cts_pins: uart1_rts_cts_pins { ++ uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; +@@ -638,6 +800,14 @@ + status = "disabled"; + }; + ++ lradc: lradc@1c21800 { ++ compatible = "allwinner,sun50i-a64-lradc", ++ "allwinner,sun8i-a83t-r-lradc"; ++ reg = <0x01c21800 0x400>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-a64-i2s", +@@ -666,6 +836,41 @@ + status = "disabled"; + }; + ++ dai: dai@1c22c00 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun50i-a64-codec-i2s"; ++ reg = <0x01c22c00 0x200>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; ++ clock-names = "apb", "mod"; ++ resets = <&ccu RST_BUS_CODEC>; ++ dmas = <&dma 15>, <&dma 15>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ codec: codec@1c22e00 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun8i-a33-codec"; ++ reg = <0x01c22e00 0x600>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; ++ clock-names = "bus", "mod"; ++ status = "disabled"; ++ }; ++ ++ ths: thermal-sensor@1c25000 { ++ compatible = "allwinner,sun50i-a64-ths"; ++ reg = <0x01c25000 0x100>; ++ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; ++ clock-names = "bus", "mod"; ++ interrupts = ; ++ resets = <&ccu RST_BUS_THS>; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ #thermal-sensor-cells = <1>; ++ }; ++ + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; +@@ -727,6 +932,8 @@ + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +@@ -738,6 +945,8 @@ + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +@@ -808,6 +1017,28 @@ + }; + }; + ++ mali: gpu@1c40000 { ++ compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; ++ reg = <0x01c40000 0x10000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "gp", ++ "gpmmu", ++ "pp0", ++ "ppmmu0", ++ "pp1", ++ "ppmmu1", ++ "pmu"; ++ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; ++ clock-names = "bus", "core"; ++ resets = <&ccu RST_BUS_GPU>; ++ }; ++ + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, +@@ -830,6 +1061,51 @@ + status = "disabled"; + }; + ++ csi: csi@1cb0000 { ++ compatible = "allwinner,sun50i-a64-csi"; ++ reg = <0x01cb0000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CSI>, ++ <&ccu CLK_CSI_SCLK>, ++ <&ccu CLK_DRAM_CSI>; ++ clock-names = "bus", "mod", "ram"; ++ resets = <&ccu RST_BUS_CSI>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&csi_pins>; ++ status = "disabled"; ++ }; ++ ++ dsi: dsi@1ca0000 { ++ compatible = "allwinner,sun50i-a64-mipi-dsi"; ++ reg = <0x01ca0000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_MIPI_DSI>; ++ resets = <&ccu RST_BUS_MIPI_DSI>; ++ phys = <&dphy>; ++ phy-names = "dphy"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port { ++ dsi_in_tcon0: endpoint { ++ remote-endpoint = <&tcon0_out_dsi>; ++ }; ++ }; ++ }; ++ ++ dphy: d-phy@1ca1000 { ++ compatible = "allwinner,sun50i-a64-mipi-dphy", ++ "allwinner,sun6i-a31-mipi-dphy"; ++ reg = <0x01ca1000 0x1000>; ++ clocks = <&ccu CLK_BUS_MIPI_DSI>, ++ <&ccu CLK_DSI_DPHY>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_MIPI_DSI>; ++ status = "disabled"; ++ #phy-cells = <0>; ++ }; ++ + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun50i-a64-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; +@@ -842,7 +1118,7 @@ + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; +- phy-names = "hdmi-phy"; ++ phy-names = "phy"; + status = "disabled"; + + ports { +@@ -867,7 +1143,7 @@ + compatible = "allwinner,sun50i-a64-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, +- <&ccu 7>; ++ <&ccu CLK_PLL_VIDEO0>; + clock-names = "bus", "mod", "pll-0"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; +@@ -875,11 +1151,12 @@ + }; + + rtc: rtc@1f00000 { +- compatible = "allwinner,sun6i-a31-rtc"; +- reg = <0x01f00000 0x54>; ++ compatible = "allwinner,sun50i-a64-rtc", ++ "allwinner,sun8i-h3-rtc"; ++ reg = <0x01f00000 0x400>; + interrupts = , + ; +- clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; ++ clock-output-names = "osc32k", "osc32k-out", "iosc"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; +@@ -896,13 +1173,19 @@ + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; +- clocks = <&osc24M>, <&osc32k>, <&iosc>, +- <&ccu 11>; ++ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, ++ <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + ++ codec_analog: codec-analog@1f015c0 { ++ compatible = "allwinner,sun50i-a64-codec-analog"; ++ reg = <0x01f015c0 0x4>; ++ status = "disabled"; ++ }; ++ + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; +@@ -915,6 +1198,19 @@ + #size-cells = <0>; + }; + ++ r_ir: ir@1f02000 { ++ compatible = "allwinner,sun50i-a64-ir", ++ "allwinner,sun6i-a31-ir"; ++ reg = <0x01f02000 0x400>; ++ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; ++ clock-names = "apb", "ir"; ++ resets = <&r_ccu RST_APB0_IR>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "disabled"; ++ }; ++ + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; +@@ -942,12 +1238,17 @@ + function = "s_i2c"; + }; + +- r_pwm_pin: pwm { ++ r_ir_rx_pin: r-ir-rx-pin { ++ pins = "PL11"; ++ function = "s_cir_rx"; ++ }; ++ ++ r_pwm_pin: r-pwm-pin { + pins = "PL10"; + function = "s_pwm"; + }; + +- r_rsb_pins: rsb { ++ r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + }; +@@ -972,6 +1273,7 @@ + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; ++ clocks = <&osc24M>; + }; + }; + }; +-- +2.26.0 + +From fbe1642e24188e96f20ab5a3b003597288104e31 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:32:51 +0000 +Subject: [PATCH 2/9] arm: dts: AllWinner: sync axp803.dtsi to 5.6-rc1 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/axp803.dtsi | 82 ++++++++++++++++++++-------------------- + 1 file changed, 41 insertions(+), 41 deletions(-) + +diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi +index e5eae8bafc..10e9186a76 100644 +--- a/arch/arm/dts/axp803.dtsi ++++ b/arch/arm/dts/axp803.dtsi +@@ -1,44 +1,5 @@ +-/* +- * Copyright 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright 2017 Icenowy Zheng + + /* + * AXP803 Integrated Power Management Chip +@@ -49,6 +10,39 @@ + interrupt-controller; + #interrupt-cells = <1>; + ++ ac_power_supply: ac-power-supply { ++ compatible = "x-powers,axp803-ac-power-supply", ++ "x-powers,axp813-ac-power-supply"; ++ status = "disabled"; ++ }; ++ ++ axp_adc: adc { ++ compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; ++ #io-channel-cells = <1>; ++ }; ++ ++ axp_gpio: gpio { ++ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ gpio0_ldo: gpio0-ldo { ++ pins = "GPIO0"; ++ function = "ldo"; ++ }; ++ ++ gpio1_ldo: gpio1-ldo { ++ pins = "GPIO1"; ++ function = "ldo"; ++ }; ++ }; ++ ++ battery_power_supply: battery-power-supply { ++ compatible = "x-powers,axp803-battery-power-supply", ++ "x-powers,axp813-battery-power-supply"; ++ status = "disabled"; ++ }; ++ + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; +@@ -152,4 +146,10 @@ + status = "disabled"; + }; + }; ++ ++ usb_power_supply: usb-power-supply { ++ compatible = "x-powers,axp803-usb-power-supply", ++ "x-powers,axp813-usb-power-supply"; ++ status = "disabled"; ++ }; + }; +-- +2.26.0 + +From f44987a0ccf064f9da4a119e7700605a3eb56447 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:34:58 +0000 +Subject: [PATCH 3/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.7-rc1 + +Adds the following two patches queued for 5.7: +- arm64: dts: sun50i-a64: Add i2c2 pins +- arm64: dts: allwinner: a64: Add MBUS controller node + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64.dtsi | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi +index 862b47dc9d..89a60fcf5a 100644 +--- a/arch/arm/dts/sun50i-a64.dtsi ++++ b/arch/arm/dts/sun50i-a64.dtsi +@@ -671,6 +671,11 @@ + function = "i2c1"; + }; + ++ i2c2_pins: i2c2-pins { ++ pins = "PE14", "PE15"; ++ function = "i2c2"; ++ }; ++ + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", +@@ -958,12 +963,13 @@ + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + +- + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; +@@ -1061,6 +1067,14 @@ + status = "disabled"; + }; + ++ mbus: dram-controller@1c62000 { ++ compatible = "allwinner,sun50i-a64-mbus"; ++ reg = <0x01c62000 0x1000>; ++ clocks = <&ccu 112>; ++ dma-ranges = <0x00000000 0x40000000 0xc0000000>; ++ #interconnect-cells = <1>; ++ }; ++ + csi: csi@1cb0000 { + compatible = "allwinner,sun50i-a64-csi"; + reg = <0x01cb0000 0x1000>; +-- +2.26.0 + +From 465dbf297edb9881e79c1b81fef8d9328fbaf7ad Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:37:39 +0000 +Subject: [PATCH 4/9] arm: dts: allwinner: Add initial support for Pine64 + PinePhone + +The initial DT for the PinePhone models are queued for 5.7-rc1: +- 1.0: Early Developer Batch +- 1.1: Braveheart Batch + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/Makefile | 2 + + arch/arm/dts/sun50i-a64-pinephone-1.0.dts | 11 + + arch/arm/dts/sun50i-a64-pinephone-1.1.dts | 11 + + arch/arm/dts/sun50i-a64-pinephone.dtsi | 379 ++++++++++++++++++++++ + 4 files changed, 403 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.0.dts + create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.1.dts + create mode 100644 arch/arm/dts/sun50i-a64-pinephone.dtsi + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 820ee9733a..fb7516ee83 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -573,6 +573,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-pine64-plus.dtb \ + sun50i-a64-pine64.dtb \ + sun50i-a64-pinebook.dtb \ ++ sun50i-a64-pinephone-1.0.dtb \ ++ sun50i-a64-pinephone-1.1.dtb \ + sun50i-a64-sopine-baseboard.dtb \ + sun50i-a64-teres-i.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ +diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts +new file mode 100644 +index 0000000000..0c42272106 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Ondrej Jirman ++ ++/dts-v1/; ++ ++#include "sun50i-a64-pinephone.dtsi" ++ ++/ { ++ model = "Pine64 PinePhone Developer Batch (1.0)"; ++ compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64"; ++}; +diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts +new file mode 100644 +index 0000000000..06a775c416 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Ondrej Jirman ++ ++/dts-v1/; ++ ++#include "sun50i-a64-pinephone.dtsi" ++ ++/ { ++ model = "Pine64 PinePhone Braveheart (1.1)"; ++ compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64"; ++}; +diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi +new file mode 100644 +index 0000000000..cefda145c3 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi +@@ -0,0 +1,379 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2019 Icenowy Zheng ++// Copyright (C) 2020 Martijn Braam ++// Copyright (C) 2020 Ondrej Jirman ++ ++#include "sun50i-a64.dtsi" ++#include "sun50i-a64-cpu-opp.dtsi" ++ ++#include ++#include ++#include ++#include ++ ++/ { ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ blue { ++ function = LED_FUNCTION_INDICATOR; ++ color = ; ++ gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ ++ }; ++ ++ green { ++ function = LED_FUNCTION_INDICATOR; ++ color = ; ++ gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ ++ }; ++ ++ red { ++ function = LED_FUNCTION_INDICATOR; ++ color = ; ++ gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ ++ }; ++ }; ++ ++ speaker_amp: audio-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ ++ sound-name-prefix = "Speaker Amp"; ++ }; ++ ++ vibrator { ++ compatible = "gpio-vibrator"; ++ enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ ++ vcc-supply = <®_dcdc1>; ++ }; ++}; ++ ++&codec { ++ status = "okay"; ++}; ++ ++&codec_analog { ++ cpvdd-supply = <®_eldo1>; ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu2 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu3 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&dai { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ /* Magnetometer */ ++ lis3mdl@1e { ++ compatible = "st,lis3mdl-magn"; ++ reg = <0x1e>; ++ vdd-supply = <®_dldo1>; ++ vddio-supply = <®_dldo1>; ++ }; ++ ++ /* Accelerometer/gyroscope */ ++ mpu6050@68 { ++ compatible = "invensense,mpu6050"; ++ reg = <0x68>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ ++ vdd-supply = <®_dldo1>; ++ vddio-supply = <®_dldo1>; ++ }; ++}; ++ ++/* Connected to pogo pins (external spring based pinheader for user addons) */ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&lradc { ++ vref-supply = <®_aldo3>; ++ status = "okay"; ++ ++ button-200 { ++ label = "Volume Up"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <200000>; ++ }; ++ ++ button-400 { ++ label = "Volume Down"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <400000>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_dcdc1>; ++ vcc-pc-supply = <®_dcdc1>; ++ vcc-pd-supply = <®_dcdc1>; ++ vcc-pe-supply = <®_aldo1>; ++ vcc-pf-supply = <®_dcdc1>; ++ vcc-pg-supply = <®_dldo4>; ++ vcc-ph-supply = <®_dcdc1>; ++}; ++ ++&r_pio { ++ /* ++ * FIXME: We can't add that supply for now since it would ++ * create a circular dependency between pinctrl, the regulator ++ * and the RSB Bus. ++ * ++ * vcc-pl-supply = <®_aldo2>; ++ */ ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++&ac_power_supply { ++ status = "okay"; ++}; ++ ++&battery_power_supply { ++ status = "okay"; ++}; ++ ++®_aldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "dovdd-csi"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-dsi-sensor"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-mipi-io"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-lpddr"; ++}; ++ ++®_eldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "dvdd-1v8-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_ldo_io0 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-lcd-ctp-stk"; ++ status = "okay"; ++}; ++ ++®_ldo_io1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-1v8-typec"; ++ status = "okay"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&sound { ++ status = "okay"; ++ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; ++ simple-audio-card,widgets = "Microphone", "Headset Microphone", ++ "Microphone", "Internal Microphone", ++ "Headphone", "Headphone Jack", ++ "Speaker", "Internal Earpiece", ++ "Speaker", "Internal Speaker"; ++ simple-audio-card,routing = ++ "Headphone Jack", "HP", ++ "Internal Earpiece", "EARPIECE", ++ "Internal Speaker", "Speaker Amp OUTL", ++ "Internal Speaker", "Speaker Amp OUTR", ++ "Speaker Amp INL", "LINEOUT", ++ "Speaker Amp INR", "LINEOUT", ++ "Left DAC", "AIF1 Slot 0 Left", ++ "Right DAC", "AIF1 Slot 0 Right", ++ "AIF1 Slot 0 Left ADC", "Left ADC", ++ "AIF1 Slot 0 Right ADC", "Right ADC", ++ "Internal Microphone", "MBIAS", ++ "MIC1", "Internal Microphone", ++ "Headset Microphone", "HBIAS", ++ "MIC2", "Headset Microphone"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pb_pins>; ++ status = "okay"; ++}; ++ ++/* Connected to the modem (hardware flow control can't be used) */ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usb_power_supply { ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +-- +2.26.0 + +From e8fd62cbf02828da817628d15111e6e974144473 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:46:43 +0000 +Subject: [PATCH 5/9] sync sun50i-a64 clocks with linux 5.6 + +Signed-off-by: Peter Robinson +--- + include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h +index d66432c6e6..e512a1c9b0 100644 +--- a/include/dt-bindings/clock/sun50i-a64-ccu.h ++++ b/include/dt-bindings/clock/sun50i-a64-ccu.h +@@ -43,8 +43,10 @@ + #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ + #define _DT_BINDINGS_CLK_SUN50I_A64_H_ + ++#define CLK_PLL_VIDEO0 7 + #define CLK_PLL_PERIPH0 11 + ++#define CLK_CPUX 21 + #define CLK_BUS_MIPI_DSI 28 + #define CLK_BUS_CE 29 + #define CLK_BUS_DMA 30 +-- +2.26.0 + +From a07a9d6cb77ea0bc21cd64922bb428faf5b7e121 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:49:11 +0000 +Subject: [PATCH 6/9] add upstream sun50i-a64-cpu-opp.dtsi added in 5.6 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 75 ++++++++++++++++++++++++++++ + 1 file changed, 75 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-cpu-opp.dtsi + +diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi +new file mode 100644 +index 0000000000..578c37490d +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi +@@ -0,0 +1,75 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020 Vasily khoruzhick ++ */ ++ ++/ { ++ cpu0_opp_table: opp_table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-648000000 { ++ opp-hz = /bits/ 64 <648000000>; ++ opp-microvolt = <1040000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-912000000 { ++ opp-hz = /bits/ 64 <912000000>; ++ opp-microvolt = <1120000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-960000000 { ++ opp-hz = /bits/ 64 <960000000>; ++ opp-microvolt = <1160000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1200000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1240000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1260000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; +-- +2.26.0 + +From 493869ec73e6ba999b6f7c49369e966ebfb8ef0b Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 14 Apr 2020 09:50:11 +0100 +Subject: [PATCH 7/9] Initial Pinephone support + +Signed-off-by: Peter Robinson +--- + configs/pinephone_defconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + create mode 100644 configs/pinephone_defconfig + +diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig +new file mode 100644 +index 0000000000..a7d1e610d4 +--- /dev/null ++++ b/configs/pinephone_defconfig +@@ -0,0 +1,26 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I=y ++CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y ++CONFIG_DRAM_CLK=552 ++CONFIG_DRAM_ZQ=3881949 ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_R_I2C_ENABLE=y ++CONFIG_SPL_SPI_SUNXI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_USE_PREBOOT=y ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1" ++CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.0" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SUNXI=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +-- +2.26.0 + +From 163b30d9cd1c0cf77107e0330567bbda063410da Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 14 Apr 2020 09:51:44 +0100 +Subject: [PATCH 8/9] Initial PineTab dts from linux 5.7-rc1 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/sun50i-a64-pinetab.dts | 460 ++++++++++++++++++++++++++++ + 2 files changed, 461 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-pinetab.dts + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index fb7516ee83..50c1d48e84 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -575,6 +575,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-pinebook.dtb \ + sun50i-a64-pinephone-1.0.dtb \ + sun50i-a64-pinephone-1.1.dtb \ ++ sun50i-a64-pinetab.dtb \ + sun50i-a64-sopine-baseboard.dtb \ + sun50i-a64-teres-i.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ +diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts +new file mode 100644 +index 0000000000..316e8a4439 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinetab.dts +@@ -0,0 +1,460 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 Icenowy Zheng ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++#include "sun50i-a64-cpu-opp.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "PineTab"; ++ compatible = "pine64,pinetab", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &rtl8723cs; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>; ++ default-brightness-level = <15>; ++ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ ++ power-supply = <&vdd_bl>; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ i2c-csi { ++ compatible = "i2c-gpio"; ++ sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */ ++ scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ ++ i2c-gpio,delay-us = <5>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Rear camera */ ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&csi_mclk_pin>; ++ clocks = <&ccu CLK_CSI_MCLK>; ++ clock-names = "xclk"; ++ ++ AVDD-supply = <®_dldo3>; ++ DOVDD-supply = <®_aldo1>; ++ DVDD-supply = <®_eldo3>; ++ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */ ++ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ ++ ++ port { ++ ov5640_ep: endpoint { ++ remote-endpoint = <&csi_ep>; ++ bus-width = <8>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++ }; ++ }; ++ ++ speaker_amp: audio-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ ++ sound-name-prefix = "Speaker Amp"; ++ }; ++ ++ vdd_bl: regulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "bl-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ ++ enable-active-high; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&codec { ++ status = "okay"; ++}; ++ ++&codec_analog { ++ hpvcc-supply = <®_eldo1>; ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu2 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu3 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&csi { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi_ep: endpoint { ++ remote-endpoint = <&ov5640_ep>; ++ bus-width = <8>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++}; ++ ++&dai { ++ status = "okay"; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&dphy { ++ status = "okay"; ++}; ++ ++&dsi { ++ vcc-dsi-supply = <®_dldo1>; ++ status = "okay"; ++ ++ panel@0 { ++ compatible = "feixin,k101-im2ba02"; ++ reg = <0>; ++ avdd-supply = <®_dc1sw>; ++ dvdd-supply = <®_dc1sw>; ++ cvdd-supply = <®_ldo_io1>; ++ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ ++ backlight = <&backlight>; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ touchscreen@5d { ++ compatible = "goodix,gt9271"; ++ reg = <0x5d>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ ++ irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ ++ AVDD28-supply = <®_ldo_io1>; ++ }; ++}; ++ ++&i2c0_pins { ++ bias-pull-up; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ /* TODO: add Bochs BMA223 accelerometer here */ ++}; ++ ++&lradc { ++ vref-supply = <®_aldo3>; ++ status = "okay"; ++ ++ button-200 { ++ label = "Volume Up"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <200000>; ++ }; ++ ++ button-400 { ++ label = "Volume Down"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <400000>; ++ }; ++}; ++ ++&mixer1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_dldo4>; ++ vqmmc-supply = <®_eldo1>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723cs: wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&pwm { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ x-powers,drive-vbus-en; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++&ac_power_supply { ++ status = "okay"; ++}; ++ ++&battery_power_supply { ++ status = "okay"; ++}; ++ ++®_aldo1 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "dovdd-csi"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dc1sw { ++ regulator-name = "vcc-lcd"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi-dsi-sensor"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++}; ++ ++®_drivevbus { ++ regulator-name = "usb0-vbus"; ++ status = "okay"; ++}; ++ ++®_eldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_eldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca-1v8"; ++}; ++ ++®_eldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "dvdd-1v8-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_ldo_io0 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-usb"; ++ status = "okay"; ++}; ++ ++®_ldo_io1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <3500000>; ++ regulator-name = "vcc-touchscreen"; ++ status = "okay"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&sound { ++ status = "okay"; ++ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; ++ simple-audio-card,widgets = "Microphone", "Internal Microphone Left", ++ "Microphone", "Internal Microphone Right", ++ "Headphone", "Headphone Jack", ++ "Speaker", "Internal Speaker"; ++ simple-audio-card,routing = ++ "Left DAC", "AIF1 Slot 0 Left", ++ "Right DAC", "AIF1 Slot 0 Right", ++ "Speaker Amp INL", "LINEOUT", ++ "Speaker Amp INR", "LINEOUT", ++ "Internal Speaker", "Speaker Amp OUTL", ++ "Internal Speaker", "Speaker Amp OUTR", ++ "Headphone Jack", "HP", ++ "AIF1 Slot 0 Left ADC", "Left ADC", ++ "AIF1 Slot 0 Right ADC", "Right ADC", ++ "Internal Microphone Left", "MBIAS", ++ "MIC1", "Internal Microphone Left", ++ "Internal Microphone Right", "HBIAS", ++ "MIC2", "Internal Microphone Right"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pb_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usb_power_supply { ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ ++ usb0_vbus_power-supply = <&usb_power_supply>; ++ usb0_vbus-supply = <®_drivevbus>; ++ usb1_vbus-supply = <®_ldo_io0>; ++ status = "okay"; ++}; +-- +2.26.0 + +From 6bf15552c2b6becb48ce7732120e0ddb2078cb1a Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 14 Apr 2020 09:53:07 +0100 +Subject: [PATCH 9/9] initial pinetab support + +Signed-off-by: Peter Robinson +--- + configs/pinetab_defconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + create mode 100644 configs/pinetab_defconfig + +diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig +new file mode 100644 +index 0000000000..5b9620f3e5 +--- /dev/null ++++ b/configs/pinetab_defconfig +@@ -0,0 +1,26 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I=y ++CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y ++CONFIG_DRAM_CLK=552 ++CONFIG_DRAM_ZQ=3881949 ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_R_I2C_ENABLE=y ++CONFIG_SPL_SPI_SUNXI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_USE_PREBOOT=y ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab" ++CONFIG_OF_LIST="sun50i-a64-pinetab" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SUNXI=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +-- +2.26.0 + diff --git a/aarch64-boards b/aarch64-boards index 4e8f97c..c449481 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -48,6 +48,8 @@ p3450-0000 pine64-lts pine64_plus pinebook +pinephone +pinetab pine_h64 poplar puma-rk3399 diff --git a/sources b/sources index 50992b8..bd41109 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2020.04-rc5.tar.bz2) = 4fed5a45e9ebfc931cb4f06bbdb9ec1a477ed7dff902b8e9013fc7e41a78e4448749b88c450ee5ce62b6756031ec250f11e9afbea01bab2702ac6e9bb22f4ad2 +SHA512 (u-boot-2020.04.tar.bz2) = e04fe54883149123730605b084324ac0d1d72ce6913467bbe587a5a2675bcf7bb393405d9a446dc0c64ba42abc1e862ae5a132e9e51aa7390e2e9fce045af8d8 diff --git a/uboot-tools.spec b/uboot-tools.spec index 2002614..e362f8a 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -%global candidate rc5 +#global candidate rc1 Name: uboot-tools Version: 2020.04 -Release: 0.7%{?candidate:.%{candidate}}%{?dist} +Release: 1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -30,10 +30,11 @@ Patch7: efi_loader-enable-RNG-if-DM_RNG-is-enabled.patch Patch10: Misc-fixes-for-Tegra.patch Patch11: arm-tegra-define-fdtfile-option-for-distro-boot.patch Patch12: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch - # Rockchips improvements -Patch20: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch -Patch21: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch +Patch13: arm-dts-rockchip-rk3399-add-and-enable-rng-node.patch +Patch14: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch +# AllWinner improvements +Patch15: AllWinner-Pine64-bits.patch BuildRequires: bc BuildRequires: dtc @@ -255,6 +256,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Tue Apr 14 2020 Peter Robinson - 2020.04-1 +- 2020.04 + * Tue Apr 7 2020 Peter Robinson 2020.04-0.7-rc5 - 2020.04 RC5