diff --git a/0001-Revert-efi_loader-consider-no-map-property-of-reserv.patch b/0001-Revert-efi_loader-consider-no-map-property-of-reserv.patch new file mode 100644 index 0000000..485f966 --- /dev/null +++ b/0001-Revert-efi_loader-consider-no-map-property-of-reserv.patch @@ -0,0 +1,82 @@ +From 62f3f85e50692b2685d1056a041d1dbb9e16f2a4 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 13 Mar 2021 14:42:29 +0000 +Subject: [PATCH] Revert: efi_loader: consider no-map property of reserved + memory + +This basically reverts 4cbb2930bd8c, but not directly as it's moved +about since. The patch breaks SMP on the Raspberry Pi 3 (original 3B +and 3B+) so on Linux only one CPU core comes online. I'm not exactly +sure why but a bisect idendified the patch and sure enough a revert +fixes the issue. + +Signed-off-by: Peter Robinson +--- + lib/efi_loader/efi_dt_fixup.c | 33 ++++++--------------------------- + 1 file changed, 6 insertions(+), 27 deletions(-) + +diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c +index a4529ee3ef..87630f7857 100644 +--- a/lib/efi_loader/efi_dt_fixup.c ++++ b/lib/efi_loader/efi_dt_fixup.c +@@ -13,29 +13,13 @@ + + const efi_guid_t efi_guid_dt_fixup_protocol = EFI_DT_FIXUP_PROTOCOL_GUID; + +-/** +- * efi_reserve_memory() - add reserved memory to memory map +- * +- * @addr: start address of the reserved memory range +- * @size: size of the reserved memory range +- * @nomap: indicates that the memory range shall not be accessed by the +- * UEFI payload +- */ +-static void efi_reserve_memory(u64 addr, u64 size, bool nomap) ++static void efi_reserve_memory(u64 addr, u64 size) + { +- int type; +- efi_uintn_t ret; +- + /* Convert from sandbox address space. */ + addr = (uintptr_t)map_sysmem(addr, 0); ++ if (efi_add_memory_map(addr, size, ++ EFI_RESERVED_MEMORY_TYPE) != EFI_SUCCESS) + +- if (nomap) +- type = EFI_RESERVED_MEMORY_TYPE; +- else +- type = EFI_BOOT_SERVICES_DATA; +- +- ret = efi_add_memory_map(addr, size, type); +- if (ret != EFI_SUCCESS) + log_err("Reserved memory mapping failed addr %llx size %llx\n", + addr, size); + } +@@ -61,7 +45,7 @@ void efi_carve_out_dt_rsv(void *fdt) + for (i = 0; i < nr_rsv; i++) { + if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0) + continue; +- efi_reserve_memory(addr, size, false); ++ efi_reserve_memory(addr, size); + } + + /* process reserved-memory */ +@@ -81,13 +65,8 @@ void efi_carve_out_dt_rsv(void *fdt) + * a size instead of a reg property. + */ + if (fdt_addr != FDT_ADDR_T_NONE && +- fdtdec_get_is_enabled(fdt, subnode)) { +- bool nomap; +- +- nomap = !!fdt_getprop(fdt, subnode, "no-map", +- NULL); +- efi_reserve_memory(fdt_addr, fdt_size, nomap); +- } ++ fdtdec_get_is_enabled(fdt, subnode)) ++ efi_reserve_memory(fdt_addr, fdt_size); + subnode = fdt_next_subnode(fdt, subnode); + } + } +-- +2.30.2 + diff --git a/sunxi-support-asymmetric-dual-rank-DRAM-on-A64.patch b/sunxi-support-asymmetric-dual-rank-DRAM-on-A64.patch new file mode 100644 index 0000000..c2b6946 --- /dev/null +++ b/sunxi-support-asymmetric-dual-rank-DRAM-on-A64.patch @@ -0,0 +1,337 @@ +From patchwork Thu Feb 25 16:13:24 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Icenowy Zheng +X-Patchwork-Id: 1444507 +X-Patchwork-Delegate: andre.przywara@arm.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=85.214.62.61; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=) +Authentication-Results: ozlabs.org; + dkim=fail reason="signature verification failed" (1024-bit key; + unprotected) header.d=mymailcheap.com header.i=@mymailcheap.com + header.a=rsa-sha256 header.s=default header.b=cioDKJo2; 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Reverse +engineering of newest libdram of A64 from Allwinner shows that A64 has +this register too. It's bit 0 (which enables dual rank in rank 0 +configuration register) means a dedicated rank size setup is used for +rank 1. + +Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB +rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank +DRAM support necessary. + +Add this support. The code could support both A64 and R40, but because +dual rank detection is broken on R40 now, we cannot really use it on R40 +currently. + +Signed-off-by: Icenowy Zheng +--- + .../include/asm/arch-sunxi/dram_sunxi_dw.h | 11 ++- + arch/arm/mach-sunxi/dram_sunxi_dw.c | 94 +++++++++++++++---- + 2 files changed, 82 insertions(+), 23 deletions(-) + +diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +index a5a7ebde44..e843c14202 100644 +--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h ++++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +@@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg { + #define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) + /* The eight data lines (DQn) plus DM, DQS and DQSN */ + #define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) +-struct dram_para { ++ ++struct rank_para { + u16 page_size; +- u8 bus_full_width; +- u8 dual_rank; + u8 row_bits; + u8 bank_bits; ++}; ++ ++struct dram_para { ++ u8 dual_rank; ++ u8 bus_full_width; ++ struct rank_para ranks[2]; + const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 ac_delays[31]; +diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c +index d0600011ff..2b9d631d49 100644 +--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c ++++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c +@@ -399,11 +399,19 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para) + #else + #error Unsupported DRAM type! + #endif +- (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | ++ (para->ranks[0].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | + MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | + (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | +- MCTL_CR_PAGE_SIZE(para->page_size) | +- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); ++ MCTL_CR_PAGE_SIZE(para->ranks[0].page_size) | ++ MCTL_CR_ROW_BITS(para->ranks[0].row_bits), &mctl_com->cr); ++ ++ if (para->dual_rank && (socid == SOCID_A64 || socid == SOCID_R40)) { ++ writel((para->ranks[1].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | ++ MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | ++ MCTL_CR_DUAL_RANK | ++ MCTL_CR_PAGE_SIZE(para->ranks[1].page_size) | ++ MCTL_CR_ROW_BITS(para->ranks[1].row_bits), &mctl_com->cr_r1); ++ } + + if (socid == SOCID_R40) { + if (para->dual_rank) +@@ -646,35 +654,63 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) + return 0; + } + +-static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) ++/* ++ * Test if memory at offset offset matches memory at a certain base ++ */ ++static bool mctl_mem_matches_base(u32 offset, ulong base) ++{ ++ /* Try to write different values to RAM at two addresses */ ++ writel(0, base); ++ writel(0xaa55aa55, base + offset); ++ dsb(); ++ /* Check if the same value is actually observed when reading back */ ++ return readl(base) == ++ readl(base + offset); ++} ++ ++static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank) + { + /* detect row address bits */ +- para->page_size = 512; +- para->row_bits = 16; +- para->bank_bits = 2; ++ rank->page_size = 512; ++ rank->row_bits = 16; ++ rank->bank_bits = 2; + mctl_set_cr(socid, para); + +- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) +- if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size)) ++ for (rank->row_bits = 11; rank->row_bits < 16; rank->row_bits++) ++ if (mctl_mem_matches_base((1 << (rank->row_bits + rank->bank_bits)) * rank->page_size, base)) + break; + + /* detect bank address bits */ +- para->bank_bits = 3; ++ rank->bank_bits = 3; + mctl_set_cr(socid, para); + +- for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++) +- if (mctl_mem_matches((1 << para->bank_bits) * para->page_size)) ++ for (rank->bank_bits = 2; rank->bank_bits < 3; rank->bank_bits++) ++ if (mctl_mem_matches_base((1 << rank->bank_bits) * rank->page_size, base)) + break; + + /* detect page size */ +- para->page_size = 8192; ++ rank->page_size = 8192; + mctl_set_cr(socid, para); + +- for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2) +- if (mctl_mem_matches(para->page_size)) ++ for (rank->page_size = 512; rank->page_size < 8192; rank->page_size *= 2) ++ if (mctl_mem_matches_base(rank->page_size, base)) + break; + } + ++static unsigned long mctl_calc_rank_size(struct rank_para *rank) ++{ ++ return (1UL << (rank->row_bits + rank->bank_bits)) * rank->page_size; ++} ++ ++static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) ++{ ++ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]); ++ ++ if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) { ++ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); ++ } ++} ++ + /* + * The actual values used here are taken from Allwinner provided boot0 + * binaries, though they are probably board specific, so would likely benefit +@@ -769,12 +805,23 @@ unsigned long sunxi_dram_init(void) + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + ++ unsigned long size; ++ + struct dram_para para = { + .dual_rank = 1, + .bus_full_width = 1, +- .row_bits = 15, +- .bank_bits = 3, +- .page_size = 4096, ++ .ranks = { ++ { ++ .row_bits = 15, ++ .bank_bits = 3, ++ .page_size = 4096, ++ }, ++ { ++ .row_bits = 15, ++ .bank_bits = 3, ++ .page_size = 4096, ++ } ++ }, + + #if defined(CONFIG_MACH_SUN8I_H3) + .dx_read_delays = SUN8I_H3_DX_READ_DELAYS, +@@ -846,6 +893,13 @@ unsigned long sunxi_dram_init(void) + mctl_auto_detect_dram_size(socid, ¶); + mctl_set_cr(socid, ¶); + +- return (1UL << (para.row_bits + para.bank_bits)) * para.page_size * +- (para.dual_rank ? 2 : 1); ++ size = mctl_calc_rank_size(¶.ranks[0]); ++ if (socid == SOCID_A64 || socid == SOCID_R40) { ++ if (para.dual_rank) ++ size += mctl_calc_rank_size(¶.ranks[1]); ++ } else if (para.dual_rank) { ++ size *= 2; ++ } ++ ++ return size; + } diff --git a/uboot-tools.spec b/uboot-tools.spec index 17539a5..5660be2 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,7 +2,7 @@ Name: uboot-tools Version: 2021.04 -Release: 0.4%{?candidate:.%{candidate}}%{?dist} +Release: 0.5%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -22,6 +22,7 @@ Patch2: uefi-use-Fedora-specific-path-name.patch Patch3: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch # Board fixes and enablement +Patch9: 0001-Revert-efi_loader-consider-no-map-property-of-reserv.patch # AllWinner improvements Patch10: AllWinner-PineTab.patch # TI fixes @@ -30,6 +31,7 @@ Patch11: 0001-Fix-BeagleAI-detection.patch Patch12: rk3399-Pinebook-pro-EDP-support.patch # Fixes for Allwinner network issues Patch13: 0001-arm-dts-allwinner-sync-from-linux-for-RGMII-RX-TX-de.patch +Patch14: sunxi-support-asymmetric-dual-rank-DRAM-on-A64.patch BuildRequires: bc BuildRequires: dtc @@ -241,6 +243,10 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Sat Mar 13 2021 Peter Robinson - 2021.04-0.5.rc3 +- Fix for SMP on RPi3B and RPi3B+ +- Initial support for Pinephone 3Gb edition + * Mon Mar 08 2021 Peter Robinson - 2021.04-0.4.rc3 - Update to 2021.04 RC3