Fixes for SMP on RPi3, initial patch for pinepohone 3g
This commit is contained in:
Peter Robinson
parent
f458c5418f
commit
2abadc5169
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@ -0,0 +1,82 @@
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From 62f3f85e50692b2685d1056a041d1dbb9e16f2a4 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Sat, 13 Mar 2021 14:42:29 +0000
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Subject: [PATCH] Revert: efi_loader: consider no-map property of reserved
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memory
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This basically reverts 4cbb2930bd8c, but not directly as it's moved
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about since. The patch breaks SMP on the Raspberry Pi 3 (original 3B
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and 3B+) so on Linux only one CPU core comes online. I'm not exactly
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sure why but a bisect idendified the patch and sure enough a revert
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fixes the issue.
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Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
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---
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lib/efi_loader/efi_dt_fixup.c | 33 ++++++---------------------------
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1 file changed, 6 insertions(+), 27 deletions(-)
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diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c
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index a4529ee3ef..87630f7857 100644
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--- a/lib/efi_loader/efi_dt_fixup.c
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+++ b/lib/efi_loader/efi_dt_fixup.c
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@@ -13,29 +13,13 @@
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const efi_guid_t efi_guid_dt_fixup_protocol = EFI_DT_FIXUP_PROTOCOL_GUID;
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-/**
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- * efi_reserve_memory() - add reserved memory to memory map
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- *
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- * @addr: start address of the reserved memory range
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- * @size: size of the reserved memory range
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- * @nomap: indicates that the memory range shall not be accessed by the
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- * UEFI payload
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- */
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-static void efi_reserve_memory(u64 addr, u64 size, bool nomap)
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+static void efi_reserve_memory(u64 addr, u64 size)
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{
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- int type;
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- efi_uintn_t ret;
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-
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/* Convert from sandbox address space. */
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addr = (uintptr_t)map_sysmem(addr, 0);
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+ if (efi_add_memory_map(addr, size,
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+ EFI_RESERVED_MEMORY_TYPE) != EFI_SUCCESS)
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- if (nomap)
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- type = EFI_RESERVED_MEMORY_TYPE;
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- else
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- type = EFI_BOOT_SERVICES_DATA;
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-
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- ret = efi_add_memory_map(addr, size, type);
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- if (ret != EFI_SUCCESS)
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log_err("Reserved memory mapping failed addr %llx size %llx\n",
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addr, size);
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}
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@@ -61,7 +45,7 @@ void efi_carve_out_dt_rsv(void *fdt)
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for (i = 0; i < nr_rsv; i++) {
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if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0)
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continue;
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- efi_reserve_memory(addr, size, false);
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+ efi_reserve_memory(addr, size);
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}
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/* process reserved-memory */
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@@ -81,13 +65,8 @@ void efi_carve_out_dt_rsv(void *fdt)
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* a size instead of a reg property.
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*/
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if (fdt_addr != FDT_ADDR_T_NONE &&
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- fdtdec_get_is_enabled(fdt, subnode)) {
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- bool nomap;
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-
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- nomap = !!fdt_getprop(fdt, subnode, "no-map",
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- NULL);
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- efi_reserve_memory(fdt_addr, fdt_size, nomap);
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- }
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+ fdtdec_get_is_enabled(fdt, subnode))
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+ efi_reserve_memory(fdt_addr, fdt_size);
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subnode = fdt_next_subnode(fdt, subnode);
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}
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}
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--
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2.30.2
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From: Icenowy Zheng <icenowy@aosc.io>
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To: Jagan Teki <jagan@amarulasolutions.com>,
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Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com,
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Icenowy Zheng <icenowy@aosc.io>
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Subject: [PATCH 1/2] sunxi: support asymmetric dual rank DRAM on A64/R40
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Date: Fri, 26 Feb 2021 00:13:24 +0800
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Previously we have known that R40 has a configuration register for its
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rank 1, which allows different configuration than rank 0. Reverse
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engineering of newest libdram of A64 from Allwinner shows that A64 has
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this register too. It's bit 0 (which enables dual rank in rank 0
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configuration register) means a dedicated rank size setup is used for
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rank 1.
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Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB
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rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank
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DRAM support necessary.
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Add this support. The code could support both A64 and R40, but because
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dual rank detection is broken on R40 now, we cannot really use it on R40
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currently.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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.../include/asm/arch-sunxi/dram_sunxi_dw.h | 11 ++-
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arch/arm/mach-sunxi/dram_sunxi_dw.c | 94 +++++++++++++++----
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2 files changed, 82 insertions(+), 23 deletions(-)
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diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
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index a5a7ebde44..e843c14202 100644
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--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
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+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
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@@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg {
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#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
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/* The eight data lines (DQn) plus DM, DQS and DQSN */
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#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
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-struct dram_para {
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+
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+struct rank_para {
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u16 page_size;
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- u8 bus_full_width;
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- u8 dual_rank;
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u8 row_bits;
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u8 bank_bits;
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+};
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+
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+struct dram_para {
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+ u8 dual_rank;
|
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+ u8 bus_full_width;
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+ struct rank_para ranks[2];
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const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 ac_delays[31];
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diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
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index d0600011ff..2b9d631d49 100644
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--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
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+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
|
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@@ -399,11 +399,19 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
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#else
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#error Unsupported DRAM type!
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#endif
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- (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
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+ (para->ranks[0].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
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MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
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(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
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- MCTL_CR_PAGE_SIZE(para->page_size) |
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- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
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+ MCTL_CR_PAGE_SIZE(para->ranks[0].page_size) |
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+ MCTL_CR_ROW_BITS(para->ranks[0].row_bits), &mctl_com->cr);
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+
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+ if (para->dual_rank && (socid == SOCID_A64 || socid == SOCID_R40)) {
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+ writel((para->ranks[1].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
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+ MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
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+ MCTL_CR_DUAL_RANK |
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+ MCTL_CR_PAGE_SIZE(para->ranks[1].page_size) |
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+ MCTL_CR_ROW_BITS(para->ranks[1].row_bits), &mctl_com->cr_r1);
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+ }
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if (socid == SOCID_R40) {
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if (para->dual_rank)
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@@ -646,35 +654,63 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
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return 0;
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}
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-static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
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+/*
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+ * Test if memory at offset offset matches memory at a certain base
|
||||
+ */
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||||
+static bool mctl_mem_matches_base(u32 offset, ulong base)
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||||
+{
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||||
+ /* Try to write different values to RAM at two addresses */
|
||||
+ writel(0, base);
|
||||
+ writel(0xaa55aa55, base + offset);
|
||||
+ dsb();
|
||||
+ /* Check if the same value is actually observed when reading back */
|
||||
+ return readl(base) ==
|
||||
+ readl(base + offset);
|
||||
+}
|
||||
+
|
||||
+static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank)
|
||||
{
|
||||
/* detect row address bits */
|
||||
- para->page_size = 512;
|
||||
- para->row_bits = 16;
|
||||
- para->bank_bits = 2;
|
||||
+ rank->page_size = 512;
|
||||
+ rank->row_bits = 16;
|
||||
+ rank->bank_bits = 2;
|
||||
mctl_set_cr(socid, para);
|
||||
|
||||
- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
|
||||
- if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))
|
||||
+ for (rank->row_bits = 11; rank->row_bits < 16; rank->row_bits++)
|
||||
+ if (mctl_mem_matches_base((1 << (rank->row_bits + rank->bank_bits)) * rank->page_size, base))
|
||||
break;
|
||||
|
||||
/* detect bank address bits */
|
||||
- para->bank_bits = 3;
|
||||
+ rank->bank_bits = 3;
|
||||
mctl_set_cr(socid, para);
|
||||
|
||||
- for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
|
||||
- if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
|
||||
+ for (rank->bank_bits = 2; rank->bank_bits < 3; rank->bank_bits++)
|
||||
+ if (mctl_mem_matches_base((1 << rank->bank_bits) * rank->page_size, base))
|
||||
break;
|
||||
|
||||
/* detect page size */
|
||||
- para->page_size = 8192;
|
||||
+ rank->page_size = 8192;
|
||||
mctl_set_cr(socid, para);
|
||||
|
||||
- for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
|
||||
- if (mctl_mem_matches(para->page_size))
|
||||
+ for (rank->page_size = 512; rank->page_size < 8192; rank->page_size *= 2)
|
||||
+ if (mctl_mem_matches_base(rank->page_size, base))
|
||||
break;
|
||||
}
|
||||
|
||||
+static unsigned long mctl_calc_rank_size(struct rank_para *rank)
|
||||
+{
|
||||
+ return (1UL << (rank->row_bits + rank->bank_bits)) * rank->page_size;
|
||||
+}
|
||||
+
|
||||
+static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
|
||||
+{
|
||||
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]);
|
||||
+
|
||||
+ if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
|
||||
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* The actual values used here are taken from Allwinner provided boot0
|
||||
* binaries, though they are probably board specific, so would likely benefit
|
||||
@@ -769,12 +805,23 @@ unsigned long sunxi_dram_init(void)
|
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl =
|
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
|
||||
|
||||
+ unsigned long size;
|
||||
+
|
||||
struct dram_para para = {
|
||||
.dual_rank = 1,
|
||||
.bus_full_width = 1,
|
||||
- .row_bits = 15,
|
||||
- .bank_bits = 3,
|
||||
- .page_size = 4096,
|
||||
+ .ranks = {
|
||||
+ {
|
||||
+ .row_bits = 15,
|
||||
+ .bank_bits = 3,
|
||||
+ .page_size = 4096,
|
||||
+ },
|
||||
+ {
|
||||
+ .row_bits = 15,
|
||||
+ .bank_bits = 3,
|
||||
+ .page_size = 4096,
|
||||
+ }
|
||||
+ },
|
||||
|
||||
#if defined(CONFIG_MACH_SUN8I_H3)
|
||||
.dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
|
||||
@@ -846,6 +893,13 @@ unsigned long sunxi_dram_init(void)
|
||||
mctl_auto_detect_dram_size(socid, ¶);
|
||||
mctl_set_cr(socid, ¶);
|
||||
|
||||
- return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
|
||||
- (para.dual_rank ? 2 : 1);
|
||||
+ size = mctl_calc_rank_size(¶.ranks[0]);
|
||||
+ if (socid == SOCID_A64 || socid == SOCID_R40) {
|
||||
+ if (para.dual_rank)
|
||||
+ size += mctl_calc_rank_size(¶.ranks[1]);
|
||||
+ } else if (para.dual_rank) {
|
||||
+ size *= 2;
|
||||
+ }
|
||||
+
|
||||
+ return size;
|
||||
}
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
Name: uboot-tools
|
||||
Version: 2021.04
|
||||
Release: 0.4%{?candidate:.%{candidate}}%{?dist}
|
||||
Release: 0.5%{?candidate:.%{candidate}}%{?dist}
|
||||
Summary: U-Boot utilities
|
||||
License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
|
||||
URL: http://www.denx.de/wiki/U-Boot
|
||||
|
|
@ -22,6 +22,7 @@ Patch2: uefi-use-Fedora-specific-path-name.patch
|
|||
Patch3: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
|
||||
|
||||
# Board fixes and enablement
|
||||
Patch9: 0001-Revert-efi_loader-consider-no-map-property-of-reserv.patch
|
||||
# AllWinner improvements
|
||||
Patch10: AllWinner-PineTab.patch
|
||||
# TI fixes
|
||||
|
|
@ -30,6 +31,7 @@ Patch11: 0001-Fix-BeagleAI-detection.patch
|
|||
Patch12: rk3399-Pinebook-pro-EDP-support.patch
|
||||
# Fixes for Allwinner network issues
|
||||
Patch13: 0001-arm-dts-allwinner-sync-from-linux-for-RGMII-RX-TX-de.patch
|
||||
Patch14: sunxi-support-asymmetric-dual-rank-DRAM-on-A64.patch
|
||||
|
||||
BuildRequires: bc
|
||||
BuildRequires: dtc
|
||||
|
|
@ -241,6 +243,10 @@ cp -p board/warp7/README builds/docs/README.warp7
|
|||
%endif
|
||||
|
||||
%changelog
|
||||
* Sat Mar 13 2021 Peter Robinson <pbrobinson@fedoraproject.org> - 2021.04-0.5.rc3
|
||||
- Fix for SMP on RPi3B and RPi3B+
|
||||
- Initial support for Pinephone 3Gb edition
|
||||
|
||||
* Mon Mar 08 2021 Peter Robinson <pbrobinson@fedoraproject.org> - 2021.04-0.4.rc3
|
||||
- Update to 2021.04 RC3
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue