diff --git a/AllWinner-Pine64-bits.patch b/AllWinner-Pine64-bits.patch index 569afc8..8ce13e7 100644 --- a/AllWinner-Pine64-bits.patch +++ b/AllWinner-Pine64-bits.patch @@ -1,15 +1,403 @@ -From 2c213379d9ec786480a655f8c5687b2df376017f Mon Sep 17 00:00:00 2001 +From 6e5d771060dff5350e5940b7e457884b47a560ac Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 10 Mar 2020 12:27:15 +0000 -Subject: [PATCH 1/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.6-rc1 +Date: Thu, 9 Jul 2020 12:20:53 +0100 +Subject: [PATCH 1/8] dt-bindings: clk: sync sun50i-a64-ccu.h to linux 5.8-rc1 + +Sync the clock bindings for the Allwinner A64 to Linux Signed-off-by: Peter Robinson --- - arch/arm/dts/sun50i-a64.dtsi | 472 ++++++++++++++++++++++++++++------- - 1 file changed, 387 insertions(+), 85 deletions(-) + include/dt-bindings/clock/sun50i-a64-ccu.h | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h +index d66432c6e6..318eb15c41 100644 +--- a/include/dt-bindings/clock/sun50i-a64-ccu.h ++++ b/include/dt-bindings/clock/sun50i-a64-ccu.h +@@ -43,8 +43,10 @@ + #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ + #define _DT_BINDINGS_CLK_SUN50I_A64_H_ + ++#define CLK_PLL_VIDEO0 7 + #define CLK_PLL_PERIPH0 11 + ++#define CLK_CPUX 21 + #define CLK_BUS_MIPI_DSI 28 + #define CLK_BUS_CE 29 + #define CLK_BUS_DMA 30 +@@ -129,7 +131,7 @@ + #define CLK_AVS 109 + #define CLK_HDMI 110 + #define CLK_HDMI_DDC 111 +- ++#define CLK_MBUS 112 + #define CLK_DSI_DPHY 113 + #define CLK_GPU 114 + +-- +2.26.2 + +From 274dff055e80778277860f72a903c01ef33f87c7 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 9 Jul 2020 12:29:15 +0100 +Subject: [PATCH 2/8] dt-bindings: leds: sync leds common.h to linux from + 5.8-rc1 + +Sync the leds common.h to the latest Linux version. + +Signed-off-by: Peter Robinson +--- + include/dt-bindings/leds/common.h | 36 ++++++++++++++++++++++--------- + 1 file changed, 26 insertions(+), 10 deletions(-) + +diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h +index 9e1256a7c1..0ce7dfc00d 100644 +--- a/include/dt-bindings/leds/common.h ++++ b/include/dt-bindings/leds/common.h +@@ -6,6 +6,7 @@ + * Author: Jacek Anaszewski + * + * Copyright (C) 2019 Jacek Anaszewski ++ * Copyright (C) 2020 Pavel Machek + */ + + #ifndef __DT_BINDINGS_LEDS_H +@@ -32,16 +33,38 @@ + #define LED_COLOR_ID_MAX 8 + + /* Standard LED functions */ ++/* Keyboard LEDs, usually it would be input4::capslock etc. */ ++/* Obsolete equivalent: "shift-key-light" */ ++#define LED_FUNCTION_CAPSLOCK "capslock" ++#define LED_FUNCTION_SCROLLLOCK "scrolllock" ++#define LED_FUNCTION_NUMLOCK "numlock" ++/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads), ++ "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */ ++#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" ++ ++/* System LEDs, usually found on system body. ++ platform::mute (etc) is sometimes seen, :mute would be better */ ++#define LED_FUNCTION_POWER "power" ++#define LED_FUNCTION_DISK "disk" ++ ++/* Obsolete: "platform:*:charging" (allwinner sun50i) */ ++#define LED_FUNCTION_CHARGING "charging" ++/* Used RGB notification LEDs common on phones. ++ Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4), ++ "lp5523:{r,g,b}" (Nokia N900) */ ++#define LED_FUNCTION_STATUS "status" ++ ++#define LED_FUNCTION_MICMUTE "micmute" ++#define LED_FUNCTION_MUTE "mute" ++ ++/* Miscelleaus functions. Use functions above if you can. */ + #define LED_FUNCTION_ACTIVITY "activity" + #define LED_FUNCTION_ALARM "alarm" + #define LED_FUNCTION_BACKLIGHT "backlight" + #define LED_FUNCTION_BLUETOOTH "bluetooth" + #define LED_FUNCTION_BOOT "boot" + #define LED_FUNCTION_CPU "cpu" +-#define LED_FUNCTION_CAPSLOCK "capslock" +-#define LED_FUNCTION_CHARGING "charging" + #define LED_FUNCTION_DEBUG "debug" +-#define LED_FUNCTION_DISK "disk" + #define LED_FUNCTION_DISK_ACTIVITY "disk-activity" + #define LED_FUNCTION_DISK_ERR "disk-err" + #define LED_FUNCTION_DISK_READ "disk-read" +@@ -50,21 +73,14 @@ + #define LED_FUNCTION_FLASH "flash" + #define LED_FUNCTION_HEARTBEAT "heartbeat" + #define LED_FUNCTION_INDICATOR "indicator" +-#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" + #define LED_FUNCTION_LAN "lan" + #define LED_FUNCTION_MAIL "mail" + #define LED_FUNCTION_MTD "mtd" +-#define LED_FUNCTION_MICMUTE "micmute" +-#define LED_FUNCTION_MUTE "mute" +-#define LED_FUNCTION_NUMLOCK "numlock" + #define LED_FUNCTION_PANIC "panic" + #define LED_FUNCTION_PROGRAMMING "programming" +-#define LED_FUNCTION_POWER "power" + #define LED_FUNCTION_RX "rx" + #define LED_FUNCTION_SD "sd" +-#define LED_FUNCTION_SCROLLLOCK "scrolllock" + #define LED_FUNCTION_STANDBY "standby" +-#define LED_FUNCTION_STATUS "status" + #define LED_FUNCTION_TORCH "torch" + #define LED_FUNCTION_TX "tx" + #define LED_FUNCTION_USB "usb" +-- +2.26.2 + +From 7010e7d2b19d2ded674e376855d2716b7cd421b7 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 10 Jul 2020 12:46:11 +0100 +Subject: [PATCH 3/8] dt-bindings: clk/reset: sync updated bindings for + Allwinner DE2 display engine + +Sync the clock and reset bindings for the Allwinner DE2 display engine to Linux 5.8-rc1. + +Signed-off-by: Peter Robinson +--- + include/dt-bindings/clock/sun8i-de2.h | 3 +++ + include/dt-bindings/reset/sun8i-de2.h | 1 + + 2 files changed, 4 insertions(+) + +diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h +index 3bed63b524..7768f73b05 100644 +--- a/include/dt-bindings/clock/sun8i-de2.h ++++ b/include/dt-bindings/clock/sun8i-de2.h +@@ -15,4 +15,7 @@ + #define CLK_MIXER1 7 + #define CLK_WB 8 + ++#define CLK_BUS_ROT 9 ++#define CLK_ROT 10 ++ + #endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ +diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h +index 9526017432..1c36a6ac86 100644 +--- a/include/dt-bindings/reset/sun8i-de2.h ++++ b/include/dt-bindings/reset/sun8i-de2.h +@@ -10,5 +10,6 @@ + #define RST_MIXER0 0 + #define RST_MIXER1 1 + #define RST_WB 2 ++#define RST_ROT 3 + + #endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ +-- +2.26.2 + +From bdbf5f21343571af989754c908299854e81f44dd Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 9 Jul 2020 12:24:41 +0100 +Subject: [PATCH 4/8] arm: dts: sync axp803.dtsi from linux 5.8-rc1 + +Sync the Allwinner axp803 device tree to the latest upstream Linux. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/axp803.dtsi | 82 ++++++++++++++++++++-------------------- + 1 file changed, 41 insertions(+), 41 deletions(-) + +diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi +index e5eae8bafc..10e9186a76 100644 +--- a/arch/arm/dts/axp803.dtsi ++++ b/arch/arm/dts/axp803.dtsi +@@ -1,44 +1,5 @@ +-/* +- * Copyright 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright 2017 Icenowy Zheng + + /* + * AXP803 Integrated Power Management Chip +@@ -49,6 +10,39 @@ + interrupt-controller; + #interrupt-cells = <1>; + ++ ac_power_supply: ac-power-supply { ++ compatible = "x-powers,axp803-ac-power-supply", ++ "x-powers,axp813-ac-power-supply"; ++ status = "disabled"; ++ }; ++ ++ axp_adc: adc { ++ compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; ++ #io-channel-cells = <1>; ++ }; ++ ++ axp_gpio: gpio { ++ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ gpio0_ldo: gpio0-ldo { ++ pins = "GPIO0"; ++ function = "ldo"; ++ }; ++ ++ gpio1_ldo: gpio1-ldo { ++ pins = "GPIO1"; ++ function = "ldo"; ++ }; ++ }; ++ ++ battery_power_supply: battery-power-supply { ++ compatible = "x-powers,axp803-battery-power-supply", ++ "x-powers,axp813-battery-power-supply"; ++ status = "disabled"; ++ }; ++ + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; +@@ -152,4 +146,10 @@ + status = "disabled"; + }; + }; ++ ++ usb_power_supply: usb-power-supply { ++ compatible = "x-powers,axp803-usb-power-supply", ++ "x-powers,axp813-usb-power-supply"; ++ status = "disabled"; ++ }; + }; +-- +2.26.2 + +From e0f7e9ce1a8a889bf7a1c5842700f0cb368bc81b Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 9 Jul 2020 12:26:34 +0100 +Subject: [PATCH 5/8] arm: dts: Add new sun50i-a64-cpu-opp.dtsi from Linux + 5.8-rc1 + +Sync the Allwinner A64 CPU operating points dtsi from Linux. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 75 ++++++++++++++++++++++++++++ + 1 file changed, 75 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-cpu-opp.dtsi + +diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi +new file mode 100644 +index 0000000000..578c37490d +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi +@@ -0,0 +1,75 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020 Vasily khoruzhick ++ */ ++ ++/ { ++ cpu0_opp_table: opp_table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-648000000 { ++ opp-hz = /bits/ 64 <648000000>; ++ opp-microvolt = <1040000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-912000000 { ++ opp-hz = /bits/ 64 <912000000>; ++ opp-microvolt = <1120000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-960000000 { ++ opp-hz = /bits/ 64 <960000000>; ++ opp-microvolt = <1160000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1200000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1240000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1260000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; +-- +2.26.2 + +From b077a5962ba631e198d42c14516426b878c157eb Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 10 Jul 2020 12:39:21 +0100 +Subject: [PATCH 6/8] arm: dts: Sync the sun50i-a64.dtsi from Linux 5.8-rc1 + +Sync the Allwinner A64 sun50i-a64.dtsi from Linux. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64.dtsi | 532 ++++++++++++++++++++++++++++------- + 1 file changed, 434 insertions(+), 98 deletions(-) diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi -index ff41abc96a..862b47dc9d 100644 +index ff41abc96a..8dfbcd1440 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -1,46 +1,7 @@ @@ -147,12 +535,14 @@ index ff41abc96a..862b47dc9d 100644 }; psci { -@@ -155,6 +130,30 @@ +@@ -155,26 +130,33 @@ method = "smc"; }; +- sound_spdif { + sound: sound { -+ compatible = "simple-audio-card"; + compatible = "simple-audio-card"; +- simple-audio-card,name = "On-board SPDIF"; + simple-audio-card,name = "sun50i-a64-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; @@ -165,28 +555,32 @@ index ff41abc96a..862b47dc9d 100644 + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC"; + status = "disabled"; -+ + +- simple-audio-card,cpu { +- sound-dai = <&spdif>; + cpudai: simple-audio-card,cpu { + sound-dai = <&dai>; -+ }; -+ + }; + +- simple-audio-card,codec { +- sound-dai = <&spdif_out>; + link_codec: simple-audio-card,codec { + sound-dai = <&codec>; -+ }; -+ }; -+ - sound_spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; -@@ -175,6 +174,7 @@ + }; + }; +- spdif_out: spdif-out { +- #sound-dai-cells = <0>; +- compatible = "linux,spdif-dit"; +- }; +- timer { compatible = "arm,armv8-timer"; + allwinner,erratum-unknown1; interrupts = , ; }; @@ -264,14 +658,16 @@ index ff41abc96a..862b47dc9d 100644 compatible = "allwinner,sun50i-a64-de2"; reg = <0x1000000 0x400000>; allwinner,sram = <&de2_sram 1>; -@@ -202,10 +265,10 @@ +@@ -201,16 +246,28 @@ + display_clocks: clock@0 { compatible = "allwinner,sun50i-a64-de2-clk"; - reg = <0x0 0x100000>; +- reg = <0x0 0x100000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; ++ reg = <0x0 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", @@ -279,7 +675,24 @@ index ff41abc96a..862b47dc9d 100644 resets = <&ccu RST_BUS_DE>; #clock-cells = <1>; #reset-cells = <1>; -@@ -225,11 +288,19 @@ + }; + ++ rotate: rotate@20000 { ++ compatible = "allwinner,sun50i-a64-de2-rotate", ++ "allwinner,sun8i-a83t-de2-rotate"; ++ reg = <0x20000 0x10000>; ++ interrupts = ; ++ clocks = <&display_clocks CLK_BUS_ROT>, ++ <&display_clocks CLK_ROT>; ++ clock-names = "bus", ++ "mod"; ++ resets = <&display_clocks RST_ROT>; ++ }; ++ + mixer0: mixer@100000 { + compatible = "allwinner,sun50i-a64-de2-mixer-0"; + reg = <0x100000 0x100000>; +@@ -225,11 +282,19 @@ #size-cells = <0>; mixer0_out: port@1 { @@ -300,7 +713,7 @@ index ff41abc96a..862b47dc9d 100644 }; }; }; -@@ -248,9 +319,17 @@ +@@ -248,9 +313,17 @@ #size-cells = <0>; mixer1_out: port@1 { @@ -319,7 +732,7 @@ index ff41abc96a..862b47dc9d 100644 remote-endpoint = <&tcon1_in_mixer1>; }; }; -@@ -259,8 +338,7 @@ +@@ -259,8 +332,7 @@ }; syscon: syscon@1c00000 { @@ -329,7 +742,7 @@ index ff41abc96a..862b47dc9d 100644 reg = <0x01c00000 0x1000>; #address-cells = <1>; #size-cells = <1>; -@@ -278,6 +356,20 @@ +@@ -278,6 +350,20 @@ reg = <0x0000 0x28000>; }; }; @@ -350,7 +763,7 @@ index ff41abc96a..862b47dc9d 100644 }; dma: dma-controller@1c02000 { -@@ -299,6 +391,7 @@ +@@ -299,6 +385,7 @@ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-pixel-clock"; @@ -358,7 +771,7 @@ index ff41abc96a..862b47dc9d 100644 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; -@@ -315,12 +408,23 @@ +@@ -315,12 +402,23 @@ reg = <0>; remote-endpoint = <&mixer0_out_tcon0>; }; @@ -382,7 +795,7 @@ index ff41abc96a..862b47dc9d 100644 }; }; }; -@@ -340,9 +444,17 @@ +@@ -340,9 +438,17 @@ #size-cells = <0>; tcon1_in: port@0 { @@ -401,7 +814,7 @@ index ff41abc96a..862b47dc9d 100644 remote-endpoint = <&mixer1_out_tcon1>; }; }; -@@ -360,6 +472,17 @@ +@@ -360,6 +466,17 @@ }; }; @@ -419,7 +832,7 @@ index ff41abc96a..862b47dc9d 100644 mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c0f000 0x1000>; -@@ -405,6 +528,21 @@ +@@ -405,6 +522,31 @@ sid: eeprom@1c14000 { compatible = "allwinner,sun50i-a64-sid"; reg = <0x1c14000 0x400>; @@ -438,10 +851,20 @@ index ff41abc96a..862b47dc9d 100644 + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; ++ }; ++ ++ msgbox: mailbox@1c17000 { ++ compatible = "allwinner,sun50i-a64-msgbox", ++ "allwinner,sun6i-a31-msgbox"; ++ reg = <0x01c17000 0x1000>; ++ clocks = <&ccu CLK_BUS_MSGBOX>; ++ resets = <&ccu RST_BUS_MSGBOX>; ++ interrupts = ; ++ #mbox-cells = <1>; }; usb_otg: usb@1c19000 { -@@ -417,6 +555,7 @@ +@@ -417,6 +559,7 @@ phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>; @@ -449,7 +872,7 @@ index ff41abc96a..862b47dc9d 100644 status = "disabled"; }; -@@ -491,7 +630,7 @@ +@@ -491,7 +634,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; @@ -458,7 +881,7 @@ index ff41abc96a..862b47dc9d 100644 clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; -@@ -503,22 +642,45 @@ +@@ -503,22 +646,50 @@ interrupts = , , ; @@ -494,6 +917,11 @@ index ff41abc96a..862b47dc9d 100644 function = "i2c1"; }; ++ i2c2_pins: i2c2-pins { ++ pins = "PE14", "PE15"; ++ function = "i2c2"; ++ }; ++ + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", @@ -507,7 +935,7 @@ index ff41abc96a..862b47dc9d 100644 mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; -@@ -551,19 +713,19 @@ +@@ -551,19 +722,19 @@ bias-pull-up; }; @@ -530,7 +958,7 @@ index ff41abc96a..862b47dc9d 100644 pins = "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23"; -@@ -571,17 +733,17 @@ +@@ -571,17 +742,17 @@ drive-strength = <40>; }; @@ -551,7 +979,7 @@ index ff41abc96a..862b47dc9d 100644 pins = "PD0", "PD1", "PD2", "PD3"; function = "spi1"; }; -@@ -591,12 +753,12 @@ +@@ -591,12 +762,12 @@ function = "uart0"; }; @@ -566,7 +994,7 @@ index ff41abc96a..862b47dc9d 100644 pins = "PG8", "PG9"; function = "uart1"; }; -@@ -638,6 +800,14 @@ +@@ -638,6 +809,14 @@ status = "disabled"; }; @@ -581,7 +1009,7 @@ index ff41abc96a..862b47dc9d 100644 i2s0: i2s@1c22000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-i2s", -@@ -666,6 +836,41 @@ +@@ -666,6 +845,41 @@ status = "disabled"; }; @@ -623,7 +1051,7 @@ index ff41abc96a..862b47dc9d 100644 uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -@@ -727,6 +932,8 @@ +@@ -727,6 +941,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; @@ -632,7 +1060,7 @@ index ff41abc96a..862b47dc9d 100644 status = "disabled"; #address-cells = <1>; #size-cells = <0>; -@@ -738,6 +945,8 @@ +@@ -738,6 +954,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; @@ -641,7 +1069,22 @@ index ff41abc96a..862b47dc9d 100644 status = "disabled"; #address-cells = <1>; #size-cells = <0>; -@@ -808,6 +1017,28 @@ +@@ -749,12 +967,13 @@ + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + +- + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; +@@ -808,6 +1027,28 @@ }; }; @@ -670,10 +1113,20 @@ index ff41abc96a..862b47dc9d 100644 gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, -@@ -830,6 +1061,51 @@ +@@ -830,6 +1071,75 @@ status = "disabled"; }; ++ mbus: dram-controller@1c62000 { ++ compatible = "allwinner,sun50i-a64-mbus"; ++ reg = <0x01c62000 0x1000>; ++ clocks = <&ccu 112>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ dma-ranges = <0x00000000 0x40000000 0xc0000000>; ++ #interconnect-cells = <1>; ++ }; ++ + csi: csi@1cb0000 { + compatible = "allwinner,sun50i-a64-csi"; + reg = <0x01cb0000 0x1000>; @@ -718,11 +1171,25 @@ index ff41abc96a..862b47dc9d 100644 + status = "disabled"; + #phy-cells = <0>; + }; ++ ++ deinterlace: deinterlace@1e00000 { ++ compatible = "allwinner,sun50i-a64-deinterlace", ++ "allwinner,sun8i-h3-deinterlace"; ++ reg = <0x01e00000 0x20000>; ++ clocks = <&ccu CLK_BUS_DEINTERLACE>, ++ <&ccu CLK_DEINTERLACE>, ++ <&ccu CLK_DRAM_DEINTERLACE>; ++ clock-names = "bus", "mod", "ram"; ++ resets = <&ccu RST_BUS_DEINTERLACE>; ++ interrupts = ; ++ interconnects = <&mbus 9>; ++ interconnect-names = "dma-mem"; ++ }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; -@@ -842,7 +1118,7 @@ +@@ -842,7 +1152,7 @@ resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; @@ -731,7 +1198,7 @@ index ff41abc96a..862b47dc9d 100644 status = "disabled"; ports { -@@ -867,7 +1143,7 @@ +@@ -867,7 +1177,7 @@ compatible = "allwinner,sun50i-a64-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, @@ -740,7 +1207,7 @@ index ff41abc96a..862b47dc9d 100644 clock-names = "bus", "mod", "pll-0"; resets = <&ccu RST_BUS_HDMI0>; reset-names = "phy"; -@@ -875,11 +1151,12 @@ +@@ -875,11 +1185,12 @@ }; rtc: rtc@1f00000 { @@ -756,7 +1223,7 @@ index ff41abc96a..862b47dc9d 100644 clocks = <&osc32k>; #clock-cells = <1>; }; -@@ -896,13 +1173,19 @@ +@@ -896,13 +1207,19 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; @@ -778,7 +1245,7 @@ index ff41abc96a..862b47dc9d 100644 r_i2c: i2c@1f02400 { compatible = "allwinner,sun50i-a64-i2c", "allwinner,sun6i-a31-i2c"; -@@ -915,6 +1198,19 @@ +@@ -915,6 +1232,19 @@ #size-cells = <0>; }; @@ -798,7 +1265,7 @@ index ff41abc96a..862b47dc9d 100644 r_pwm: pwm@1f03800 { compatible = "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm"; -@@ -942,12 +1238,17 @@ +@@ -942,12 +1272,17 @@ function = "s_i2c"; }; @@ -818,7 +1285,7 @@ index ff41abc96a..862b47dc9d 100644 pins = "PL0", "PL1"; function = "s_rsb"; }; -@@ -972,6 +1273,7 @@ +@@ -972,6 +1307,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = ; @@ -827,196 +1294,21 @@ index ff41abc96a..862b47dc9d 100644 }; }; -- -2.26.0 +2.26.2 -From fbe1642e24188e96f20ab5a3b003597288104e31 Mon Sep 17 00:00:00 2001 +From 9e91885814f880ce13ee98cab79876338811949f Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 10 Mar 2020 15:32:51 +0000 -Subject: [PATCH 2/9] arm: dts: AllWinner: sync axp803.dtsi to 5.6-rc1 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/axp803.dtsi | 82 ++++++++++++++++++++-------------------- - 1 file changed, 41 insertions(+), 41 deletions(-) - -diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi -index e5eae8bafc..10e9186a76 100644 ---- a/arch/arm/dts/axp803.dtsi -+++ b/arch/arm/dts/axp803.dtsi -@@ -1,44 +1,5 @@ --/* -- * Copyright 2017 Icenowy Zheng -- * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPL or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This file is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This file is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- */ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright 2017 Icenowy Zheng - - /* - * AXP803 Integrated Power Management Chip -@@ -49,6 +10,39 @@ - interrupt-controller; - #interrupt-cells = <1>; - -+ ac_power_supply: ac-power-supply { -+ compatible = "x-powers,axp803-ac-power-supply", -+ "x-powers,axp813-ac-power-supply"; -+ status = "disabled"; -+ }; -+ -+ axp_adc: adc { -+ compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; -+ #io-channel-cells = <1>; -+ }; -+ -+ axp_gpio: gpio { -+ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ gpio0_ldo: gpio0-ldo { -+ pins = "GPIO0"; -+ function = "ldo"; -+ }; -+ -+ gpio1_ldo: gpio1-ldo { -+ pins = "GPIO1"; -+ function = "ldo"; -+ }; -+ }; -+ -+ battery_power_supply: battery-power-supply { -+ compatible = "x-powers,axp803-battery-power-supply", -+ "x-powers,axp813-battery-power-supply"; -+ status = "disabled"; -+ }; -+ - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; -@@ -152,4 +146,10 @@ - status = "disabled"; - }; - }; -+ -+ usb_power_supply: usb-power-supply { -+ compatible = "x-powers,axp803-usb-power-supply", -+ "x-powers,axp813-usb-power-supply"; -+ status = "disabled"; -+ }; - }; --- -2.26.0 - -From f44987a0ccf064f9da4a119e7700605a3eb56447 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:34:58 +0000 -Subject: [PATCH 3/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.7-rc1 - -Adds the following two patches queued for 5.7: -- arm64: dts: sun50i-a64: Add i2c2 pins -- arm64: dts: allwinner: a64: Add MBUS controller node - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/sun50i-a64.dtsi | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi -index 862b47dc9d..89a60fcf5a 100644 ---- a/arch/arm/dts/sun50i-a64.dtsi -+++ b/arch/arm/dts/sun50i-a64.dtsi -@@ -671,6 +671,11 @@ - function = "i2c1"; - }; - -+ i2c2_pins: i2c2-pins { -+ pins = "PE14", "PE15"; -+ function = "i2c2"; -+ }; -+ - /omit-if-no-ref/ - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", -@@ -958,12 +963,13 @@ - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - -- - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; -@@ -1061,6 +1067,14 @@ - status = "disabled"; - }; - -+ mbus: dram-controller@1c62000 { -+ compatible = "allwinner,sun50i-a64-mbus"; -+ reg = <0x01c62000 0x1000>; -+ clocks = <&ccu 112>; -+ dma-ranges = <0x00000000 0x40000000 0xc0000000>; -+ #interconnect-cells = <1>; -+ }; -+ - csi: csi@1cb0000 { - compatible = "allwinner,sun50i-a64-csi"; - reg = <0x01cb0000 0x1000>; --- -2.26.0 - -From 465dbf297edb9881e79c1b81fef8d9328fbaf7ad Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:37:39 +0000 -Subject: [PATCH 4/9] arm: dts: allwinner: Add initial support for Pine64 +Date: Thu, 9 Jul 2020 12:44:55 +0100 +Subject: [PATCH 7/8] arm64: dts: allwinner: Add initial support for Pine64 PinePhone -The initial DT for the PinePhone models are queued for 5.7-rc1: +At the moment PinePhone comes in two slightly incompatible variants: + - 1.0: Early Developer Batch - 1.1: Braveheart Batch +This syncs the Pinephone DTs from Linux 5.8-rc1. + Signed-off-by: Peter Robinson --- arch/arm/dts/Makefile | 2 + @@ -1029,10 +1321,10 @@ Signed-off-by: Peter Robinson create mode 100644 arch/arm/dts/sun50i-a64-pinephone.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 820ee9733a..fb7516ee83 100644 +index cee10f533f..efaadeecf3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -573,6 +573,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ +@@ -597,6 +597,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb \ sun50i-a64-pinebook.dtb \ @@ -1461,148 +1753,50 @@ index 0000000000..cefda145c3 + status = "okay"; +}; -- -2.26.0 +2.26.2 -From e8fd62cbf02828da817628d15111e6e974144473 Mon Sep 17 00:00:00 2001 +From ab4bad52587be7da4262d943f19b5db02a24a045 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 10 Mar 2020 15:46:43 +0000 -Subject: [PATCH 5/9] sync sun50i-a64 clocks with linux 5.6 +Date: Wed, 15 Jul 2020 13:14:09 +0100 +Subject: [PATCH 8/8] Initial Pine64 Pinephone support + +The Pine64 Pinephone is a smartphone based on the AllWinner A64 SoC. +It has the following features: +* 2GB LPDDR3 SDRAM +* 5.95 inch 1440x720 HD IPS capacitive touchscreen +* 16GB eMMC, mSD slot +* Quectel EG25 LTE Modem +* Realtek RTL8723CS WiFi/BT +* Front and read cameras +* Accelerometer, gyro, proximity, ambient light, compass sensors +* A USB Type-C, USB Host, DisplayPort alt mode output, 15W 5V 3A Quick Charge, follows USB PD specification Signed-off-by: Peter Robinson --- - include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h -index d66432c6e6..e512a1c9b0 100644 ---- a/include/dt-bindings/clock/sun50i-a64-ccu.h -+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h -@@ -43,8 +43,10 @@ - #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ - #define _DT_BINDINGS_CLK_SUN50I_A64_H_ - -+#define CLK_PLL_VIDEO0 7 - #define CLK_PLL_PERIPH0 11 - -+#define CLK_CPUX 21 - #define CLK_BUS_MIPI_DSI 28 - #define CLK_BUS_CE 29 - #define CLK_BUS_DMA 30 --- -2.26.0 - -From a07a9d6cb77ea0bc21cd64922bb428faf5b7e121 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:49:11 +0000 -Subject: [PATCH 6/9] add upstream sun50i-a64-cpu-opp.dtsi added in 5.6 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 75 ++++++++++++++++++++++++++++ - 1 file changed, 75 insertions(+) - create mode 100644 arch/arm/dts/sun50i-a64-cpu-opp.dtsi - -diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi -new file mode 100644 -index 0000000000..578c37490d ---- /dev/null -+++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi -@@ -0,0 +1,75 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2020 Vasily khoruzhick -+ */ -+ -+/ { -+ cpu0_opp_table: opp_table0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-648000000 { -+ opp-hz = /bits/ 64 <648000000>; -+ opp-microvolt = <1040000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-816000000 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-912000000 { -+ opp-hz = /bits/ 64 <912000000>; -+ opp-microvolt = <1120000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-960000000 { -+ opp-hz = /bits/ 64 <960000000>; -+ opp-microvolt = <1160000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <1200000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1240000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1104000000 { -+ opp-hz = /bits/ 64 <1104000000>; -+ opp-microvolt = <1260000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1152000000 { -+ opp-hz = /bits/ 64 <1152000000>; -+ opp-microvolt = <1300000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ }; -+}; -+ -+&cpu0 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; -+ -+&cpu1 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; -+ -+&cpu2 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; -+ -+&cpu3 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; --- -2.26.0 - -From 493869ec73e6ba999b6f7c49369e966ebfb8ef0b Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 14 Apr 2020 09:50:11 +0100 -Subject: [PATCH 7/9] Initial Pinephone support - -Signed-off-by: Peter Robinson ---- - configs/pinephone_defconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) + arch/arm/Kconfig | 2 +- + configs/pinephone_defconfig | 38 +++++++++++++++++++++++++++++++++++++ + 2 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 configs/pinephone_defconfig +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index e16fe03887..636ba26938 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1004,7 +1004,7 @@ config ARCH_SUNXI + bool "Support sunxi (Allwinner) SoCs" + select BINMAN + select CMD_GPIO +- select CMD_MMC if MMC ++select CMD_MMC if MMC + select CMD_USB if DISTRO_DEFAULTS + select CLK + select DM diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig new file mode 100644 -index 0000000000..a7d1e610d4 +index 0000000000..d5750aa954 --- /dev/null +++ b/configs/pinephone_defconfig -@@ -0,0 +1,26 @@ +@@ -0,0 +1,38 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y @@ -1610,11 +1804,11 @@ index 0000000000..a7d1e610d4 +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 ++CONFIG_NR_DRAM_BANKS=1 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y -+CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_USE_PREBOOT=y ++# CONFIG_SPL_SPI_SUNXI is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1" @@ -1624,14 +1818,25 @@ index 0000000000..a7d1e610d4 +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_SUNXI=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++# CONFIG_CMD_MII is not set ++# CONFIG_CMD_NFS is not set ++# CONFIG_DM_ETH is not set ++# CONFIG_PHY is not set ++# CONFIG_PHY_GIGE is not set ++# CONFIG_SUN8I_EMAC is not set ++# CONFIG_PHY_REALTEK is not set ++# CONFIG_CMD_SF is not set ++# CONFIG_SPI is not set ++# CONFIG_DM_SPI is not set ++# CONFIG_SPI_FLASH is not set ++# CONFIG_SPI_MEM is not set ++# CONFIG_DM_SPI_FLASH is not set -- -2.26.0 - +2.26.2 From 163b30d9cd1c0cf77107e0330567bbda063410da Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 14 Apr 2020 09:51:44 +0100 diff --git a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch deleted file mode 100644 index 720b1ba..0000000 --- a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch +++ /dev/null @@ -1,993 +0,0 @@ -From 47d0df70fbe5997770090aca05b07d774a19a722 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 10 Jun 2020 13:15:45 +0100 -Subject: [PATCH] USB host support for Raspberry Pi 4 board (64-bit) - -Signed-off-by: Peter Robinson ---- - arch/arm/mach-bcm283x/init.c | 20 +- - configs/rpi_4_defconfig | 9 + - configs/rpi_arm64_defconfig | 8 +- - drivers/pci/Kconfig | 9 + - drivers/pci/Makefile | 1 + - drivers/pci/pci-rcar-gen3.c | 8 - - drivers/pci/pcie_brcmstb.c | 623 ++++++++++++++++++++++++++++++++++ - drivers/pci/pcie_intel_fpga.c | 3 - - drivers/usb/host/xhci-mem.c | 3 + - include/linux/bitfield.h | 52 +++ - include/pci.h | 22 +- - include/usb/xhci.h | 8 - - 12 files changed, 740 insertions(+), 26 deletions(-) - create mode 100644 drivers/pci/pcie_brcmstb.c - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index f4d00d892d..cf4c5b245d 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -12,10 +12,15 @@ - #include - #include - -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL -+ - #ifdef CONFIG_ARM64 - #include - --static struct mm_region bcm283x_mem_map[] = { -+#define MEM_MAP_MAX_ENTRIES (4) -+ -+static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -@@ -35,11 +40,11 @@ static struct mm_region bcm283x_mem_map[] = { - } - }; - --static struct mm_region bcm2711_mem_map[] = { -+static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -- .size = 0xfe000000UL, -+ .size = 0xfc000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { -@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, -@@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) - { - int i; - -- for (i = 0; i < 2; i++) { -+ for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) { - mem_map[i].virt = pd[i].virt; - mem_map[i].phys = pd[i].phys; - mem_map[i].size = pd[i].size; -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index f0301dc8bc..b42efe6072 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 - CONFIG_ENV_SIZE=0x4000 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_DFU=y - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y - CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -@@ -26,12 +30,17 @@ CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_DM_USB_GADGET=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_GADGET=y - CONFIG_USB_GADGET_MANUFACTURER="FSL" - CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index d16c2388af..0feea7f0be 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_USE_PREBOOT=y --CONFIG_PREBOOT="usb start" -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y -@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_DWC2=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y -diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig -index 6d8c22aacf..7e1e51d9ea 100644 ---- a/drivers/pci/Kconfig -+++ b/drivers/pci/Kconfig -@@ -205,4 +205,13 @@ config PCIE_ROCKCHIP - Say Y here if you want to enable PCIe controller support on - Rockchip SoCs. - -+config PCI_BRCMSTB -+ bool "Broadcom STB PCIe controller" -+ depends on DM_PCI -+ depends on ARCH_BCM283X -+ help -+ Say Y here if you want to enable support for PCIe controller -+ on Broadcom set-top-box (STB) SoCs. -+ This driver currently supports only BCM2711 SoC and RC mode -+ of the controller. - endif -diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile -index 955351c5c2..3e1ff417d7 100644 ---- a/drivers/pci/Makefile -+++ b/drivers/pci/Makefile -@@ -43,4 +43,5 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o - obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o - obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o - obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o -+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o - obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o -diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c -index df7b37a592..1f51854ccc 100644 ---- a/drivers/pci/pci-rcar-gen3.c -+++ b/drivers/pci/pci-rcar-gen3.c -@@ -118,14 +118,6 @@ - #define RCAR_PCI_MAX_RESOURCES 4 - #define MAX_NR_INBOUND_MAPS 6 - --#define PCI_EXP_FLAGS 2 /* Capabilities register */ --#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ --#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ --#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ --#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ --#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ --#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -- - enum { - RCAR_PCI_ACCESS_READ, - RCAR_PCI_ACCESS_WRITE, -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -new file mode 100644 -index 0000000000..dade79e9c8 ---- /dev/null -+++ b/drivers/pci/pcie_brcmstb.c -@@ -0,0 +1,623 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Broadcom STB PCIe controller driver -+ * -+ * Copyright (C) 2020 Samsung Electronics Co., Ltd. -+ * -+ * Based on upstream Linux kernel driver: -+ * drivers/pci/controller/pcie-brcmstb.c -+ * Copyright (C) 2009 - 2017 Broadcom -+ * -+ * Based driver by Nicolas Saenz Julienne -+ * Copyright (C) 2020 Nicolas Saenz Julienne -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Offset of the mandatory PCIe capability config registers */ -+#define BRCM_PCIE_CAP_REGS 0x00ac -+ -+/* The PCIe controller register offsets */ -+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188 -+#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc -+#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0 -+ -+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c -+#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff -+ -+#define PCIE_RC_DL_MDIO_ADDR 0x1100 -+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 -+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 -+ -+#define PCIE_MISC_MISC_CTRL 0x4008 -+#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 -+#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 -+#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 -+#define MISC_CTRL_MAX_BURST_SIZE_128 0x0 -+#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c -+#define PCIE_MEM_WIN0_LO(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 -+#define PCIE_MEM_WIN0_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) -+ -+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c -+#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f -+ -+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 -+#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f -+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 -+ -+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c -+#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f -+ -+#define PCIE_MISC_PCIE_STATUS 0x4068 -+#define STATUS_PCIE_PORT_MASK 0x80 -+#define STATUS_PCIE_PORT_SHIFT 7 -+#define STATUS_PCIE_DL_ACTIVE_MASK 0x20 -+#define STATUS_PCIE_DL_ACTIVE_SHIFT 5 -+#define STATUS_PCIE_PHYLINKUP_MASK 0x10 -+#define STATUS_PCIE_PHYLINKUP_SHIFT 4 -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 -+#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 -+#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 -+#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 -+#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 -+#define MEM_WIN0_BASE_HI_BASE_MASK 0xff -+#define PCIE_MEM_WIN0_BASE_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 -+#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff -+#define PCIE_MEM_WIN0_LIMIT_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) -+ -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 -+#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 -+#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 -+ -+#define PCIE_MSI_INTR2_CLR 0x4508 -+#define PCIE_MSI_INTR2_MASK_SET 0x4510 -+ -+#define PCIE_EXT_CFG_DATA 0x8000 -+ -+#define PCIE_EXT_CFG_INDEX 0x9000 -+#define PCIE_EXT_BUSNUM_SHIFT 20 -+#define PCIE_EXT_SLOT_SHIFT 15 -+#define PCIE_EXT_FUNC_SHIFT 12 -+ -+#define PCIE_RGR1_SW_INIT_1 0x9210 -+#define RGR1_SW_INIT_1_PERST_MASK 0x1 -+#define RGR1_SW_INIT_1_INIT_MASK 0x2 -+ -+/* PCIe parameters */ -+#define BRCM_NUM_PCIE_OUT_WINS 4 -+ -+/* MDIO registers */ -+#define MDIO_PORT0 0x0 -+#define MDIO_DATA_MASK 0x7fffffff -+#define MDIO_DATA_SHIFT 0 -+#define MDIO_PORT_MASK 0xf0000 -+#define MDIO_PORT_SHIFT 16 -+#define MDIO_REGAD_MASK 0xffff -+#define MDIO_REGAD_SHIFT 0 -+#define MDIO_CMD_MASK 0xfff00000 -+#define MDIO_CMD_SHIFT 20 -+#define MDIO_CMD_READ 0x1 -+#define MDIO_CMD_WRITE 0x0 -+#define MDIO_DATA_DONE_MASK 0x80000000 -+#define SSC_REGS_ADDR 0x1100 -+#define SET_ADDR_OFFSET 0x1f -+#define SSC_CNTL_OFFSET 0x2 -+#define SSC_CNTL_OVRD_EN_MASK 0x8000 -+#define SSC_CNTL_OVRD_VAL_MASK 0x4000 -+#define SSC_STATUS_OFFSET 0x1 -+#define SSC_STATUS_SSC_MASK 0x400 -+#define SSC_STATUS_SSC_SHIFT 10 -+#define SSC_STATUS_PLL_LOCK_MASK 0x800 -+#define SSC_STATUS_PLL_LOCK_SHIFT 11 -+ -+/** -+ * struct brcm_pcie - the PCIe controller state -+ * @base: Base address of memory mapped IO registers of the controller -+ * @gen: Non-zero value indicates limitation of the PCIe controller operation -+ * to a specific generation (1, 2 or 3) -+ * @ssc: true indicates active Spread Spectrum Clocking operation -+ */ -+struct brcm_pcie { -+ void __iomem *base; -+ -+ int gen; -+ bool ssc; -+}; -+ -+/** -+ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size -+ * @size: The inbound region size -+ * -+ * This function converts size of the inbound "BAR" region to the non-linear -+ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field. -+ * -+ * Return: The encoded inbound region size -+ */ -+static int brcm_pcie_encode_ibar_size(u64 size) -+{ -+ int log2_in = ilog2(size); -+ -+ if (log2_in >= 12 && log2_in <= 15) -+ /* Covers 4KB to 32KB (inclusive) */ -+ return (log2_in - 12) + 0x1c; -+ else if (log2_in >= 16 && log2_in <= 37) -+ /* Covers 64KB to 32GB, (inclusive) */ -+ return log2_in - 15; -+ -+ /* Something is awry so disable */ -+ return 0; -+} -+ -+/** -+ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode -+ * @pcie: Pointer to the PCIe controller state -+ * -+ * The controller is capable of serving in both RC and EP roles. -+ * -+ * Return: true for RC mode, false for EP mode. -+ */ -+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) -+{ -+ u32 val; -+ -+ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); -+ -+ return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; -+} -+ -+/** -+ * brcm_pcie_link_up() - Check whether the PCIe link is up -+ * @pcie: Pointer to the PCIe controller state -+ * -+ * Return: true if the link is up, false otherwise. -+ */ -+static bool brcm_pcie_link_up(struct brcm_pcie *pcie) -+{ -+ u32 val, dla, plu; -+ -+ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); -+ dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT; -+ plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT; -+ -+ return dla && plu; -+} -+ -+static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, -+ uint offset, void **paddress) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ unsigned int pci_bus = PCI_BUS(bdf); -+ unsigned int pci_dev = PCI_DEV(bdf); -+ unsigned int pci_func = PCI_FUNC(bdf); -+ int idx; -+ -+ /* -+ * Busses 0 (host PCIe bridge) and 1 (its immediate child) -+ * are limited to a single device each -+ */ -+ if (pci_bus < 2 && pci_dev > 0) -+ return -EINVAL; -+ -+ /* Accesses to the RC go right to the RC registers */ -+ if (pci_bus == 0) { -+ *paddress = pcie->base + offset; -+ return 0; -+ } -+ -+ /* For devices, write to the config space index register */ -+ idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT) -+ | (pci_dev << PCIE_EXT_SLOT_SHIFT) -+ | (pci_func << PCIE_EXT_FUNC_SHIFT); -+ -+ writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); -+ *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; -+ -+ return 0; -+} -+ -+static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong *valuep, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, -+ bdf, offset, valuep, size); -+} -+ -+static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong value, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, -+ bdf, offset, value, size); -+} -+ -+static const char *link_speed_to_str(unsigned int cls) -+{ -+ switch (cls) { -+ case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5"; -+ case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0"; -+ case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0"; -+ default: -+ break; -+ } -+ -+ return "??"; -+} -+ -+static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad, -+ unsigned int cmd) -+{ -+ u32 pkt; -+ -+ pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK; -+ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK; -+ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK; -+ -+ return pkt; -+} -+ -+/** -+ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus -+ * @base: Pointer to the PCIe controller IO registers -+ * @port: The MDIO port number -+ * @regad: The register address -+ * @val: A pointer at which to store the read value -+ * -+ * Return: 0 on success and register value in @val, negative error value -+ * on failure. -+ */ -+static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port, -+ unsigned int regad, u32 *val) -+{ -+ u32 data, addr; -+ int ret; -+ -+ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ); -+ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ -+ ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data, -+ (data & MDIO_DATA_DONE_MASK), 100); -+ -+ *val = data & MDIO_DATA_MASK; -+ -+ return ret; -+} -+ -+/** -+ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus -+ * @base: Pointer to the PCIe controller IO registers -+ * @port: The MDIO port number -+ * @regad: Address of the register -+ * @wrdata: The value to write -+ * -+ * Return: 0 on success, negative error value on failure. -+ */ -+static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port, -+ unsigned int regad, u16 wrdata) -+{ -+ u32 data, addr; -+ -+ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE); -+ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); -+ -+ return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data, -+ !(data & MDIO_DATA_DONE_MASK), 100); -+} -+ -+/** -+ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking -+ * @base: pointer to the PCIe controller IO registers -+ * -+ * Return: 0 on success, negative error value on failure. -+ */ -+static int brcm_pcie_set_ssc(void __iomem *base) -+{ -+ int pll, ssc; -+ int ret; -+ u32 tmp; -+ -+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, -+ SSC_REGS_ADDR); -+ if (ret < 0) -+ return ret; -+ -+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); -+ if (ret < 0) -+ return ret; -+ -+ tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK); -+ -+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); -+ if (ret < 0) -+ return ret; -+ -+ udelay(1000); -+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); -+ if (ret < 0) -+ return ret; -+ -+ ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT; -+ pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT; -+ -+ return ssc && pll ? 0 : -EIO; -+} -+ -+/** -+ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3) -+ * @pcie: pointer to the PCIe controller state -+ * @gen: PCIe generation to limit the controller's operation to -+ */ -+static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen) -+{ -+ void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS; -+ -+ u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2); -+ u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP); -+ -+ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; -+ writel(lnkcap, cap_base + PCI_EXP_LNKCAP); -+ -+ lnkctl2 = (lnkctl2 & ~0xf) | gen; -+ writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2); -+} -+ -+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, -+ unsigned int win, u64 phys_addr, -+ u64 pcie_addr, u64 size) -+{ -+ void __iomem *base = pcie->base; -+ u32 phys_addr_mb_high, limit_addr_mb_high; -+ phys_addr_t phys_addr_mb, limit_addr_mb; -+ int high_addr_shift; -+ u32 tmp; -+ -+ /* Set the base of the pcie_addr window */ -+ writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); -+ writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); -+ -+ /* Write the addr base & limit lower bits (in MBs) */ -+ phys_addr_mb = phys_addr / SZ_1M; -+ limit_addr_mb = (phys_addr + size - 1) / SZ_1M; -+ -+ tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); -+ u32p_replace_bits(&tmp, phys_addr_mb, -+ MEM_WIN0_BASE_LIMIT_BASE_MASK); -+ u32p_replace_bits(&tmp, limit_addr_mb, -+ MEM_WIN0_BASE_LIMIT_LIMIT_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); -+ -+ /* Write the cpu & limit addr upper bits */ -+ high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; -+ phys_addr_mb_high = phys_addr_mb >> high_addr_shift; -+ tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); -+ u32p_replace_bits(&tmp, phys_addr_mb_high, -+ MEM_WIN0_BASE_HI_BASE_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); -+ -+ limit_addr_mb_high = limit_addr_mb >> high_addr_shift; -+ tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); -+ u32p_replace_bits(&tmp, limit_addr_mb_high, -+ PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); -+} -+ -+static int brcm_pcie_probe(struct udevice *dev) -+{ -+ struct udevice *ctlr = pci_get_controller(dev); -+ struct pci_controller *hose = dev_get_uclass_priv(ctlr); -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ void __iomem *base = pcie->base; -+ bool ssc_good = false; -+ int num_out_wins = 0; -+ u64 rc_bar2_offset, rc_bar2_size; -+ unsigned int scb_size_val; -+ int i, ret; -+ u16 nlw, cls, lnksta; -+ u32 tmp; -+ -+ /* -+ * Reset the bridge, assert the fundamental reset. Note for some SoCs, -+ * e.g. BCM7278, the fundamental reset should not be asserted here. -+ * This will need to be changed when support for other SoCs is added. -+ */ -+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, -+ RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK); -+ /* -+ * The delay is a safety precaution to preclude the reset signal -+ * from looking like a glitch. -+ */ -+ udelay(100); -+ -+ /* Take the bridge out of reset */ -+ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); -+ -+ clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, -+ PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); -+ -+ /* Wait for SerDes to be stable */ -+ udelay(100); -+ -+ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ -+ clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, -+ MISC_CTRL_MAX_BURST_SIZE_MASK, -+ MISC_CTRL_SCB_ACCESS_EN_MASK | -+ MISC_CTRL_CFG_READ_UR_MODE_MASK | -+ MISC_CTRL_MAX_BURST_SIZE_128); -+ /* -+ * TODO: When support for other SoCs than BCM2711 is added we may -+ * need to use the base address and size(s) provided in the dma-ranges -+ * property. -+ */ -+ rc_bar2_offset = 0; -+ rc_bar2_size = 0xc0000000; -+ -+ tmp = lower_32_bits(rc_bar2_offset); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), -+ RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); -+ writel(upper_32_bits(rc_bar2_offset), -+ base + PCIE_MISC_RC_BAR2_CONFIG_HI); -+ -+ scb_size_val = rc_bar2_size ? -+ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ -+ -+ tmp = readl(base + PCIE_MISC_MISC_CTRL); -+ u32p_replace_bits(&tmp, scb_size_val, -+ MISC_CTRL_SCB0_SIZE_MASK); -+ writel(tmp, base + PCIE_MISC_MISC_CTRL); -+ -+ /* Disable the PCIe->GISB memory window (RC_BAR1) */ -+ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, -+ RC_BAR1_CONFIG_LO_SIZE_MASK); -+ -+ /* Disable the PCIe->SCB memory window (RC_BAR3) */ -+ clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO, -+ RC_BAR3_CONFIG_LO_SIZE_MASK); -+ -+ /* Mask all interrupts since we are not handling any yet */ -+ writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); -+ -+ /* Clear any interrupts we find on boot */ -+ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); -+ -+ if (pcie->gen) -+ brcm_pcie_set_gen(pcie, pcie->gen); -+ -+ /* Unassert the fundamental reset */ -+ clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, -+ RGR1_SW_INIT_1_PERST_MASK); -+ -+ /* Give the RC/EP time to wake up, before trying to configure RC. -+ * Intermittently check status for link-up, up to a total of 100ms. -+ */ -+ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) -+ mdelay(5); -+ -+ if (!brcm_pcie_link_up(pcie)) { -+ printf("PCIe BRCM: link down\n"); -+ return -EINVAL; -+ } -+ -+ if (!brcm_pcie_rc_mode(pcie)) { -+ printf("PCIe misconfigured; is in EP mode\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < hose->region_count; i++) { -+ struct pci_region *reg = &hose->regions[i]; -+ -+ if (reg->flags != PCI_REGION_MEM) -+ continue; -+ -+ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) -+ return -EINVAL; -+ -+ brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, -+ reg->bus_start, reg->size); -+ -+ num_out_wins++; -+ } -+ -+ /* -+ * For config space accesses on the RC, show the right class for -+ * a PCIe-PCIe bridge (the default setting is to be EP mode). -+ */ -+ clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3, -+ CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400); -+ -+ if (pcie->ssc) { -+ ret = brcm_pcie_set_ssc(pcie->base); -+ if (!ret) -+ ssc_good = true; -+ else -+ printf("PCIe BRCM: failed attempt to enter SSC mode\n"); -+ } -+ -+ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); -+ cls = lnksta & PCI_EXP_LNKSTA_CLS; -+ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; -+ -+ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), -+ nlw, ssc_good ? "(SSC)" : "(!SSC)"); -+ -+ /* PCIe->SCB endian mode for BAR */ -+ clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1, -+ VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK, -+ VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN); -+ /* -+ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 -+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. -+ */ -+ setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, -+ PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK); -+ -+ return 0; -+} -+ -+static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ ofnode dn = dev_ofnode(dev); -+ u32 max_link_speed; -+ int ret; -+ -+ /* Get the controller base address */ -+ pcie->base = dev_read_addr_ptr(dev); -+ if (!pcie->base) -+ return -EINVAL; -+ -+ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); -+ -+ ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); -+ if (ret < 0 || max_link_speed > 4) -+ pcie->gen = 0; -+ else -+ pcie->gen = max_link_speed; -+ -+ return 0; -+} -+ -+static const struct dm_pci_ops brcm_pcie_ops = { -+ .read_config = brcm_pcie_read_config, -+ .write_config = brcm_pcie_write_config, -+}; -+ -+static const struct udevice_id brcm_pcie_ids[] = { -+ { .compatible = "brcm,bcm2711-pcie" }, -+ { } -+}; -+ -+U_BOOT_DRIVER(pcie_brcm_base) = { -+ .name = "pcie_brcm", -+ .id = UCLASS_PCI, -+ .ops = &brcm_pcie_ops, -+ .of_match = brcm_pcie_ids, -+ .probe = brcm_pcie_probe, -+ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, -+ .priv_auto_alloc_size = sizeof(struct brcm_pcie), -+}; -diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c -index aa1903e547..9f102c64c6 100644 ---- a/drivers/pci/pcie_intel_fpga.c -+++ b/drivers/pci/pcie_intel_fpga.c -@@ -67,9 +67,6 @@ - #define IS_ROOT_PORT(pcie, bdf) \ - ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) - --#define PCI_EXP_LNKSTA 18 /* Link Status */ --#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -- - /** - * struct intel_fpga_pcie - Intel FPGA PCIe controller state - * @bus: Pointer to the PCI bus -diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c -index 2d968aafb0..f446520528 100644 ---- a/drivers/usb/host/xhci-mem.c -+++ b/drivers/usb/host/xhci-mem.c -@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) - scratchpad->sp_array[i] = cpu_to_le64(ptr); - } - -+ xhci_flush_cache((uintptr_t)scratchpad->sp_array, -+ sizeof(u64) * num_sp); -+ - return 0; - - fail_sp3: -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index 8b9d6fff00..7ad8b088ed 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -103,4 +103,56 @@ - (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ - }) - -+extern void __compiletime_error("value doesn't fit into mask") -+__field_overflow(void); -+extern void __compiletime_error("bad bitfield mask") -+__bad_mask(void); -+ -+static __always_inline u64 field_multiplier(u64 field) -+{ -+ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) -+ __bad_mask(); -+ return field & -field; -+} -+ -+static __always_inline u64 field_mask(u64 field) -+{ -+ return field / field_multiplier(field); -+} -+ -+#define ____MAKE_OP(type, base, to, from) \ -+static __always_inline __##type type##_encode_bits(base v, base field) \ -+{ \ -+ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ -+ __field_overflow(); \ -+ return to((v & field_mask(field)) * field_multiplier(field)); \ -+} \ -+static __always_inline __##type type##_replace_bits(__##type old, \ -+ base val, base field) \ -+{ \ -+ return (old & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline void type##p_replace_bits(__##type * p, \ -+ base val, base field) \ -+{ \ -+ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline base type##_get_bits(__##type v, base field) \ -+{ \ -+ return (from(v) & field) / field_multiplier(field); \ -+} -+ -+#define __MAKE_OP(size) \ -+ ____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \ -+ ____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \ -+ ____MAKE_OP(u##size, u##size, ,) -+ -+____MAKE_OP(u8, u8, ,) -+__MAKE_OP(16) -+__MAKE_OP(32) -+__MAKE_OP(64) -+ -+#undef __MAKE_OP -+#undef ____MAKE_OP -+ - #endif -diff --git a/include/pci.h b/include/pci.h -index 19c9244b94..281f353916 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -471,10 +471,28 @@ - #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ - - /* PCI Express capabilities */ -+#define PCI_EXP_FLAGS 2 /* Capabilities register */ -+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ - #define PCI_EXP_DEVCAP 4 /* Device capabilities */ --#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ -+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ - #define PCI_EXP_DEVCTL 8 /* Device Control */ --#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ -+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ -+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -+#define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ -+#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ -+#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ -+#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ -+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ -+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ -+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ - - /* Include the ID list */ - -diff --git a/include/usb/xhci.h b/include/usb/xhci.h -index 20e4a21066..1170c0ac69 100644 ---- a/include/usb/xhci.h -+++ b/include/usb/xhci.h -@@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) - */ - static inline u64 xhci_readq(__le64 volatile *regs) - { --#if BITS_PER_LONG == 64 -- return readq(regs); --#else - __u32 *ptr = (__u32 *)regs; - u64 val_lo = readl(ptr); - u64 val_hi = readl(ptr + 1); - return val_lo + (val_hi << 32); --#endif - } - - static inline void xhci_writeq(__le64 volatile *regs, const u64 val) - { --#if BITS_PER_LONG == 64 -- writeq(val, regs); --#else - __u32 *ptr = (__u32 *)regs; - u32 val_lo = lower_32_bits(val); - /* FIXME */ - u32 val_hi = upper_32_bits(val); - writel(val_lo, ptr); - writel(val_hi, ptr + 1); --#endif - } - - int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, --- -2.26.2 - diff --git a/rockchip-Pinebook-Pro-Fixes.patch b/rockchip-Pinebook-Pro-Fixes.patch deleted file mode 100644 index 0b0a2d7..0000000 --- a/rockchip-Pinebook-Pro-Fixes.patch +++ /dev/null @@ -1,200 +0,0 @@ -From e27621a7c2c0e090977c17f604093c720ca01fe4 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 8 Jun 2020 20:31:33 +0100 -Subject: [PATCH 1/3] rockchip: Pinebook Pro: enable rng to provide an entropy - source - -Enable the rng so UEFI can provide entropy for KASLR - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ++++ - arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ - configs/pinebook-pro-rk3399_defconfig | 2 ++ - 3 files changed, 10 insertions(+) - -diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -index 1a2e24d3ef..296321d697 100644 ---- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -@@ -24,6 +24,10 @@ - u-boot,dm-pre-reloc; - }; - -+&rng { -+ status = "okay"; -+}; -+ - &sdhci { - max-frequency = <25000000>; - u-boot,dm-pre-reloc; -diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -index bac09df4a3..cb8991aa25 100644 ---- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -@@ -19,6 +19,10 @@ - }; - }; - -+&rng { -+ status = "okay"; -+}; -+ - &spi1 { - spi_flash: flash@0 { - u-boot,dm-pre-reloc; -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index 0c129b9aeb..21eecf477c 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -54,6 +54,8 @@ CONFIG_DM_PMIC_FAN53555=y - CONFIG_PMIC_RK8XX=y - CONFIG_REGULATOR_PWM=y - CONFIG_REGULATOR_RK8XX=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_PWM_ROCKCHIP=y - CONFIG_RAM_RK3399_LPDDR4=y - CONFIG_DM_RESET=y --- -2.26.2 - -From 99a3c9ba5a8ab7a94aa700649e031f53d498e857 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 8 Jun 2020 22:23:05 +0100 -Subject: [PATCH 2/3] rockchip: Pinebook Pro: Fix USB and the USB attached - keyboard - -The built in keyboard on the Pinebook Pro is attached via USB so -fix this up to ensure USB works as expected. - -Signed-off-by: Peter Robinson ---- - configs/pinebook-pro-rk3399_defconfig | 5 +++++ - include/configs/pinebook-pro-rk3399.h | 3 +++ - 2 files changed, 8 insertions(+) - -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index 21eecf477c..733463556a 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -61,6 +61,8 @@ CONFIG_RAM_RK3399_LPDDR4=y - CONFIG_DM_RESET=y - CONFIG_BAUDRATE=1500000 - CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="usb start" - CONFIG_ROCKCHIP_SPI=y - CONFIG_SYSRESET=y - CONFIG_USB=y -@@ -68,8 +70,11 @@ CONFIG_USB_XHCI_HCD=y - CONFIG_USB_XHCI_DWC3=y - CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y - CONFIG_USB_DWC3=y - CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_DM_KEYBOARD=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_ASIX=y -diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h -index 4bc8802d11..d910830582 100644 ---- a/include/configs/pinebook-pro-rk3399.h -+++ b/include/configs/pinebook-pro-rk3399.h -@@ -25,4 +25,7 @@ - - #define SDRAM_BANK_SIZE (2UL << 30) - -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ - #endif --- -2.26.2 - -From 64d43a4f0a135486a9a524b107c853831e492eb6 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 8 Jun 2020 23:41:50 +0100 -Subject: [PATCH 3/3] rockchip: Pinebook Pro: Fix SPI flash and store env on it - -Some minor fixes for SPI flash on the Pinebook Pro and also -default to saving environment to the SPI flash as it's -guaranteed to be on board. - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 6 +++++- - configs/pinebook-pro-rk3399_defconfig | 3 +++ - include/configs/pinebook-pro-rk3399.h | 9 --------- - 3 files changed, 8 insertions(+), 10 deletions(-) - -diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -index 296321d697..ded7db0aef 100644 ---- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -@@ -12,7 +12,11 @@ - }; - - chosen { -- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; -+ }; -+ -+ config { -+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ - }; - }; - -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index 733463556a..18b2d74253 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -1,6 +1,7 @@ - CONFIG_ARM=y - CONFIG_ARCH_ROCKCHIP=y - CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_SIZE=0x8000 - CONFIG_ROCKCHIP_RK3399=y - CONFIG_TARGET_PINEBOOK_PRO_RK3399=y - CONFIG_NR_DRAM_BANKS=1 -@@ -17,6 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y - CONFIG_SPL_STACK_R=y - CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 - CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_SPI_LOAD=y - CONFIG_TPL=y - CONFIG_CMD_BOOTZ=y - CONFIG_CMD_GPIO=y -@@ -32,6 +34,7 @@ CONFIG_CMD_REGULATOR=y - CONFIG_SPL_OF_CONTROL=y - CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" - CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_SPI_FLASH=y - CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y -diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h -index d910830582..d478b19917 100644 ---- a/include/configs/pinebook-pro-rk3399.h -+++ b/include/configs/pinebook-pro-rk3399.h -@@ -14,15 +14,6 @@ - - #include - --#if defined(CONFIG_ENV_IS_IN_MMC) --#define CONFIG_SYS_MMC_ENV_DEV 0 --#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) --#define CONFIG_ENV_SECT_SIZE (8 * 1024) --#endif -- --#undef CONFIG_SYS_SPI_U_BOOT_OFFS --#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 -- - #define SDRAM_BANK_SIZE (2UL << 30) - - #define CONFIG_USB_OHCI_NEW --- -2.26.2 - diff --git a/sources b/sources index 7678d2e..dcf9aad 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2020.07.tar.bz2) = df91264fe8a42e676c3f2aa09d644c6a3035cc8169bf52a8ab95efe7e542cfc758a0ef150949b0d9f03c7dec7d95f8d20a2efe2dbb60c2ef1a61c8063770478d +SHA512 (u-boot-2020.10-rc1.tar.bz2) = 8a8841280249e35de95fb2438733adafcfd7bb8a9bb15daaff8406b616fcfa63b90c40a0b54a529c66ad16ee06b2ab309fda3dd452ce2482846ebed1d08851d0 diff --git a/uboot-tools.spec b/uboot-tools.spec index 7f5fdd1..c9cb437 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,9 +1,8 @@ -#global candidate rc5 -%global _default_patch_fuzz 2 +%global candidate rc1 Name: uboot-tools -Version: 2020.07 -Release: 2%{?candidate:.%{candidate}}%{?dist} +Version: 2020.10 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -22,8 +21,8 @@ Patch1: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch Patch2: uefi-use-Fedora-specific-path-name.patch # Board fixes and enablement -Patch4: usb-kbd-fixes.patch -Patch5: dragonboard-fixes.patch +Patch3: usb-kbd-fixes.patch +Patch4: dragonboard-fixes.patch # Tegra improvements Patch10: arm-tegra-define-fdtfile-option-for-distro-boot.patch @@ -32,11 +31,8 @@ Patch11: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch Patch12: AllWinner-Pine64-bits.patch # Rockchips improvements Patch13: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch -Patch14: rockchip-Pinebook-Pro-Fixes.patch -# RPi4 -Patch16: USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch -Patch17: usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch -Patch18: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch +# RPi +Patch14: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch BuildRequires: bc BuildRequires: dtc @@ -250,6 +246,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Tue Jul 28 2020 Peter Robinson - 2020.10-0.1.rc1 +- 2020.10 RC1 + * Tue Jul 14 2020 Tom Stellard - 2020.07-2 - Use make macros - https://fedoraproject.org/wiki/Changes/UseMakeBuildInstallMacro diff --git a/usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch b/usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch deleted file mode 100644 index e167bb6..0000000 --- a/usb-xhci-Load-Raspberry-Pi-4-VL805-s-firmware.patch +++ /dev/null @@ -1,707 +0,0 @@ -From patchwork Mon Jun 22 15:30:48 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Nicolas Saenz Julienne -X-Patchwork-Id: 1314562 -X-Patchwork-Delegate: matthias.bgg@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=none (p=none dis=none) header.from=suse.de -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest - SHA256) (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49rD0h00Mbz9s6w - for ; Tue, 23 Jun 2020 01:31:47 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 1284581DC9; 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- Mon, 22 Jun 2020 15:31:22 +0000 (UTC) -From: Nicolas Saenz Julienne -To: mbrugger@suse.com, u-boot@lists.denx.de, bmeng.cn@gmail.com, - sjg@chromium.org, marex@denx.de -Cc: m.szyprowski@samsung.com, s.nawrocki@samsung.com, - Nicolas Saenz Julienne -Subject: [PATCH v5 1/4] arm: rpi: Add function to trigger VL805's firmware load -Date: Mon, 22 Jun 2020 17:30:48 +0200 -Message-Id: <20200622153050.23193-2-nsaenzjulienne@suse.de> -X-Mailer: git-send-email 2.27.0 -In-Reply-To: <20200622153050.23193-1-nsaenzjulienne@suse.de> -References: <20200622153050.23193-1-nsaenzjulienne@suse.de> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware -may either be loaded directly from an EEPROM or, if not present, by the -SoC's VideCore (the SoC's co-processor). Introduce the function that -informs VideCore that VL805 may need its firmware loaded. - -Signed-off-by: Nicolas Saenz Julienne ---- -Changes since v1: - - Rename function so it's not mistaken with regular firmware loading - - arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++ - arch/arm/mach-bcm283x/include/mach/msg.h | 7 ++++ - arch/arm/mach-bcm283x/msg.c | 46 +++++++++++++++++++++++ - 3 files changed, 66 insertions(+) - -diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h -index 60e226ce1d..2ae2d3d97c 100644 ---- a/arch/arm/mach-bcm283x/include/mach/mbox.h -+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h -@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette { - } body; - }; - -+#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 -+ -+struct bcm2835_mbox_tag_pci_dev_addr { -+ struct bcm2835_mbox_tag_hdr tag_hdr; -+ union { -+ struct { -+ u32 dev_addr; -+ } req; -+ struct { -+ } resp; -+ } body; -+}; -+ - /* - * Pass a raw u32 message to the VC, and receive a raw u32 back. - * -diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h -index 4afb08631b..e45c1bf010 100644 ---- a/arch/arm/mach-bcm283x/include/mach/msg.h -+++ b/arch/arm/mach-bcm283x/include/mach/msg.h -@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, - int pixel_order, int alpha_mode, ulong *fb_basep, - ulong *fb_sizep, int *pitchp); - -+/** -+ * bcm2711_load_vl805_firmware() - get vl805's firmware loaded -+ * -+ * @return 0 if OK, -EIO on error -+ */ -+int bcm2711_notify_vl805_reset(void); -+ - #endif -diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c -index 94b75283f8..347aece3cd 100644 ---- a/arch/arm/mach-bcm283x/msg.c -+++ b/arch/arm/mach-bcm283x/msg.c -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - - struct msg_set_power_state { - struct bcm2835_mbox_hdr hdr; -@@ -40,6 +41,12 @@ struct msg_setup { - u32 end_tag; - }; - -+struct msg_notify_vl805_reset { -+ struct bcm2835_mbox_hdr hdr; -+ struct bcm2835_mbox_tag_pci_dev_addr dev_addr; -+ u32 end_tag; -+}; -+ - int bcm2835_power_on_module(u32 module) - { - ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1); -@@ -151,3 +158,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, - - return 0; - } -+ -+/* -+ * On the Raspberry Pi 4, after a PCI reset, VL805's (the xHCI chip) firmware -+ * may either be loaded directly from an EEPROM or, if not present, by the -+ * SoC's VideoCore. This informs VideoCore that VL805 needs its firmware -+ * loaded. -+ */ -+int bcm2711_notify_vl805_reset(void) -+{ -+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset, -+ msg_notify_vl805_reset, 1); -+ int ret; -+ -+ BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset); -+ BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr, -+ NOTIFY_XHCI_RESET); -+ -+ /* -+ * The pci device address is expected like this: -+ * -+ * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12 -+ * -+ * But since RPi4's PCIe setup is hardwired, we know the address in -+ * advance. -+ */ -+ msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000; -+ -+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, -+ &msg_notify_vl805_reset->hdr); -+ if (ret) { -+ printf("bcm2711: Faild to load vl805's firmware, %d\n", ret); -+ return -EIO; -+ } -+ -+ udelay(200); -+ -+ return 0; -+} -+ - -From patchwork Mon Jun 22 15:30:49 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Nicolas Saenz Julienne -X-Patchwork-Id: 1314565 -X-Patchwork-Delegate: matthias.bgg@gmail.com -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; - spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de - (client-ip=85.214.62.61; helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; receiver=) -Authentication-Results: ozlabs.org; - dmarc=none (p=none dis=none) header.from=suse.de -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 49rD1F72RYz9s6w - for ; Tue, 23 Jun 2020 01:32:17 +1000 (AEST) -Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id 10E5481E20; - Mon, 22 Jun 2020 17:31:41 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=none (p=none dis=none) header.from=suse.de -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Received: by phobos.denx.de (Postfix, from userid 109) - id 9851E81DE9; Mon, 22 Jun 2020 17:31:30 +0200 (CEST) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, - RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) - (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id A2A2281D52 - for ; Mon, 22 Jun 2020 17:31:23 +0200 (CEST) -Authentication-Results: phobos.denx.de; - dmarc=none (p=none dis=none) header.from=suse.de -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=nsaenzjulienne@suse.de -Received: from relay2.suse.de (unknown [195.135.221.27]) - by mx2.suse.de (Postfix) with ESMTP id CFE01C204; - Mon, 22 Jun 2020 15:31:22 +0000 (UTC) -From: Nicolas Saenz Julienne -To: mbrugger@suse.com, u-boot@lists.denx.de, bmeng.cn@gmail.com, - sjg@chromium.org, marex@denx.de -Cc: m.szyprowski@samsung.com, s.nawrocki@samsung.com, - Nicolas Saenz Julienne -Subject: [PATCH v5 2/4] reset: Add Raspberry Pi 4 firmware reset controller -Date: Mon, 22 Jun 2020 17:30:49 +0200 -Message-Id: <20200622153050.23193-3-nsaenzjulienne@suse.de> -X-Mailer: git-send-email 2.27.0 -In-Reply-To: <20200622153050.23193-1-nsaenzjulienne@suse.de> -References: <20200622153050.23193-1-nsaenzjulienne@suse.de> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Raspberry Pi 4's co-processor controls some of the board's HW -initialization process, but it's up to Linux to trigger it when -relevant. Introduce a reset controller capable of interfacing with -RPi4's co-processor that models these firmware initialization routines as -reset lines. - -Signed-off-by: Nicolas Saenz Julienne ---- - drivers/reset/Kconfig | 10 ++++ - drivers/reset/Makefile | 1 + - drivers/reset/reset-raspberrypi.c | 60 +++++++++++++++++++ - .../reset/raspberrypi,firmware-reset.h | 13 ++++ - 4 files changed, 84 insertions(+) - create mode 100644 drivers/reset/reset-raspberrypi.c - create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h - -diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index 88d3be1593..d02c1522e5 100644 ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -148,4 +148,14 @@ config RESET_IMX7 - help - Support for reset controller on i.MX7/8 SoCs. - -+config RESET_RASPBERRYPI -+ bool "Raspberry Pi 4 Firmware Reset Controller Driver" -+ depends on DM_RESET && ARCH_BCM283X -+ default USB_XHCI_PCI -+ help -+ Raspberry Pi 4's co-processor controls some of the board's HW -+ initialization process, but it's up to Linux to trigger it when -+ relevant. This driver provides a reset controller capable of -+ interfacing with RPi4's co-processor and model these firmware -+ initialization routines as reset lines. - endmenu -diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index 0a044d5d8c..be54dae725 100644 ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o - obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o - obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o - obj-$(CONFIG_RESET_IMX7) += reset-imx7.o -+obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o -diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c -new file mode 100644 -index 0000000000..e2d284e5ac ---- /dev/null -+++ b/drivers/reset/reset-raspberrypi.c -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Raspberry Pi 4 firmware reset driver -+ * -+ * Copyright (C) 2020 Nicolas Saenz Julienne -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+static int raspberrypi_reset_request(struct reset_ctl *reset_ctl) -+{ -+ if (reset_ctl->id >= RASPBERRYPI_FIRMWARE_RESET_NUM_IDS) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int raspberrypi_reset_free(struct reset_ctl *reset_ctl) -+{ -+ return 0; -+} -+ -+static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl) -+{ -+ switch (reset_ctl->id) { -+ case RASPBERRYPI_FIRMWARE_RESET_ID_USB: -+ bcm2711_notify_vl805_reset(); -+ return 0; -+ default: -+ return -EINVAL; -+ } -+} -+ -+static int raspberrypi_reset_deassert(struct reset_ctl *reset_ctl) -+{ -+ return 0; -+} -+ -+struct reset_ops raspberrypi_reset_ops = { -+ .request = raspberrypi_reset_request, -+ .rfree = raspberrypi_reset_free, -+ .rst_assert = raspberrypi_reset_assert, -+ .rst_deassert = raspberrypi_reset_deassert, -+}; -+ -+static const struct udevice_id raspberrypi_reset_ids[] = { -+ { .compatible = "raspberrypi,firmware-reset" }, -+ { } -+}; -+ -+U_BOOT_DRIVER(raspberrypi_reset) = { -+ .name = "raspberrypi-reset", -+ .id = UCLASS_RESET, -+ .of_match = raspberrypi_reset_ids, -+ .ops = &raspberrypi_reset_ops, -+}; -+ -diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h -new file mode 100644 -index 0000000000..1a4f4c7927 ---- /dev/null -+++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h -@@ -0,0 +1,13 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2020 Nicolas Saenz Julienne -+ * Author: Nicolas Saenz Julienne -+ */ -+ -+#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H -+#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H -+ -+#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0 -+#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1 -+ -+#endif - -From patchwork Mon Jun 22 15:30:50 2020 -Content-Type: text/plain; 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- Mon, 22 Jun 2020 15:31:23 +0000 (UTC) -From: Nicolas Saenz Julienne -To: mbrugger@suse.com, u-boot@lists.denx.de, bmeng.cn@gmail.com, - sjg@chromium.org, marex@denx.de -Cc: m.szyprowski@samsung.com, s.nawrocki@samsung.com, - Nicolas Saenz Julienne -Subject: [PATCH v5 3/4] configs: Enable support for reset controllers on RPi4 -Date: Mon, 22 Jun 2020 17:30:50 +0200 -Message-Id: <20200622153050.23193-4-nsaenzjulienne@suse.de> -X-Mailer: git-send-email 2.27.0 -In-Reply-To: <20200622153050.23193-1-nsaenzjulienne@suse.de> -References: <20200622153050.23193-1-nsaenzjulienne@suse.de> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -This is required in order to access the reset controller used to -initialize the board's xHCI chip. - -Signed-off-by: Nicolas Saenz Julienne ---- - configs/rpi_4_32b_defconfig | 1 + - configs/rpi_4_defconfig | 1 + - configs/rpi_arm64_defconfig | 1 + - 3 files changed, 3 insertions(+) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index b0797373b5..00c8d963ab 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -35,6 +35,7 @@ CONFIG_DM_PCI=y - CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set -+CONFIG_DM_RESET=y - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index 932b768164..c73eccb61c 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -35,6 +35,7 @@ CONFIG_DM_PCI=y - CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set -+CONFIG_DM_RESET=y - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index 855afcf1cf..800b51e6f5 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -32,6 +32,7 @@ CONFIG_DM_PCI=y - CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set -+CONFIG_DM_RESET=y - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y - -From patchwork Mon Jun 22 15:30:51 2020 -Content-Type: text/plain; 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- Mon, 22 Jun 2020 15:31:23 +0000 (UTC) -From: Nicolas Saenz Julienne -To: mbrugger@suse.com, u-boot@lists.denx.de, bmeng.cn@gmail.com, - sjg@chromium.org, marex@denx.de -Cc: m.szyprowski@samsung.com, s.nawrocki@samsung.com, - Nicolas Saenz Julienne -Subject: [PATCH v5 4/4] usb: xhci: Add reset controller support -Date: Mon, 22 Jun 2020 17:30:51 +0200 -Message-Id: <20200622153050.23193-5-nsaenzjulienne@suse.de> -X-Mailer: git-send-email 2.27.0 -In-Reply-To: <20200622153050.23193-1-nsaenzjulienne@suse.de> -References: <20200622153050.23193-1-nsaenzjulienne@suse.de> -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.30rc1 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de -X-Virus-Status: Clean - -Some atypical users of xhci might need to manually reset their xHCI -controller before starting the HCD setup. Check if a reset controller -device is available to the PCI bus and trigger a reset. - -Signed-off-by: Nicolas Saenz Julienne ---- - -Changes since v3: - - Move reset support to xchi core - - drivers/usb/host/xhci-mem.c | 2 ++ - drivers/usb/host/xhci.c | 33 +++++++++++++++++++++++++++++++++ - include/usb/xhci.h | 2 ++ - 3 files changed, 37 insertions(+) - -diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c -index f446520528..108f4bd8cf 100644 ---- a/drivers/usb/host/xhci-mem.c -+++ b/drivers/usb/host/xhci-mem.c -@@ -180,6 +180,8 @@ void xhci_cleanup(struct xhci_ctrl *ctrl) - xhci_free_virt_devices(ctrl); - free(ctrl->erst.entries); - free(ctrl->dcbaa); -+ if (reset_valid(&ctrl->reset)) -+ reset_free(&ctrl->reset); - memset(ctrl, '\0', sizeof(struct xhci_ctrl)); - } - -diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c -index ebd2954571..03b41cc855 100644 ---- a/drivers/usb/host/xhci.c -+++ b/drivers/usb/host/xhci.c -@@ -190,6 +190,35 @@ static int xhci_start(struct xhci_hcor *hcor) - return ret; - } - -+/** -+ * Resets XHCI Hardware -+ * -+ * @param ctrl pointer to host controller -+ * @return 0 if OK, or a negative error code. -+ */ -+static int xhci_reset_hw(struct xhci_ctrl *ctrl) -+{ -+ int ret; -+ -+ ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset); -+ if (ret && ret != -ENOENT) { -+ dev_err(ctrl->dev, "failed to get reset\n"); -+ return ret; -+ } -+ -+ if (reset_valid(&ctrl->reset)) { -+ ret = reset_assert(&ctrl->reset); -+ if (ret) -+ return ret; -+ -+ ret = reset_deassert(&ctrl->reset); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ - /** - * Resets the XHCI Controller - * -@@ -1508,6 +1537,10 @@ int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, - - ctrl->dev = dev; - -+ ret = xhci_reset_hw(ctrl); -+ if (ret) -+ goto err; -+ - /* - * XHCI needs to issue a Address device command to setup - * proper device context structures, before it can interact -diff --git a/include/usb/xhci.h b/include/usb/xhci.h -index 1170c0ac69..7d34103fd5 100644 ---- a/include/usb/xhci.h -+++ b/include/usb/xhci.h -@@ -16,6 +16,7 @@ - #ifndef HOST_XHCI_H_ - #define HOST_XHCI_H_ - -+#include - #include - #include - #include -@@ -1209,6 +1210,7 @@ struct xhci_ctrl { - #if CONFIG_IS_ENABLED(DM_USB) - struct udevice *dev; - #endif -+ struct reset_ctl reset; - struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ - struct xhci_hcor *hcor; - struct xhci_doorbell_array *dba;