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Rebase riscv64 patches for new U-Boot version 

Signed-off-by: David Abdurachmanov <davidlt@rivosinc.com>
This commit is contained in:
David Abdurachmanov 2022-06-03 12:21:11 +03:00
parent 4a4a00dc45
commit 2189c7b147
Signed by: davidlt
GPG Key ID: 8B7F1DA0E2C9FDBB
12 changed files with 290 additions and 266 deletions
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26
0001-riscv-SiFive-Unleashed-booti-compressed-kernel-suppo.patch
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@ -1,26 +0,0 @@
From c29c7b09b2c66b3601bcd08f522fccdbb8dde474 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:30:49 +0000
Subject: [PATCH 1/7] riscv: SiFive Unleashed booti compressed kernel support
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
include/configs/sifive-unleashed.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index b6c29f8c..db0ebaf9 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -71,6 +71,8 @@
"script_size_f=0x1000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
+ "kernel_comp_addr_r=0x90300000\0" \
+ "kernel_comp_size=0x4000000\0" \
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
--
2.32.0

40
0001-riscv-sifive-unmatched-Adjust-for-big-ramdisk-image.patch Normal file
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@ -0,0 +1,40 @@
From 9c139c603f308608cf4a60426779edfe031181ca Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 24 May 2022 12:31:12 +0800
Subject: [PATCH 1/6] riscv: sifive: unmatched: Adjust for big ramdisk image
Move kernel_comp_addr_r to an address that comes before the ramdisk
image, since the decompressed kernel size is known to us. This way
we can allow big ramdisk image to be loaded.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
include/configs/sifive-unmatched.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 08776466..fa734a66 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -56,12 +56,12 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x84000000\0" \
- "fdt_addr_r=0x88000000\0" \
- "scriptaddr=0x88100000\0" \
- "pxefile_addr_r=0x88200000\0" \
- "ramdisk_addr_r=0x88300000\0" \
- "kernel_comp_addr_r=0x90000000\0" \
+ "kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
+ "fdt_addr_r=0x8c000000\0" \
+ "scriptaddr=0x8c100000\0" \
+ "pxefile_addr_r=0x8c200000\0" \
+ "ramdisk_addr_r=0x8c300000\0" \
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
--
2.36.1

60
0002-riscv-sifive-unleashed-Set-kernel_comp_addr_r-for-co.patch Normal file
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@ -0,0 +1,60 @@
From a47efb51d082b419a7b76a51682390b413ed7771 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 24 May 2022 12:31:13 +0800
Subject: [PATCH 2/6] riscv: sifive: unleashed: Set kernel_comp_addr_r for
compressed kernel
Set kernel_comp_addr_r and kernel_comp_size for compressed kernel.
Adjust existing addresses for ramdisk, so that kernel_comp_addr_r
comes before the ramdisk image, since the decompressed kernel size
is known to us. This way we can allow big ramdisk image to be loaded.
Update unleashed.rst to remove the manual environment configuration
for compressed kernel boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
doc/board/sifive/unleashed.rst | 2 --
include/configs/sifive-unleashed.h | 10 ++++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/doc/board/sifive/unleashed.rst b/doc/board/sifive/unleashed.rst
index c8a62068..ce38b701 100644
--- a/doc/board/sifive/unleashed.rst
+++ b/doc/board/sifive/unleashed.rst
@@ -216,8 +216,6 @@ Or if you want to use a compressed kernel image file such as Image.gz
1.2 MiB/s
done
Bytes transferred = 4809458 (4962f2 hex)
- =>setenv kernel_comp_addr_r 0x90000000
- =>setenv kernel_comp_size 0x500000
By this time, correct kernel image is loaded and required environment variables
are set. You can proceed to load the ramdisk and device tree from the tftp server
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 920f3140..96e2eb67 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -61,12 +61,14 @@
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x84000000\0" \
- "fdt_addr_r=0x88000000\0" \
- "scriptaddr=0x88100000\0" \
+ "kernel_comp_addr_r=0x88000000\0" \
+ "kernel_comp_size=0x4000000\0" \
+ "fdt_addr_r=0x8c000000\0" \
+ "scriptaddr=0x8c100000\0" \
"script_offset_f=0x1fff000\0" \
"script_size_f=0x1000\0" \
- "pxefile_addr_r=0x88200000\0" \
- "ramdisk_addr_r=0x88300000\0" \
+ "pxefile_addr_r=0x8c200000\0" \
+ "ramdisk_addr_r=0x8c300000\0" \
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
--
2.36.1

40
0003-riscv-qemu-Set-kernel_comp_addr_r-for-compressed-ker.patch Normal file
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@ -0,0 +1,40 @@
From 33b94b09b2e45e0c9058415135338e4fd589de3e Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Tue, 24 May 2022 12:31:14 +0800
Subject: [PATCH 3/6] riscv: qemu: Set kernel_comp_addr_r for compressed kernel
Set kernel_comp_addr_r and kernel_comp_size for compressed kernel.
Adjust existing addresses for ramdisk, so that kernel_comp_addr_r
comes before the ramdisk image, since the decompressed kernel size
is known to us. This way we can allow big ramdisk image to be loaded.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
include/configs/qemu-riscv.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 618c3b63..f462895f 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -54,10 +54,12 @@
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x84000000\0" \
- "fdt_addr_r=0x88000000\0" \
- "scriptaddr=0x88100000\0" \
- "pxefile_addr_r=0x88200000\0" \
- "ramdisk_addr_r=0x88300000\0" \
+ "kernel_comp_addr_r=0x88000000\0" \
+ "kernel_comp_size=0x4000000\0" \
+ "fdt_addr_r=0x8c000000\0" \
+ "scriptaddr=0x8c100000\0" \
+ "pxefile_addr_r=0x8c200000\0" \
+ "ramdisk_addr_r=0x8c300000\0" \
BOOTENV
#endif
--
2.36.1

29
0003-riscv-sifive-unmatched-leave-128MiB-for-ramdisk.patch
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@ -1,29 +0,0 @@
From 5a334103bbd44f7577ff19d2d9a4e184175d7724 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Mon, 13 Sep 2021 03:15:35 -0700
Subject: [PATCH 3/7] riscv: sifive: unmatched: leave 128MiB for ramdisk
The current configuration only allows 125MiB, but the max allowed size should
be 128MiB.
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
include/configs/sifive-unmatched.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 31513058..10b71f75 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -70,7 +70,7 @@
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
- "kernel_comp_addr_r=0x90000000\0" \
+ "kernel_comp_addr_r=0x90300000\0" \
"kernel_comp_size=0x4000000\0" \
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
--
2.32.0

14
0004-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch
View File

@ -1,7 +1,7 @@
From c7bf5ac2e954ed19db605b475c9905cb399e1cc9 Mon Sep 17 00:00:00 2001
From d4546cee228b86b8ade6db23b4310880f7756ae0 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Mon, 13 Sep 2021 03:22:32 -0700
Subject: [PATCH 4/7] riscv: sifive: unmatched: disable FDT and initrd
Subject: [PATCH 4/6] riscv: sifive: unmatched: disable FDT and initrd
relocation
Same as on SiFive Unleashed we need to disable fdt and initrd relocation. Tom
@ -18,18 +18,18 @@ Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
1 file changed, 2 insertions(+)
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 10b71f75..3ed3318d 100644
index fa734a66..e62ad6ac 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -65,6 +65,8 @@
@@ -55,6 +55,8 @@
"name=system,size=-,bootable,type=${type_guid_gpt_system};"
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x84000000\0" \
"fdt_addr_r=0x88000000\0" \
"scriptaddr=0x88100000\0" \
"kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
--
2.32.0
2.36.1

104
0005-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch Normal file
View File

@ -0,0 +1,104 @@
From fbb43136d726289aba68f6222bf449b7e27ea70b Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Mon, 15 Nov 2021 03:31:04 -0800
Subject: [PATCH 5/6] board: sifive: spl: Initialized the PWM setting in the
SPL stage
LEDs and multiple fans can be controlled by SPL. This patch ensures
that all fans have been enabled in the SPL stage. In addition, the
LED's color will be set to yellow.
---
board/sifive/unmatched/Makefile | 1 +
board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++
board/sifive/unmatched/spl.c | 2 ++
3 files changed, 60 insertions(+)
create mode 100644 board/sifive/unmatched/pwm.c
diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
index 13453300..5df01982 100644
--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
@@ -9,3 +9,4 @@ obj-y += spl.o
else
obj-y += unmatched.o
endif
+obj-y += pwm.o
diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
new file mode 100644
index 00000000..e1cc0231
--- /dev/null
+++ b/board/sifive/unmatched/pwm.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021, SiFive Inc
+ *
+ * Authors:
+ * Vincent Chen <vincent.chen@sifive.com>
+ * David Abdurachmanov <david.abdurachmanov@sifive.com>
+ */
+
+#include <linux/io.h>
+#include <asm/arch/eeprom.h>
+
+struct pwm_sifive_regs {
+ unsigned int cfg; /* PWM configuration register */
+ unsigned int pad0; /* Reserved */
+ unsigned int cnt; /* PWM count register */
+ unsigned int pad1; /* Reserved */
+ unsigned int pwms; /* Scaled PWM count register */
+ unsigned int pad2; /* Reserved */
+ unsigned int pad3; /* Reserved */
+ unsigned int pad4; /* Reserved */
+ unsigned int cmp0; /* PWM 0 compare register */
+ unsigned int cmp1; /* PWM 1 compare register */
+ unsigned int cmp2; /* PWM 2 compare register */
+ unsigned int cmp3; /* PWM 3 compare register */
+};
+
+#define PWM0_BASE 0x10020000
+#define PWM1_BASE 0x10021000
+#define PWM_CFG_INIT 0x1000
+#define PWM_CMP_ENABLE_VAL 0x0
+#define PWM_CMP_DISABLE_VAL 0xffff
+
+void pwm_device_init(void)
+{
+ struct pwm_sifive_regs *pwm0, *pwm1;
+ pwm0 = (struct pwm_sifive_regs *)PWM0_BASE;
+ pwm1 = (struct pwm_sifive_regs *)PWM1_BASE;
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp0);
+ /* Set the 3-color PWM LEDs to yellow in SPL */
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp2);
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm0->cfg);
+
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm0->cmp3);
+ /* Turn on all the fans, (J21), (J23) and (J24), on the unmatched board */
+ /* The SoC fan(J21) on the rev3 board cannot be controled by PWM_COMP0,
+ so here sets the initial value of PWM_COMP0 as DISABLE */
+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3)
+ writel(PWM_CMP_DISABLE_VAL, (void *)&pwm1->cmp1);
+ else
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp1);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp2);
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+}
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 7c0beedc..f3a661a8 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -90,6 +90,8 @@ int spl_board_init_f(void)
goto end;
}
+ pwm_device_init();
+
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
--
2.36.1

26
0005-riscv-add-compressed-kernel-support-for-qemu-riscv.patch
View File

@ -1,26 +0,0 @@
From a039aad79c2ca97fdad90699801a875df349b791 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:52:13 +0000
Subject: [PATCH 5/7] riscv: add compressed kernel support for qemu-riscv
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
include/configs/qemu-riscv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index bbeea96e..0ede2a51 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -64,6 +64,8 @@
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
+ "kernel_comp_addr_r=0x90300000\0" \
+ "kernel_comp_size=0x4000000\0" \
BOOTENV
#endif
--
2.32.0

77
0002-riscv-SiFive-Unmatched-set-85C-as-the-limit.patch → 0006-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
View File

@ -1,23 +1,20 @@
From f85c3a2877b9ed884e0d2565d4ea11f071211ea6 Mon Sep 17 00:00:00 2001
From c920399ac5a2bd0d770b1f6833843b7abeb641e7 Mon Sep 17 00:00:00 2001
From: Vincent Chen <vincent.chen@sifive.com>
Date: Fri, 8 Oct 2021 11:48:06 +0000
Subject: [PATCH 2/7] riscv: SiFive Unmatched set 85C as the limit
Date: Mon, 24 Jan 2022 02:57:40 -0800
Subject: [PATCH 6/6] board: sifive: spl: Set remote thermal of TMP451 to 85
deg C for the unmatched board
Origin patch:
https://github.com/sifive/meta-sifive/blob/2021.09/recipes-bsp/u-boot/files/riscv64/0013-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
Fixed a typo in TMP451_RETMOE_THERM_LIMIT_INIT_VALUE
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
For TMP451 on the unmatched board, the default value of the remote
thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL.
---
board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++
drivers/misc/Kconfig | 10 ++++++++++
include/configs/sifive-unmatched.h | 3 +++
include/configs/sifive-unmatched.h | 4 ++++
scripts/config_whitelist.txt | 1 +
4 files changed, 43 insertions(+)
4 files changed, 44 insertions(+)
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index d5663274..0d56792a 100644
index f3a661a8..05ba5916 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -10,6 +10,8 @@
@ -29,7 +26,7 @@ index d5663274..0d56792a 100644
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
@@ -25,6 +27,27 @@
@@ -26,6 +28,27 @@
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
@ -57,9 +54,9 @@ index d5663274..0d56792a 100644
static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
{
int ret;
@@ -89,6 +112,12 @@ int spl_board_init_f(void)
goto end;
}
@@ -92,6 +115,12 @@ int spl_board_init_f(void)
pwm_device_init();
+ ret = init_tmp451_remote_therm_limit();
+ if (ret) {
@ -71,24 +68,17 @@ index d5663274..0d56792a 100644
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 997b7132..2878313b 100644
index 85ae7f62..38229cdf 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -404,6 +404,10 @@ config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
default 0
@@ -463,6 +463,16 @@ config SYS_I2C_EEPROM_ADDR
if I2C_EEPROM
+config SYS_I2C_TMP451_ADDR
+ hex "Chip address of the TMP451 device"
+ default 0
+
config SYS_I2C_EEPROM_BUS
int "I2C bus of the EEPROM device."
default 0
@@ -429,6 +433,12 @@ config SYS_I2C_EEPROM_ADDR_LEN
help
Note: This is NOT the chip address length!
+config SYS_I2C_TMP451_ADDR_LEN
+ int "Length in bytes of the TMP451 memory array address"
+ default 1
@ -97,33 +87,34 @@ index 997b7132..2878313b 100644
+
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
default 0
default 0x0
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index bea0eebe..31513058 100644
index e62ad6ac..718108a3 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -87,6 +87,9 @@
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1
+#define CONFIG_SYS_TMP451_BUS_NUM 0
+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c
+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1
@@ -32,6 +32,10 @@
#define CONFIG_ID_EEPROM
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
+#define CONFIG_SYS_TMP451_BUS_NUM 0
+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c
+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1
+
/* Environment options */
#ifndef CONFIG_SPL_BUILD
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index a9c2380d..20c7209a 100644
index cecdda67..378faa09 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3179,6 +3179,7 @@ CONFIG_SYS_TIMER_COUNTER
@@ -1671,6 +1671,7 @@ CONFIG_SYS_TIMER_BASE
CONFIG_SYS_TIMER_COUNTER
CONFIG_SYS_TIMER_COUNTS_DOWN
CONFIG_SYS_TIMER_PRESCALER
CONFIG_SYS_TIMER_RATE
+CONFIG_SYS_TMP451_BUS_NUM
CONFIG_SYS_TMPVIRT
CONFIG_SYS_TMRINTR_MASK
CONFIG_SYS_TMRINTR_NO
CONFIG_SYS_TSEC1_OFFSET
CONFIG_SYS_TSEC2_OFFSET
--
2.32.0
2.36.1

62
0006-riscv-set-NRCPUS-to-32.patch
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@ -1,62 +0,0 @@
From 51fd1cf2a83f39b1c786b79a476b5e2efaa4aa81 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:54:54 +0000
Subject: [PATCH 6/7] riscv: set NRCPUS to 32
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
configs/qemu-riscv64_defconfig | 1 +
configs/qemu-riscv64_smode_defconfig | 1 +
configs/qemu-riscv64_spl_defconfig | 1 +
configs/sifive_unleashed_defconfig | 1 +
configs/sifive_unmatched_defconfig | 1 +
5 files changed, 5 insertions(+)
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index daf5d655..aa79abc1 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -13,3 +13,4 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_NR_CPUS=32
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index 4a6416e2..ebe35d4c 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -16,3 +16,4 @@ CONFIG_CMD_NVEDIT_EFI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_NR_CPUS=32
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 429d4d81..8d08d50c 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -16,3 +16,4 @@ CONFIG_CMD_SBI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_NR_CPUS=32
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index fd686dfa..d0c53888 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -28,3 +28,4 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
CONFIG_DM_RESET=y
+CONFIG_NR_CPUS=32
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 1dde98e0..ebaa945e 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -42,3 +42,4 @@ CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_NR_CPUS=32
--
2.32.0

67
0007-riscv-add-CONFIG_CMD_GPT_RENAME.patch
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@ -1,67 +0,0 @@
From 2815d0a6c66822c8fd6c1fcf2d345e5b8a9b011a Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@gmail.com>
Date: Fri, 8 Oct 2021 11:58:16 +0000
Subject: [PATCH 7/7] riscv: add CONFIG_CMD_GPT_RENAME
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com>
---
configs/qemu-riscv64_defconfig | 2 ++
configs/qemu-riscv64_smode_defconfig | 2 ++
configs/qemu-riscv64_spl_defconfig | 2 ++
configs/sifive_unleashed_defconfig | 2 ++
configs/sifive_unmatched_defconfig | 2 ++
5 files changed, 10 insertions(+)
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index aa79abc1..625e7295 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -14,3 +14,5 @@ CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index ebe35d4c..fde8c0f5 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -17,3 +17,5 @@ CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 8d08d50c..8795edee 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -17,3 +17,5 @@ CONFIG_OF_PRIOR_STAGE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index d0c53888..8e40eead 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -29,3 +29,5 @@ CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
CONFIG_DM_RESET=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index ebaa945e..92b7608f 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -43,3 +43,5 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_NR_CPUS=32
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
--
2.32.0

11
uboot-tools.spec
View File

@ -30,13 +30,12 @@ Patch8: 0001-Revert-spi-spi-uclass-Add-support-to-manually-reloca.patch
Patch9: rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
# RISC-V (riscv64) patches
Patch40: 0001-riscv-SiFive-Unleashed-booti-compressed-kernel-suppo.patch
Patch41: 0002-riscv-SiFive-Unmatched-set-85C-as-the-limit.patch
Patch42: 0003-riscv-sifive-unmatched-leave-128MiB-for-ramdisk.patch
Patch40: 0001-riscv-sifive-unmatched-Adjust-for-big-ramdisk-image.patch
Patch41: 0002-riscv-sifive-unleashed-Set-kernel_comp_addr_r-for-co.patch
Patch42: 0003-riscv-qemu-Set-kernel_comp_addr_r-for-compressed-ker.patch
Patch43: 0004-riscv-sifive-unmatched-disable-FDT-and-initrd-reloca.patch
Patch44: 0005-riscv-add-compressed-kernel-support-for-qemu-riscv.patch
Patch45: 0006-riscv-set-NRCPUS-to-32.patch
Patch46: 0007-riscv-add-CONFIG_CMD_GPT_RENAME.patch
Patch44: 0005-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch
Patch45: 0006-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch
BuildRequires: bc
BuildRequires: bison