From 200f91fffd40759e2aa301b46f6557537c506963 Mon Sep 17 00:00:00 2001 From: David Abdurachmanov Date: Sun, 20 Nov 2022 17:33:47 +0200 Subject: [PATCH] Backport fix for binutils 2.38+ Signed-off-by: David Abdurachmanov --- ...977518f13824b847e23275001191139bc384.patch | 52 +++++++++++++++++++ uboot-tools.spec | 1 + 2 files changed, 53 insertions(+) create mode 100644 1dde977518f13824b847e23275001191139bc384.patch diff --git a/1dde977518f13824b847e23275001191139bc384.patch b/1dde977518f13824b847e23275001191139bc384.patch new file mode 100644 index 0000000..1533934 --- /dev/null +++ b/1dde977518f13824b847e23275001191139bc384.patch @@ -0,0 +1,52 @@ +From 1dde977518f13824b847e23275001191139bc384 Mon Sep 17 00:00:00 2001 +From: Alexandre Ghiti +Date: Mon, 3 Oct 2022 18:07:54 +0200 +Subject: [PATCH] riscv: Fix build against binutils 2.38 + +The following description is copied from the equivalent patch for the +Linux Kernel proposed by Aurelien Jarno: + +>From version 2.38, binutils default to ISA spec version 20191213. This +means that the csr read/write (csrr*/csrw*) instructions and fence.i +instruction has separated from the `I` extension, become two standalone +extensions: Zicsr and Zifencei. As the kernel uses those instruction, +this causes the following build failure: + +arch/riscv/cpu/mtrap.S: Assembler messages: +arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' +arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' +arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' +arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' + +Signed-off-by: Alexandre Ghiti +Reviewed-by: Bin Meng +Tested-by: Heinrich Schuchardt +Tested-by: Heiko Stuebner +Tested-by: Christian Stewart +Reviewed-by: Rick Chen +--- + arch/riscv/Makefile | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 0b80eb8d8645..53d1194ffb64 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany + endif + +-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ ++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) ++ ++# Newer binutils versions default to ISA spec version 20191213 which moves some ++# instructions from the I extension to the Zicsr and Zifencei extensions. ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) ++ifeq ($(toolchain-need-zicsr-zifencei),y) ++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei ++endif ++ ++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ + -mcmodel=$(CMODEL) + + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) diff --git a/uboot-tools.spec b/uboot-tools.spec index 2ee9ee7..29213bc 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -39,6 +39,7 @@ Patch8: 0001-Revert-power-pmic-rk8xx-Support-sysreset-shutdown-me.patch Patch20: 0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch Patch21: 0002-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch Patch22: 0003-Enable-sbi-command-and-SBI-sysreset.patch +Patch23: 1dde977518f13824b847e23275001191139bc384.patch BuildRequires: bc BuildRequires: bison