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2019.04, Fixes for AllWinner and NVIDIA Jetson devices

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This commit is contained in:
Peter Robinson 2019-04-18 15:53:13 +01:00
parent 7f3f828546
commit 178f1bba0f
11 changed files with 2757 additions and 1875 deletions
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777
ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch
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@ -1,777 +0,0 @@
From patchwork Mon Mar 18 23:24:22 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot, v2,
15/15] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com>
X-Patchwork-Id: 1058155
X-Patchwork-Delegate: twarren@nvidia.com
Message-Id: <20190318232422.24404-16-thierry.reding@gmail.com>
To: Tom Warren <twarren@nvidia.com>
Cc: u-boot@lists.denx.de, Stephen Warren <swarren@nvidia.com>
Date: Tue, 19 Mar 2019 00:24:22 +0100
From: Thierry Reding <thierry.reding@gmail.com>
List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: Thierry Reding <treding@nvidia.com>
The Jetson Nano Developer Kit is a Tegra X1 based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity.
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/dts/tegra210-p3450-0000.dts | 130 +++++++++
arch/arm/mach-tegra/tegra210/Kconfig | 7 +
board/nvidia/p3450-0000/Kconfig | 12 +
board/nvidia/p3450-0000/MAINTAINERS | 6 +
board/nvidia/p3450-0000/Makefile | 8 +
board/nvidia/p3450-0000/p3450-0000.c | 143 ++++++++++
.../p3450-0000/pinmux-config-p3450-0000.h | 257 ++++++++++++++++++
configs/p3450-0000_defconfig | 54 ++++
include/configs/p3450-0000.h | 44 +++
9 files changed, 661 insertions(+)
create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts
create mode 100644 board/nvidia/p3450-0000/Kconfig
create mode 100644 board/nvidia/p3450-0000/MAINTAINERS
create mode 100644 board/nvidia/p3450-0000/Makefile
create mode 100644 board/nvidia/p3450-0000/p3450-0000.c
create mode 100644 board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
create mode 100644 configs/p3450-0000_defconfig
create mode 100644 include/configs/p3450-0000.h
diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts
new file mode 100644
index 000000000000..a2119165e2f6
--- /dev/null
+++ b/arch/arm/dts/tegra210-p3450-0000.dts
@@ -0,0 +1,130 @@
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+ model = "NVIDIA Jetson Nano Development Kit";
+ compatible = "nvidia,p3450-0000", "nvidia,tegra210";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = "/i2c@7000d000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ sdhci0 = "/sdhci@700b0600";
+ sdhci1 = "/sdhci@700b0000";
+ spi0 = "/spi@70410000";
+ usb0 = "/usb@7d000000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0xc0000000>;
+ };
+
+ pcie-controller@01003000 {
+ status = "okay";
+
+ pci@1,0 {
+ status = "okay";
+ };
+
+ pci@2,0 {
+ status = "okay";
+ };
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ padctl@7009f000 {
+ pinctrl-0 = <&padctl_default>;
+ pinctrl-names = "default";
+
+ padctl_default: pinmux {
+ xusb {
+ nvidia,lanes = "otg-1", "otg-2";
+ nvidia,function = "xusb";
+ nvidia,iddq = <0>;
+ };
+
+ usb3 {
+ nvidia,lanes = "pcie-5", "pcie-6";
+ nvidia,function = "usb3";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x1 {
+ nvidia,lanes = "pcie-0";
+ nvidia,function = "pcie-x1";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x4 {
+ nvidia,lanes = "pcie-1", "pcie-2",
+ "pcie-3", "pcie-4";
+ nvidia,function = "pcie-x4";
+ nvidia,iddq = <0>;
+ };
+
+ sata {
+ nvidia,lanes = "sata-0";
+ nvidia,function = "sata";
+ nvidia,iddq = <0>;
+ };
+ };
+ };
+
+ sdhci@700b0000 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ spi@70410000 {
+ status = "okay";
+ };
+
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index 250738aed312..60dde5435940 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -35,6 +35,12 @@ config TARGET_P2571
help
P2571 is a P2530 married to a P1963 I/O board
+config TARGET_P3450_0000
+ bool "NVIDIA Jetson Nano Development Kit"
+ select BOARD_LATE_INIT
+ help
+ P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
+
endchoice
config SYS_SOC
@@ -47,5 +53,6 @@ source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
source "board/nvidia/p2371-2180/Kconfig"
source "board/nvidia/p2571/Kconfig"
+source "board/nvidia/p3450-0000/Kconfig"
endif
diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig
new file mode 100644
index 000000000000..7a08cd88675f
--- /dev/null
+++ b/board/nvidia/p3450-0000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P3450_0000
+
+config SYS_BOARD
+ default "p3450-0000"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "p3450-0000"
+
+endif
diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS
new file mode 100644
index 000000000000..40700066bf39
--- /dev/null
+++ b/board/nvidia/p3450-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P3450-0000 BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/p3450-0000/
+F: include/configs/p3450-0000.h
+F: configs/p3450-0000_defconfig
diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile
new file mode 100644
index 000000000000..993c506d8200
--- /dev/null
+++ b/board/nvidia/p3450-0000/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2018
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p3450-0000.o
diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c
new file mode 100644
index 000000000000..fc13185c36b6
--- /dev/null
+++ b/board/nvidia/p3450-0000/p3450-0000.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2018
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <i2c.h>
+#include <linux/libfdt.h>
+#include <pca953x.h>
+#include <asm/arch-tegra/cboot.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "../p2571/max77620_init.h"
+#include "pinmux-config-p3450-0000.h"
+
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return;
+ }
+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xF2;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+ /* Disable LDO4 discharge */
+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret) {
+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+ } else {
+ val &= ~BIT(1); /* ADE */
+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+ }
+
+ /* Set MBLPD */
+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret) {
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ } else {
+ val |= BIT(6); /* MBLPD */
+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ }
+}
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_clear_tristate_input_clamping();
+
+ gpio_config_table(p3450_0000_gpio_inits,
+ ARRAY_SIZE(p3450_0000_gpio_inits));
+
+ pinmux_config_pingrp_table(p3450_0000_pingrps,
+ ARRAY_SIZE(p3450_0000_pingrps));
+
+ pinmux_config_drvgrp_table(p3450_0000_drvgrps,
+ ARRAY_SIZE(p3450_0000_drvgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO1 to 1.05V for PEX power */
+ debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return -1;
+ }
+ /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xCA;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
+
+ return 0;
+}
+#endif /* PCI */
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return 0;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0)
+ return 0;
+
+ debug("PCI ethernet device tree node found\n");
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+
+ return 0;
+}
diff --git a/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
new file mode 100644
index 000000000000..d491bffccd72
--- /dev/null
+++ b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py p3450-0000".
+ */
+
+#ifndef _PINMUX_CONFIG_P3450_0000_H_
+#define _PINMUX_CONFIG_P3450_0000_H_
+
+#define GPIO_INIT(_port, _gpio, _init) \
+ { \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config p3450_0000_gpio_inits[] = {
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(A, 6, OUT0),
+ GPIO_INIT(B, 4, IN),
+ GPIO_INIT(B, 5, IN),
+ GPIO_INIT(B, 6, IN),
+ GPIO_INIT(B, 7, IN),
+ GPIO_INIT(C, 0, IN),
+ GPIO_INIT(C, 1, IN),
+ GPIO_INIT(C, 2, IN),
+ GPIO_INIT(C, 3, IN),
+ GPIO_INIT(C, 4, IN),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, OUT0),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(J, 4, IN),
+ GPIO_INIT(J, 5, IN),
+ GPIO_INIT(J, 6, IN),
+ GPIO_INIT(J, 7, IN),
+ GPIO_INIT(S, 5, IN),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(V, 1, IN),
+ GPIO_INIT(X, 3, OUT1),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Y, 2, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 2, IN),
+ GPIO_INIT(Z, 3, OUT0),
+ GPIO_INIT(BB, 0, IN),
+ GPIO_INIT(CC, 4, IN),
+ GPIO_INIT(DD, 0, IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config p3450_0000_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
+ PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
+ PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
+ PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PA6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MOSI_PB4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MISO_PB5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_SCK_PB6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_CS0_PB7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RTS_PD3, UARTC, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_CLK_PE4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RX_PG1, UARTB, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RTS_PG2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_CTS_PG3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_INT_PI1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_CTS_PI7, UARTD, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_AF_EN_PS5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RX_PU1, UARTA, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RTS_PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_CTS_PU3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_PWM_PV0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_RST_PV6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(ALS_PROX_INT_PX3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_DOWN_PX7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_TE_PY2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CLK_32K_OUT_PY5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_CLK_PBB2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(HDMI_INT_DP_HPD_PCC1, DP, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PCC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(DP_HPD0_PCC6, DP, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(SPI2_CS1_PDD0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CPU_PWR_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config p3450_0000_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_P3450_0000_H */
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
new file mode 100644
index 000000000000..32c2b65a2979
--- /dev/null
+++ b/configs/p3450-0000_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_TEGRA210=y
+CONFIG_TARGET_P3450_0000=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA114_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0955
+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_ENV_IS_IN_MMC is not set
diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
new file mode 100644
index 000000000000..37c71421acbb
--- /dev/null
+++ b/include/configs/p3450-0000.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018-2019 NVIDIA Corporation. All rights reserved.
+ */
+
+#ifndef _P3450_0000_H
+#define _P3450_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* Only MMC1/PXE/DHCP for now, add USB back in later when supported */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+/* SPI */
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+#define CONFIG_PREBOOT
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
+ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
+ "source ${scriptaddr}; " \
+ "fi\0"
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY 19200000
+
+#endif /* _P3450_0000_H */

761
ARM-tegra-Add-support-for-framebuffer-carveouts.patch
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File diff suppressed because it is too large Load Diff

2237
ARM-tegra-Miscellaneous-improvements.patch
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File diff suppressed because it is too large Load Diff

162
arm-tegra-defaine-fdtfile-for-all-devices.patch Normal file
View File

@ -0,0 +1,162 @@
From 1e93c98419e6a1ea62ef697ed915617024eb6da0 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Thu, 18 Apr 2019 14:03:33 +0100
Subject: [PATCH] arm: tegra: defaine fdtfile for all devices
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
include/configs/tegra-common.h | 6 ++++++
include/configs/tegra114-common.h | 1 +
include/configs/tegra124-common.h | 1 +
include/configs/tegra186-common.h | 1 +
include/configs/tegra20-common.h | 1 +
include/configs/tegra210-common.h | 1 +
include/configs/tegra30-common.h | 1 +
7 files changed, 12 insertions(+)
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 84f671d00c..c3e16d8cfc 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -56,6 +56,12 @@
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
+#ifdef CONFIG_ARM64
+#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#else
+#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#endif
+
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 1aa4412645..0c44a7673b 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -50,6 +50,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 3530684164..29da06c8f7 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -52,6 +52,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
index b4936cc731..5c3ad35c76 100644
--- a/include/configs/tegra186-common.h
+++ b/include/configs/tegra186-common.h
@@ -49,6 +49,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index e58477e289..73c94d993b 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -51,6 +51,7 @@
"scriptaddr=0x10000000\0" \
"pxefile_addr_r=0x10100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x03000000\0" \
"ramdisk_addr_r=0x03100000\0"
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index 1c533118ad..69e446ed58 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -46,6 +46,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 2d8948d9d9..27696009cd 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -47,6 +47,7 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x83000000\0" \
"ramdisk_addr_r=0x83100000\0"
--
2.21.0
From 267dc15aa8f247362b04387d6a1ab01d94d41aef Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Thu, 18 Apr 2019 15:44:59 +0100
Subject: [PATCH] add BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 because tx2
variants
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
include/config_distro_bootcmd.h | 2 ++
include/configs/tegra186-common.h | 7 ++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 4993303f4d..cd317bb457 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -118,8 +118,10 @@
"setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \
"fi; "
#else
+#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK
#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
#endif
+#endif
#define BOOTENV_SHARED_EFI \
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
index 5c3ad35c76..d5f21e0907 100644
--- a/include/configs/tegra186-common.h
+++ b/include/configs/tegra186-common.h
@@ -20,6 +20,12 @@
/* Generic Interrupt Controller */
#define CONFIG_GICV2
+#undef FDTFILE
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
+ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
+ "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \
+ "fi; "
+
/*
* Memory layout for where various images get loaded by boot scripts:
*
@@ -49,7 +55,6 @@
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "fdtfile=" FDTFILE "\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
--
2.21.0

224
net-eth-uclass-Write-MAC-address-to-hardware-after-probe.patch
View File

@ -1,16 +1,15 @@
From patchwork Fri Mar 8 19:51:25 2019 From patchwork Tue Apr 16 16:24:16 2019
Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0 MIME-Version: 1.0
Content-Transfer-Encoding: 7bit Content-Transfer-Encoding: 7bit
Subject: [U-Boot, Subject: [U-Boot, v2,
1/3] net: eth-uclass: Write MAC address to hardware after probe 1/2] net: eth-uclass: Write MAC address to hardware after probe
X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com> X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com>
X-Patchwork-Id: 1053669 X-Patchwork-Id: 1086417
Message-Id: <20190308195127.32711-1-thierry.reding@gmail.com> Message-Id: <20190416162417.25799-1-thierry.reding@gmail.com>
To: Joe Hershberger <joe.hershberger@ni.com> To: Simon Glass <sjg@chromium.org>, Joe Hershberger <joe.hershberger@ni.com>
Cc: u-boot@lists.denx.de, Stephen Warren <swarren@nvidia.com>, Cc: u-boot@lists.denx.de
Tom Warren <twarren@nvidia.com> Date: Tue, 16 Apr 2019 18:24:16 +0200
Date: Fri, 8 Mar 2019 20:51:25 +0100
From: Thierry Reding <thierry.reding@gmail.com> From: Thierry Reding <thierry.reding@gmail.com>
List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Id: U-Boot discussion <u-boot.lists.denx.de>
@ -44,104 +43,155 @@ index 2ef20df19203..4225aabf1fa1 100644
} }
From patchwork Fri Mar 8 19:51:26 2019 From patchwork Tue Apr 16 16:24:17 2019
Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0 MIME-Version: 1.0
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Subject: [U-Boot,2/3] net: rtl8169: Implement ->hwaddr_write() callback Subject: [U-Boot,v2,2/2] net: eth-uclass: Support device tree MAC addresses
X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com> X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com>
X-Patchwork-Id: 1053670 X-Patchwork-Id: 1086418
Message-Id: <20190308195127.32711-2-thierry.reding@gmail.com> Message-Id: <20190416162417.25799-2-thierry.reding@gmail.com>
To: Joe Hershberger <joe.hershberger@ni.com> To: Simon Glass <sjg@chromium.org>, Joe Hershberger <joe.hershberger@ni.com>
Cc: u-boot@lists.denx.de, Stephen Warren <swarren@nvidia.com>, Cc: u-boot@lists.denx.de
Tom Warren <twarren@nvidia.com> Date: Tue, 16 Apr 2019 18:24:17 +0200
Date: Fri, 8 Mar 2019 20:51:26 +0100
From: Thierry Reding <thierry.reding@gmail.com> From: Thierry Reding <thierry.reding@gmail.com>
List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: Thierry Reding <treding@nvidia.com> From: Thierry Reding <treding@nvidia.com>
Implement this callback that allows the MAC address to be set for the Add the standard Ethernet device tree bindings (imported from v5.0 of
Ethernet card. This is necessary in order for the device to be able to the Linux kernel) and implement support for reading the MAC address for
receive packets for the MAC address that U-Boot advertises. Ethernet devices in the Ethernet uclass. If the "mac-address" property
exists, the MAC address will be parsed from that. If that property does
not exist, the "local-mac-address" property will be tried as fallback.
MAC addresses from device tree take precedence over the ones stored in
a network interface card's ROM.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
--- ---
drivers/net/rtl8169.c | 18 ++++++++++++++++++ Changes in v2:
1 file changed, 18 insertions(+) - use dev_read_u8_array_ptr()
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c .../devicetree/bindings/net/ethernet.txt | 66 +++++++++++++++++++
index a78f3d233f1a..27e27b34176b 100644 net/eth-uclass.c | 26 +++++++-
--- a/drivers/net/rtl8169.c 2 files changed, 89 insertions(+), 3 deletions(-)
+++ b/drivers/net/rtl8169.c create mode 100644 Documentation/devicetree/bindings/net/ethernet.txt
@@ -941,6 +941,23 @@ static void rtl_halt(struct eth_device *dev)
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt
new file mode 100644
index 000000000000..cfc376bc977a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -0,0 +1,66 @@
+The following properties are common to the Ethernet controllers:
+
+NOTE: All 'phy*' properties documented below are Ethernet specific. For the
+generic PHY 'phys' property, see
+Documentation/devicetree/bindings/phy/phy-bindings.txt.
+
+- local-mac-address: array of 6 bytes, specifies the MAC address that was
+ assigned to the network device;
+- mac-address: array of 6 bytes, specifies the MAC address that was last used by
+ the boot program; should be used in cases where the MAC address assigned to
+ the device by the boot program is different from the "local-mac-address"
+ property;
+- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
+- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
+- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
+- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
+ the maximum frame size (there's contradiction in the Devicetree
+ Specification).
+- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
+ standard property; supported values are:
+ * "internal"
+ * "mii"
+ * "gmii"
+ * "sgmii"
+ * "qsgmii"
+ * "tbi"
+ * "rev-mii"
+ * "rmii"
+ * "rgmii" (RX and TX delays are added by the MAC when required)
+ * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
+ MAC should not add the RX or TX delays in this case)
+ * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
+ should not add an RX delay in this case)
+ * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
+ should not add an TX delay in this case)
+ * "rtbi"
+ * "smii"
+ * "xgmii"
+ * "trgmii"
+ * "2000base-x",
+ * "2500base-x",
+ * "rxaui"
+ * "xaui"
+ * "10gbase-kr" (10GBASE-KR, XFI, SFI)
+- phy-connection-type: the same as "phy-mode" property but described in the
+ Devicetree Specification;
+- phy-handle: phandle, specifies a reference to a node representing a PHY
+ device; this property is described in the Devicetree Specification and so
+ preferred;
+- phy: the same as "phy-handle" property, not recommended for new bindings.
+- phy-device: the same as "phy-handle" property, not recommended for new
+ bindings.
+- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
+ is used for components that can have configurable receive fifo sizes,
+ and is useful for determining certain configuration settings such as
+ flow control thresholds.
+- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
+ is used for components that can have configurable fifo sizes.
+- managed: string, specifies the PHY management type. Supported values are:
+ "auto", "in-band-status". "auto" is the default, it usess MDIO for
+ management if fixed-link is not specified.
+
+Child nodes of the Ethernet controller are typically the individual PHY devices
+connected via the MDIO bus (sometimes the MDIO bus controller is separate).
+They are described in the phy.txt file in this same directory.
+For non-MDIO PHY management see fixed-link.txt.
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 4225aabf1fa1..c6d5ec013bd8 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -455,6 +455,23 @@ static int eth_pre_unbind(struct udevice *dev)
return 0;
} }
#endif
+#ifdef CONFIG_DM_ETH +static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN])
+static int rtl8169_write_hwaddr(struct udevice *dev)
+{ +{
+ struct eth_pdata *plat = dev_get_platdata(dev); + const uint8_t *p;
+ unsigned int i;
+ +
+ RTL_W8(Cfg9346, Cfg9346_Unlock); + p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN);
+ if (!p)
+ p = dev_read_u8_array_ptr(dev, "local-mac-address", ARP_HLEN);
+ +
+ for (i = 0; i < MAC_ADDR_LEN; i++) + if (!p) {
+ RTL_W8(MAC0 + i, plat->enetaddr[i]); + memset(mac, 0, ARP_HLEN);
+ return false;
+ }
+ +
+ RTL_W8(Cfg9346, Cfg9346_Lock); + memcpy(mac, p, ARP_HLEN);
+ + return true;
+ return 0;
+} +}
+#endif
+ +
/************************************************************************** static int eth_post_probe(struct udevice *dev)
INIT - Look for an adapter, this routine's visible to the outside {
***************************************************************************/ struct eth_device_priv *priv = dev->uclass_priv;
@@ -1195,6 +1212,7 @@ static const struct eth_ops rtl8169_eth_ops = { @@ -489,9 +506,12 @@ static int eth_post_probe(struct udevice *dev)
.send = rtl8169_eth_send,
.recv = rtl8169_eth_recv,
.stop = rtl8169_eth_stop,
+ .write_hwaddr = rtl8169_write_hwaddr,
};
static const struct udevice_id rtl8169_eth_ids[] = { priv->state = ETH_STATE_INIT;
From patchwork Fri Mar 8 19:51:27 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot,3/3] net: rtl8169: Support RTL-8168h/8111h
X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com>
X-Patchwork-Id: 1053671
Message-Id: <20190308195127.32711-3-thierry.reding@gmail.com>
To: Joe Hershberger <joe.hershberger@ni.com>
Cc: u-boot@lists.denx.de, Stephen Warren <swarren@nvidia.com>,
Tom Warren <twarren@nvidia.com>
Date: Fri, 8 Mar 2019 20:51:27 +0100
From: Thierry Reding <thierry.reding@gmail.com>
List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: Thierry Reding <treding@nvidia.com>
This version of the RTL-8168 is present on some development boards and
is compatible with this driver. Add support for identifying this version
of the chip so that U-Boot won't complain about it being unknown.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/net/rtl8169.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 27e27b34176b..bc052e72564b 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -257,6 +257,7 @@ static struct {
{"RTL-8168/8111g", 0x4c, 0xff7e1880,},
{"RTL-8101e", 0x34, 0xff7e1880,},
{"RTL-8100e", 0x32, 0xff7e1880,},
+ {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
};
enum _DescStatusBit { - /* Check if the device has a MAC address in ROM */
- if (eth_get_ops(dev)->read_rom_hwaddr)
- eth_get_ops(dev)->read_rom_hwaddr(dev);
+ /* Check if the device has a MAC address in device tree */
+ if (!eth_dev_get_mac_address(dev, pdata->enetaddr)) {
+ /* Check if the device has a MAC address in ROM */
+ if (eth_get_ops(dev)->read_rom_hwaddr)
+ eth_get_ops(dev)->read_rom_hwaddr(dev);
+ }
eth_env_get_enetaddr_by_index("eth", dev->seq, env_enetaddr);
if (!is_zero_ethaddr(env_enetaddr)) {

102
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@ -0,0 +1,102 @@
From patchwork Tue Apr 16 16:20:29 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot, RESEND,
1/2] net: rtl8169: Implement ->hwaddr_write() callback
X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com>
X-Patchwork-Id: 1086411
Message-Id: <20190416162030.13590-1-thierry.reding@gmail.com>
To: Joe Hershberger <joe.hershberger@ni.com>
Cc: u-boot@lists.denx.de
Date: Tue, 16 Apr 2019 18:20:29 +0200
From: Thierry Reding <thierry.reding@gmail.com>
List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: Thierry Reding <treding@nvidia.com>
Implement this callback that allows the MAC address to be set for the
Ethernet card. This is necessary in order for the device to be able to
receive packets for the MAC address that U-Boot advertises.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
drivers/net/rtl8169.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index a78f3d233f1a..27e27b34176b 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -941,6 +941,23 @@ static void rtl_halt(struct eth_device *dev)
}
#endif
+#ifdef CONFIG_DM_ETH
+static int rtl8169_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ unsigned int i;
+
+ RTL_W8(Cfg9346, Cfg9346_Unlock);
+
+ for (i = 0; i < MAC_ADDR_LEN; i++)
+ RTL_W8(MAC0 + i, plat->enetaddr[i]);
+
+ RTL_W8(Cfg9346, Cfg9346_Lock);
+
+ return 0;
+}
+#endif
+
/**************************************************************************
INIT - Look for an adapter, this routine's visible to the outside
***************************************************************************/
@@ -1195,6 +1212,7 @@ static const struct eth_ops rtl8169_eth_ops = {
.send = rtl8169_eth_send,
.recv = rtl8169_eth_recv,
.stop = rtl8169_eth_stop,
+ .write_hwaddr = rtl8169_write_hwaddr,
};
static const struct udevice_id rtl8169_eth_ids[] = {
From patchwork Tue Apr 16 16:20:30 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot,RESEND,2/2] net: rtl8169: Support RTL-8168h/8111h
X-Patchwork-Submitter: Thierry Reding <thierry.reding@gmail.com>
X-Patchwork-Id: 1086412
Message-Id: <20190416162030.13590-2-thierry.reding@gmail.com>
To: Joe Hershberger <joe.hershberger@ni.com>
Cc: u-boot@lists.denx.de
Date: Tue, 16 Apr 2019 18:20:30 +0200
From: Thierry Reding <thierry.reding@gmail.com>
List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: Thierry Reding <treding@nvidia.com>
This version of the RTL-8168 is present on some development boards and
is compatible with this driver. Add support for identifying this version
of the chip so that U-Boot won't complain about it being unknown.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
drivers/net/rtl8169.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 27e27b34176b..bc052e72564b 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -257,6 +257,7 @@ static struct {
{"RTL-8168/8111g", 0x4c, 0xff7e1880,},
{"RTL-8101e", 0x34, 0xff7e1880,},
{"RTL-8100e", 0x32, 0xff7e1880,},
+ {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
};
enum _DescStatusBit {

2
sources
View File

@ -1 +1 @@
SHA512 (u-boot-2019.04-rc4.tar.bz2) = 33a57e4acb51dbe04123055b159a5b3a933ea8340aa81a4148572ee5fc12288413a6c6c0b80b6fe099ac79ea6359be2d9034ead1edfcc0403895f3f8eb56746e SHA512 (u-boot-2019.04.tar.bz2) = 357fe94b5b043885472ea1b7dcbbac601d0c1f7c64f71026b9e1279b53160847c6478d6ec98a2f678e562db21e39037d6e6fbc1e6b19beaac02ca14e93c5de0e

22
uboot-tools.spec
View File

@ -1,8 +1,8 @@
%global candidate rc4 #global candidate rc4
Name: uboot-tools Name: uboot-tools
Version: 2019.04 Version: 2019.04
Release: 0.9%{?candidate:.%{candidate}}%{?dist} Release: 1%{?candidate:.%{candidate}}%{?dist}
Summary: U-Boot utilities Summary: U-Boot utilities
License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+
URL: http://www.denx.de/wiki/U-Boot URL: http://www.denx.de/wiki/U-Boot
@ -18,17 +18,19 @@ Source5: 10-devicetree.install
Patch1: uefi-use-Fedora-specific-path-name.patch Patch1: uefi-use-Fedora-specific-path-name.patch
# general fixes # general fixes
Patch2: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch Patch2: usb-kbd-fixes.patch
Patch3: usb-kbd-fixes.patch Patch3: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch
Patch4: uefi-rc5-fixes.patch Patch4: uefi-fix-memory-calculation-overflow-on-32-bit-systems.patch
Patch5: uefi-Change-FDT-memory-type-from-runtime-data-to-boot-services-data.patch
# Board fixes and enablement # Board fixes and enablement
Patch10: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch10: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch
Patch11: dragonboard-fixes.patch Patch11: dragonboard-fixes.patch
Patch12: ARM-tegra-Miscellaneous-improvements.patch Patch12: ARM-tegra-Add-support-for-framebuffer-carveouts.patch
Patch13: ARM-tegra-Add-support-for-framebuffer-carveouts.patch Patch13: ARM-tegra-Miscellaneous-improvements.patch
Patch14: ARM-tegra-Add-NVIDIA-Jetson-Nano-Developer-Kit-support.patch
Patch15: net-eth-uclass-Write-MAC-address-to-hardware-after-probe.patch Patch15: net-eth-uclass-Write-MAC-address-to-hardware-after-probe.patch
Patch16: net-rtl8169-Implement---hwaddr_write-callback.patch
Patch17: arm-tegra-defaine-fdtfile-for-all-devices.patch
BuildRequires: bc BuildRequires: bc
BuildRequires: dtc BuildRequires: dtc
@ -303,6 +305,10 @@ cp -p board/warp7/README builds/docs/README.warp7
%endif %endif
%changelog %changelog
* Sun Apr 14 2019 Peter Robinson <pbrobinson@fedoraproject.org> 2019.04-1
- 2019.04
- Fixes for AllWinner and NVIDIA Jetson devices
* Thu Apr 4 2019 Peter Robinson <pbrobinson@fedoraproject.org> 2019.04-0.9-rc4 * Thu Apr 4 2019 Peter Robinson <pbrobinson@fedoraproject.org> 2019.04-0.9-rc4
- Latest Tegra patch revision - Latest Tegra patch revision

54
uefi-Change-FDT-memory-type-from-runtime-data-to-boot-services-data.patch Normal file
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@ -0,0 +1,54 @@
From patchwork Fri Apr 12 18:26:28 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot,
U-boot] : Change FDT memory type from runtime data to boot services
data
X-Patchwork-Submitter: Ilias Apalodimas <ilias.apalodimas@linaro.org>
X-Patchwork-Id: 1084888
X-Patchwork-Delegate: xypron.glpk@gmx.de
Message-Id: <1555093588-21916-1-git-send-email-ilias.apalodimas@linaro.org>
To: u-boot@lists.denx.de,
xypron.glpk@gmx.de
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>, agraf@csgraf.de,
ard.biesheuvel@linaro.org
Date: Fri, 12 Apr 2019 21:26:28 +0300
From: Ilias Apalodimas <ilias.apalodimas@linaro.org>
List-Id: U-Boot discussion <u-boot.lists.denx.de>
Following Ard's suggestion:
Runtime data sections are intended for data that is used by the runtime
services implementation.
Let's change the type to EFI_BOOT_SERVICES_DATA
This also fixes booting of armv7 using efi and fdtcontroladdr
Suggested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
cmd/bootefi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 3619a20e6433..15ee4af45667 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -111,13 +111,13 @@ static efi_status_t copy_fdt(void **fdtp)
new_fdt_addr = (uintptr_t)map_sysmem(fdt_ram_start + 0x7f00000 +
fdt_size, 0);
ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RUNTIME_SERVICES_DATA, fdt_pages,
+ EFI_BOOT_SERVICES_DATA, fdt_pages,
&new_fdt_addr);
if (ret != EFI_SUCCESS) {
/* If we can't put it there, put it somewhere */
new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size);
ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RUNTIME_SERVICES_DATA, fdt_pages,
+ EFI_BOOT_SERVICES_DATA, fdt_pages,
&new_fdt_addr);
if (ret != EFI_SUCCESS) {
printf("ERROR: Failed to reserve space for FDT\n");

46
uefi-fix-memory-calculation-overflow-on-32-bit-systems.patch Normal file
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@ -0,0 +1,46 @@
From patchwork Tue Apr 9 20:58:30 2019
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [U-Boot] efi: fix memory calculation overflow on 32-bit systems
X-Patchwork-Submitter: Patrick Wildt <patrick@blueri.se>
X-Patchwork-Id: 1082739
X-Patchwork-Delegate: xypron.glpk@gmx.de
Message-Id: <20190409205830.GA5818@nyx.fritz.box>
To: u-boot@lists.denx.de
Date: Tue, 9 Apr 2019 22:58:30 +0200
From: Patrick Wildt <patrick@blueri.se>
List-Id: U-Boot discussion <u-boot.lists.denx.de>
Hi,
There are Cubox-i machines out there with nearly 4 GiB of RAM. The
RAM starts at 0x10000000 with a size of 0xf0000000. Thus the end
of RAM is at 0x100000000. This overflows a 32-bit integer, which
should be fine since in the EFI memory code the variables used are
all 64-bit with a fixed size. Unfortunately EFI_PAGE_MASK, which is
used in the EFI memory code to remove the lower bits, is based on
the EFI_PAGE_SIZE macro which, uses 1UL with a shift. This means
the resulting mask is UL, which is only 32-bit on ARMv7. Use ULL to
make sure that even on 32-bit platforms we use a 64-bit long mask.
Without this there will be no memory available in the EFI memory map
and bootefi will fail allocating pages.
Best regards,
Patrick
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
diff --git a/include/efi.h b/include/efi.h
index d98441ab19d..3c9d20f8c0b 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -190,7 +190,7 @@ enum efi_mem_type {
#define EFI_MEM_DESC_VERSION 1
#define EFI_PAGE_SHIFT 12
-#define EFI_PAGE_SIZE (1UL << EFI_PAGE_SHIFT)
+#define EFI_PAGE_SIZE (1ULL << EFI_PAGE_SHIFT)
#define EFI_PAGE_MASK (EFI_PAGE_SIZE - 1)
struct efi_mem_desc {

245
uefi-rc5-fixes.patch
View File

@ -1,245 +0,0 @@
From 306b16718edddd660b84bf3c6627ce5d41b53ce7 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Mon, 18 Mar 2019 20:01:59 +0100
Subject: [PATCH 01/25] efi_loader: correct parameter size in efi_allocate_pool
efi_allocate_pages() expects a (uint64_t *) pointer to pass the address of
the assigned memory. If we pass the address of a pointer here, an illegal
memory access occurs on 32bit systems.
Fixes: 282a06cbcae8 ("efi_loader: Expose U-Boot addresses in memory map
for sandbox")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
lib/efi_loader/efi_memory.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index ebd2b36c03..55622d2fb4 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -440,6 +440,7 @@ efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer)
{
efi_status_t r;
+ u64 addr;
struct efi_pool_allocation *alloc;
u64 num_pages = efi_size_in_pages(size +
sizeof(struct efi_pool_allocation));
@@ -453,9 +454,9 @@ efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer)
}
r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, pool_type, num_pages,
- (uint64_t *)&alloc);
-
+ &addr);
if (r == EFI_SUCCESS) {
+ alloc = (struct efi_pool_allocation *)(uintptr_t)addr;
alloc->num_pages = num_pages;
*buffer = alloc->data;
}
--
2.20.1
From bd3b7478d1e17b4d487d276f5cc0e4f4ef9fc4b7 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Tue, 19 Mar 2019 12:30:27 +0100
Subject: [PATCH 02/25] efi_loader: endless loop in add_strings_package()
Avoid an endless loop in add_strings_package().
Suggested-by: Takahiro Akashi <takahiro.akashi@linaro.org>
Reported-by: Coverity (CID 185833)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
lib/efi_loader/efi_hii.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c
index 3a966fa4df..61b71dec62 100644
--- a/lib/efi_loader/efi_hii.c
+++ b/lib/efi_loader/efi_hii.c
@@ -227,9 +227,8 @@ out:
error:
if (stbl) {
free(stbl->language);
- if (idx > 0)
- while (--idx >= 0)
- free(stbl->strings[idx].string);
+ while (idx > 0)
+ free(stbl->strings[--idx].string);
free(stbl->strings);
}
free(stbl);
--
2.20.1
From e7dae584b05feaf507c5b85a704a2c1d25abffc9 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Tue, 19 Mar 2019 18:36:21 +0100
Subject: [PATCH 03/25] efi_loader: missing return in
efi_get_next_variable_name()
Add a missing return statement in efi_get_next_variable_name().
Reported-by: Coverity (CID 185834)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
lib/efi_loader/efi_variable.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index e0d7f5736d..699f4184d9 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -335,7 +335,7 @@ efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t *variable_name_size,
EFI_ENTRY("%p \"%ls\" %pUl", variable_name_size, variable_name, vendor);
if (!variable_name_size || !variable_name || !vendor)
- EFI_EXIT(EFI_INVALID_PARAMETER);
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
if (variable_name[0]) {
/* check null-terminated string */
--
2.20.1
From 1fd7a4764103781e424ef687034da06de3cb60b7 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Tue, 19 Mar 2019 18:44:05 +0100
Subject: [PATCH 04/25] efi_loader: memory leak in efi_dump_single_var()
A misplaced return statement lead to a memory leak in
efi_dump_single_var().
Reported-by: Coverity (CID 185829)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
cmd/nvedit_efi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index ca32566a61..e65b38dbf3 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -80,7 +80,6 @@ static void efi_dump_single_var(u16 *name, efi_guid_t *guid)
printf(", DataSize = 0x%zx\n", size);
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, data, size, true);
- return;
out:
free(data);
}
--
2.20.1
From d5974af7f7626777b5c41894f75c813ff35c1793 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Tue, 19 Mar 2019 18:58:58 +0100
Subject: [PATCH 05/25] efi_loader: remove superfluous check in
efi_setup_loaded_image()
It does not make any sense to check if a pointer is NULL if we have
dereferenced it before.
Reported-by: Coverity (CID 185827)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
lib/efi_loader/efi_boottime.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index bd8b8a17ae..4fc550d9f3 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1581,10 +1581,8 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path,
goto failure;
#endif
- if (info_ptr)
- *info_ptr = info;
- if (handle_ptr)
- *handle_ptr = obj;
+ *info_ptr = info;
+ *handle_ptr = obj;
return ret;
failure:
--
2.20.1
From 1646e0928c8eb052bfa2283a6ab8d9f2a92a10e9 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Tue, 19 Mar 2019 19:16:23 +0100
Subject: [PATCH 06/25] efi_loader: superfluous conversion in efi_file_open()
printf("%ls", ..) expects u16 * as argument to print. There is not need for
a conversion to wchar_t *.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
lib/efi_loader/efi_file.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 3a7323765b..bc715218a1 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -226,7 +226,7 @@ static efi_status_t EFIAPI efi_file_open(struct efi_file_handle *file,
efi_status_t ret;
EFI_ENTRY("%p, %p, \"%ls\", %llx, %llu", file, new_handle,
- (wchar_t *)file_name, open_mode, attributes);
+ file_name, open_mode, attributes);
/* Check parameters */
if (!file || !new_handle || !file_name) {
--
2.20.1
From d0bd87612f410a723d5ddb3001e805485e3efb4f Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Tue, 19 Mar 2019 20:08:46 +0100
Subject: [PATCH 07/25] efi_selftest: fix test_hii_string_get_string()
The check testing the string result of get_string() returned the wrong
result. The result was ignored.
Use efi_st_strcmp_16_8() for the string comparison.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
lib/efi_selftest/efi_selftest_hii.c | 17 ++++-------------
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c
index 8a0b3bc353..f4b70f7950 100644
--- a/lib/efi_selftest/efi_selftest_hii.c
+++ b/lib/efi_selftest/efi_selftest_hii.c
@@ -783,19 +783,10 @@ static int test_hii_string_get_string(void)
goto out;
}
-#if 1
- u16 *c1, *c2;
-
- for (c1 = string, c2 = L"Japanese"; *c1 == *c2; c1++, c2++)
- ;
- if (!*c1 && !*c2)
- result = EFI_ST_SUCCESS;
- else
- result = EFI_ST_FAILURE;
-#else
- /* TODO: %ls */
- efi_st_printf("got string is %s (can be wrong)\n", string);
-#endif
+ if (efi_st_strcmp_16_8(string, "Japanese")) {
+ efi_st_error("get_string returned incorrect string\n");
+ goto out;
+ }
result = EFI_ST_SUCCESS;
--
2.20.1