48 lines
1.4 KiB
Diff
48 lines
1.4 KiB
Diff
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From e9b55c2e26b83bffe6dea6ea4be8fbc249bb85d5 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <marc.zyngier@arm.com>
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Date: Sat, 26 Apr 2014 13:17:09 +0100
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Subject: [PATCH 34/36] ARM: HYP/non-sec: add the option for a second-stage
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monitor
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Allow the switch to a second stage secure monitor just before
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switching to non-secure.
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This allows a resident piece of firmware to be active once the
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kernel has been entered (the u-boot monitor is dead anyway,
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its pages being reused).
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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---
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arch/arm/cpu/armv7/nonsec_virt.S | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
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index 2a43e3c..745670e 100644
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--- a/arch/arm/cpu/armv7/nonsec_virt.S
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+++ b/arch/arm/cpu/armv7/nonsec_virt.S
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@@ -44,10 +44,19 @@ _monitor_vectors:
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* ip: target PC
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*/
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_secure_monitor:
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+#ifdef CONFIG_ARMV7_PSCI
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+ ldr r5, =_psci_vectors @ Switch to the next monitor
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+ mcr p15, 0, r5, c12, c0, 1
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+ isb
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+
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+ @ Obtain a secure stack, and configure the PSCI backend
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+ bl psci_arch_init
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+#endif
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+
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mrc p15, 0, r5, c1, c1, 0 @ read SCR
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- bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits
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+ bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
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orr r5, r5, #0x31 @ enable NS, AW, FW bits
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-
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+ @ FIQ preserved for secure mode
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mov r6, #SVC_MODE @ default mode is SVC
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is_cpu_virt_capable r4
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#ifdef CONFIG_ARMV7_VIRT
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--
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1.9.0
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