51 lines
1.6 KiB
Diff
51 lines
1.6 KiB
Diff
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From 2e19eb7de158a26c335d8820becaf859602dd401 Mon Sep 17 00:00:00 2001
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From: Marc Zyngier <marc.zyngier@arm.com>
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Date: Sat, 26 Apr 2014 13:17:04 +0100
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Subject: [PATCH 29/36] ARM: non-sec: reset CNTVOFF to zero
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Before switching to non-secure, make sure that CNTVOFF is set
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to zero on all CPUs. Otherwise, kernel running in non-secure
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without HYP enabled (hence using virtual timers) may observe
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timers that are not synchronized, effectively seeing time
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going backward...
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Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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---
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arch/arm/cpu/armv7/nonsec_virt.S | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
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index 12de5c2..b5c946f 100644
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--- a/arch/arm/cpu/armv7/nonsec_virt.S
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+++ b/arch/arm/cpu/armv7/nonsec_virt.S
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@@ -38,10 +38,10 @@ _secure_monitor:
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bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
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orr r1, r1, #0x31 @ enable NS, AW, FW bits
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-#ifdef CONFIG_ARMV7_VIRT
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
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cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
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+#ifdef CONFIG_ARMV7_VIRT
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orreq r1, r1, #0x100 @ allow HVC instruction
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#endif
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@@ -52,7 +52,14 @@ _secure_monitor:
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mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
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mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR
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#endif
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+ bne 1f
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+ @ Reset CNTVOFF to 0 before leaving monitor mode
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+ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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+ ands r0, r0, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
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+ movne r0, #0
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+ mcrrne p15, 4, r0, r0, c14 @ Reset CNTVOFF to zero
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+1:
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movs pc, lr @ return to non-secure SVC
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_hyp_trap:
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--
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1.9.0
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