36 lines
2.0 KiB
Diff
36 lines
2.0 KiB
Diff
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From 105edd7a5c55db2f9abd927634aabeb90bc120f3 Mon Sep 17 00:00:00 2001
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From: Stephen Warren <swarren@nvidia.com>
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Date: Fri, 22 Aug 2014 15:04:08 -0600
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Subject: [PATCH] ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables
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This pinmux tables currently omit any configuration for PCIe clk_req,
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wake, and rst pins, which in turn causes intermittent failures in
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U-Boot's PCIe support. Import an updated version of the pinmux tables
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which rectifies this.
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Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
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---
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board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 5 +++++
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1 files changed, 5 insertions(+), 0 deletions(-)
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diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
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index d338818..de4eb35 100644
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--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
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+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
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@@ -283,6 +283,11 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
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PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
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PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
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PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
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+ PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
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+ PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
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+ PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
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+ PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
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+ PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
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PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
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PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
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PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
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--
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1.7.2.5
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